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initial commit with v2.6.32.60
[linux-2.6.32.60-moxart.git] / drivers / gpu / drm / radeon / r100.c
bloba2ae151e1326c94b5fe3771ada4af108d02df9d7
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/seq_file.h>
29 #include "drmP.h"
30 #include "drm.h"
31 #include "radeon_drm.h"
32 #include "radeon_reg.h"
33 #include "radeon.h"
34 #include "r100d.h"
35 #include "rs100d.h"
36 #include "rv200d.h"
37 #include "rv250d.h"
38
39 #include <linux/firmware.h>
40 #include <linux/platform_device.h>
41
42 #include "r100_reg_safe.h"
43 #include "rn50_reg_safe.h"
44
45 /* Firmware Names */
46 #define FIRMWARE_R100 "radeon/R100_cp.bin"
47 #define FIRMWARE_R200 "radeon/R200_cp.bin"
48 #define FIRMWARE_R300 "radeon/R300_cp.bin"
49 #define FIRMWARE_R420 "radeon/R420_cp.bin"
50 #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
51 #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
52 #define FIRMWARE_R520 "radeon/R520_cp.bin"
53
54 MODULE_FIRMWARE(FIRMWARE_R100);
55 MODULE_FIRMWARE(FIRMWARE_R200);
56 MODULE_FIRMWARE(FIRMWARE_R300);
57 MODULE_FIRMWARE(FIRMWARE_R420);
58 MODULE_FIRMWARE(FIRMWARE_RS690);
59 MODULE_FIRMWARE(FIRMWARE_RS600);
60 MODULE_FIRMWARE(FIRMWARE_R520);
61
62 #include "r100_track.h"
63
64 /* This files gather functions specifics to:
65 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
66 */
67
68 /*
69 * PCI GART
70 */
71 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
72 {
73 /* TODO: can we do somethings here ? */
74 /* It seems hw only cache one entry so we should discard this
75 * entry otherwise if first GPU GART read hit this entry it
76 * could end up in wrong address. */
77 }
78
79 int r100_pci_gart_init(struct radeon_device *rdev)
80 {
81 int r;
82
83 if (rdev->gart.table.ram.ptr) {
84 WARN(1, "R100 PCI GART already initialized.\n");
85 return 0;
86 }
87 /* Initialize common gart structure */
88 r = radeon_gart_init(rdev);
89 if (r)
90 return r;
91 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
92 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
93 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
94 return radeon_gart_table_ram_alloc(rdev);
95 }
96
97 int r100_pci_gart_enable(struct radeon_device *rdev)
98 {
99 uint32_t tmp;
100
101 /* discard memory request outside of configured range */
102 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
103 WREG32(RADEON_AIC_CNTL, tmp);
104 /* set address range for PCI address translate */
105 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location);
106 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
107 WREG32(RADEON_AIC_HI_ADDR, tmp);
108 /* Enable bus mastering */
109 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
110 WREG32(RADEON_BUS_CNTL, tmp);
111 /* set PCI GART page-table base address */
112 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
113 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
114 WREG32(RADEON_AIC_CNTL, tmp);
115 r100_pci_gart_tlb_flush(rdev);
116 rdev->gart.ready = true;
117 return 0;
118 }
119
120 void r100_pci_gart_disable(struct radeon_device *rdev)
121 {
122 uint32_t tmp;
123
124 /* discard memory request outside of configured range */
125 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
126 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
127 WREG32(RADEON_AIC_LO_ADDR, 0);
128 WREG32(RADEON_AIC_HI_ADDR, 0);
129 }
130
131 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
132 {
133 if (i < 0 || i > rdev->gart.num_gpu_pages) {
134 return -EINVAL;
135 }
136 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
137 return 0;
138 }
139
140 void r100_pci_gart_fini(struct radeon_device *rdev)
141 {
142 r100_pci_gart_disable(rdev);
143 radeon_gart_table_ram_free(rdev);
144 radeon_gart_fini(rdev);
145 }
146
147 int r100_irq_set(struct radeon_device *rdev)
148 {
149 uint32_t tmp = 0;
150
151 if (rdev->irq.sw_int) {
152 tmp |= RADEON_SW_INT_ENABLE;
153 }
154 if (rdev->irq.crtc_vblank_int[0]) {
155 tmp |= RADEON_CRTC_VBLANK_MASK;
156 }
157 if (rdev->irq.crtc_vblank_int[1]) {
158 tmp |= RADEON_CRTC2_VBLANK_MASK;
159 }
160 WREG32(RADEON_GEN_INT_CNTL, tmp);
161 return 0;
162 }
163
164 void r100_irq_disable(struct radeon_device *rdev)
165 {
166 u32 tmp;
167
168 WREG32(R_000040_GEN_INT_CNTL, 0);
169 /* Wait and acknowledge irq */
170 mdelay(1);
171 tmp = RREG32(R_000044_GEN_INT_STATUS);
172 WREG32(R_000044_GEN_INT_STATUS, tmp);
173 }
174
175 static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
176 {
177 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
178 uint32_t irq_mask = RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT |
179 RADEON_CRTC2_VBLANK_STAT;
180
181 if (irqs) {
182 WREG32(RADEON_GEN_INT_STATUS, irqs);
183 }
184 return irqs & irq_mask;
185 }
186
187 int r100_irq_process(struct radeon_device *rdev)
188 {
189 uint32_t status, msi_rearm;
190
191 status = r100_irq_ack(rdev);
192 if (!status) {
193 return IRQ_NONE;
194 }
195 if (rdev->shutdown) {
196 return IRQ_NONE;
197 }
198 while (status) {
199 /* SW interrupt */
200 if (status & RADEON_SW_INT_TEST) {
201 radeon_fence_process(rdev);
202 }
203 /* Vertical blank interrupts */
204 if (status & RADEON_CRTC_VBLANK_STAT) {
205 drm_handle_vblank(rdev->ddev, 0);
206 }
207 if (status & RADEON_CRTC2_VBLANK_STAT) {
208 drm_handle_vblank(rdev->ddev, 1);
209 }
210 status = r100_irq_ack(rdev);
211 }
212 if (rdev->msi_enabled) {
213 switch (rdev->family) {
214 case CHIP_RS400:
215 case CHIP_RS480:
216 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
217 WREG32(RADEON_AIC_CNTL, msi_rearm);
218 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
219 break;
220 default:
221 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
222 break;
223 }
224 }
225 return IRQ_HANDLED;
226 }
227
228 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
229 {
230 if (crtc == 0)
231 return RREG32(RADEON_CRTC_CRNT_FRAME);
232 else
233 return RREG32(RADEON_CRTC2_CRNT_FRAME);
234 }
235
236 void r100_fence_ring_emit(struct radeon_device *rdev,
237 struct radeon_fence *fence)
238 {
239 /* Who ever call radeon_fence_emit should call ring_lock and ask
240 * for enough space (today caller are ib schedule and buffer move) */
241 /* Wait until IDLE & CLEAN */
242 radeon_ring_write(rdev, PACKET0(0x1720, 0));
243 radeon_ring_write(rdev, (1 << 16) | (1 << 17));
244 /* Emit fence sequence & fire IRQ */
245 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
246 radeon_ring_write(rdev, fence->seq);
247 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
248 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
249 }
250
251 int r100_wb_init(struct radeon_device *rdev)
252 {
253 int r;
254
255 if (rdev->wb.wb_obj == NULL) {
256 r = radeon_object_create(rdev, NULL, RADEON_GPU_PAGE_SIZE,
257 true,
258 RADEON_GEM_DOMAIN_GTT,
259 false, &rdev->wb.wb_obj);
260 if (r) {
261 DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r);
262 return r;
263 }
264 r = radeon_object_pin(rdev->wb.wb_obj,
265 RADEON_GEM_DOMAIN_GTT,
266 &rdev->wb.gpu_addr);
267 if (r) {
268 DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r);
269 return r;
270 }
271 r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
272 if (r) {
273 DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r);
274 return r;
275 }
276 }
277 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
278 WREG32(R_00070C_CP_RB_RPTR_ADDR,
279 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
280 WREG32(R_000770_SCRATCH_UMSK, 0xff);
281 return 0;
282 }
283
284 void r100_wb_disable(struct radeon_device *rdev)
285 {
286 WREG32(R_000770_SCRATCH_UMSK, 0);
287 }
288
289 void r100_wb_fini(struct radeon_device *rdev)
290 {
291 r100_wb_disable(rdev);
292 if (rdev->wb.wb_obj) {
293 radeon_object_kunmap(rdev->wb.wb_obj);
294 radeon_object_unpin(rdev->wb.wb_obj);
295 radeon_object_unref(&rdev->wb.wb_obj);
296 rdev->wb.wb = NULL;
297 rdev->wb.wb_obj = NULL;
298 }
299 }
300
301 int r100_copy_blit(struct radeon_device *rdev,
302 uint64_t src_offset,
303 uint64_t dst_offset,
304 unsigned num_pages,
305 struct radeon_fence *fence)
306 {
307 uint32_t cur_pages;
308 uint32_t stride_bytes = PAGE_SIZE;
309 uint32_t pitch;
310 uint32_t stride_pixels;
311 unsigned ndw;
312 int num_loops;
313 int r = 0;
314
315 /* radeon limited to 16k stride */
316 stride_bytes &= 0x3fff;
317 /* radeon pitch is /64 */
318 pitch = stride_bytes / 64;
319 stride_pixels = stride_bytes / 4;
320 num_loops = DIV_ROUND_UP(num_pages, 8191);
321
322 /* Ask for enough room for blit + flush + fence */
323 ndw = 64 + (10 * num_loops);
324 r = radeon_ring_lock(rdev, ndw);
325 if (r) {
326 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
327 return -EINVAL;
328 }
329 while (num_pages > 0) {
330 cur_pages = num_pages;
331 if (cur_pages > 8191) {
332 cur_pages = 8191;
333 }
334 num_pages -= cur_pages;
335
336 /* pages are in Y direction - height
337 page width in X direction - width */
338 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
339 radeon_ring_write(rdev,
340 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
341 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
342 RADEON_GMC_SRC_CLIPPING |
343 RADEON_GMC_DST_CLIPPING |
344 RADEON_GMC_BRUSH_NONE |
345 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
346 RADEON_GMC_SRC_DATATYPE_COLOR |
347 RADEON_ROP3_S |
348 RADEON_DP_SRC_SOURCE_MEMORY |
349 RADEON_GMC_CLR_CMP_CNTL_DIS |
350 RADEON_GMC_WR_MSK_DIS);
351 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
352 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
353 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
354 radeon_ring_write(rdev, 0);
355 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
356 radeon_ring_write(rdev, num_pages);
357 radeon_ring_write(rdev, num_pages);
358 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
359 }
360 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
361 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
362 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
363 radeon_ring_write(rdev,
364 RADEON_WAIT_2D_IDLECLEAN |
365 RADEON_WAIT_HOST_IDLECLEAN |
366 RADEON_WAIT_DMA_GUI_IDLE);
367 if (fence) {
368 r = radeon_fence_emit(rdev, fence);
369 }
370 radeon_ring_unlock_commit(rdev);
371 return r;
372 }
373
374 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
375 {
376 unsigned i;
377 u32 tmp;
378
379 for (i = 0; i < rdev->usec_timeout; i++) {
380 tmp = RREG32(R_000E40_RBBM_STATUS);
381 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
382 return 0;
383 }
384 udelay(1);
385 }
386 return -1;
387 }
388
389 void r100_ring_start(struct radeon_device *rdev)
390 {
391 int r;
392
393 r = radeon_ring_lock(rdev, 2);
394 if (r) {
395 return;
396 }
397 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
398 radeon_ring_write(rdev,
399 RADEON_ISYNC_ANY2D_IDLE3D |
400 RADEON_ISYNC_ANY3D_IDLE2D |
401 RADEON_ISYNC_WAIT_IDLEGUI |
402 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
403 radeon_ring_unlock_commit(rdev);
404 }
405
406
407 /* Load the microcode for the CP */
408 static int r100_cp_init_microcode(struct radeon_device *rdev)
409 {
410 struct platform_device *pdev;
411 const char *fw_name = NULL;
412 int err;
413
414 DRM_DEBUG("\n");
415
416 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
417 err = IS_ERR(pdev);
418 if (err) {
419 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
420 return -EINVAL;
421 }
422 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
423 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
424 (rdev->family == CHIP_RS200)) {
425 DRM_INFO("Loading R100 Microcode\n");
426 fw_name = FIRMWARE_R100;
427 } else if ((rdev->family == CHIP_R200) ||
428 (rdev->family == CHIP_RV250) ||
429 (rdev->family == CHIP_RV280) ||
430 (rdev->family == CHIP_RS300)) {
431 DRM_INFO("Loading R200 Microcode\n");
432 fw_name = FIRMWARE_R200;
433 } else if ((rdev->family == CHIP_R300) ||
434 (rdev->family == CHIP_R350) ||
435 (rdev->family == CHIP_RV350) ||
436 (rdev->family == CHIP_RV380) ||
437 (rdev->family == CHIP_RS400) ||
438 (rdev->family == CHIP_RS480)) {
439 DRM_INFO("Loading R300 Microcode\n");
440 fw_name = FIRMWARE_R300;
441 } else if ((rdev->family == CHIP_R420) ||
442 (rdev->family == CHIP_R423) ||
443 (rdev->family == CHIP_RV410)) {
444 DRM_INFO("Loading R400 Microcode\n");
445 fw_name = FIRMWARE_R420;
446 } else if ((rdev->family == CHIP_RS690) ||
447 (rdev->family == CHIP_RS740)) {
448 DRM_INFO("Loading RS690/RS740 Microcode\n");
449 fw_name = FIRMWARE_RS690;
450 } else if (rdev->family == CHIP_RS600) {
451 DRM_INFO("Loading RS600 Microcode\n");
452 fw_name = FIRMWARE_RS600;
453 } else if ((rdev->family == CHIP_RV515) ||
454 (rdev->family == CHIP_R520) ||
455 (rdev->family == CHIP_RV530) ||
456 (rdev->family == CHIP_R580) ||
457 (rdev->family == CHIP_RV560) ||
458 (rdev->family == CHIP_RV570)) {
459 DRM_INFO("Loading R500 Microcode\n");
460 fw_name = FIRMWARE_R520;
461 }
462
463 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
464 platform_device_unregister(pdev);
465 if (err) {
466 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
467 fw_name);
468 } else if (rdev->me_fw->size % 8) {
469 printk(KERN_ERR
470 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
471 rdev->me_fw->size, fw_name);
472 err = -EINVAL;
473 release_firmware(rdev->me_fw);
474 rdev->me_fw = NULL;
475 }
476 return err;
477 }
478
479 static void r100_cp_load_microcode(struct radeon_device *rdev)
480 {
481 const __be32 *fw_data;
482 int i, size;
483
484 if (r100_gui_wait_for_idle(rdev)) {
485 printk(KERN_WARNING "Failed to wait GUI idle while "
486 "programming pipes. Bad things might happen.\n");
487 }
488
489 if (rdev->me_fw) {
490 size = rdev->me_fw->size / 4;
491 fw_data = (const __be32 *)&rdev->me_fw->data[0];
492 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
493 for (i = 0; i < size; i += 2) {
494 WREG32(RADEON_CP_ME_RAM_DATAH,
495 be32_to_cpup(&fw_data[i]));
496 WREG32(RADEON_CP_ME_RAM_DATAL,
497 be32_to_cpup(&fw_data[i + 1]));
498 }
499 }
500 }
501
502 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
503 {
504 unsigned rb_bufsz;
505 unsigned rb_blksz;
506 unsigned max_fetch;
507 unsigned pre_write_timer;
508 unsigned pre_write_limit;
509 unsigned indirect2_start;
510 unsigned indirect1_start;
511 uint32_t tmp;
512 int r;
513
514 if (r100_debugfs_cp_init(rdev)) {
515 DRM_ERROR("Failed to register debugfs file for CP !\n");
516 }
517 /* Reset CP */
518 tmp = RREG32(RADEON_CP_CSQ_STAT);
519 if ((tmp & (1 << 31))) {
520 DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
521 WREG32(RADEON_CP_CSQ_MODE, 0);
522 WREG32(RADEON_CP_CSQ_CNTL, 0);
523 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
524 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
525 mdelay(2);
526 WREG32(RADEON_RBBM_SOFT_RESET, 0);
527 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
528 mdelay(2);
529 tmp = RREG32(RADEON_CP_CSQ_STAT);
530 if ((tmp & (1 << 31))) {
531 DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
532 }
533 } else {
534 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
535 }
536
537 if (!rdev->me_fw) {
538 r = r100_cp_init_microcode(rdev);
539 if (r) {
540 DRM_ERROR("Failed to load firmware!\n");
541 return r;
542 }
543 }
544
545 /* Align ring size */
546 rb_bufsz = drm_order(ring_size / 8);
547 ring_size = (1 << (rb_bufsz + 1)) * 4;
548 r100_cp_load_microcode(rdev);
549 r = radeon_ring_init(rdev, ring_size);
550 if (r) {
551 return r;
552 }
553 /* Each time the cp read 1024 bytes (16 dword/quadword) update
554 * the rptr copy in system ram */
555 rb_blksz = 9;
556 /* cp will read 128bytes at a time (4 dwords) */
557 max_fetch = 1;
558 rdev->cp.align_mask = 16 - 1;
559 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
560 pre_write_timer = 64;
561 /* Force CP_RB_WPTR write if written more than one time before the
562 * delay expire
563 */
564 pre_write_limit = 0;
565 /* Setup the cp cache like this (cache size is 96 dwords) :
566 * RING 0 to 15
567 * INDIRECT1 16 to 79
568 * INDIRECT2 80 to 95
569 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
570 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
571 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
572 * Idea being that most of the gpu cmd will be through indirect1 buffer
573 * so it gets the bigger cache.
574 */
575 indirect2_start = 80;
576 indirect1_start = 16;
577 /* cp setup */
578 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
579 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
580 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
581 REG_SET(RADEON_MAX_FETCH, max_fetch) |
582 RADEON_RB_NO_UPDATE);
583 #ifdef __BIG_ENDIAN
584 tmp |= RADEON_BUF_SWAP_32BIT;
585 #endif
586 WREG32(RADEON_CP_RB_CNTL, tmp);
587
588 /* Set ring address */
589 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
590 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
591 /* Force read & write ptr to 0 */
592 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
593 WREG32(RADEON_CP_RB_RPTR_WR, 0);
594 WREG32(RADEON_CP_RB_WPTR, 0);
595 WREG32(RADEON_CP_RB_CNTL, tmp);
596 udelay(10);
597 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
598 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
599 /* Set cp mode to bus mastering & enable cp*/
600 WREG32(RADEON_CP_CSQ_MODE,
601 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
602 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
603 WREG32(0x718, 0);
604 WREG32(0x744, 0x00004D4D);
605 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
606 radeon_ring_start(rdev);
607 r = radeon_ring_test(rdev);
608 if (r) {
609 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
610 return r;
611 }
612 rdev->cp.ready = true;
613 return 0;
614 }
615
616 void r100_cp_fini(struct radeon_device *rdev)
617 {
618 if (r100_cp_wait_for_idle(rdev)) {
619 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
620 }
621 /* Disable ring */
622 r100_cp_disable(rdev);
623 radeon_ring_fini(rdev);
624 DRM_INFO("radeon: cp finalized\n");
625 }
626
627 void r100_cp_disable(struct radeon_device *rdev)
628 {
629 /* Disable ring */
630 rdev->cp.ready = false;
631 WREG32(RADEON_CP_CSQ_MODE, 0);
632 WREG32(RADEON_CP_CSQ_CNTL, 0);
633 if (r100_gui_wait_for_idle(rdev)) {
634 printk(KERN_WARNING "Failed to wait GUI idle while "
635 "programming pipes. Bad things might happen.\n");
636 }
637 }
638
639 int r100_cp_reset(struct radeon_device *rdev)
640 {
641 uint32_t tmp;
642 bool reinit_cp;
643 int i;
644
645 reinit_cp = rdev->cp.ready;
646 rdev->cp.ready = false;
647 WREG32(RADEON_CP_CSQ_MODE, 0);
648 WREG32(RADEON_CP_CSQ_CNTL, 0);
649 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
650 (void)RREG32(RADEON_RBBM_SOFT_RESET);
651 udelay(200);
652 WREG32(RADEON_RBBM_SOFT_RESET, 0);
653 /* Wait to prevent race in RBBM_STATUS */
654 mdelay(1);
655 for (i = 0; i < rdev->usec_timeout; i++) {
656 tmp = RREG32(RADEON_RBBM_STATUS);
657 if (!(tmp & (1 << 16))) {
658 DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
659 tmp);
660 if (reinit_cp) {
661 return r100_cp_init(rdev, rdev->cp.ring_size);
662 }
663 return 0;
664 }
665 DRM_UDELAY(1);
666 }
667 tmp = RREG32(RADEON_RBBM_STATUS);
668 DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
669 return -1;
670 }
671
672 void r100_cp_commit(struct radeon_device *rdev)
673 {
674 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
675 (void)RREG32(RADEON_CP_RB_WPTR);
676 }
677
678
679 /*
680 * CS functions
681 */
682 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
683 struct radeon_cs_packet *pkt,
684 const unsigned *auth, unsigned n,
685 radeon_packet0_check_t check)
686 {
687 unsigned reg;
688 unsigned i, j, m;
689 unsigned idx;
690 int r;
691
692 idx = pkt->idx + 1;
693 reg = pkt->reg;
694 /* Check that register fall into register range
695 * determined by the number of entry (n) in the
696 * safe register bitmap.
697 */
698 if (pkt->one_reg_wr) {
699 if ((reg >> 7) > n) {
700 return -EINVAL;
701 }
702 } else {
703 if (((reg + (pkt->count << 2)) >> 7) > n) {
704 return -EINVAL;
705 }
706 }
707 for (i = 0; i <= pkt->count; i++, idx++) {
708 j = (reg >> 7);
709 m = 1 << ((reg >> 2) & 31);
710 if (auth[j] & m) {
711 r = check(p, pkt, idx, reg);
712 if (r) {
713 return r;
714 }
715 }
716 if (pkt->one_reg_wr) {
717 if (!(auth[j] & m)) {
718 break;
719 }
720 } else {
721 reg += 4;
722 }
723 }
724 return 0;
725 }
726
727 void r100_cs_dump_packet(struct radeon_cs_parser *p,
728 struct radeon_cs_packet *pkt)
729 {
730 volatile uint32_t *ib;
731 unsigned i;
732 unsigned idx;
733
734 ib = p->ib->ptr;
735 idx = pkt->idx;
736 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
737 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
738 }
739 }
740
741 /**
742 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
743 * @parser: parser structure holding parsing context.
744 * @pkt: where to store packet informations
745 *
746 * Assume that chunk_ib_index is properly set. Will return -EINVAL
747 * if packet is bigger than remaining ib size. or if packets is unknown.
748 **/
749 int r100_cs_packet_parse(struct radeon_cs_parser *p,
750 struct radeon_cs_packet *pkt,
751 unsigned idx)
752 {
753 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
754 uint32_t header;
755
756 if (idx >= ib_chunk->length_dw) {
757 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
758 idx, ib_chunk->length_dw);
759 return -EINVAL;
760 }
761 header = radeon_get_ib_value(p, idx);
762 pkt->idx = idx;
763 pkt->type = CP_PACKET_GET_TYPE(header);
764 pkt->count = CP_PACKET_GET_COUNT(header);
765 switch (pkt->type) {
766 case PACKET_TYPE0:
767 pkt->reg = CP_PACKET0_GET_REG(header);
768 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
769 break;
770 case PACKET_TYPE3:
771 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
772 break;
773 case PACKET_TYPE2:
774 pkt->count = -1;
775 break;
776 default:
777 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
778 return -EINVAL;
779 }
780 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
781 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
782 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
783 return -EINVAL;
784 }
785 return 0;
786 }
787
788 /**
789 * r100_cs_packet_next_vline() - parse userspace VLINE packet
790 * @parser: parser structure holding parsing context.
791 *
792 * Userspace sends a special sequence for VLINE waits.
793 * PACKET0 - VLINE_START_END + value
794 * PACKET0 - WAIT_UNTIL +_value
795 * RELOC (P3) - crtc_id in reloc.
796 *
797 * This function parses this and relocates the VLINE START END
798 * and WAIT UNTIL packets to the correct crtc.
799 * It also detects a switched off crtc and nulls out the
800 * wait in that case.
801 */
802 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
803 {
804 struct drm_mode_object *obj;
805 struct drm_crtc *crtc;
806 struct radeon_crtc *radeon_crtc;
807 struct radeon_cs_packet p3reloc, waitreloc;
808 int crtc_id;
809 int r;
810 uint32_t header, h_idx, reg;
811 volatile uint32_t *ib;
812
813 ib = p->ib->ptr;
814
815 /* parse the wait until */
816 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
817 if (r)
818 return r;
819
820 /* check its a wait until and only 1 count */
821 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
822 waitreloc.count != 0) {
823 DRM_ERROR("vline wait had illegal wait until segment\n");
824 r = -EINVAL;
825 return r;
826 }
827
828 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
829 DRM_ERROR("vline wait had illegal wait until\n");
830 r = -EINVAL;
831 return r;
832 }
833
834 /* jump over the NOP */
835 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
836 if (r)
837 return r;
838
839 h_idx = p->idx - 2;
840 p->idx += waitreloc.count + 2;
841 p->idx += p3reloc.count + 2;
842
843 header = radeon_get_ib_value(p, h_idx);
844 crtc_id = radeon_get_ib_value(p, h_idx + 5);
845 reg = CP_PACKET0_GET_REG(header);
846 mutex_lock(&p->rdev->ddev->mode_config.mutex);
847 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
848 if (!obj) {
849 DRM_ERROR("cannot find crtc %d\n", crtc_id);
850 r = -EINVAL;
851 goto out;
852 }
853 crtc = obj_to_crtc(obj);
854 radeon_crtc = to_radeon_crtc(crtc);
855 crtc_id = radeon_crtc->crtc_id;
856
857 if (!crtc->enabled) {
858 /* if the CRTC isn't enabled - we need to nop out the wait until */
859 ib[h_idx + 2] = PACKET2(0);
860 ib[h_idx + 3] = PACKET2(0);
861 } else if (crtc_id == 1) {
862 switch (reg) {
863 case AVIVO_D1MODE_VLINE_START_END:
864 header &= ~R300_CP_PACKET0_REG_MASK;
865 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
866 break;
867 case RADEON_CRTC_GUI_TRIG_VLINE:
868 header &= ~R300_CP_PACKET0_REG_MASK;
869 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
870 break;
871 default:
872 DRM_ERROR("unknown crtc reloc\n");
873 r = -EINVAL;
874 goto out;
875 }
876 ib[h_idx] = header;
877 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
878 }
879 out:
880 mutex_unlock(&p->rdev->ddev->mode_config.mutex);
881 return r;
882 }
883
884 /**
885 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
886 * @parser: parser structure holding parsing context.
887 * @data: pointer to relocation data
888 * @offset_start: starting offset
889 * @offset_mask: offset mask (to align start offset on)
890 * @reloc: reloc informations
891 *
892 * Check next packet is relocation packet3, do bo validation and compute
893 * GPU offset using the provided start.
894 **/
895 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
896 struct radeon_cs_reloc **cs_reloc)
897 {
898 struct radeon_cs_chunk *relocs_chunk;
899 struct radeon_cs_packet p3reloc;
900 unsigned idx;
901 int r;
902
903 if (p->chunk_relocs_idx == -1) {
904 DRM_ERROR("No relocation chunk !\n");
905 return -EINVAL;
906 }
907 *cs_reloc = NULL;
908 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
909 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
910 if (r) {
911 return r;
912 }
913 p->idx += p3reloc.count + 2;
914 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
915 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
916 p3reloc.idx);
917 r100_cs_dump_packet(p, &p3reloc);
918 return -EINVAL;
919 }
920 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
921 if (idx >= relocs_chunk->length_dw) {
922 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
923 idx, relocs_chunk->length_dw);
924 r100_cs_dump_packet(p, &p3reloc);
925 return -EINVAL;
926 }
927 /* FIXME: we assume reloc size is 4 dwords */
928 *cs_reloc = p->relocs_ptr[(idx / 4)];
929 return 0;
930 }
931
932 static int r100_get_vtx_size(uint32_t vtx_fmt)
933 {
934 int vtx_size;
935 vtx_size = 2;
936 /* ordered according to bits in spec */
937 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
938 vtx_size++;
939 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
940 vtx_size += 3;
941 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
942 vtx_size++;
943 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
944 vtx_size++;
945 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
946 vtx_size += 3;
947 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
948 vtx_size++;
949 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
950 vtx_size++;
951 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
952 vtx_size += 2;
953 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
954 vtx_size += 2;
955 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
956 vtx_size++;
957 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
958 vtx_size += 2;
959 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
960 vtx_size++;
961 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
962 vtx_size += 2;
963 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
964 vtx_size++;
965 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
966 vtx_size++;
967 /* blend weight */
968 if (vtx_fmt & (0x7 << 15))
969 vtx_size += (vtx_fmt >> 15) & 0x7;
970 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
971 vtx_size += 3;
972 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
973 vtx_size += 2;
974 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
975 vtx_size++;
976 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
977 vtx_size++;
978 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
979 vtx_size++;
980 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
981 vtx_size++;
982 return vtx_size;
983 }
984
985 static int r100_packet0_check(struct radeon_cs_parser *p,
986 struct radeon_cs_packet *pkt,
987 unsigned idx, unsigned reg)
988 {
989 struct radeon_cs_reloc *reloc;
990 struct r100_cs_track *track;
991 volatile uint32_t *ib;
992 uint32_t tmp;
993 int r;
994 int i, face;
995 u32 tile_flags = 0;
996 u32 idx_value;
997
998 ib = p->ib->ptr;
999 track = (struct r100_cs_track *)p->track;
1000
1001 idx_value = radeon_get_ib_value(p, idx);
1002
1003 switch (reg) {
1004 case RADEON_CRTC_GUI_TRIG_VLINE:
1005 r = r100_cs_packet_parse_vline(p);
1006 if (r) {
1007 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1008 idx, reg);
1009 r100_cs_dump_packet(p, pkt);
1010 return r;
1011 }
1012 break;
1013 /* FIXME: only allow PACKET3 blit? easier to check for out of
1014 * range access */
1015 case RADEON_DST_PITCH_OFFSET:
1016 case RADEON_SRC_PITCH_OFFSET:
1017 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1018 if (r)
1019 return r;
1020 break;
1021 case RADEON_RB3D_DEPTHOFFSET:
1022 r = r100_cs_packet_next_reloc(p, &reloc);
1023 if (r) {
1024 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1025 idx, reg);
1026 r100_cs_dump_packet(p, pkt);
1027 return r;
1028 }
1029 track->zb.robj = reloc->robj;
1030 track->zb.offset = idx_value;
1031 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1032 break;
1033 case RADEON_RB3D_COLOROFFSET:
1034 r = r100_cs_packet_next_reloc(p, &reloc);
1035 if (r) {
1036 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1037 idx, reg);
1038 r100_cs_dump_packet(p, pkt);
1039 return r;
1040 }
1041 track->cb[0].robj = reloc->robj;
1042 track->cb[0].offset = idx_value;
1043 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1044 break;
1045 case RADEON_PP_TXOFFSET_0:
1046 case RADEON_PP_TXOFFSET_1:
1047 case RADEON_PP_TXOFFSET_2:
1048 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1049 r = r100_cs_packet_next_reloc(p, &reloc);
1050 if (r) {
1051 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1052 idx, reg);
1053 r100_cs_dump_packet(p, pkt);
1054 return r;
1055 }
1056 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1057 track->textures[i].robj = reloc->robj;
1058 break;
1059 case RADEON_PP_CUBIC_OFFSET_T0_0:
1060 case RADEON_PP_CUBIC_OFFSET_T0_1:
1061 case RADEON_PP_CUBIC_OFFSET_T0_2:
1062 case RADEON_PP_CUBIC_OFFSET_T0_3:
1063 case RADEON_PP_CUBIC_OFFSET_T0_4:
1064 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1065 r = r100_cs_packet_next_reloc(p, &reloc);
1066 if (r) {
1067 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1068 idx, reg);
1069 r100_cs_dump_packet(p, pkt);
1070 return r;
1071 }
1072 track->textures[0].cube_info[i].offset = idx_value;
1073 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1074 track->textures[0].cube_info[i].robj = reloc->robj;
1075 break;
1076 case RADEON_PP_CUBIC_OFFSET_T1_0:
1077 case RADEON_PP_CUBIC_OFFSET_T1_1:
1078 case RADEON_PP_CUBIC_OFFSET_T1_2:
1079 case RADEON_PP_CUBIC_OFFSET_T1_3:
1080 case RADEON_PP_CUBIC_OFFSET_T1_4:
1081 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1082 r = r100_cs_packet_next_reloc(p, &reloc);
1083 if (r) {
1084 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1085 idx, reg);
1086 r100_cs_dump_packet(p, pkt);
1087 return r;
1088 }
1089 track->textures[1].cube_info[i].offset = idx_value;
1090 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1091 track->textures[1].cube_info[i].robj = reloc->robj;
1092 break;
1093 case RADEON_PP_CUBIC_OFFSET_T2_0:
1094 case RADEON_PP_CUBIC_OFFSET_T2_1:
1095 case RADEON_PP_CUBIC_OFFSET_T2_2:
1096 case RADEON_PP_CUBIC_OFFSET_T2_3:
1097 case RADEON_PP_CUBIC_OFFSET_T2_4:
1098 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1099 r = r100_cs_packet_next_reloc(p, &reloc);
1100 if (r) {
1101 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1102 idx, reg);
1103 r100_cs_dump_packet(p, pkt);
1104 return r;
1105 }
1106 track->textures[2].cube_info[i].offset = idx_value;
1107 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1108 track->textures[2].cube_info[i].robj = reloc->robj;
1109 break;
1110 case RADEON_RE_WIDTH_HEIGHT:
1111 track->maxy = ((idx_value >> 16) & 0x7FF);
1112 break;
1113 case RADEON_RB3D_COLORPITCH:
1114 r = r100_cs_packet_next_reloc(p, &reloc);
1115 if (r) {
1116 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1117 idx, reg);
1118 r100_cs_dump_packet(p, pkt);
1119 return r;
1120 }
1121
1122 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1123 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1124 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1125 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1126
1127 tmp = idx_value & ~(0x7 << 16);
1128 tmp |= tile_flags;
1129 ib[idx] = tmp;
1130
1131 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1132 break;
1133 case RADEON_RB3D_DEPTHPITCH:
1134 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1135 break;
1136 case RADEON_RB3D_CNTL:
1137 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1138 case 7:
1139 case 8:
1140 case 9:
1141 case 11:
1142 case 12:
1143 track->cb[0].cpp = 1;
1144 break;
1145 case 3:
1146 case 4:
1147 case 15:
1148 track->cb[0].cpp = 2;
1149 break;
1150 case 6:
1151 track->cb[0].cpp = 4;
1152 break;
1153 default:
1154 DRM_ERROR("Invalid color buffer format (%d) !\n",
1155 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1156 return -EINVAL;
1157 }
1158 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1159 break;
1160 case RADEON_RB3D_ZSTENCILCNTL:
1161 switch (idx_value & 0xf) {
1162 case 0:
1163 track->zb.cpp = 2;
1164 break;
1165 case 2:
1166 case 3:
1167 case 4:
1168 case 5:
1169 case 9:
1170 case 11:
1171 track->zb.cpp = 4;
1172 break;
1173 default:
1174 break;
1175 }
1176 break;
1177 case RADEON_RB3D_ZPASS_ADDR:
1178 r = r100_cs_packet_next_reloc(p, &reloc);
1179 if (r) {
1180 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1181 idx, reg);
1182 r100_cs_dump_packet(p, pkt);
1183 return r;
1184 }
1185 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1186 break;
1187 case RADEON_PP_CNTL:
1188 {
1189 uint32_t temp = idx_value >> 4;
1190 for (i = 0; i < track->num_texture; i++)
1191 track->textures[i].enabled = !!(temp & (1 << i));
1192 }
1193 break;
1194 case RADEON_SE_VF_CNTL:
1195 track->vap_vf_cntl = idx_value;
1196 break;
1197 case RADEON_SE_VTX_FMT:
1198 track->vtx_size = r100_get_vtx_size(idx_value);
1199 break;
1200 case RADEON_PP_TEX_SIZE_0:
1201 case RADEON_PP_TEX_SIZE_1:
1202 case RADEON_PP_TEX_SIZE_2:
1203 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1204 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1205 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1206 break;
1207 case RADEON_PP_TEX_PITCH_0:
1208 case RADEON_PP_TEX_PITCH_1:
1209 case RADEON_PP_TEX_PITCH_2:
1210 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1211 track->textures[i].pitch = idx_value + 32;
1212 break;
1213 case RADEON_PP_TXFILTER_0:
1214 case RADEON_PP_TXFILTER_1:
1215 case RADEON_PP_TXFILTER_2:
1216 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1217 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1218 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1219 tmp = (idx_value >> 23) & 0x7;
1220 if (tmp == 2 || tmp == 6)
1221 track->textures[i].roundup_w = false;
1222 tmp = (idx_value >> 27) & 0x7;
1223 if (tmp == 2 || tmp == 6)
1224 track->textures[i].roundup_h = false;
1225 break;
1226 case RADEON_PP_TXFORMAT_0:
1227 case RADEON_PP_TXFORMAT_1:
1228 case RADEON_PP_TXFORMAT_2:
1229 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1230 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1231 track->textures[i].use_pitch = 1;
1232 } else {
1233 track->textures[i].use_pitch = 0;
1234 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1235 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1236 }
1237 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1238 track->textures[i].tex_coord_type = 2;
1239 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1240 case RADEON_TXFORMAT_I8:
1241 case RADEON_TXFORMAT_RGB332:
1242 case RADEON_TXFORMAT_Y8:
1243 track->textures[i].cpp = 1;
1244 break;
1245 case RADEON_TXFORMAT_AI88:
1246 case RADEON_TXFORMAT_ARGB1555:
1247 case RADEON_TXFORMAT_RGB565:
1248 case RADEON_TXFORMAT_ARGB4444:
1249 case RADEON_TXFORMAT_VYUY422:
1250 case RADEON_TXFORMAT_YVYU422:
1251 case RADEON_TXFORMAT_DXT1:
1252 case RADEON_TXFORMAT_SHADOW16:
1253 case RADEON_TXFORMAT_LDUDV655:
1254 case RADEON_TXFORMAT_DUDV88:
1255 track->textures[i].cpp = 2;
1256 break;
1257 case RADEON_TXFORMAT_ARGB8888:
1258 case RADEON_TXFORMAT_RGBA8888:
1259 case RADEON_TXFORMAT_DXT23:
1260 case RADEON_TXFORMAT_DXT45:
1261 case RADEON_TXFORMAT_SHADOW32:
1262 case RADEON_TXFORMAT_LDUDUV8888:
1263 track->textures[i].cpp = 4;
1264 break;
1265 }
1266 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1267 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1268 break;
1269 case RADEON_PP_CUBIC_FACES_0:
1270 case RADEON_PP_CUBIC_FACES_1:
1271 case RADEON_PP_CUBIC_FACES_2:
1272 tmp = idx_value;
1273 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1274 for (face = 0; face < 4; face++) {
1275 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1276 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1277 }
1278 break;
1279 default:
1280 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1281 reg, idx);
1282 return -EINVAL;
1283 }
1284 return 0;
1285 }
1286
1287 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1288 struct radeon_cs_packet *pkt,
1289 struct radeon_object *robj)
1290 {
1291 unsigned idx;
1292 u32 value;
1293 idx = pkt->idx + 1;
1294 value = radeon_get_ib_value(p, idx + 2);
1295 if ((value + 1) > radeon_object_size(robj)) {
1296 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1297 "(need %u have %lu) !\n",
1298 value + 1,
1299 radeon_object_size(robj));
1300 return -EINVAL;
1301 }
1302 return 0;
1303 }
1304
1305 static int r100_packet3_check(struct radeon_cs_parser *p,
1306 struct radeon_cs_packet *pkt)
1307 {
1308 struct radeon_cs_reloc *reloc;
1309 struct r100_cs_track *track;
1310 unsigned idx;
1311 volatile uint32_t *ib;
1312 int r;
1313
1314 ib = p->ib->ptr;
1315 idx = pkt->idx + 1;
1316 track = (struct r100_cs_track *)p->track;
1317 switch (pkt->opcode) {
1318 case PACKET3_3D_LOAD_VBPNTR:
1319 r = r100_packet3_load_vbpntr(p, pkt, idx);
1320 if (r)
1321 return r;
1322 break;
1323 case PACKET3_INDX_BUFFER:
1324 r = r100_cs_packet_next_reloc(p, &reloc);
1325 if (r) {
1326 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1327 r100_cs_dump_packet(p, pkt);
1328 return r;
1329 }
1330 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1331 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1332 if (r) {
1333 return r;
1334 }
1335 break;
1336 case 0x23:
1337 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1338 r = r100_cs_packet_next_reloc(p, &reloc);
1339 if (r) {
1340 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1341 r100_cs_dump_packet(p, pkt);
1342 return r;
1343 }
1344 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1345 track->num_arrays = 1;
1346 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1347
1348 track->arrays[0].robj = reloc->robj;
1349 track->arrays[0].esize = track->vtx_size;
1350
1351 track->max_indx = radeon_get_ib_value(p, idx+1);
1352
1353 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1354 track->immd_dwords = pkt->count - 1;
1355 r = r100_cs_track_check(p->rdev, track);
1356 if (r)
1357 return r;
1358 break;
1359 case PACKET3_3D_DRAW_IMMD:
1360 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1361 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1362 return -EINVAL;
1363 }
1364 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1365 track->immd_dwords = pkt->count - 1;
1366 r = r100_cs_track_check(p->rdev, track);
1367 if (r)
1368 return r;
1369 break;
1370 /* triggers drawing using in-packet vertex data */
1371 case PACKET3_3D_DRAW_IMMD_2:
1372 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1373 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1374 return -EINVAL;
1375 }
1376 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1377 track->immd_dwords = pkt->count;
1378 r = r100_cs_track_check(p->rdev, track);
1379 if (r)
1380 return r;
1381 break;
1382 /* triggers drawing using in-packet vertex data */
1383 case PACKET3_3D_DRAW_VBUF_2:
1384 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1385 r = r100_cs_track_check(p->rdev, track);
1386 if (r)
1387 return r;
1388 break;
1389 /* triggers drawing of vertex buffers setup elsewhere */
1390 case PACKET3_3D_DRAW_INDX_2:
1391 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1392 r = r100_cs_track_check(p->rdev, track);
1393 if (r)
1394 return r;
1395 break;
1396 /* triggers drawing using indices to vertex buffer */
1397 case PACKET3_3D_DRAW_VBUF:
1398 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1399 r = r100_cs_track_check(p->rdev, track);
1400 if (r)
1401 return r;
1402 break;
1403 /* triggers drawing of vertex buffers setup elsewhere */
1404 case PACKET3_3D_DRAW_INDX:
1405 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1406 r = r100_cs_track_check(p->rdev, track);
1407 if (r)
1408 return r;
1409 break;
1410 /* triggers drawing using indices to vertex buffer */
1411 case PACKET3_NOP:
1412 break;
1413 default:
1414 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1415 return -EINVAL;
1416 }
1417 return 0;
1418 }
1419
1420 int r100_cs_parse(struct radeon_cs_parser *p)
1421 {
1422 struct radeon_cs_packet pkt;
1423 struct r100_cs_track *track;
1424 int r;
1425
1426 track = kzalloc(sizeof(*track), GFP_KERNEL);
1427 r100_cs_track_clear(p->rdev, track);
1428 p->track = track;
1429 do {
1430 r = r100_cs_packet_parse(p, &pkt, p->idx);
1431 if (r) {
1432 return r;
1433 }
1434 p->idx += pkt.count + 2;
1435 switch (pkt.type) {
1436 case PACKET_TYPE0:
1437 if (p->rdev->family >= CHIP_R200)
1438 r = r100_cs_parse_packet0(p, &pkt,
1439 p->rdev->config.r100.reg_safe_bm,
1440 p->rdev->config.r100.reg_safe_bm_size,
1441 &r200_packet0_check);
1442 else
1443 r = r100_cs_parse_packet0(p, &pkt,
1444 p->rdev->config.r100.reg_safe_bm,
1445 p->rdev->config.r100.reg_safe_bm_size,
1446 &r100_packet0_check);
1447 break;
1448 case PACKET_TYPE2:
1449 break;
1450 case PACKET_TYPE3:
1451 r = r100_packet3_check(p, &pkt);
1452 break;
1453 default:
1454 DRM_ERROR("Unknown packet type %d !\n",
1455 pkt.type);
1456 return -EINVAL;
1457 }
1458 if (r) {
1459 return r;
1460 }
1461 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1462 return 0;
1463 }
1464
1465
1466 /*
1467 * Global GPU functions
1468 */
1469 void r100_errata(struct radeon_device *rdev)
1470 {
1471 rdev->pll_errata = 0;
1472
1473 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1474 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1475 }
1476
1477 if (rdev->family == CHIP_RV100 ||
1478 rdev->family == CHIP_RS100 ||
1479 rdev->family == CHIP_RS200) {
1480 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1481 }
1482 }
1483
1484 /* Wait for vertical sync on primary CRTC */
1485 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1486 {
1487 uint32_t crtc_gen_cntl, tmp;
1488 int i;
1489
1490 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1491 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1492 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1493 return;
1494 }
1495 /* Clear the CRTC_VBLANK_SAVE bit */
1496 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1497 for (i = 0; i < rdev->usec_timeout; i++) {
1498 tmp = RREG32(RADEON_CRTC_STATUS);
1499 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1500 return;
1501 }
1502 DRM_UDELAY(1);
1503 }
1504 }
1505
1506 /* Wait for vertical sync on secondary CRTC */
1507 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1508 {
1509 uint32_t crtc2_gen_cntl, tmp;
1510 int i;
1511
1512 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1513 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1514 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1515 return;
1516
1517 /* Clear the CRTC_VBLANK_SAVE bit */
1518 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1519 for (i = 0; i < rdev->usec_timeout; i++) {
1520 tmp = RREG32(RADEON_CRTC2_STATUS);
1521 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1522 return;
1523 }
1524 DRM_UDELAY(1);
1525 }
1526 }
1527
1528 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1529 {
1530 unsigned i;
1531 uint32_t tmp;
1532
1533 for (i = 0; i < rdev->usec_timeout; i++) {
1534 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1535 if (tmp >= n) {
1536 return 0;
1537 }
1538 DRM_UDELAY(1);
1539 }
1540 return -1;
1541 }
1542
1543 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1544 {
1545 unsigned i;
1546 uint32_t tmp;
1547
1548 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1549 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1550 " Bad things might happen.\n");
1551 }
1552 for (i = 0; i < rdev->usec_timeout; i++) {
1553 tmp = RREG32(RADEON_RBBM_STATUS);
1554 if (!(tmp & (1 << 31))) {
1555 return 0;
1556 }
1557 DRM_UDELAY(1);
1558 }
1559 return -1;
1560 }
1561
1562 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1563 {
1564 unsigned i;
1565 uint32_t tmp;
1566
1567 for (i = 0; i < rdev->usec_timeout; i++) {
1568 /* read MC_STATUS */
1569 tmp = RREG32(0x0150);
1570 if (tmp & (1 << 2)) {
1571 return 0;
1572 }
1573 DRM_UDELAY(1);
1574 }
1575 return -1;
1576 }
1577
1578 void r100_gpu_init(struct radeon_device *rdev)
1579 {
1580 /* TODO: anythings to do here ? pipes ? */
1581 r100_hdp_reset(rdev);
1582 }
1583
1584 void r100_hdp_reset(struct radeon_device *rdev)
1585 {
1586 uint32_t tmp;
1587
1588 tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
1589 tmp |= (7 << 28);
1590 WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
1591 (void)RREG32(RADEON_HOST_PATH_CNTL);
1592 udelay(200);
1593 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1594 WREG32(RADEON_HOST_PATH_CNTL, tmp);
1595 (void)RREG32(RADEON_HOST_PATH_CNTL);
1596 }
1597
1598 int r100_rb2d_reset(struct radeon_device *rdev)
1599 {
1600 uint32_t tmp;
1601 int i;
1602
1603 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
1604 (void)RREG32(RADEON_RBBM_SOFT_RESET);
1605 udelay(200);
1606 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1607 /* Wait to prevent race in RBBM_STATUS */
1608 mdelay(1);
1609 for (i = 0; i < rdev->usec_timeout; i++) {
1610 tmp = RREG32(RADEON_RBBM_STATUS);
1611 if (!(tmp & (1 << 26))) {
1612 DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
1613 tmp);
1614 return 0;
1615 }
1616 DRM_UDELAY(1);
1617 }
1618 tmp = RREG32(RADEON_RBBM_STATUS);
1619 DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
1620 return -1;
1621 }
1622
1623 int r100_gpu_reset(struct radeon_device *rdev)
1624 {
1625 uint32_t status;
1626
1627 /* reset order likely matter */
1628 status = RREG32(RADEON_RBBM_STATUS);
1629 /* reset HDP */
1630 r100_hdp_reset(rdev);
1631 /* reset rb2d */
1632 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
1633 r100_rb2d_reset(rdev);
1634 }
1635 /* TODO: reset 3D engine */
1636 /* reset CP */
1637 status = RREG32(RADEON_RBBM_STATUS);
1638 if (status & (1 << 16)) {
1639 r100_cp_reset(rdev);
1640 }
1641 /* Check if GPU is idle */
1642 status = RREG32(RADEON_RBBM_STATUS);
1643 if (status & (1 << 31)) {
1644 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1645 return -1;
1646 }
1647 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
1648 return 0;
1649 }
1650
1651
1652 /*
1653 * VRAM info
1654 */
1655 static void r100_vram_get_type(struct radeon_device *rdev)
1656 {
1657 uint32_t tmp;
1658
1659 rdev->mc.vram_is_ddr = false;
1660 if (rdev->flags & RADEON_IS_IGP)
1661 rdev->mc.vram_is_ddr = true;
1662 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1663 rdev->mc.vram_is_ddr = true;
1664 if ((rdev->family == CHIP_RV100) ||
1665 (rdev->family == CHIP_RS100) ||
1666 (rdev->family == CHIP_RS200)) {
1667 tmp = RREG32(RADEON_MEM_CNTL);
1668 if (tmp & RV100_HALF_MODE) {
1669 rdev->mc.vram_width = 32;
1670 } else {
1671 rdev->mc.vram_width = 64;
1672 }
1673 if (rdev->flags & RADEON_SINGLE_CRTC) {
1674 rdev->mc.vram_width /= 4;
1675 rdev->mc.vram_is_ddr = true;
1676 }
1677 } else if (rdev->family <= CHIP_RV280) {
1678 tmp = RREG32(RADEON_MEM_CNTL);
1679 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
1680 rdev->mc.vram_width = 128;
1681 } else {
1682 rdev->mc.vram_width = 64;
1683 }
1684 } else {
1685 /* newer IGPs */
1686 rdev->mc.vram_width = 128;
1687 }
1688 }
1689
1690 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
1691 {
1692 u32 aper_size;
1693 u8 byte;
1694
1695 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1696
1697 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
1698 * that is has the 2nd generation multifunction PCI interface
1699 */
1700 if (rdev->family == CHIP_RV280 ||
1701 rdev->family >= CHIP_RV350) {
1702 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
1703 ~RADEON_HDP_APER_CNTL);
1704 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
1705 return aper_size * 2;
1706 }
1707
1708 /* Older cards have all sorts of funny issues to deal with. First
1709 * check if it's a multifunction card by reading the PCI config
1710 * header type... Limit those to one aperture size
1711 */
1712 pci_read_config_byte(rdev->pdev, 0xe, &byte);
1713 if (byte & 0x80) {
1714 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
1715 DRM_INFO("Limiting VRAM to one aperture\n");
1716 return aper_size;
1717 }
1718
1719 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
1720 * have set it up. We don't write this as it's broken on some ASICs but
1721 * we expect the BIOS to have done the right thing (might be too optimistic...)
1722 */
1723 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
1724 return aper_size * 2;
1725 return aper_size;
1726 }
1727
1728 void r100_vram_init_sizes(struct radeon_device *rdev)
1729 {
1730 u64 config_aper_size;
1731 u32 accessible;
1732
1733 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1734
1735 if (rdev->flags & RADEON_IS_IGP) {
1736 uint32_t tom;
1737 /* read NB_TOM to get the amount of ram stolen for the GPU */
1738 tom = RREG32(RADEON_NB_TOM);
1739 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
1740 /* for IGPs we need to keep VRAM where it was put by the BIOS */
1741 rdev->mc.vram_location = (tom & 0xffff) << 16;
1742 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1743 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1744 } else {
1745 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
1746 /* Some production boards of m6 will report 0
1747 * if it's 8 MB
1748 */
1749 if (rdev->mc.real_vram_size == 0) {
1750 rdev->mc.real_vram_size = 8192 * 1024;
1751 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1752 }
1753 /* let driver place VRAM */
1754 rdev->mc.vram_location = 0xFFFFFFFFUL;
1755 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1756 * Novell bug 204882 + along with lots of ubuntu ones */
1757 if (config_aper_size > rdev->mc.real_vram_size)
1758 rdev->mc.mc_vram_size = config_aper_size;
1759 else
1760 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1761 }
1762
1763 /* work out accessible VRAM */
1764 accessible = r100_get_accessible_vram(rdev);
1765
1766 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1767 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1768
1769 if (accessible > rdev->mc.aper_size)
1770 accessible = rdev->mc.aper_size;
1771
1772 if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
1773 rdev->mc.mc_vram_size = rdev->mc.aper_size;
1774
1775 if (rdev->mc.real_vram_size > rdev->mc.aper_size)
1776 rdev->mc.real_vram_size = rdev->mc.aper_size;
1777 }
1778
1779 void r100_vga_set_state(struct radeon_device *rdev, bool state)
1780 {
1781 uint32_t temp;
1782
1783 temp = RREG32(RADEON_CONFIG_CNTL);
1784 if (state == false) {
1785 temp &= ~(1<<8);
1786 temp |= (1<<9);
1787 } else {
1788 temp &= ~(1<<9);
1789 }
1790 WREG32(RADEON_CONFIG_CNTL, temp);
1791 }
1792
1793 void r100_vram_info(struct radeon_device *rdev)
1794 {
1795 r100_vram_get_type(rdev);
1796
1797 r100_vram_init_sizes(rdev);
1798 }
1799
1800
1801 /*
1802 * Indirect registers accessor
1803 */
1804 void r100_pll_errata_after_index(struct radeon_device *rdev)
1805 {
1806 if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
1807 return;
1808 }
1809 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
1810 (void)RREG32(RADEON_CRTC_GEN_CNTL);
1811 }
1812
1813 static void r100_pll_errata_after_data(struct radeon_device *rdev)
1814 {
1815 /* This workarounds is necessary on RV100, RS100 and RS200 chips
1816 * or the chip could hang on a subsequent access
1817 */
1818 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
1819 udelay(5000);
1820 }
1821
1822 /* This function is required to workaround a hardware bug in some (all?)
1823 * revisions of the R300. This workaround should be called after every
1824 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
1825 * may not be correct.
1826 */
1827 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
1828 uint32_t save, tmp;
1829
1830 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
1831 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
1832 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
1833 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
1834 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
1835 }
1836 }
1837
1838 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
1839 {
1840 uint32_t data;
1841
1842 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
1843 r100_pll_errata_after_index(rdev);
1844 data = RREG32(RADEON_CLOCK_CNTL_DATA);
1845 r100_pll_errata_after_data(rdev);
1846 return data;
1847 }
1848
1849 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1850 {
1851 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
1852 r100_pll_errata_after_index(rdev);
1853 WREG32(RADEON_CLOCK_CNTL_DATA, v);
1854 r100_pll_errata_after_data(rdev);
1855 }
1856
1857 void r100_set_safe_registers(struct radeon_device *rdev)
1858 {
1859 if (ASIC_IS_RN50(rdev)) {
1860 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
1861 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
1862 } else if (rdev->family < CHIP_R200) {
1863 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
1864 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
1865 } else {
1866 r200_set_safe_registers(rdev);
1867 }
1868 }
1869
1870 /*
1871 * Debugfs info
1872 */
1873 #if defined(CONFIG_DEBUG_FS)
1874 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
1875 {
1876 struct drm_info_node *node = (struct drm_info_node *) m->private;
1877 struct drm_device *dev = node->minor->dev;
1878 struct radeon_device *rdev = dev->dev_private;
1879 uint32_t reg, value;
1880 unsigned i;
1881
1882 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
1883 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
1884 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
1885 for (i = 0; i < 64; i++) {
1886 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
1887 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
1888 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
1889 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
1890 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
1891 }
1892 return 0;
1893 }
1894
1895 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
1896 {
1897 struct drm_info_node *node = (struct drm_info_node *) m->private;
1898 struct drm_device *dev = node->minor->dev;
1899 struct radeon_device *rdev = dev->dev_private;
1900 uint32_t rdp, wdp;
1901 unsigned count, i, j;
1902
1903 radeon_ring_free_size(rdev);
1904 rdp = RREG32(RADEON_CP_RB_RPTR);
1905 wdp = RREG32(RADEON_CP_RB_WPTR);
1906 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
1907 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
1908 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
1909 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
1910 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
1911 seq_printf(m, "%u dwords in ring\n", count);
1912 for (j = 0; j <= count; j++) {
1913 i = (rdp + j) & rdev->cp.ptr_mask;
1914 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
1915 }
1916 return 0;
1917 }
1918
1919
1920 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
1921 {
1922 struct drm_info_node *node = (struct drm_info_node *) m->private;
1923 struct drm_device *dev = node->minor->dev;
1924 struct radeon_device *rdev = dev->dev_private;
1925 uint32_t csq_stat, csq2_stat, tmp;
1926 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
1927 unsigned i;
1928
1929 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
1930 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
1931 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
1932 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
1933 r_rptr = (csq_stat >> 0) & 0x3ff;
1934 r_wptr = (csq_stat >> 10) & 0x3ff;
1935 ib1_rptr = (csq_stat >> 20) & 0x3ff;
1936 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
1937 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
1938 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
1939 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
1940 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
1941 seq_printf(m, "Ring rptr %u\n", r_rptr);
1942 seq_printf(m, "Ring wptr %u\n", r_wptr);
1943 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
1944 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
1945 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
1946 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
1947 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
1948 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
1949 seq_printf(m, "Ring fifo:\n");
1950 for (i = 0; i < 256; i++) {
1951 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
1952 tmp = RREG32(RADEON_CP_CSQ_DATA);
1953 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
1954 }
1955 seq_printf(m, "Indirect1 fifo:\n");
1956 for (i = 256; i <= 512; i++) {
1957 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
1958 tmp = RREG32(RADEON_CP_CSQ_DATA);
1959 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
1960 }
1961 seq_printf(m, "Indirect2 fifo:\n");
1962 for (i = 640; i < ib1_wptr; i++) {
1963 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
1964 tmp = RREG32(RADEON_CP_CSQ_DATA);
1965 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
1966 }
1967 return 0;
1968 }
1969
1970 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
1971 {
1972 struct drm_info_node *node = (struct drm_info_node *) m->private;
1973 struct drm_device *dev = node->minor->dev;
1974 struct radeon_device *rdev = dev->dev_private;
1975 uint32_t tmp;
1976
1977 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
1978 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
1979 tmp = RREG32(RADEON_MC_FB_LOCATION);
1980 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
1981 tmp = RREG32(RADEON_BUS_CNTL);
1982 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
1983 tmp = RREG32(RADEON_MC_AGP_LOCATION);
1984 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
1985 tmp = RREG32(RADEON_AGP_BASE);
1986 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
1987 tmp = RREG32(RADEON_HOST_PATH_CNTL);
1988 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
1989 tmp = RREG32(0x01D0);
1990 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
1991 tmp = RREG32(RADEON_AIC_LO_ADDR);
1992 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
1993 tmp = RREG32(RADEON_AIC_HI_ADDR);
1994 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
1995 tmp = RREG32(0x01E4);
1996 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
1997 return 0;
1998 }
1999
2000 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2001 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2002 };
2003
2004 static struct drm_info_list r100_debugfs_cp_list[] = {
2005 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2006 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2007 };
2008
2009 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2010 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2011 };
2012 #endif
2013
2014 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2015 {
2016 #if defined(CONFIG_DEBUG_FS)
2017 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2018 #else
2019 return 0;
2020 #endif
2021 }
2022
2023 int r100_debugfs_cp_init(struct radeon_device *rdev)
2024 {
2025 #if defined(CONFIG_DEBUG_FS)
2026 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2027 #else
2028 return 0;
2029 #endif
2030 }
2031
2032 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2033 {
2034 #if defined(CONFIG_DEBUG_FS)
2035 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2036 #else
2037 return 0;
2038 #endif
2039 }
2040
2041 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2042 uint32_t tiling_flags, uint32_t pitch,
2043 uint32_t offset, uint32_t obj_size)
2044 {
2045 int surf_index = reg * 16;
2046 int flags = 0;
2047
2048 /* r100/r200 divide by 16 */
2049 if (rdev->family < CHIP_R300)
2050 flags = pitch / 16;
2051 else
2052 flags = pitch / 8;
2053
2054 if (rdev->family <= CHIP_RS200) {
2055 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2056 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2057 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2058 if (tiling_flags & RADEON_TILING_MACRO)
2059 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2060 } else if (rdev->family <= CHIP_RV280) {
2061 if (tiling_flags & (RADEON_TILING_MACRO))
2062 flags |= R200_SURF_TILE_COLOR_MACRO;
2063 if (tiling_flags & RADEON_TILING_MICRO)
2064 flags |= R200_SURF_TILE_COLOR_MICRO;
2065 } else {
2066 if (tiling_flags & RADEON_TILING_MACRO)
2067 flags |= R300_SURF_TILE_MACRO;
2068 if (tiling_flags & RADEON_TILING_MICRO)
2069 flags |= R300_SURF_TILE_MICRO;
2070 }
2071
2072 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2073 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2074 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2075 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2076
2077 DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2078 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2079 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2080 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2081 return 0;
2082 }
2083
2084 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2085 {
2086 int surf_index = reg * 16;
2087 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2088 }
2089
2090 void r100_bandwidth_update(struct radeon_device *rdev)
2091 {
2092 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2093 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2094 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2095 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2096 fixed20_12 memtcas_ff[8] = {
2097 fixed_init(1),
2098 fixed_init(2),
2099 fixed_init(3),
2100 fixed_init(0),
2101 fixed_init_half(1),
2102 fixed_init_half(2),
2103 fixed_init(0),
2104 };
2105 fixed20_12 memtcas_rs480_ff[8] = {
2106 fixed_init(0),
2107 fixed_init(1),
2108 fixed_init(2),
2109 fixed_init(3),
2110 fixed_init(0),
2111 fixed_init_half(1),
2112 fixed_init_half(2),
2113 fixed_init_half(3),
2114 };
2115 fixed20_12 memtcas2_ff[8] = {
2116 fixed_init(0),
2117 fixed_init(1),
2118 fixed_init(2),
2119 fixed_init(3),
2120 fixed_init(4),
2121 fixed_init(5),
2122 fixed_init(6),
2123 fixed_init(7),
2124 };
2125 fixed20_12 memtrbs[8] = {
2126 fixed_init(1),
2127 fixed_init_half(1),
2128 fixed_init(2),
2129 fixed_init_half(2),
2130 fixed_init(3),
2131 fixed_init_half(3),
2132 fixed_init(4),
2133 fixed_init_half(4)
2134 };
2135 fixed20_12 memtrbs_r4xx[8] = {
2136 fixed_init(4),
2137 fixed_init(5),
2138 fixed_init(6),
2139 fixed_init(7),
2140 fixed_init(8),
2141 fixed_init(9),
2142 fixed_init(10),
2143 fixed_init(11)
2144 };
2145 fixed20_12 min_mem_eff;
2146 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2147 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2148 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2149 disp_drain_rate2, read_return_rate;
2150 fixed20_12 time_disp1_drop_priority;
2151 int c;
2152 int cur_size = 16; /* in octawords */
2153 int critical_point = 0, critical_point2;
2154 /* uint32_t read_return_rate, time_disp1_drop_priority; */
2155 int stop_req, max_stop_req;
2156 struct drm_display_mode *mode1 = NULL;
2157 struct drm_display_mode *mode2 = NULL;
2158 uint32_t pixel_bytes1 = 0;
2159 uint32_t pixel_bytes2 = 0;
2160
2161 if (rdev->mode_info.crtcs[0]->base.enabled) {
2162 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2163 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2164 }
2165 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2166 if (rdev->mode_info.crtcs[1]->base.enabled) {
2167 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2168 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2169 }
2170 }
2171
2172 min_mem_eff.full = rfixed_const_8(0);
2173 /* get modes */
2174 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2175 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2176 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2177 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2178 /* check crtc enables */
2179 if (mode2)
2180 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2181 if (mode1)
2182 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2183 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2184 }
2185
2186 /*
2187 * determine is there is enough bw for current mode
2188 */
2189 mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
2190 temp_ff.full = rfixed_const(100);
2191 mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
2192 sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
2193 sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
2194
2195 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2196 temp_ff.full = rfixed_const(temp);
2197 mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
2198
2199 pix_clk.full = 0;
2200 pix_clk2.full = 0;
2201 peak_disp_bw.full = 0;
2202 if (mode1) {
2203 temp_ff.full = rfixed_const(1000);
2204 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
2205 pix_clk.full = rfixed_div(pix_clk, temp_ff);
2206 temp_ff.full = rfixed_const(pixel_bytes1);
2207 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
2208 }
2209 if (mode2) {
2210 temp_ff.full = rfixed_const(1000);
2211 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
2212 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
2213 temp_ff.full = rfixed_const(pixel_bytes2);
2214 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
2215 }
2216
2217 mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
2218 if (peak_disp_bw.full >= mem_bw.full) {
2219 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2220 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2221 }
2222
2223 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2224 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2225 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2226 mem_trcd = ((temp >> 2) & 0x3) + 1;
2227 mem_trp = ((temp & 0x3)) + 1;
2228 mem_tras = ((temp & 0x70) >> 4) + 1;
2229 } else if (rdev->family == CHIP_R300 ||
2230 rdev->family == CHIP_R350) { /* r300, r350 */
2231 mem_trcd = (temp & 0x7) + 1;
2232 mem_trp = ((temp >> 8) & 0x7) + 1;
2233 mem_tras = ((temp >> 11) & 0xf) + 4;
2234 } else if (rdev->family == CHIP_RV350 ||
2235 rdev->family <= CHIP_RV380) {
2236 /* rv3x0 */
2237 mem_trcd = (temp & 0x7) + 3;
2238 mem_trp = ((temp >> 8) & 0x7) + 3;
2239 mem_tras = ((temp >> 11) & 0xf) + 6;
2240 } else if (rdev->family == CHIP_R420 ||
2241 rdev->family == CHIP_R423 ||
2242 rdev->family == CHIP_RV410) {
2243 /* r4xx */
2244 mem_trcd = (temp & 0xf) + 3;
2245 if (mem_trcd > 15)
2246 mem_trcd = 15;
2247 mem_trp = ((temp >> 8) & 0xf) + 3;
2248 if (mem_trp > 15)
2249 mem_trp = 15;
2250 mem_tras = ((temp >> 12) & 0x1f) + 6;
2251 if (mem_tras > 31)
2252 mem_tras = 31;
2253 } else { /* RV200, R200 */
2254 mem_trcd = (temp & 0x7) + 1;
2255 mem_trp = ((temp >> 8) & 0x7) + 1;
2256 mem_tras = ((temp >> 12) & 0xf) + 4;
2257 }
2258 /* convert to FF */
2259 trcd_ff.full = rfixed_const(mem_trcd);
2260 trp_ff.full = rfixed_const(mem_trp);
2261 tras_ff.full = rfixed_const(mem_tras);
2262
2263 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2264 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2265 data = (temp & (7 << 20)) >> 20;
2266 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2267 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2268 tcas_ff = memtcas_rs480_ff[data];
2269 else
2270 tcas_ff = memtcas_ff[data];
2271 } else
2272 tcas_ff = memtcas2_ff[data];
2273
2274 if (rdev->family == CHIP_RS400 ||
2275 rdev->family == CHIP_RS480) {
2276 /* extra cas latency stored in bits 23-25 0-4 clocks */
2277 data = (temp >> 23) & 0x7;
2278 if (data < 5)
2279 tcas_ff.full += rfixed_const(data);
2280 }
2281
2282 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2283 /* on the R300, Tcas is included in Trbs.
2284 */
2285 temp = RREG32(RADEON_MEM_CNTL);
2286 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2287 if (data == 1) {
2288 if (R300_MEM_USE_CD_CH_ONLY & temp) {
2289 temp = RREG32(R300_MC_IND_INDEX);
2290 temp &= ~R300_MC_IND_ADDR_MASK;
2291 temp |= R300_MC_READ_CNTL_CD_mcind;
2292 WREG32(R300_MC_IND_INDEX, temp);
2293 temp = RREG32(R300_MC_IND_DATA);
2294 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2295 } else {
2296 temp = RREG32(R300_MC_READ_CNTL_AB);
2297 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2298 }
2299 } else {
2300 temp = RREG32(R300_MC_READ_CNTL_AB);
2301 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2302 }
2303 if (rdev->family == CHIP_RV410 ||
2304 rdev->family == CHIP_R420 ||
2305 rdev->family == CHIP_R423)
2306 trbs_ff = memtrbs_r4xx[data];
2307 else
2308 trbs_ff = memtrbs[data];
2309 tcas_ff.full += trbs_ff.full;
2310 }
2311
2312 sclk_eff_ff.full = sclk_ff.full;
2313
2314 if (rdev->flags & RADEON_IS_AGP) {
2315 fixed20_12 agpmode_ff;
2316 agpmode_ff.full = rfixed_const(radeon_agpmode);
2317 temp_ff.full = rfixed_const_666(16);
2318 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
2319 }
2320 /* TODO PCIE lanes may affect this - agpmode == 16?? */
2321
2322 if (ASIC_IS_R300(rdev)) {
2323 sclk_delay_ff.full = rfixed_const(250);
2324 } else {
2325 if ((rdev->family == CHIP_RV100) ||
2326 rdev->flags & RADEON_IS_IGP) {
2327 if (rdev->mc.vram_is_ddr)
2328 sclk_delay_ff.full = rfixed_const(41);
2329 else
2330 sclk_delay_ff.full = rfixed_const(33);
2331 } else {
2332 if (rdev->mc.vram_width == 128)
2333 sclk_delay_ff.full = rfixed_const(57);
2334 else
2335 sclk_delay_ff.full = rfixed_const(41);
2336 }
2337 }
2338
2339 mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
2340
2341 if (rdev->mc.vram_is_ddr) {
2342 if (rdev->mc.vram_width == 32) {
2343 k1.full = rfixed_const(40);
2344 c = 3;
2345 } else {
2346 k1.full = rfixed_const(20);
2347 c = 1;
2348 }
2349 } else {
2350 k1.full = rfixed_const(40);
2351 c = 3;
2352 }
2353
2354 temp_ff.full = rfixed_const(2);
2355 mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
2356 temp_ff.full = rfixed_const(c);
2357 mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
2358 temp_ff.full = rfixed_const(4);
2359 mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
2360 mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
2361 mc_latency_mclk.full += k1.full;
2362
2363 mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
2364 mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
2365
2366 /*
2367 HW cursor time assuming worst case of full size colour cursor.
2368 */
2369 temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2370 temp_ff.full += trcd_ff.full;
2371 if (temp_ff.full < tras_ff.full)
2372 temp_ff.full = tras_ff.full;
2373 cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
2374
2375 temp_ff.full = rfixed_const(cur_size);
2376 cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
2377 /*
2378 Find the total latency for the display data.
2379 */
2380 disp_latency_overhead.full = rfixed_const(8);
2381 disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
2382 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2383 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2384
2385 if (mc_latency_mclk.full > mc_latency_sclk.full)
2386 disp_latency.full = mc_latency_mclk.full;
2387 else
2388 disp_latency.full = mc_latency_sclk.full;
2389
2390 /* setup Max GRPH_STOP_REQ default value */
2391 if (ASIC_IS_RV100(rdev))
2392 max_stop_req = 0x5c;
2393 else
2394 max_stop_req = 0x7c;
2395
2396 if (mode1) {
2397 /* CRTC1
2398 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2399 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2400 */
2401 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2402
2403 if (stop_req > max_stop_req)
2404 stop_req = max_stop_req;
2405
2406 /*
2407 Find the drain rate of the display buffer.
2408 */
2409 temp_ff.full = rfixed_const((16/pixel_bytes1));
2410 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
2411
2412 /*
2413 Find the critical point of the display buffer.
2414 */
2415 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
2416 crit_point_ff.full += rfixed_const_half(0);
2417
2418 critical_point = rfixed_trunc(crit_point_ff);
2419
2420 if (rdev->disp_priority == 2) {
2421 critical_point = 0;
2422 }
2423
2424 /*
2425 The critical point should never be above max_stop_req-4. Setting
2426 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2427 */
2428 if (max_stop_req - critical_point < 4)
2429 critical_point = 0;
2430
2431 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
2432 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2433 critical_point = 0x10;
2434 }
2435
2436 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
2437 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
2438 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2439 temp &= ~(RADEON_GRPH_START_REQ_MASK);
2440 if ((rdev->family == CHIP_R350) &&
2441 (stop_req > 0x15)) {
2442 stop_req -= 0x10;
2443 }
2444 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2445 temp |= RADEON_GRPH_BUFFER_SIZE;
2446 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
2447 RADEON_GRPH_CRITICAL_AT_SOF |
2448 RADEON_GRPH_STOP_CNTL);
2449 /*
2450 Write the result into the register.
2451 */
2452 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2453 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2454
2455 #if 0
2456 if ((rdev->family == CHIP_RS400) ||
2457 (rdev->family == CHIP_RS480)) {
2458 /* attempt to program RS400 disp regs correctly ??? */
2459 temp = RREG32(RS400_DISP1_REG_CNTL);
2460 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
2461 RS400_DISP1_STOP_REQ_LEVEL_MASK);
2462 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
2463 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2464 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2465 temp = RREG32(RS400_DMIF_MEM_CNTL1);
2466 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
2467 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
2468 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
2469 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
2470 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
2471 }
2472 #endif
2473
2474 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
2475 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
2476 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
2477 }
2478
2479 if (mode2) {
2480 u32 grph2_cntl;
2481 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
2482
2483 if (stop_req > max_stop_req)
2484 stop_req = max_stop_req;
2485
2486 /*
2487 Find the drain rate of the display buffer.
2488 */
2489 temp_ff.full = rfixed_const((16/pixel_bytes2));
2490 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
2491
2492 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
2493 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
2494 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2495 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
2496 if ((rdev->family == CHIP_R350) &&
2497 (stop_req > 0x15)) {
2498 stop_req -= 0x10;
2499 }
2500 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2501 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
2502 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
2503 RADEON_GRPH_CRITICAL_AT_SOF |
2504 RADEON_GRPH_STOP_CNTL);
2505
2506 if ((rdev->family == CHIP_RS100) ||
2507 (rdev->family == CHIP_RS200))
2508 critical_point2 = 0;
2509 else {
2510 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
2511 temp_ff.full = rfixed_const(temp);
2512 temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
2513 if (sclk_ff.full < temp_ff.full)
2514 temp_ff.full = sclk_ff.full;
2515
2516 read_return_rate.full = temp_ff.full;
2517
2518 if (mode1) {
2519 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
2520 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
2521 } else {
2522 time_disp1_drop_priority.full = 0;
2523 }
2524 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
2525 crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
2526 crit_point_ff.full += rfixed_const_half(0);
2527
2528 critical_point2 = rfixed_trunc(crit_point_ff);
2529
2530 if (rdev->disp_priority == 2) {
2531 critical_point2 = 0;
2532 }
2533
2534 if (max_stop_req - critical_point2 < 4)
2535 critical_point2 = 0;
2536
2537 }
2538
2539 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
2540 /* some R300 cards have problem with this set to 0 */
2541 critical_point2 = 0x10;
2542 }
2543
2544 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2545 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2546
2547 if ((rdev->family == CHIP_RS400) ||
2548 (rdev->family == CHIP_RS480)) {
2549 #if 0
2550 /* attempt to program RS400 disp2 regs correctly ??? */
2551 temp = RREG32(RS400_DISP2_REQ_CNTL1);
2552 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
2553 RS400_DISP2_STOP_REQ_LEVEL_MASK);
2554 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
2555 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2556 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2557 temp = RREG32(RS400_DISP2_REQ_CNTL2);
2558 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
2559 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
2560 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
2561 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
2562 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
2563 #endif
2564 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
2565 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
2566 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
2567 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
2568 }
2569
2570 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
2571 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
2572 }
2573 }
2574
2575 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2576 {
2577 DRM_ERROR("pitch %d\n", t->pitch);
2578 DRM_ERROR("use_pitch %d\n", t->use_pitch);
2579 DRM_ERROR("width %d\n", t->width);
2580 DRM_ERROR("width_11 %d\n", t->width_11);
2581 DRM_ERROR("height %d\n", t->height);
2582 DRM_ERROR("height_11 %d\n", t->height_11);
2583 DRM_ERROR("num levels %d\n", t->num_levels);
2584 DRM_ERROR("depth %d\n", t->txdepth);
2585 DRM_ERROR("bpp %d\n", t->cpp);
2586 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2587 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2588 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2589 }
2590
2591 static int r100_cs_track_cube(struct radeon_device *rdev,
2592 struct r100_cs_track *track, unsigned idx)
2593 {
2594 unsigned face, w, h;
2595 struct radeon_object *cube_robj;
2596 unsigned long size;
2597
2598 for (face = 0; face < 5; face++) {
2599 cube_robj = track->textures[idx].cube_info[face].robj;
2600 w = track->textures[idx].cube_info[face].width;
2601 h = track->textures[idx].cube_info[face].height;
2602
2603 size = w * h;
2604 size *= track->textures[idx].cpp;
2605
2606 size += track->textures[idx].cube_info[face].offset;
2607
2608 if (size > radeon_object_size(cube_robj)) {
2609 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2610 size, radeon_object_size(cube_robj));
2611 r100_cs_track_texture_print(&track->textures[idx]);
2612 return -1;
2613 }
2614 }
2615 return 0;
2616 }
2617
2618 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2619 struct r100_cs_track *track)
2620 {
2621 struct radeon_object *robj;
2622 unsigned long size;
2623 unsigned u, i, w, h;
2624 int ret;
2625
2626 for (u = 0; u < track->num_texture; u++) {
2627 if (!track->textures[u].enabled)
2628 continue;
2629 robj = track->textures[u].robj;
2630 if (robj == NULL) {
2631 DRM_ERROR("No texture bound to unit %u\n", u);
2632 return -EINVAL;
2633 }
2634 size = 0;
2635 for (i = 0; i <= track->textures[u].num_levels; i++) {
2636 if (track->textures[u].use_pitch) {
2637 if (rdev->family < CHIP_R300)
2638 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2639 else
2640 w = track->textures[u].pitch / (1 << i);
2641 } else {
2642 w = track->textures[u].width;
2643 if (rdev->family >= CHIP_RV515)
2644 w |= track->textures[u].width_11;
2645 w = w / (1 << i);
2646 if (track->textures[u].roundup_w)
2647 w = roundup_pow_of_two(w);
2648 }
2649 h = track->textures[u].height;
2650 if (rdev->family >= CHIP_RV515)
2651 h |= track->textures[u].height_11;
2652 h = h / (1 << i);
2653 if (track->textures[u].roundup_h)
2654 h = roundup_pow_of_two(h);
2655 size += w * h;
2656 }
2657 size *= track->textures[u].cpp;
2658 switch (track->textures[u].tex_coord_type) {
2659 case 0:
2660 break;
2661 case 1:
2662 size *= (1 << track->textures[u].txdepth);
2663 break;
2664 case 2:
2665 if (track->separate_cube) {
2666 ret = r100_cs_track_cube(rdev, track, u);
2667 if (ret)
2668 return ret;
2669 } else
2670 size *= 6;
2671 break;
2672 default:
2673 DRM_ERROR("Invalid texture coordinate type %u for unit "
2674 "%u\n", track->textures[u].tex_coord_type, u);
2675 return -EINVAL;
2676 }
2677 if (size > radeon_object_size(robj)) {
2678 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2679 "%lu\n", u, size, radeon_object_size(robj));
2680 r100_cs_track_texture_print(&track->textures[u]);
2681 return -EINVAL;
2682 }
2683 }
2684 return 0;
2685 }
2686
2687 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2688 {
2689 unsigned i;
2690 unsigned long size;
2691 unsigned prim_walk;
2692 unsigned nverts;
2693
2694 for (i = 0; i < track->num_cb; i++) {
2695 if (track->cb[i].robj == NULL) {
2696 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2697 return -EINVAL;
2698 }
2699 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2700 size += track->cb[i].offset;
2701 if (size > radeon_object_size(track->cb[i].robj)) {
2702 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2703 "(need %lu have %lu) !\n", i, size,
2704 radeon_object_size(track->cb[i].robj));
2705 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2706 i, track->cb[i].pitch, track->cb[i].cpp,
2707 track->cb[i].offset, track->maxy);
2708 return -EINVAL;
2709 }
2710 }
2711 if (track->z_enabled) {
2712 if (track->zb.robj == NULL) {
2713 DRM_ERROR("[drm] No buffer for z buffer !\n");
2714 return -EINVAL;
2715 }
2716 size = track->zb.pitch * track->zb.cpp * track->maxy;
2717 size += track->zb.offset;
2718 if (size > radeon_object_size(track->zb.robj)) {
2719 DRM_ERROR("[drm] Buffer too small for z buffer "
2720 "(need %lu have %lu) !\n", size,
2721 radeon_object_size(track->zb.robj));
2722 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2723 track->zb.pitch, track->zb.cpp,
2724 track->zb.offset, track->maxy);
2725 return -EINVAL;
2726 }
2727 }
2728 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2729 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2730 switch (prim_walk) {
2731 case 1:
2732 for (i = 0; i < track->num_arrays; i++) {
2733 size = track->arrays[i].esize * track->max_indx * 4;
2734 if (track->arrays[i].robj == NULL) {
2735 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2736 "bound\n", prim_walk, i);
2737 return -EINVAL;
2738 }
2739 if (size > radeon_object_size(track->arrays[i].robj)) {
2740 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
2741 "have %lu dwords\n", prim_walk, i,
2742 size >> 2,
2743 radeon_object_size(track->arrays[i].robj) >> 2);
2744 DRM_ERROR("Max indices %u\n", track->max_indx);
2745 return -EINVAL;
2746 }
2747 }
2748 break;
2749 case 2:
2750 for (i = 0; i < track->num_arrays; i++) {
2751 size = track->arrays[i].esize * (nverts - 1) * 4;
2752 if (track->arrays[i].robj == NULL) {
2753 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2754 "bound\n", prim_walk, i);
2755 return -EINVAL;
2756 }
2757 if (size > radeon_object_size(track->arrays[i].robj)) {
2758 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
2759 "have %lu dwords\n", prim_walk, i, size >> 2,
2760 radeon_object_size(track->arrays[i].robj) >> 2);
2761 return -EINVAL;
2762 }
2763 }
2764 break;
2765 case 3:
2766 size = track->vtx_size * nverts;
2767 if (size != track->immd_dwords) {
2768 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2769 track->immd_dwords, size);
2770 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2771 nverts, track->vtx_size);
2772 return -EINVAL;
2773 }
2774 break;
2775 default:
2776 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2777 prim_walk);
2778 return -EINVAL;
2779 }
2780 return r100_cs_track_texture_check(rdev, track);
2781 }
2782
2783 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2784 {
2785 unsigned i, face;
2786
2787 if (rdev->family < CHIP_R300) {
2788 track->num_cb = 1;
2789 if (rdev->family <= CHIP_RS200)
2790 track->num_texture = 3;
2791 else
2792 track->num_texture = 6;
2793 track->maxy = 2048;
2794 track->separate_cube = 1;
2795 } else {
2796 track->num_cb = 4;
2797 track->num_texture = 16;
2798 track->maxy = 4096;
2799 track->separate_cube = 0;
2800 }
2801
2802 for (i = 0; i < track->num_cb; i++) {
2803 track->cb[i].robj = NULL;
2804 track->cb[i].pitch = 8192;
2805 track->cb[i].cpp = 16;
2806 track->cb[i].offset = 0;
2807 }
2808 track->z_enabled = true;
2809 track->zb.robj = NULL;
2810 track->zb.pitch = 8192;
2811 track->zb.cpp = 4;
2812 track->zb.offset = 0;
2813 track->vtx_size = 0x7F;
2814 track->immd_dwords = 0xFFFFFFFFUL;
2815 track->num_arrays = 11;
2816 track->max_indx = 0x00FFFFFFUL;
2817 for (i = 0; i < track->num_arrays; i++) {
2818 track->arrays[i].robj = NULL;
2819 track->arrays[i].esize = 0x7F;
2820 }
2821 for (i = 0; i < track->num_texture; i++) {
2822 track->textures[i].pitch = 16536;
2823 track->textures[i].width = 16536;
2824 track->textures[i].height = 16536;
2825 track->textures[i].width_11 = 1 << 11;
2826 track->textures[i].height_11 = 1 << 11;
2827 track->textures[i].num_levels = 12;
2828 if (rdev->family <= CHIP_RS200) {
2829 track->textures[i].tex_coord_type = 0;
2830 track->textures[i].txdepth = 0;
2831 } else {
2832 track->textures[i].txdepth = 16;
2833 track->textures[i].tex_coord_type = 1;
2834 }
2835 track->textures[i].cpp = 64;
2836 track->textures[i].robj = NULL;
2837 /* CS IB emission code makes sure texture unit are disabled */
2838 track->textures[i].enabled = false;
2839 track->textures[i].roundup_w = true;
2840 track->textures[i].roundup_h = true;
2841 if (track->separate_cube)
2842 for (face = 0; face < 5; face++) {
2843 track->textures[i].cube_info[face].robj = NULL;
2844 track->textures[i].cube_info[face].width = 16536;
2845 track->textures[i].cube_info[face].height = 16536;
2846 track->textures[i].cube_info[face].offset = 0;
2847 }
2848 }
2849 }
2850
2851 int r100_ring_test(struct radeon_device *rdev)
2852 {
2853 uint32_t scratch;
2854 uint32_t tmp = 0;
2855 unsigned i;
2856 int r;
2857
2858 r = radeon_scratch_get(rdev, &scratch);
2859 if (r) {
2860 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2861 return r;
2862 }
2863 WREG32(scratch, 0xCAFEDEAD);
2864 r = radeon_ring_lock(rdev, 2);
2865 if (r) {
2866 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2867 radeon_scratch_free(rdev, scratch);
2868 return r;
2869 }
2870 radeon_ring_write(rdev, PACKET0(scratch, 0));
2871 radeon_ring_write(rdev, 0xDEADBEEF);
2872 radeon_ring_unlock_commit(rdev);
2873 for (i = 0; i < rdev->usec_timeout; i++) {
2874 tmp = RREG32(scratch);
2875 if (tmp == 0xDEADBEEF) {
2876 break;
2877 }
2878 DRM_UDELAY(1);
2879 }
2880 if (i < rdev->usec_timeout) {
2881 DRM_INFO("ring test succeeded in %d usecs\n", i);
2882 } else {
2883 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
2884 scratch, tmp);
2885 r = -EINVAL;
2886 }
2887 radeon_scratch_free(rdev, scratch);
2888 return r;
2889 }
2890
2891 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2892 {
2893 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
2894 radeon_ring_write(rdev, ib->gpu_addr);
2895 radeon_ring_write(rdev, ib->length_dw);
2896 }
2897
2898 int r100_ib_test(struct radeon_device *rdev)
2899 {
2900 struct radeon_ib *ib;
2901 uint32_t scratch;
2902 uint32_t tmp = 0;
2903 unsigned i;
2904 int r;
2905
2906 r = radeon_scratch_get(rdev, &scratch);
2907 if (r) {
2908 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2909 return r;
2910 }
2911 WREG32(scratch, 0xCAFEDEAD);
2912 r = radeon_ib_get(rdev, &ib);
2913 if (r) {
2914 return r;
2915 }
2916 ib->ptr[0] = PACKET0(scratch, 0);
2917 ib->ptr[1] = 0xDEADBEEF;
2918 ib->ptr[2] = PACKET2(0);
2919 ib->ptr[3] = PACKET2(0);
2920 ib->ptr[4] = PACKET2(0);
2921 ib->ptr[5] = PACKET2(0);
2922 ib->ptr[6] = PACKET2(0);
2923 ib->ptr[7] = PACKET2(0);
2924 ib->length_dw = 8;
2925 r = radeon_ib_schedule(rdev, ib);
2926 if (r) {
2927 radeon_scratch_free(rdev, scratch);
2928 radeon_ib_free(rdev, &ib);
2929 return r;
2930 }
2931 r = radeon_fence_wait(ib->fence, false);
2932 if (r) {
2933 return r;
2934 }
2935 for (i = 0; i < rdev->usec_timeout; i++) {
2936 tmp = RREG32(scratch);
2937 if (tmp == 0xDEADBEEF) {
2938 break;
2939 }
2940 DRM_UDELAY(1);
2941 }
2942 if (i < rdev->usec_timeout) {
2943 DRM_INFO("ib test succeeded in %u usecs\n", i);
2944 } else {
2945 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
2946 scratch, tmp);
2947 r = -EINVAL;
2948 }
2949 radeon_scratch_free(rdev, scratch);
2950 radeon_ib_free(rdev, &ib);
2951 return r;
2952 }
2953
2954 void r100_ib_fini(struct radeon_device *rdev)
2955 {
2956 radeon_ib_pool_fini(rdev);
2957 }
2958
2959 int r100_ib_init(struct radeon_device *rdev)
2960 {
2961 int r;
2962
2963 r = radeon_ib_pool_init(rdev);
2964 if (r) {
2965 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
2966 r100_ib_fini(rdev);
2967 return r;
2968 }
2969 r = r100_ib_test(rdev);
2970 if (r) {
2971 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
2972 r100_ib_fini(rdev);
2973 return r;
2974 }
2975 return 0;
2976 }
2977
2978 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
2979 {
2980 /* Shutdown CP we shouldn't need to do that but better be safe than
2981 * sorry
2982 */
2983 rdev->cp.ready = false;
2984 WREG32(R_000740_CP_CSQ_CNTL, 0);
2985
2986 /* Save few CRTC registers */
2987 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
2988 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
2989 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
2990 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
2991 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2992 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
2993 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
2994 }
2995
2996 /* Disable VGA aperture access */
2997 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
2998 /* Disable cursor, overlay, crtc */
2999 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3000 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3001 S_000054_CRTC_DISPLAY_DIS(1));
3002 WREG32(R_000050_CRTC_GEN_CNTL,
3003 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3004 S_000050_CRTC_DISP_REQ_EN_B(1));
3005 WREG32(R_000420_OV0_SCALE_CNTL,
3006 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3007 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3008 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3009 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3010 S_000360_CUR2_LOCK(1));
3011 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3012 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3013 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3014 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3015 WREG32(R_000360_CUR2_OFFSET,
3016 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3017 }
3018 }
3019
3020 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3021 {
3022 /* Update base address for crtc */
3023 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_location);
3024 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3025 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR,
3026 rdev->mc.vram_location);
3027 }
3028 /* Restore CRTC registers */
3029 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3030 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3031 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3032 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3033 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3034 }
3035 }
3036
3037 void r100_vga_render_disable(struct radeon_device *rdev)
3038 {
3039 u32 tmp;
3040
3041 tmp = RREG8(R_0003C2_GENMO_WT);
3042 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3043 }
3044
3045 static void r100_debugfs(struct radeon_device *rdev)
3046 {
3047 int r;
3048
3049 r = r100_debugfs_mc_info_init(rdev);
3050 if (r)
3051 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3052 }
3053
3054 static void r100_mc_program(struct radeon_device *rdev)
3055 {
3056 struct r100_mc_save save;
3057
3058 /* Stops all mc clients */
3059 r100_mc_stop(rdev, &save);
3060 if (rdev->flags & RADEON_IS_AGP) {
3061 WREG32(R_00014C_MC_AGP_LOCATION,
3062 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3063 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3064 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3065 if (rdev->family > CHIP_RV200)
3066 WREG32(R_00015C_AGP_BASE_2,
3067 upper_32_bits(rdev->mc.agp_base) & 0xff);
3068 } else {
3069 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3070 WREG32(R_000170_AGP_BASE, 0);
3071 if (rdev->family > CHIP_RV200)
3072 WREG32(R_00015C_AGP_BASE_2, 0);
3073 }
3074 /* Wait for mc idle */
3075 if (r100_mc_wait_for_idle(rdev))
3076 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3077 /* Program MC, should be a 32bits limited address space */
3078 WREG32(R_000148_MC_FB_LOCATION,
3079 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3080 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3081 r100_mc_resume(rdev, &save);
3082 }
3083
3084 void r100_clock_startup(struct radeon_device *rdev)
3085 {
3086 u32 tmp;
3087
3088 if (radeon_dynclks != -1 && radeon_dynclks)
3089 radeon_legacy_set_clock_gating(rdev, 1);
3090 /* We need to force on some of the block */
3091 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3092 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3093 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3094 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3095 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3096 }
3097
3098 static int r100_startup(struct radeon_device *rdev)
3099 {
3100 int r;
3101
3102 r100_mc_program(rdev);
3103 /* Resume clock */
3104 r100_clock_startup(rdev);
3105 /* Initialize GPU configuration (# pipes, ...) */
3106 r100_gpu_init(rdev);
3107 /* Initialize GART (initialize after TTM so we can allocate
3108 * memory through TTM but finalize after TTM) */
3109 if (rdev->flags & RADEON_IS_PCI) {
3110 r = r100_pci_gart_enable(rdev);
3111 if (r)
3112 return r;
3113 }
3114 /* Enable IRQ */
3115 rdev->irq.sw_int = true;
3116 r100_irq_set(rdev);
3117 /* 1M ring buffer */
3118 r = r100_cp_init(rdev, 1024 * 1024);
3119 if (r) {
3120 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3121 return r;
3122 }
3123 r = r100_wb_init(rdev);
3124 if (r)
3125 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
3126 r = r100_ib_init(rdev);
3127 if (r) {
3128 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3129 return r;
3130 }
3131 return 0;
3132 }
3133
3134 int r100_resume(struct radeon_device *rdev)
3135 {
3136 /* Make sur GART are not working */
3137 if (rdev->flags & RADEON_IS_PCI)
3138 r100_pci_gart_disable(rdev);
3139 /* Resume clock before doing reset */
3140 r100_clock_startup(rdev);
3141 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3142 if (radeon_gpu_reset(rdev)) {
3143 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3144 RREG32(R_000E40_RBBM_STATUS),
3145 RREG32(R_0007C0_CP_STAT));
3146 }
3147 /* post */
3148 radeon_combios_asic_init(rdev->ddev);
3149 /* Resume clock after posting */
3150 r100_clock_startup(rdev);
3151 return r100_startup(rdev);
3152 }
3153
3154 int r100_suspend(struct radeon_device *rdev)
3155 {
3156 r100_cp_disable(rdev);
3157 r100_wb_disable(rdev);
3158 r100_irq_disable(rdev);
3159 if (rdev->flags & RADEON_IS_PCI)
3160 r100_pci_gart_disable(rdev);
3161 return 0;
3162 }
3163
3164 void r100_fini(struct radeon_device *rdev)
3165 {
3166 r100_suspend(rdev);
3167 r100_cp_fini(rdev);
3168 r100_wb_fini(rdev);
3169 r100_ib_fini(rdev);
3170 radeon_gem_fini(rdev);
3171 if (rdev->flags & RADEON_IS_PCI)
3172 r100_pci_gart_fini(rdev);
3173 radeon_irq_kms_fini(rdev);
3174 radeon_fence_driver_fini(rdev);
3175 radeon_object_fini(rdev);
3176 radeon_atombios_fini(rdev);
3177 kfree(rdev->bios);
3178 rdev->bios = NULL;
3179 }
3180
3181 int r100_mc_init(struct radeon_device *rdev)
3182 {
3183 int r;
3184 u32 tmp;
3185
3186 /* Setup GPU memory space */
3187 rdev->mc.vram_location = 0xFFFFFFFFUL;
3188 rdev->mc.gtt_location = 0xFFFFFFFFUL;
3189 if (rdev->flags & RADEON_IS_IGP) {
3190 tmp = G_00015C_MC_FB_START(RREG32(R_00015C_NB_TOM));
3191 rdev->mc.vram_location = tmp << 16;
3192 }
3193 if (rdev->flags & RADEON_IS_AGP) {
3194 r = radeon_agp_init(rdev);
3195 if (r) {
3196 printk(KERN_WARNING "[drm] Disabling AGP\n");
3197 rdev->flags &= ~RADEON_IS_AGP;
3198 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
3199 } else {
3200 rdev->mc.gtt_location = rdev->mc.agp_base;
3201 }
3202 }
3203 r = radeon_mc_setup(rdev);
3204 if (r)
3205 return r;
3206 return 0;
3207 }
3208
3209 int r100_init(struct radeon_device *rdev)
3210 {
3211 int r;
3212
3213 /* Register debugfs file specific to this group of asics */
3214 r100_debugfs(rdev);
3215 /* Disable VGA */
3216 r100_vga_render_disable(rdev);
3217 /* Initialize scratch registers */
3218 radeon_scratch_init(rdev);
3219 /* Initialize surface registers */
3220 radeon_surface_init(rdev);
3221 /* TODO: disable VGA need to use VGA request */
3222 /* BIOS*/
3223 if (!radeon_get_bios(rdev)) {
3224 if (ASIC_IS_AVIVO(rdev))
3225 return -EINVAL;
3226 }
3227 if (rdev->is_atom_bios) {
3228 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3229 return -EINVAL;
3230 } else {
3231 r = radeon_combios_init(rdev);
3232 if (r)
3233 return r;
3234 }
3235 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3236 if (radeon_gpu_reset(rdev)) {
3237 dev_warn(rdev->dev,
3238 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3239 RREG32(R_000E40_RBBM_STATUS),
3240 RREG32(R_0007C0_CP_STAT));
3241 }
3242 /* check if cards are posted or not */
3243 if (!radeon_card_posted(rdev) && rdev->bios) {
3244 DRM_INFO("GPU not posted. posting now...\n");
3245 radeon_combios_asic_init(rdev->ddev);
3246 }
3247 /* Set asic errata */
3248 r100_errata(rdev);
3249 /* Initialize clocks */
3250 radeon_get_clock_info(rdev->ddev);
3251 /* Get vram informations */
3252 r100_vram_info(rdev);
3253 /* Initialize memory controller (also test AGP) */
3254 r = r100_mc_init(rdev);
3255 if (r)
3256 return r;
3257 /* Fence driver */
3258 r = radeon_fence_driver_init(rdev);
3259 if (r)
3260 return r;
3261 r = radeon_irq_kms_init(rdev);
3262 if (r)
3263 return r;
3264 /* Memory manager */
3265 r = radeon_object_init(rdev);
3266 if (r)
3267 return r;
3268 if (rdev->flags & RADEON_IS_PCI) {
3269 r = r100_pci_gart_init(rdev);
3270 if (r)
3271 return r;
3272 }
3273 r100_set_safe_registers(rdev);
3274 rdev->accel_working = true;
3275 r = r100_startup(rdev);
3276 if (r) {
3277 /* Somethings want wront with the accel init stop accel */
3278 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3279 r100_suspend(rdev);
3280 r100_cp_fini(rdev);
3281 r100_wb_fini(rdev);
3282 r100_ib_fini(rdev);
3283 if (rdev->flags & RADEON_IS_PCI)
3284 r100_pci_gart_fini(rdev);
3285 radeon_irq_kms_fini(rdev);
3286 rdev->accel_working = false;
3287 }
3288 return 0;
3289 }
Linux ARM platform port for MOXA ART SoC