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initial commit with v2.6.32.60
[linux-2.6.32.60-moxart.git] / drivers / mmc / host / sdhci.c
blobe6c65a78c46cc21a14cb4a903ba0a60b1c63010d
1 /*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/io.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/scatterlist.h>
21
22 #include <linux/leds.h>
23
24 #include <linux/mmc/host.h>
25
26 #include "sdhci.h"
27
28 #define DRIVER_NAME "sdhci"
29
30 #define DBG(f, x...) \
31 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
32
33 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
34 defined(CONFIG_MMC_SDHCI_MODULE))
35 #define SDHCI_USE_LEDS_CLASS
36 #endif
37
38 static unsigned int debug_quirks = 0;
39
40 static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
41 static void sdhci_finish_data(struct sdhci_host *);
42
43 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
44 static void sdhci_finish_command(struct sdhci_host *);
45
46 static void sdhci_dumpregs(struct sdhci_host *host)
47 {
48 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
49
50 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
51 sdhci_readl(host, SDHCI_DMA_ADDRESS),
52 sdhci_readw(host, SDHCI_HOST_VERSION));
53 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
54 sdhci_readw(host, SDHCI_BLOCK_SIZE),
55 sdhci_readw(host, SDHCI_BLOCK_COUNT));
56 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
57 sdhci_readl(host, SDHCI_ARGUMENT),
58 sdhci_readw(host, SDHCI_TRANSFER_MODE));
59 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
60 sdhci_readl(host, SDHCI_PRESENT_STATE),
61 sdhci_readb(host, SDHCI_HOST_CONTROL));
62 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
63 sdhci_readb(host, SDHCI_POWER_CONTROL),
64 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
65 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
66 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
67 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
68 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
69 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
70 sdhci_readl(host, SDHCI_INT_STATUS));
71 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
72 sdhci_readl(host, SDHCI_INT_ENABLE),
73 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
74 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
75 sdhci_readw(host, SDHCI_ACMD12_ERR),
76 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
77 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
78 sdhci_readl(host, SDHCI_CAPABILITIES),
79 sdhci_readl(host, SDHCI_MAX_CURRENT));
80
81 if (host->flags & SDHCI_USE_ADMA)
82 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
83 readl(host->ioaddr + SDHCI_ADMA_ERROR),
84 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
85
86 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
87 }
88
89 /*****************************************************************************\
90 * *
91 * Low level functions *
92 * *
93 \*****************************************************************************/
94
95 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
96 {
97 u32 ier;
98
99 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
100 ier &= ~clear;
101 ier |= set;
102 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
103 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
104 }
105
106 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
107 {
108 sdhci_clear_set_irqs(host, 0, irqs);
109 }
110
111 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
112 {
113 sdhci_clear_set_irqs(host, irqs, 0);
114 }
115
116 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
117 {
118 u32 irqs = SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
119
120 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
121 return;
122
123 if (enable)
124 sdhci_unmask_irqs(host, irqs);
125 else
126 sdhci_mask_irqs(host, irqs);
127 }
128
129 static void sdhci_enable_card_detection(struct sdhci_host *host)
130 {
131 sdhci_set_card_detection(host, true);
132 }
133
134 static void sdhci_disable_card_detection(struct sdhci_host *host)
135 {
136 sdhci_set_card_detection(host, false);
137 }
138
139 static void sdhci_reset(struct sdhci_host *host, u8 mask)
140 {
141 unsigned long timeout;
142 u32 uninitialized_var(ier);
143
144 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
145 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
146 SDHCI_CARD_PRESENT))
147 return;
148 }
149
150 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
151 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
152
153 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
154
155 if (mask & SDHCI_RESET_ALL)
156 host->clock = 0;
157
158 /* Wait max 100 ms */
159 timeout = 100;
160
161 /* hw clears the bit when it's done */
162 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
163 if (timeout == 0) {
164 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
165 mmc_hostname(host->mmc), (int)mask);
166 sdhci_dumpregs(host);
167 return;
168 }
169 timeout--;
170 mdelay(1);
171 }
172
173 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
174 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
175 }
176
177 static void sdhci_init(struct sdhci_host *host)
178 {
179 sdhci_reset(host, SDHCI_RESET_ALL);
180
181 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
182 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
183 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
184 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
185 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
186 }
187
188 static void sdhci_reinit(struct sdhci_host *host)
189 {
190 sdhci_init(host);
191 sdhci_enable_card_detection(host);
192 }
193
194 static void sdhci_activate_led(struct sdhci_host *host)
195 {
196 u8 ctrl;
197
198 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
199 ctrl |= SDHCI_CTRL_LED;
200 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
201 }
202
203 static void sdhci_deactivate_led(struct sdhci_host *host)
204 {
205 u8 ctrl;
206
207 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
208 ctrl &= ~SDHCI_CTRL_LED;
209 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
210 }
211
212 #ifdef SDHCI_USE_LEDS_CLASS
213 static void sdhci_led_control(struct led_classdev *led,
214 enum led_brightness brightness)
215 {
216 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
217 unsigned long flags;
218
219 spin_lock_irqsave(&host->lock, flags);
220
221 if (brightness == LED_OFF)
222 sdhci_deactivate_led(host);
223 else
224 sdhci_activate_led(host);
225
226 spin_unlock_irqrestore(&host->lock, flags);
227 }
228 #endif
229
230 /*****************************************************************************\
231 * *
232 * Core functions *
233 * *
234 \*****************************************************************************/
235
236 static void sdhci_read_block_pio(struct sdhci_host *host)
237 {
238 unsigned long flags;
239 size_t blksize, len, chunk;
240 u32 uninitialized_var(scratch);
241 u8 *buf;
242
243 DBG("PIO reading\n");
244
245 blksize = host->data->blksz;
246 chunk = 0;
247
248 local_irq_save(flags);
249
250 while (blksize) {
251 if (!sg_miter_next(&host->sg_miter))
252 BUG();
253
254 len = min(host->sg_miter.length, blksize);
255
256 blksize -= len;
257 host->sg_miter.consumed = len;
258
259 buf = host->sg_miter.addr;
260
261 while (len) {
262 if (chunk == 0) {
263 scratch = sdhci_readl(host, SDHCI_BUFFER);
264 chunk = 4;
265 }
266
267 *buf = scratch & 0xFF;
268
269 buf++;
270 scratch >>= 8;
271 chunk--;
272 len--;
273 }
274 }
275
276 sg_miter_stop(&host->sg_miter);
277
278 local_irq_restore(flags);
279 }
280
281 static void sdhci_write_block_pio(struct sdhci_host *host)
282 {
283 unsigned long flags;
284 size_t blksize, len, chunk;
285 u32 scratch;
286 u8 *buf;
287
288 DBG("PIO writing\n");
289
290 blksize = host->data->blksz;
291 chunk = 0;
292 scratch = 0;
293
294 local_irq_save(flags);
295
296 while (blksize) {
297 if (!sg_miter_next(&host->sg_miter))
298 BUG();
299
300 len = min(host->sg_miter.length, blksize);
301
302 blksize -= len;
303 host->sg_miter.consumed = len;
304
305 buf = host->sg_miter.addr;
306
307 while (len) {
308 scratch |= (u32)*buf << (chunk * 8);
309
310 buf++;
311 chunk++;
312 len--;
313
314 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
315 sdhci_writel(host, scratch, SDHCI_BUFFER);
316 chunk = 0;
317 scratch = 0;
318 }
319 }
320 }
321
322 sg_miter_stop(&host->sg_miter);
323
324 local_irq_restore(flags);
325 }
326
327 static void sdhci_transfer_pio(struct sdhci_host *host)
328 {
329 u32 mask;
330
331 BUG_ON(!host->data);
332
333 if (host->blocks == 0)
334 return;
335
336 if (host->data->flags & MMC_DATA_READ)
337 mask = SDHCI_DATA_AVAILABLE;
338 else
339 mask = SDHCI_SPACE_AVAILABLE;
340
341 /*
342 * Some controllers (JMicron JMB38x) mess up the buffer bits
343 * for transfers < 4 bytes. As long as it is just one block,
344 * we can ignore the bits.
345 */
346 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
347 (host->data->blocks == 1))
348 mask = ~0;
349
350 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
351 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
352 udelay(100);
353
354 if (host->data->flags & MMC_DATA_READ)
355 sdhci_read_block_pio(host);
356 else
357 sdhci_write_block_pio(host);
358
359 host->blocks--;
360 if (host->blocks == 0)
361 break;
362 }
363
364 DBG("PIO transfer complete.\n");
365 }
366
367 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
368 {
369 local_irq_save(*flags);
370 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
371 }
372
373 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
374 {
375 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
376 local_irq_restore(*flags);
377 }
378
379 static int sdhci_adma_table_pre(struct sdhci_host *host,
380 struct mmc_data *data)
381 {
382 int direction;
383
384 u8 *desc;
385 u8 *align;
386 dma_addr_t addr;
387 dma_addr_t align_addr;
388 int len, offset;
389
390 struct scatterlist *sg;
391 int i;
392 char *buffer;
393 unsigned long flags;
394
395 /*
396 * The spec does not specify endianness of descriptor table.
397 * We currently guess that it is LE.
398 */
399
400 if (data->flags & MMC_DATA_READ)
401 direction = DMA_FROM_DEVICE;
402 else
403 direction = DMA_TO_DEVICE;
404
405 /*
406 * The ADMA descriptor table is mapped further down as we
407 * need to fill it with data first.
408 */
409
410 host->align_addr = dma_map_single(mmc_dev(host->mmc),
411 host->align_buffer, 128 * 4, direction);
412 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
413 goto fail;
414 BUG_ON(host->align_addr & 0x3);
415
416 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
417 data->sg, data->sg_len, direction);
418 if (host->sg_count == 0)
419 goto unmap_align;
420
421 desc = host->adma_desc;
422 align = host->align_buffer;
423
424 align_addr = host->align_addr;
425
426 for_each_sg(data->sg, sg, host->sg_count, i) {
427 addr = sg_dma_address(sg);
428 len = sg_dma_len(sg);
429
430 /*
431 * The SDHCI specification states that ADMA
432 * addresses must be 32-bit aligned. If they
433 * aren't, then we use a bounce buffer for
434 * the (up to three) bytes that screw up the
435 * alignment.
436 */
437 offset = (4 - (addr & 0x3)) & 0x3;
438 if (offset) {
439 if (data->flags & MMC_DATA_WRITE) {
440 buffer = sdhci_kmap_atomic(sg, &flags);
441 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
442 memcpy(align, buffer, offset);
443 sdhci_kunmap_atomic(buffer, &flags);
444 }
445
446 desc[7] = (align_addr >> 24) & 0xff;
447 desc[6] = (align_addr >> 16) & 0xff;
448 desc[5] = (align_addr >> 8) & 0xff;
449 desc[4] = (align_addr >> 0) & 0xff;
450
451 BUG_ON(offset > 65536);
452
453 desc[3] = (offset >> 8) & 0xff;
454 desc[2] = (offset >> 0) & 0xff;
455
456 desc[1] = 0x00;
457 desc[0] = 0x21; /* tran, valid */
458
459 align += 4;
460 align_addr += 4;
461
462 desc += 8;
463
464 addr += offset;
465 len -= offset;
466 }
467
468 desc[7] = (addr >> 24) & 0xff;
469 desc[6] = (addr >> 16) & 0xff;
470 desc[5] = (addr >> 8) & 0xff;
471 desc[4] = (addr >> 0) & 0xff;
472
473 BUG_ON(len > 65536);
474
475 desc[3] = (len >> 8) & 0xff;
476 desc[2] = (len >> 0) & 0xff;
477
478 desc[1] = 0x00;
479 desc[0] = 0x21; /* tran, valid */
480
481 desc += 8;
482
483 /*
484 * If this triggers then we have a calculation bug
485 * somewhere. :/
486 */
487 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
488 }
489
490 /*
491 * Add a terminating entry.
492 */
493 desc[7] = 0;
494 desc[6] = 0;
495 desc[5] = 0;
496 desc[4] = 0;
497
498 desc[3] = 0;
499 desc[2] = 0;
500
501 desc[1] = 0x00;
502 desc[0] = 0x03; /* nop, end, valid */
503
504 /*
505 * Resync align buffer as we might have changed it.
506 */
507 if (data->flags & MMC_DATA_WRITE) {
508 dma_sync_single_for_device(mmc_dev(host->mmc),
509 host->align_addr, 128 * 4, direction);
510 }
511
512 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
513 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
514 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
515 goto unmap_entries;
516 BUG_ON(host->adma_addr & 0x3);
517
518 return 0;
519
520 unmap_entries:
521 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
522 data->sg_len, direction);
523 unmap_align:
524 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
525 128 * 4, direction);
526 fail:
527 return -EINVAL;
528 }
529
530 static void sdhci_adma_table_post(struct sdhci_host *host,
531 struct mmc_data *data)
532 {
533 int direction;
534
535 struct scatterlist *sg;
536 int i, size;
537 u8 *align;
538 char *buffer;
539 unsigned long flags;
540
541 if (data->flags & MMC_DATA_READ)
542 direction = DMA_FROM_DEVICE;
543 else
544 direction = DMA_TO_DEVICE;
545
546 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
547 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
548
549 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
550 128 * 4, direction);
551
552 if (data->flags & MMC_DATA_READ) {
553 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
554 data->sg_len, direction);
555
556 align = host->align_buffer;
557
558 for_each_sg(data->sg, sg, host->sg_count, i) {
559 if (sg_dma_address(sg) & 0x3) {
560 size = 4 - (sg_dma_address(sg) & 0x3);
561
562 buffer = sdhci_kmap_atomic(sg, &flags);
563 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
564 memcpy(buffer, align, size);
565 sdhci_kunmap_atomic(buffer, &flags);
566
567 align += 4;
568 }
569 }
570 }
571
572 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
573 data->sg_len, direction);
574 }
575
576 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
577 {
578 u8 count;
579 unsigned target_timeout, current_timeout;
580
581 /*
582 * If the host controller provides us with an incorrect timeout
583 * value, just skip the check and use 0xE. The hardware may take
584 * longer to time out, but that's much better than having a too-short
585 * timeout value.
586 */
587 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
588 return 0xE;
589
590 /* timeout in us */
591 target_timeout = data->timeout_ns / 1000 +
592 data->timeout_clks / host->clock;
593
594 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
595 host->timeout_clk = host->clock / 1000;
596
597 /*
598 * Figure out needed cycles.
599 * We do this in steps in order to fit inside a 32 bit int.
600 * The first step is the minimum timeout, which will have a
601 * minimum resolution of 6 bits:
602 * (1) 2^13*1000 > 2^22,
603 * (2) host->timeout_clk < 2^16
604 * =>
605 * (1) / (2) > 2^6
606 */
607 count = 0;
608 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
609 while (current_timeout < target_timeout) {
610 count++;
611 current_timeout <<= 1;
612 if (count >= 0xF)
613 break;
614 }
615
616 if (count >= 0xF) {
617 printk(KERN_WARNING "%s: Too large timeout requested!\n",
618 mmc_hostname(host->mmc));
619 count = 0xE;
620 }
621
622 return count;
623 }
624
625 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
626 {
627 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
628 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
629
630 if (host->flags & SDHCI_REQ_USE_DMA)
631 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
632 else
633 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
634 }
635
636 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
637 {
638 u8 count;
639 u8 ctrl;
640 int ret;
641
642 WARN_ON(host->data);
643
644 if (data == NULL)
645 return;
646
647 /* Sanity checks */
648 BUG_ON(data->blksz * data->blocks > 524288);
649 BUG_ON(data->blksz > host->mmc->max_blk_size);
650 BUG_ON(data->blocks > 65535);
651
652 host->data = data;
653 host->data_early = 0;
654
655 count = sdhci_calc_timeout(host, data);
656 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
657
658 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
659 host->flags |= SDHCI_REQ_USE_DMA;
660
661 /*
662 * FIXME: This doesn't account for merging when mapping the
663 * scatterlist.
664 */
665 if (host->flags & SDHCI_REQ_USE_DMA) {
666 int broken, i;
667 struct scatterlist *sg;
668
669 broken = 0;
670 if (host->flags & SDHCI_USE_ADMA) {
671 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
672 broken = 1;
673 } else {
674 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
675 broken = 1;
676 }
677
678 if (unlikely(broken)) {
679 for_each_sg(data->sg, sg, data->sg_len, i) {
680 if (sg->length & 0x3) {
681 DBG("Reverting to PIO because of "
682 "transfer size (%d)\n",
683 sg->length);
684 host->flags &= ~SDHCI_REQ_USE_DMA;
685 break;
686 }
687 }
688 }
689 }
690
691 /*
692 * The assumption here being that alignment is the same after
693 * translation to device address space.
694 */
695 if (host->flags & SDHCI_REQ_USE_DMA) {
696 int broken, i;
697 struct scatterlist *sg;
698
699 broken = 0;
700 if (host->flags & SDHCI_USE_ADMA) {
701 /*
702 * As we use 3 byte chunks to work around
703 * alignment problems, we need to check this
704 * quirk.
705 */
706 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
707 broken = 1;
708 } else {
709 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
710 broken = 1;
711 }
712
713 if (unlikely(broken)) {
714 for_each_sg(data->sg, sg, data->sg_len, i) {
715 if (sg->offset & 0x3) {
716 DBG("Reverting to PIO because of "
717 "bad alignment\n");
718 host->flags &= ~SDHCI_REQ_USE_DMA;
719 break;
720 }
721 }
722 }
723 }
724
725 if (host->flags & SDHCI_REQ_USE_DMA) {
726 if (host->flags & SDHCI_USE_ADMA) {
727 ret = sdhci_adma_table_pre(host, data);
728 if (ret) {
729 /*
730 * This only happens when someone fed
731 * us an invalid request.
732 */
733 WARN_ON(1);
734 host->flags &= ~SDHCI_REQ_USE_DMA;
735 } else {
736 sdhci_writel(host, host->adma_addr,
737 SDHCI_ADMA_ADDRESS);
738 }
739 } else {
740 int sg_cnt;
741
742 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
743 data->sg, data->sg_len,
744 (data->flags & MMC_DATA_READ) ?
745 DMA_FROM_DEVICE :
746 DMA_TO_DEVICE);
747 if (sg_cnt == 0) {
748 /*
749 * This only happens when someone fed
750 * us an invalid request.
751 */
752 WARN_ON(1);
753 host->flags &= ~SDHCI_REQ_USE_DMA;
754 } else {
755 WARN_ON(sg_cnt != 1);
756 sdhci_writel(host, sg_dma_address(data->sg),
757 SDHCI_DMA_ADDRESS);
758 }
759 }
760 }
761
762 /*
763 * Always adjust the DMA selection as some controllers
764 * (e.g. JMicron) can't do PIO properly when the selection
765 * is ADMA.
766 */
767 if (host->version >= SDHCI_SPEC_200) {
768 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
769 ctrl &= ~SDHCI_CTRL_DMA_MASK;
770 if ((host->flags & SDHCI_REQ_USE_DMA) &&
771 (host->flags & SDHCI_USE_ADMA))
772 ctrl |= SDHCI_CTRL_ADMA32;
773 else
774 ctrl |= SDHCI_CTRL_SDMA;
775 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
776 }
777
778 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
779 int flags;
780
781 flags = SG_MITER_ATOMIC;
782 if (host->data->flags & MMC_DATA_READ)
783 flags |= SG_MITER_TO_SG;
784 else
785 flags |= SG_MITER_FROM_SG;
786 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
787 host->blocks = data->blocks;
788 }
789
790 sdhci_set_transfer_irqs(host);
791
792 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
793 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, data->blksz), SDHCI_BLOCK_SIZE);
794 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
795 }
796
797 static void sdhci_set_transfer_mode(struct sdhci_host *host,
798 struct mmc_data *data)
799 {
800 u16 mode;
801
802 if (data == NULL)
803 return;
804
805 WARN_ON(!host->data);
806
807 mode = SDHCI_TRNS_BLK_CNT_EN;
808 if (data->blocks > 1)
809 mode |= SDHCI_TRNS_MULTI;
810 if (data->flags & MMC_DATA_READ)
811 mode |= SDHCI_TRNS_READ;
812 if (host->flags & SDHCI_REQ_USE_DMA)
813 mode |= SDHCI_TRNS_DMA;
814
815 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
816 }
817
818 static void sdhci_finish_data(struct sdhci_host *host)
819 {
820 struct mmc_data *data;
821
822 BUG_ON(!host->data);
823
824 data = host->data;
825 host->data = NULL;
826
827 if (host->flags & SDHCI_REQ_USE_DMA) {
828 if (host->flags & SDHCI_USE_ADMA)
829 sdhci_adma_table_post(host, data);
830 else {
831 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
832 data->sg_len, (data->flags & MMC_DATA_READ) ?
833 DMA_FROM_DEVICE : DMA_TO_DEVICE);
834 }
835 }
836
837 /*
838 * The specification states that the block count register must
839 * be updated, but it does not specify at what point in the
840 * data flow. That makes the register entirely useless to read
841 * back so we have to assume that nothing made it to the card
842 * in the event of an error.
843 */
844 if (data->error)
845 data->bytes_xfered = 0;
846 else
847 data->bytes_xfered = data->blksz * data->blocks;
848
849 if (data->stop) {
850 /*
851 * The controller needs a reset of internal state machines
852 * upon error conditions.
853 */
854 if (data->error) {
855 sdhci_reset(host, SDHCI_RESET_CMD);
856 sdhci_reset(host, SDHCI_RESET_DATA);
857 }
858
859 sdhci_send_command(host, data->stop);
860 } else
861 tasklet_schedule(&host->finish_tasklet);
862 }
863
864 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
865 {
866 int flags;
867 u32 mask;
868 unsigned long timeout;
869
870 WARN_ON(host->cmd);
871
872 /* Wait max 10 ms */
873 timeout = 10;
874
875 mask = SDHCI_CMD_INHIBIT;
876 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
877 mask |= SDHCI_DATA_INHIBIT;
878
879 /* We shouldn't wait for data inihibit for stop commands, even
880 though they might use busy signaling */
881 if (host->mrq->data && (cmd == host->mrq->data->stop))
882 mask &= ~SDHCI_DATA_INHIBIT;
883
884 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
885 if (timeout == 0) {
886 printk(KERN_ERR "%s: Controller never released "
887 "inhibit bit(s).\n", mmc_hostname(host->mmc));
888 sdhci_dumpregs(host);
889 cmd->error = -EIO;
890 tasklet_schedule(&host->finish_tasklet);
891 return;
892 }
893 timeout--;
894 mdelay(1);
895 }
896
897 mod_timer(&host->timer, jiffies + 10 * HZ);
898
899 host->cmd = cmd;
900
901 sdhci_prepare_data(host, cmd->data);
902
903 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
904
905 sdhci_set_transfer_mode(host, cmd->data);
906
907 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
908 printk(KERN_ERR "%s: Unsupported response type!\n",
909 mmc_hostname(host->mmc));
910 cmd->error = -EINVAL;
911 tasklet_schedule(&host->finish_tasklet);
912 return;
913 }
914
915 if (!(cmd->flags & MMC_RSP_PRESENT))
916 flags = SDHCI_CMD_RESP_NONE;
917 else if (cmd->flags & MMC_RSP_136)
918 flags = SDHCI_CMD_RESP_LONG;
919 else if (cmd->flags & MMC_RSP_BUSY)
920 flags = SDHCI_CMD_RESP_SHORT_BUSY;
921 else
922 flags = SDHCI_CMD_RESP_SHORT;
923
924 if (cmd->flags & MMC_RSP_CRC)
925 flags |= SDHCI_CMD_CRC;
926 if (cmd->flags & MMC_RSP_OPCODE)
927 flags |= SDHCI_CMD_INDEX;
928 if (cmd->data)
929 flags |= SDHCI_CMD_DATA;
930
931 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
932 }
933
934 static void sdhci_finish_command(struct sdhci_host *host)
935 {
936 int i;
937
938 BUG_ON(host->cmd == NULL);
939
940 if (host->cmd->flags & MMC_RSP_PRESENT) {
941 if (host->cmd->flags & MMC_RSP_136) {
942 /* CRC is stripped so we need to do some shifting. */
943 for (i = 0;i < 4;i++) {
944 host->cmd->resp[i] = sdhci_readl(host,
945 SDHCI_RESPONSE + (3-i)*4) << 8;
946 if (i != 3)
947 host->cmd->resp[i] |=
948 sdhci_readb(host,
949 SDHCI_RESPONSE + (3-i)*4-1);
950 }
951 } else {
952 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
953 }
954 }
955
956 host->cmd->error = 0;
957
958 if (host->data && host->data_early)
959 sdhci_finish_data(host);
960
961 if (!host->cmd->data)
962 tasklet_schedule(&host->finish_tasklet);
963
964 host->cmd = NULL;
965 }
966
967 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
968 {
969 int div;
970 u16 clk;
971 unsigned long timeout;
972
973 if (clock == host->clock)
974 return;
975
976 if (host->ops->set_clock) {
977 host->ops->set_clock(host, clock);
978 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
979 return;
980 }
981
982 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
983
984 if (clock == 0)
985 goto out;
986
987 for (div = 1;div < 256;div *= 2) {
988 if ((host->max_clk / div) <= clock)
989 break;
990 }
991 div >>= 1;
992
993 clk = div << SDHCI_DIVIDER_SHIFT;
994 clk |= SDHCI_CLOCK_INT_EN;
995 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
996
997 /* Wait max 20 ms */
998 timeout = 20;
999 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1000 & SDHCI_CLOCK_INT_STABLE)) {
1001 if (timeout == 0) {
1002 printk(KERN_ERR "%s: Internal clock never "
1003 "stabilised.\n", mmc_hostname(host->mmc));
1004 sdhci_dumpregs(host);
1005 return;
1006 }
1007 timeout--;
1008 mdelay(1);
1009 }
1010
1011 clk |= SDHCI_CLOCK_CARD_EN;
1012 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1013
1014 out:
1015 host->clock = clock;
1016 }
1017
1018 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1019 {
1020 u8 pwr;
1021
1022 if (power == (unsigned short)-1)
1023 pwr = 0;
1024 else {
1025 switch (1 << power) {
1026 case MMC_VDD_165_195:
1027 pwr = SDHCI_POWER_180;
1028 break;
1029 case MMC_VDD_29_30:
1030 case MMC_VDD_30_31:
1031 pwr = SDHCI_POWER_300;
1032 break;
1033 case MMC_VDD_32_33:
1034 case MMC_VDD_33_34:
1035 pwr = SDHCI_POWER_330;
1036 break;
1037 default:
1038 BUG();
1039 }
1040 }
1041
1042 if (host->pwr == pwr)
1043 return;
1044
1045 host->pwr = pwr;
1046
1047 if (pwr == 0) {
1048 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1049 return;
1050 }
1051
1052 /*
1053 * Spec says that we should clear the power reg before setting
1054 * a new value. Some controllers don't seem to like this though.
1055 */
1056 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1057 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1058
1059 /*
1060 * At least the Marvell CaFe chip gets confused if we set the voltage
1061 * and set turn on power at the same time, so set the voltage first.
1062 */
1063 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1064 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1065
1066 pwr |= SDHCI_POWER_ON;
1067
1068 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1069
1070 /*
1071 * Some controllers need an extra 10ms delay of 10ms before they
1072 * can apply clock after applying power
1073 */
1074 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1075 mdelay(10);
1076 }
1077
1078 /*****************************************************************************\
1079 * *
1080 * MMC callbacks *
1081 * *
1082 \*****************************************************************************/
1083
1084 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1085 {
1086 struct sdhci_host *host;
1087 bool present;
1088 unsigned long flags;
1089
1090 host = mmc_priv(mmc);
1091
1092 spin_lock_irqsave(&host->lock, flags);
1093
1094 WARN_ON(host->mrq != NULL);
1095
1096 #ifndef SDHCI_USE_LEDS_CLASS
1097 sdhci_activate_led(host);
1098 #endif
1099
1100 host->mrq = mrq;
1101
1102 /* If polling, assume that the card is always present. */
1103 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1104 present = true;
1105 else
1106 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1107 SDHCI_CARD_PRESENT;
1108
1109 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1110 host->mrq->cmd->error = -ENOMEDIUM;
1111 tasklet_schedule(&host->finish_tasklet);
1112 } else
1113 sdhci_send_command(host, mrq->cmd);
1114
1115 mmiowb();
1116 spin_unlock_irqrestore(&host->lock, flags);
1117 }
1118
1119 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1120 {
1121 struct sdhci_host *host;
1122 unsigned long flags;
1123 u8 ctrl;
1124
1125 host = mmc_priv(mmc);
1126
1127 spin_lock_irqsave(&host->lock, flags);
1128
1129 if (host->flags & SDHCI_DEVICE_DEAD)
1130 goto out;
1131
1132 /*
1133 * Reset the chip on each power off.
1134 * Should clear out any weird states.
1135 */
1136 if (ios->power_mode == MMC_POWER_OFF) {
1137 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1138 sdhci_reinit(host);
1139 }
1140
1141 sdhci_set_clock(host, ios->clock);
1142
1143 if (ios->power_mode == MMC_POWER_OFF)
1144 sdhci_set_power(host, -1);
1145 else
1146 sdhci_set_power(host, ios->vdd);
1147
1148 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1149
1150 if (ios->bus_width == MMC_BUS_WIDTH_4)
1151 ctrl |= SDHCI_CTRL_4BITBUS;
1152 else
1153 ctrl &= ~SDHCI_CTRL_4BITBUS;
1154
1155 if (ios->timing == MMC_TIMING_SD_HS)
1156 ctrl |= SDHCI_CTRL_HISPD;
1157 else
1158 ctrl &= ~SDHCI_CTRL_HISPD;
1159
1160 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1161
1162 /*
1163 * Some (ENE) controllers go apeshit on some ios operation,
1164 * signalling timeout and CRC errors even on CMD0. Resetting
1165 * it on each ios seems to solve the problem.
1166 */
1167 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1168 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1169
1170 out:
1171 mmiowb();
1172 spin_unlock_irqrestore(&host->lock, flags);
1173 }
1174
1175 static int sdhci_get_ro(struct mmc_host *mmc)
1176 {
1177 struct sdhci_host *host;
1178 unsigned long flags;
1179 int present;
1180
1181 host = mmc_priv(mmc);
1182
1183 spin_lock_irqsave(&host->lock, flags);
1184
1185 if (host->flags & SDHCI_DEVICE_DEAD)
1186 present = 0;
1187 else
1188 present = sdhci_readl(host, SDHCI_PRESENT_STATE);
1189
1190 spin_unlock_irqrestore(&host->lock, flags);
1191
1192 if (host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT)
1193 return !!(present & SDHCI_WRITE_PROTECT);
1194 return !(present & SDHCI_WRITE_PROTECT);
1195 }
1196
1197 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1198 {
1199 struct sdhci_host *host;
1200 unsigned long flags;
1201
1202 host = mmc_priv(mmc);
1203
1204 spin_lock_irqsave(&host->lock, flags);
1205
1206 if (host->flags & SDHCI_DEVICE_DEAD)
1207 goto out;
1208
1209 if (enable)
1210 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1211 else
1212 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1213 out:
1214 mmiowb();
1215
1216 spin_unlock_irqrestore(&host->lock, flags);
1217 }
1218
1219 static const struct mmc_host_ops sdhci_ops = {
1220 .request = sdhci_request,
1221 .set_ios = sdhci_set_ios,
1222 .get_ro = sdhci_get_ro,
1223 .enable_sdio_irq = sdhci_enable_sdio_irq,
1224 };
1225
1226 /*****************************************************************************\
1227 * *
1228 * Tasklets *
1229 * *
1230 \*****************************************************************************/
1231
1232 static void sdhci_tasklet_card(unsigned long param)
1233 {
1234 struct sdhci_host *host;
1235 unsigned long flags;
1236
1237 host = (struct sdhci_host*)param;
1238
1239 spin_lock_irqsave(&host->lock, flags);
1240
1241 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1242 if (host->mrq) {
1243 printk(KERN_ERR "%s: Card removed during transfer!\n",
1244 mmc_hostname(host->mmc));
1245 printk(KERN_ERR "%s: Resetting controller.\n",
1246 mmc_hostname(host->mmc));
1247
1248 sdhci_reset(host, SDHCI_RESET_CMD);
1249 sdhci_reset(host, SDHCI_RESET_DATA);
1250
1251 host->mrq->cmd->error = -ENOMEDIUM;
1252 tasklet_schedule(&host->finish_tasklet);
1253 }
1254 }
1255
1256 spin_unlock_irqrestore(&host->lock, flags);
1257
1258 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1259 }
1260
1261 static void sdhci_tasklet_finish(unsigned long param)
1262 {
1263 struct sdhci_host *host;
1264 unsigned long flags;
1265 struct mmc_request *mrq;
1266
1267 host = (struct sdhci_host*)param;
1268
1269 /*
1270 * If this tasklet gets rescheduled while running, it will
1271 * be run again afterwards but without any active request.
1272 */
1273 if (!host->mrq)
1274 return;
1275
1276 spin_lock_irqsave(&host->lock, flags);
1277
1278 del_timer(&host->timer);
1279
1280 mrq = host->mrq;
1281
1282 /*
1283 * The controller needs a reset of internal state machines
1284 * upon error conditions.
1285 */
1286 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1287 ((mrq->cmd && mrq->cmd->error) ||
1288 (mrq->data && (mrq->data->error ||
1289 (mrq->data->stop && mrq->data->stop->error))) ||
1290 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1291
1292 /* Some controllers need this kick or reset won't work here */
1293 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1294 unsigned int clock;
1295
1296 /* This is to force an update */
1297 clock = host->clock;
1298 host->clock = 0;
1299 sdhci_set_clock(host, clock);
1300 }
1301
1302 /* Spec says we should do both at the same time, but Ricoh
1303 controllers do not like that. */
1304 sdhci_reset(host, SDHCI_RESET_CMD);
1305 sdhci_reset(host, SDHCI_RESET_DATA);
1306 }
1307
1308 host->mrq = NULL;
1309 host->cmd = NULL;
1310 host->data = NULL;
1311
1312 #ifndef SDHCI_USE_LEDS_CLASS
1313 sdhci_deactivate_led(host);
1314 #endif
1315
1316 mmiowb();
1317 spin_unlock_irqrestore(&host->lock, flags);
1318
1319 mmc_request_done(host->mmc, mrq);
1320 }
1321
1322 static void sdhci_timeout_timer(unsigned long data)
1323 {
1324 struct sdhci_host *host;
1325 unsigned long flags;
1326
1327 host = (struct sdhci_host*)data;
1328
1329 spin_lock_irqsave(&host->lock, flags);
1330
1331 if (host->mrq) {
1332 printk(KERN_ERR "%s: Timeout waiting for hardware "
1333 "interrupt.\n", mmc_hostname(host->mmc));
1334 sdhci_dumpregs(host);
1335
1336 if (host->data) {
1337 host->data->error = -ETIMEDOUT;
1338 sdhci_finish_data(host);
1339 } else {
1340 if (host->cmd)
1341 host->cmd->error = -ETIMEDOUT;
1342 else
1343 host->mrq->cmd->error = -ETIMEDOUT;
1344
1345 tasklet_schedule(&host->finish_tasklet);
1346 }
1347 }
1348
1349 mmiowb();
1350 spin_unlock_irqrestore(&host->lock, flags);
1351 }
1352
1353 /*****************************************************************************\
1354 * *
1355 * Interrupt handling *
1356 * *
1357 \*****************************************************************************/
1358
1359 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1360 {
1361 BUG_ON(intmask == 0);
1362
1363 if (!host->cmd) {
1364 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1365 "though no command operation was in progress.\n",
1366 mmc_hostname(host->mmc), (unsigned)intmask);
1367 sdhci_dumpregs(host);
1368 return;
1369 }
1370
1371 if (intmask & SDHCI_INT_TIMEOUT)
1372 host->cmd->error = -ETIMEDOUT;
1373 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1374 SDHCI_INT_INDEX))
1375 host->cmd->error = -EILSEQ;
1376
1377 if (host->cmd->error) {
1378 tasklet_schedule(&host->finish_tasklet);
1379 return;
1380 }
1381
1382 /*
1383 * The host can send and interrupt when the busy state has
1384 * ended, allowing us to wait without wasting CPU cycles.
1385 * Unfortunately this is overloaded on the "data complete"
1386 * interrupt, so we need to take some care when handling
1387 * it.
1388 *
1389 * Note: The 1.0 specification is a bit ambiguous about this
1390 * feature so there might be some problems with older
1391 * controllers.
1392 */
1393 if (host->cmd->flags & MMC_RSP_BUSY) {
1394 if (host->cmd->data)
1395 DBG("Cannot wait for busy signal when also "
1396 "doing a data transfer");
1397 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
1398 return;
1399
1400 /* The controller does not support the end-of-busy IRQ,
1401 * fall through and take the SDHCI_INT_RESPONSE */
1402 }
1403
1404 if (intmask & SDHCI_INT_RESPONSE)
1405 sdhci_finish_command(host);
1406 }
1407
1408 #ifdef DEBUG
1409 static void sdhci_show_adma_error(struct sdhci_host *host)
1410 {
1411 const char *name = mmc_hostname(host->mmc);
1412 u8 *desc = host->adma_desc;
1413 __le32 *dma;
1414 __le16 *len;
1415 u8 attr;
1416
1417 sdhci_dumpregs(host);
1418
1419 while (true) {
1420 dma = (__le32 *)(desc + 4);
1421 len = (__le16 *)(desc + 2);
1422 attr = *desc;
1423
1424 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
1425 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
1426
1427 desc += 8;
1428
1429 if (attr & 2)
1430 break;
1431 }
1432 }
1433 #else
1434 static void sdhci_show_adma_error(struct sdhci_host *host) { }
1435 #endif
1436
1437 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1438 {
1439 BUG_ON(intmask == 0);
1440
1441 if (!host->data) {
1442 /*
1443 * The "data complete" interrupt is also used to
1444 * indicate that a busy state has ended. See comment
1445 * above in sdhci_cmd_irq().
1446 */
1447 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
1448 if (intmask & SDHCI_INT_DATA_END) {
1449 sdhci_finish_command(host);
1450 return;
1451 }
1452 }
1453
1454 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1455 "though no data operation was in progress.\n",
1456 mmc_hostname(host->mmc), (unsigned)intmask);
1457 sdhci_dumpregs(host);
1458
1459 return;
1460 }
1461
1462 if (intmask & SDHCI_INT_DATA_TIMEOUT)
1463 host->data->error = -ETIMEDOUT;
1464 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1465 host->data->error = -EILSEQ;
1466 else if (intmask & SDHCI_INT_ADMA_ERROR) {
1467 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
1468 sdhci_show_adma_error(host);
1469 host->data->error = -EIO;
1470 }
1471
1472 if (host->data->error)
1473 sdhci_finish_data(host);
1474 else {
1475 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1476 sdhci_transfer_pio(host);
1477
1478 /*
1479 * We currently don't do anything fancy with DMA
1480 * boundaries, but as we can't disable the feature
1481 * we need to at least restart the transfer.
1482 */
1483 if (intmask & SDHCI_INT_DMA_END)
1484 sdhci_writel(host, sdhci_readl(host, SDHCI_DMA_ADDRESS),
1485 SDHCI_DMA_ADDRESS);
1486
1487 if (intmask & SDHCI_INT_DATA_END) {
1488 if (host->cmd) {
1489 /*
1490 * Data managed to finish before the
1491 * command completed. Make sure we do
1492 * things in the proper order.
1493 */
1494 host->data_early = 1;
1495 } else {
1496 sdhci_finish_data(host);
1497 }
1498 }
1499 }
1500 }
1501
1502 static irqreturn_t sdhci_irq(int irq, void *dev_id)
1503 {
1504 irqreturn_t result;
1505 struct sdhci_host* host = dev_id;
1506 u32 intmask;
1507 int cardint = 0;
1508
1509 spin_lock(&host->lock);
1510
1511 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
1512
1513 if (!intmask || intmask == 0xffffffff) {
1514 result = IRQ_NONE;
1515 goto out;
1516 }
1517
1518 DBG("*** %s got interrupt: 0x%08x\n",
1519 mmc_hostname(host->mmc), intmask);
1520
1521 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1522 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
1523 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
1524 tasklet_schedule(&host->card_tasklet);
1525 }
1526
1527 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1528
1529 if (intmask & SDHCI_INT_CMD_MASK) {
1530 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
1531 SDHCI_INT_STATUS);
1532 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1533 }
1534
1535 if (intmask & SDHCI_INT_DATA_MASK) {
1536 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
1537 SDHCI_INT_STATUS);
1538 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1539 }
1540
1541 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1542
1543 intmask &= ~SDHCI_INT_ERROR;
1544
1545 if (intmask & SDHCI_INT_BUS_POWER) {
1546 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1547 mmc_hostname(host->mmc));
1548 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
1549 }
1550
1551 intmask &= ~SDHCI_INT_BUS_POWER;
1552
1553 if (intmask & SDHCI_INT_CARD_INT)
1554 cardint = 1;
1555
1556 intmask &= ~SDHCI_INT_CARD_INT;
1557
1558 if (intmask) {
1559 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1560 mmc_hostname(host->mmc), intmask);
1561 sdhci_dumpregs(host);
1562
1563 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
1564 }
1565
1566 result = IRQ_HANDLED;
1567
1568 mmiowb();
1569 out:
1570 spin_unlock(&host->lock);
1571
1572 /*
1573 * We have to delay this as it calls back into the driver.
1574 */
1575 if (cardint)
1576 mmc_signal_sdio_irq(host->mmc);
1577
1578 return result;
1579 }
1580
1581 /*****************************************************************************\
1582 * *
1583 * Suspend/resume *
1584 * *
1585 \*****************************************************************************/
1586
1587 #ifdef CONFIG_PM
1588
1589 int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
1590 {
1591 int ret;
1592
1593 sdhci_disable_card_detection(host);
1594
1595 ret = mmc_suspend_host(host->mmc, state);
1596 if (ret)
1597 return ret;
1598
1599 free_irq(host->irq, host);
1600
1601 return 0;
1602 }
1603
1604 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
1605
1606 int sdhci_resume_host(struct sdhci_host *host)
1607 {
1608 int ret;
1609
1610 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1611 if (host->ops->enable_dma)
1612 host->ops->enable_dma(host);
1613 }
1614
1615 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1616 mmc_hostname(host->mmc), host);
1617 if (ret)
1618 return ret;
1619
1620 sdhci_init(host);
1621 mmiowb();
1622
1623 ret = mmc_resume_host(host->mmc);
1624 if (ret)
1625 return ret;
1626
1627 sdhci_enable_card_detection(host);
1628
1629 return 0;
1630 }
1631
1632 EXPORT_SYMBOL_GPL(sdhci_resume_host);
1633
1634 #endif /* CONFIG_PM */
1635
1636 /*****************************************************************************\
1637 * *
1638 * Device allocation/registration *
1639 * *
1640 \*****************************************************************************/
1641
1642 struct sdhci_host *sdhci_alloc_host(struct device *dev,
1643 size_t priv_size)
1644 {
1645 struct mmc_host *mmc;
1646 struct sdhci_host *host;
1647
1648 WARN_ON(dev == NULL);
1649
1650 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
1651 if (!mmc)
1652 return ERR_PTR(-ENOMEM);
1653
1654 host = mmc_priv(mmc);
1655 host->mmc = mmc;
1656
1657 return host;
1658 }
1659
1660 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
1661
1662 int sdhci_add_host(struct sdhci_host *host)
1663 {
1664 struct mmc_host *mmc;
1665 unsigned int caps;
1666 int ret;
1667
1668 WARN_ON(host == NULL);
1669 if (host == NULL)
1670 return -EINVAL;
1671
1672 mmc = host->mmc;
1673
1674 if (debug_quirks)
1675 host->quirks = debug_quirks;
1676
1677 sdhci_reset(host, SDHCI_RESET_ALL);
1678
1679 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
1680 host->version = (host->version & SDHCI_SPEC_VER_MASK)
1681 >> SDHCI_SPEC_VER_SHIFT;
1682 if (host->version > SDHCI_SPEC_200) {
1683 printk(KERN_ERR "%s: Unknown controller version (%d). "
1684 "You may experience problems.\n", mmc_hostname(mmc),
1685 host->version);
1686 }
1687
1688 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
1689
1690 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
1691 host->flags |= SDHCI_USE_SDMA;
1692 else if (!(caps & SDHCI_CAN_DO_SDMA))
1693 DBG("Controller doesn't have SDMA capability\n");
1694 else
1695 host->flags |= SDHCI_USE_SDMA;
1696
1697 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
1698 (host->flags & SDHCI_USE_SDMA)) {
1699 DBG("Disabling DMA as it is marked broken\n");
1700 host->flags &= ~SDHCI_USE_SDMA;
1701 }
1702
1703 if ((host->version >= SDHCI_SPEC_200) && (caps & SDHCI_CAN_DO_ADMA2))
1704 host->flags |= SDHCI_USE_ADMA;
1705
1706 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
1707 (host->flags & SDHCI_USE_ADMA)) {
1708 DBG("Disabling ADMA as it is marked broken\n");
1709 host->flags &= ~SDHCI_USE_ADMA;
1710 }
1711
1712 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1713 if (host->ops->enable_dma) {
1714 if (host->ops->enable_dma(host)) {
1715 printk(KERN_WARNING "%s: No suitable DMA "
1716 "available. Falling back to PIO.\n",
1717 mmc_hostname(mmc));
1718 host->flags &=
1719 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
1720 }
1721 }
1722 }
1723
1724 if (host->flags & SDHCI_USE_ADMA) {
1725 /*
1726 * We need to allocate descriptors for all sg entries
1727 * (128) and potentially one alignment transfer for
1728 * each of those entries.
1729 */
1730 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
1731 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
1732 if (!host->adma_desc || !host->align_buffer) {
1733 kfree(host->adma_desc);
1734 kfree(host->align_buffer);
1735 printk(KERN_WARNING "%s: Unable to allocate ADMA "
1736 "buffers. Falling back to standard DMA.\n",
1737 mmc_hostname(mmc));
1738 host->flags &= ~SDHCI_USE_ADMA;
1739 }
1740 }
1741
1742 /*
1743 * If we use DMA, then it's up to the caller to set the DMA
1744 * mask, but PIO does not need the hw shim so we set a new
1745 * mask here in that case.
1746 */
1747 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
1748 host->dma_mask = DMA_BIT_MASK(64);
1749 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
1750 }
1751
1752 host->max_clk =
1753 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1754 host->max_clk *= 1000000;
1755 if (host->max_clk == 0) {
1756 if (!host->ops->get_max_clock) {
1757 printk(KERN_ERR
1758 "%s: Hardware doesn't specify base clock "
1759 "frequency.\n", mmc_hostname(mmc));
1760 return -ENODEV;
1761 }
1762 host->max_clk = host->ops->get_max_clock(host);
1763 }
1764
1765 host->timeout_clk =
1766 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1767 if (host->timeout_clk == 0) {
1768 if (host->ops->get_timeout_clock) {
1769 host->timeout_clk = host->ops->get_timeout_clock(host);
1770 } else if (!(host->quirks &
1771 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
1772 printk(KERN_ERR
1773 "%s: Hardware doesn't specify timeout clock "
1774 "frequency.\n", mmc_hostname(mmc));
1775 return -ENODEV;
1776 }
1777 }
1778 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1779 host->timeout_clk *= 1000;
1780
1781 /*
1782 * Set host parameters.
1783 */
1784 mmc->ops = &sdhci_ops;
1785 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK &&
1786 host->ops->set_clock && host->ops->get_min_clock)
1787 mmc->f_min = host->ops->get_min_clock(host);
1788 else
1789 mmc->f_min = host->max_clk / 256;
1790 mmc->f_max = host->max_clk;
1791 mmc->caps = MMC_CAP_SDIO_IRQ;
1792
1793 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
1794 mmc->caps |= MMC_CAP_4_BIT_DATA;
1795
1796 if (caps & SDHCI_CAN_DO_HISPD)
1797 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1798
1799 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1800 mmc->caps |= MMC_CAP_NEEDS_POLL;
1801
1802 mmc->ocr_avail = 0;
1803 if (caps & SDHCI_CAN_VDD_330)
1804 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1805 if (caps & SDHCI_CAN_VDD_300)
1806 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1807 if (caps & SDHCI_CAN_VDD_180)
1808 mmc->ocr_avail |= MMC_VDD_165_195;
1809
1810 if (mmc->ocr_avail == 0) {
1811 printk(KERN_ERR "%s: Hardware doesn't report any "
1812 "support voltages.\n", mmc_hostname(mmc));
1813 return -ENODEV;
1814 }
1815
1816 spin_lock_init(&host->lock);
1817
1818 /*
1819 * Maximum number of segments. Depends on if the hardware
1820 * can do scatter/gather or not.
1821 */
1822 if (host->flags & SDHCI_USE_ADMA)
1823 mmc->max_hw_segs = 128;
1824 else if (host->flags & SDHCI_USE_SDMA)
1825 mmc->max_hw_segs = 1;
1826 else /* PIO */
1827 mmc->max_hw_segs = 128;
1828 mmc->max_phys_segs = 128;
1829
1830 /*
1831 * Maximum number of sectors in one transfer. Limited by DMA boundary
1832 * size (512KiB).
1833 */
1834 mmc->max_req_size = 524288;
1835
1836 /*
1837 * Maximum segment size. Could be one segment with the maximum number
1838 * of bytes. When doing hardware scatter/gather, each entry cannot
1839 * be larger than 64 KiB though.
1840 */
1841 if (host->flags & SDHCI_USE_ADMA)
1842 mmc->max_seg_size = 65536;
1843 else
1844 mmc->max_seg_size = mmc->max_req_size;
1845
1846 /*
1847 * Maximum block size. This varies from controller to controller and
1848 * is specified in the capabilities register.
1849 */
1850 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
1851 mmc->max_blk_size = 2;
1852 } else {
1853 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >>
1854 SDHCI_MAX_BLOCK_SHIFT;
1855 if (mmc->max_blk_size >= 3) {
1856 printk(KERN_WARNING "%s: Invalid maximum block size, "
1857 "assuming 512 bytes\n", mmc_hostname(mmc));
1858 mmc->max_blk_size = 0;
1859 }
1860 }
1861
1862 mmc->max_blk_size = 512 << mmc->max_blk_size;
1863
1864 /*
1865 * Maximum block count.
1866 */
1867 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
1868
1869 /*
1870 * Init tasklets.
1871 */
1872 tasklet_init(&host->card_tasklet,
1873 sdhci_tasklet_card, (unsigned long)host);
1874 tasklet_init(&host->finish_tasklet,
1875 sdhci_tasklet_finish, (unsigned long)host);
1876
1877 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
1878
1879 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1880 mmc_hostname(mmc), host);
1881 if (ret)
1882 goto untasklet;
1883
1884 sdhci_init(host);
1885
1886 #ifdef CONFIG_MMC_DEBUG
1887 sdhci_dumpregs(host);
1888 #endif
1889
1890 #ifdef SDHCI_USE_LEDS_CLASS
1891 snprintf(host->led_name, sizeof(host->led_name),
1892 "%s::", mmc_hostname(mmc));
1893 host->led.name = host->led_name;
1894 host->led.brightness = LED_OFF;
1895 host->led.default_trigger = mmc_hostname(mmc);
1896 host->led.brightness_set = sdhci_led_control;
1897
1898 ret = led_classdev_register(mmc_dev(mmc), &host->led);
1899 if (ret)
1900 goto reset;
1901 #endif
1902
1903 mmiowb();
1904
1905 mmc_add_host(mmc);
1906
1907 printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
1908 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
1909 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
1910 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
1911
1912 sdhci_enable_card_detection(host);
1913
1914 return 0;
1915
1916 #ifdef SDHCI_USE_LEDS_CLASS
1917 reset:
1918 sdhci_reset(host, SDHCI_RESET_ALL);
1919 free_irq(host->irq, host);
1920 #endif
1921 untasklet:
1922 tasklet_kill(&host->card_tasklet);
1923 tasklet_kill(&host->finish_tasklet);
1924
1925 return ret;
1926 }
1927
1928 EXPORT_SYMBOL_GPL(sdhci_add_host);
1929
1930 void sdhci_remove_host(struct sdhci_host *host, int dead)
1931 {
1932 unsigned long flags;
1933
1934 if (dead) {
1935 spin_lock_irqsave(&host->lock, flags);
1936
1937 host->flags |= SDHCI_DEVICE_DEAD;
1938
1939 if (host->mrq) {
1940 printk(KERN_ERR "%s: Controller removed during "
1941 " transfer!\n", mmc_hostname(host->mmc));
1942
1943 host->mrq->cmd->error = -ENOMEDIUM;
1944 tasklet_schedule(&host->finish_tasklet);
1945 }
1946
1947 spin_unlock_irqrestore(&host->lock, flags);
1948 }
1949
1950 sdhci_disable_card_detection(host);
1951
1952 mmc_remove_host(host->mmc);
1953
1954 #ifdef SDHCI_USE_LEDS_CLASS
1955 led_classdev_unregister(&host->led);
1956 #endif
1957
1958 if (!dead)
1959 sdhci_reset(host, SDHCI_RESET_ALL);
1960
1961 free_irq(host->irq, host);
1962
1963 del_timer_sync(&host->timer);
1964
1965 tasklet_kill(&host->card_tasklet);
1966 tasklet_kill(&host->finish_tasklet);
1967
1968 kfree(host->adma_desc);
1969 kfree(host->align_buffer);
1970
1971 host->adma_desc = NULL;
1972 host->align_buffer = NULL;
1973 }
1974
1975 EXPORT_SYMBOL_GPL(sdhci_remove_host);
1976
1977 void sdhci_free_host(struct sdhci_host *host)
1978 {
1979 mmc_free_host(host->mmc);
1980 }
1981
1982 EXPORT_SYMBOL_GPL(sdhci_free_host);
1983
1984 /*****************************************************************************\
1985 * *
1986 * Driver init/exit *
1987 * *
1988 \*****************************************************************************/
1989
1990 static int __init sdhci_drv_init(void)
1991 {
1992 printk(KERN_INFO DRIVER_NAME
1993 ": Secure Digital Host Controller Interface driver\n");
1994 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1995
1996 return 0;
1997 }
1998
1999 static void __exit sdhci_drv_exit(void)
2000 {
2001 }
2002
2003 module_init(sdhci_drv_init);
2004 module_exit(sdhci_drv_exit);
2005
2006 module_param(debug_quirks, uint, 0444);
2007
2008 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
2009 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
2010 MODULE_LICENSE("GPL");
2011
2012 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
Linux ARM platform port for MOXA ART SoC