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initial commit with v2.6.32.60
[linux-2.6.32.60-moxart.git] / drivers / net / netxen / netxen_nic_hw.c
blob7e494debb7f14bedaec08ec2e0dc1535d4f73248
1 /*
2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * Copyright (C) 2009 - QLogic Corporation.
4 * All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.
23 *
24 */
25
26 #include "netxen_nic.h"
27 #include "netxen_nic_hw.h"
28
29 #include <net/ip.h>
30
31 #define MASK(n) ((1ULL<<(n))-1)
32 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
33 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
34 #define MS_WIN(addr) (addr & 0x0ffc0000)
35
36 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
37
38 #define CRB_BLK(off) ((off >> 20) & 0x3f)
39 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
40 #define CRB_WINDOW_2M (0x130060)
41 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
42 #define CRB_INDIRECT_2M (0x1e0000UL)
43
44 #ifndef readq
45 static inline u64 readq(void __iomem *addr)
46 {
47 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
48 }
49 #endif
50
51 #ifndef writeq
52 static inline void writeq(u64 val, void __iomem *addr)
53 {
54 writel(((u32) (val)), (addr));
55 writel(((u32) (val >> 32)), (addr + 4));
56 }
57 #endif
58
59 #define ADDR_IN_RANGE(addr, low, high) \
60 (((addr) < (high)) && ((addr) >= (low)))
61
62 #define PCI_OFFSET_FIRST_RANGE(adapter, off) \
63 ((adapter)->ahw.pci_base0 + (off))
64 #define PCI_OFFSET_SECOND_RANGE(adapter, off) \
65 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
66 #define PCI_OFFSET_THIRD_RANGE(adapter, off) \
67 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
68
69 static void __iomem *pci_base_offset(struct netxen_adapter *adapter,
70 unsigned long off)
71 {
72 if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END))
73 return PCI_OFFSET_FIRST_RANGE(adapter, off);
74
75 if (ADDR_IN_RANGE(off, SECOND_PAGE_GROUP_START, SECOND_PAGE_GROUP_END))
76 return PCI_OFFSET_SECOND_RANGE(adapter, off);
77
78 if (ADDR_IN_RANGE(off, THIRD_PAGE_GROUP_START, THIRD_PAGE_GROUP_END))
79 return PCI_OFFSET_THIRD_RANGE(adapter, off);
80
81 return NULL;
82 }
83
84 static crb_128M_2M_block_map_t
85 crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
86 {{{0, 0, 0, 0} } }, /* 0: PCI */
87 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
88 {1, 0x0110000, 0x0120000, 0x130000},
89 {1, 0x0120000, 0x0122000, 0x124000},
90 {1, 0x0130000, 0x0132000, 0x126000},
91 {1, 0x0140000, 0x0142000, 0x128000},
92 {1, 0x0150000, 0x0152000, 0x12a000},
93 {1, 0x0160000, 0x0170000, 0x110000},
94 {1, 0x0170000, 0x0172000, 0x12e000},
95 {0, 0x0000000, 0x0000000, 0x000000},
96 {0, 0x0000000, 0x0000000, 0x000000},
97 {0, 0x0000000, 0x0000000, 0x000000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {1, 0x01e0000, 0x01e0800, 0x122000},
102 {0, 0x0000000, 0x0000000, 0x000000} } },
103 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
104 {{{0, 0, 0, 0} } }, /* 3: */
105 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
106 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
107 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
108 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
109 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
110 {0, 0x0000000, 0x0000000, 0x000000},
111 {0, 0x0000000, 0x0000000, 0x000000},
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {1, 0x08f0000, 0x08f2000, 0x172000} } },
125 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {1, 0x09f0000, 0x09f2000, 0x176000} } },
141 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
157 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
173 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
174 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
175 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
176 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
177 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
178 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
179 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
180 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
181 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
182 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
183 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
184 {{{0, 0, 0, 0} } }, /* 23: */
185 {{{0, 0, 0, 0} } }, /* 24: */
186 {{{0, 0, 0, 0} } }, /* 25: */
187 {{{0, 0, 0, 0} } }, /* 26: */
188 {{{0, 0, 0, 0} } }, /* 27: */
189 {{{0, 0, 0, 0} } }, /* 28: */
190 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
191 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
192 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
193 {{{0} } }, /* 32: PCI */
194 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
195 {1, 0x2110000, 0x2120000, 0x130000},
196 {1, 0x2120000, 0x2122000, 0x124000},
197 {1, 0x2130000, 0x2132000, 0x126000},
198 {1, 0x2140000, 0x2142000, 0x128000},
199 {1, 0x2150000, 0x2152000, 0x12a000},
200 {1, 0x2160000, 0x2170000, 0x110000},
201 {1, 0x2170000, 0x2172000, 0x12e000},
202 {0, 0x0000000, 0x0000000, 0x000000},
203 {0, 0x0000000, 0x0000000, 0x000000},
204 {0, 0x0000000, 0x0000000, 0x000000},
205 {0, 0x0000000, 0x0000000, 0x000000},
206 {0, 0x0000000, 0x0000000, 0x000000},
207 {0, 0x0000000, 0x0000000, 0x000000},
208 {0, 0x0000000, 0x0000000, 0x000000},
209 {0, 0x0000000, 0x0000000, 0x000000} } },
210 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
211 {{{0} } }, /* 35: */
212 {{{0} } }, /* 36: */
213 {{{0} } }, /* 37: */
214 {{{0} } }, /* 38: */
215 {{{0} } }, /* 39: */
216 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
217 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
218 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
219 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
220 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
221 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
222 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
223 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
224 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
225 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
226 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
227 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
228 {{{0} } }, /* 52: */
229 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
230 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
231 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
232 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
233 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
234 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
235 {{{0} } }, /* 59: I2C0 */
236 {{{0} } }, /* 60: I2C1 */
237 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
238 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
239 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
240 };
241
242 /*
243 * top 12 bits of crb internal address (hub, agent)
244 */
245 static unsigned crb_hub_agt[64] =
246 {
247 0,
248 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
249 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
250 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
251 0,
252 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
253 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
254 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
255 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
256 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
257 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
258 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
259 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
260 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
261 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
262 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
263 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
264 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
265 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
266 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
267 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
268 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
269 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
270 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
271 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
272 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
273 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
274 0,
275 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
276 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
277 0,
278 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
279 0,
280 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
281 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
282 0,
283 0,
284 0,
285 0,
286 0,
287 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
288 0,
289 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
290 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
291 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
292 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
293 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
294 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
295 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
296 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
297 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
298 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
299 0,
300 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
301 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
302 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
303 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
304 0,
305 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
306 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
307 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
308 0,
309 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
310 0,
311 };
312
313 /* PCI Windowing for DDR regions. */
314
315 #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
316
317 #define NETXEN_PCIE_SEM_TIMEOUT 10000
318
319 int
320 netxen_pcie_sem_lock(struct netxen_adapter *adapter, int sem, u32 id_reg)
321 {
322 int done = 0, timeout = 0;
323
324 while (!done) {
325 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_LOCK(sem)));
326 if (done == 1)
327 break;
328 if (++timeout >= NETXEN_PCIE_SEM_TIMEOUT)
329 return -1;
330 msleep(1);
331 }
332
333 if (id_reg)
334 NXWR32(adapter, id_reg, adapter->portnum);
335
336 return 0;
337 }
338
339 void
340 netxen_pcie_sem_unlock(struct netxen_adapter *adapter, int sem)
341 {
342 int val;
343 val = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
344 }
345
346 int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port)
347 {
348 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
349 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1+(0x10000*port), 0x1447);
350 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0+(0x10000*port), 0x5);
351 }
352
353 return 0;
354 }
355
356 /* Disable an XG interface */
357 int netxen_niu_disable_xg_port(struct netxen_adapter *adapter)
358 {
359 __u32 mac_cfg;
360 u32 port = adapter->physical_port;
361
362 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
363 return 0;
364
365 if (port > NETXEN_NIU_MAX_XG_PORTS)
366 return -EINVAL;
367
368 mac_cfg = 0;
369 if (NXWR32(adapter,
370 NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg))
371 return -EIO;
372 return 0;
373 }
374
375 #define NETXEN_UNICAST_ADDR(port, index) \
376 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
377 #define NETXEN_MCAST_ADDR(port, index) \
378 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
379 #define MAC_HI(addr) \
380 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
381 #define MAC_LO(addr) \
382 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
383
384 int netxen_p2_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
385 {
386 u32 mac_cfg;
387 u32 cnt = 0;
388 __u32 reg = 0x0200;
389 u32 port = adapter->physical_port;
390 u16 board_type = adapter->ahw.board_type;
391
392 if (port > NETXEN_NIU_MAX_XG_PORTS)
393 return -EINVAL;
394
395 mac_cfg = NXRD32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port));
396 mac_cfg &= ~0x4;
397 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg);
398
399 if ((board_type == NETXEN_BRDTYPE_P2_SB31_10G_IMEZ) ||
400 (board_type == NETXEN_BRDTYPE_P2_SB31_10G_HMEZ))
401 reg = (0x20 << port);
402
403 NXWR32(adapter, NETXEN_NIU_FRAME_COUNT_SELECT, reg);
404
405 mdelay(10);
406
407 while (NXRD32(adapter, NETXEN_NIU_FRAME_COUNT) && ++cnt < 20)
408 mdelay(10);
409
410 if (cnt < 20) {
411
412 reg = NXRD32(adapter,
413 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port));
414
415 if (mode == NETXEN_NIU_PROMISC_MODE)
416 reg = (reg | 0x2000UL);
417 else
418 reg = (reg & ~0x2000UL);
419
420 if (mode == NETXEN_NIU_ALLMULTI_MODE)
421 reg = (reg | 0x1000UL);
422 else
423 reg = (reg & ~0x1000UL);
424
425 NXWR32(adapter,
426 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg);
427 }
428
429 mac_cfg |= 0x4;
430 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg);
431
432 return 0;
433 }
434
435 int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
436 {
437 u32 mac_hi, mac_lo;
438 u32 reg_hi, reg_lo;
439
440 u8 phy = adapter->physical_port;
441
442 if (phy >= NETXEN_NIU_MAX_XG_PORTS)
443 return -EINVAL;
444
445 mac_lo = ((u32)addr[0] << 16) | ((u32)addr[1] << 24);
446 mac_hi = addr[2] | ((u32)addr[3] << 8) |
447 ((u32)addr[4] << 16) | ((u32)addr[5] << 24);
448
449 reg_lo = NETXEN_NIU_XGE_STATION_ADDR_0_1 + (0x10000 * phy);
450 reg_hi = NETXEN_NIU_XGE_STATION_ADDR_0_HI + (0x10000 * phy);
451
452 /* write twice to flush */
453 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
454 return -EIO;
455 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
456 return -EIO;
457
458 return 0;
459 }
460
461 static int
462 netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
463 {
464 u32 val = 0;
465 u16 port = adapter->physical_port;
466 u8 *addr = adapter->mac_addr;
467
468 if (adapter->mc_enabled)
469 return 0;
470
471 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
472 val |= (1UL << (28+port));
473 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
474
475 /* add broadcast addr to filter */
476 val = 0xffffff;
477 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
478 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
479
480 /* add station addr to filter */
481 val = MAC_HI(addr);
482 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
483 val = MAC_LO(addr);
484 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, val);
485
486 adapter->mc_enabled = 1;
487 return 0;
488 }
489
490 static int
491 netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
492 {
493 u32 val = 0;
494 u16 port = adapter->physical_port;
495 u8 *addr = adapter->mac_addr;
496
497 if (!adapter->mc_enabled)
498 return 0;
499
500 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
501 val &= ~(1UL << (28+port));
502 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
503
504 val = MAC_HI(addr);
505 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
506 val = MAC_LO(addr);
507 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
508
509 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
510 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
511
512 adapter->mc_enabled = 0;
513 return 0;
514 }
515
516 static int
517 netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
518 int index, u8 *addr)
519 {
520 u32 hi = 0, lo = 0;
521 u16 port = adapter->physical_port;
522
523 lo = MAC_LO(addr);
524 hi = MAC_HI(addr);
525
526 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index), hi);
527 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index)+4, lo);
528
529 return 0;
530 }
531
532 void netxen_p2_nic_set_multi(struct net_device *netdev)
533 {
534 struct netxen_adapter *adapter = netdev_priv(netdev);
535 struct dev_mc_list *mc_ptr;
536 u8 null_addr[6];
537 int index = 0;
538
539 memset(null_addr, 0, 6);
540
541 if (netdev->flags & IFF_PROMISC) {
542
543 adapter->set_promisc(adapter,
544 NETXEN_NIU_PROMISC_MODE);
545
546 /* Full promiscuous mode */
547 netxen_nic_disable_mcast_filter(adapter);
548
549 return;
550 }
551
552 if (netdev->mc_count == 0) {
553 adapter->set_promisc(adapter,
554 NETXEN_NIU_NON_PROMISC_MODE);
555 netxen_nic_disable_mcast_filter(adapter);
556 return;
557 }
558
559 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
560 if (netdev->flags & IFF_ALLMULTI ||
561 netdev->mc_count > adapter->max_mc_count) {
562 netxen_nic_disable_mcast_filter(adapter);
563 return;
564 }
565
566 netxen_nic_enable_mcast_filter(adapter);
567
568 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next, index++)
569 netxen_nic_set_mcast_addr(adapter, index, mc_ptr->dmi_addr);
570
571 if (index != netdev->mc_count)
572 printk(KERN_WARNING "%s: %s multicast address count mismatch\n",
573 netxen_nic_driver_name, netdev->name);
574
575 /* Clear out remaining addresses */
576 for (; index < adapter->max_mc_count; index++)
577 netxen_nic_set_mcast_addr(adapter, index, null_addr);
578 }
579
580 static int
581 netxen_send_cmd_descs(struct netxen_adapter *adapter,
582 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
583 {
584 u32 i, producer, consumer;
585 struct netxen_cmd_buffer *pbuf;
586 struct cmd_desc_type0 *cmd_desc;
587 struct nx_host_tx_ring *tx_ring;
588
589 i = 0;
590
591 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)
592 return -EIO;
593
594 tx_ring = adapter->tx_ring;
595 __netif_tx_lock_bh(tx_ring->txq);
596
597 producer = tx_ring->producer;
598 consumer = tx_ring->sw_consumer;
599
600 if (nr_desc >= netxen_tx_avail(tx_ring)) {
601 netif_tx_stop_queue(tx_ring->txq);
602 __netif_tx_unlock_bh(tx_ring->txq);
603 return -EBUSY;
604 }
605
606 do {
607 cmd_desc = &cmd_desc_arr[i];
608
609 pbuf = &tx_ring->cmd_buf_arr[producer];
610 pbuf->skb = NULL;
611 pbuf->frag_count = 0;
612
613 memcpy(&tx_ring->desc_head[producer],
614 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
615
616 producer = get_next_index(producer, tx_ring->num_desc);
617 i++;
618
619 } while (i != nr_desc);
620
621 tx_ring->producer = producer;
622
623 netxen_nic_update_cmd_producer(adapter, tx_ring);
624
625 __netif_tx_unlock_bh(tx_ring->txq);
626
627 return 0;
628 }
629
630 static int
631 nx_p3_sre_macaddr_change(struct netxen_adapter *adapter, u8 *addr, unsigned op)
632 {
633 nx_nic_req_t req;
634 nx_mac_req_t *mac_req;
635 u64 word;
636
637 memset(&req, 0, sizeof(nx_nic_req_t));
638 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
639
640 word = NX_MAC_EVENT | ((u64)adapter->portnum << 16);
641 req.req_hdr = cpu_to_le64(word);
642
643 mac_req = (nx_mac_req_t *)&req.words[0];
644 mac_req->op = op;
645 memcpy(mac_req->mac_addr, addr, 6);
646
647 return netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
648 }
649
650 static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
651 u8 *addr, struct list_head *del_list)
652 {
653 struct list_head *head;
654 nx_mac_list_t *cur;
655
656 /* look up if already exists */
657 list_for_each(head, del_list) {
658 cur = list_entry(head, nx_mac_list_t, list);
659
660 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
661 list_move_tail(head, &adapter->mac_list);
662 return 0;
663 }
664 }
665
666 cur = kzalloc(sizeof(nx_mac_list_t), GFP_ATOMIC);
667 if (cur == NULL) {
668 printk(KERN_ERR "%s: failed to add mac address filter\n",
669 adapter->netdev->name);
670 return -ENOMEM;
671 }
672 memcpy(cur->mac_addr, addr, ETH_ALEN);
673 list_add_tail(&cur->list, &adapter->mac_list);
674 return nx_p3_sre_macaddr_change(adapter,
675 cur->mac_addr, NETXEN_MAC_ADD);
676 }
677
678 void netxen_p3_nic_set_multi(struct net_device *netdev)
679 {
680 struct netxen_adapter *adapter = netdev_priv(netdev);
681 struct dev_mc_list *mc_ptr;
682 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
683 u32 mode = VPORT_MISS_MODE_DROP;
684 LIST_HEAD(del_list);
685 struct list_head *head;
686 nx_mac_list_t *cur;
687
688 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)
689 return;
690
691 list_splice_tail_init(&adapter->mac_list, &del_list);
692
693 nx_p3_nic_add_mac(adapter, adapter->mac_addr, &del_list);
694 nx_p3_nic_add_mac(adapter, bcast_addr, &del_list);
695
696 if (netdev->flags & IFF_PROMISC) {
697 mode = VPORT_MISS_MODE_ACCEPT_ALL;
698 goto send_fw_cmd;
699 }
700
701 if ((netdev->flags & IFF_ALLMULTI) ||
702 (netdev->mc_count > adapter->max_mc_count)) {
703 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
704 goto send_fw_cmd;
705 }
706
707 if (netdev->mc_count > 0) {
708 for (mc_ptr = netdev->mc_list; mc_ptr;
709 mc_ptr = mc_ptr->next) {
710 nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr, &del_list);
711 }
712 }
713
714 send_fw_cmd:
715 adapter->set_promisc(adapter, mode);
716 head = &del_list;
717 while (!list_empty(head)) {
718 cur = list_entry(head->next, nx_mac_list_t, list);
719
720 nx_p3_sre_macaddr_change(adapter,
721 cur->mac_addr, NETXEN_MAC_DEL);
722 list_del(&cur->list);
723 kfree(cur);
724 }
725 }
726
727 int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
728 {
729 nx_nic_req_t req;
730 u64 word;
731
732 memset(&req, 0, sizeof(nx_nic_req_t));
733
734 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
735
736 word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
737 ((u64)adapter->portnum << 16);
738 req.req_hdr = cpu_to_le64(word);
739
740 req.words[0] = cpu_to_le64(mode);
741
742 return netxen_send_cmd_descs(adapter,
743 (struct cmd_desc_type0 *)&req, 1);
744 }
745
746 void netxen_p3_free_mac_list(struct netxen_adapter *adapter)
747 {
748 nx_mac_list_t *cur;
749 struct list_head *head = &adapter->mac_list;
750
751 while (!list_empty(head)) {
752 cur = list_entry(head->next, nx_mac_list_t, list);
753 nx_p3_sre_macaddr_change(adapter,
754 cur->mac_addr, NETXEN_MAC_DEL);
755 list_del(&cur->list);
756 kfree(cur);
757 }
758 }
759
760 int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
761 {
762 /* assuming caller has already copied new addr to netdev */
763 netxen_p3_nic_set_multi(adapter->netdev);
764 return 0;
765 }
766
767 #define NETXEN_CONFIG_INTR_COALESCE 3
768
769 /*
770 * Send the interrupt coalescing parameter set by ethtool to the card.
771 */
772 int netxen_config_intr_coalesce(struct netxen_adapter *adapter)
773 {
774 nx_nic_req_t req;
775 u64 word;
776 int rv;
777
778 memset(&req, 0, sizeof(nx_nic_req_t));
779
780 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
781
782 word = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
783 req.req_hdr = cpu_to_le64(word);
784
785 memcpy(&req.words[0], &adapter->coal, sizeof(adapter->coal));
786
787 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
788 if (rv != 0) {
789 printk(KERN_ERR "ERROR. Could not send "
790 "interrupt coalescing parameters\n");
791 }
792
793 return rv;
794 }
795
796 int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable)
797 {
798 nx_nic_req_t req;
799 u64 word;
800 int rv = 0;
801
802 if ((adapter->flags & NETXEN_NIC_LRO_ENABLED) == enable)
803 return 0;
804
805 memset(&req, 0, sizeof(nx_nic_req_t));
806
807 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
808
809 word = NX_NIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
810 req.req_hdr = cpu_to_le64(word);
811
812 req.words[0] = cpu_to_le64(enable);
813
814 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
815 if (rv != 0) {
816 printk(KERN_ERR "ERROR. Could not send "
817 "configure hw lro request\n");
818 }
819
820 adapter->flags ^= NETXEN_NIC_LRO_ENABLED;
821
822 return rv;
823 }
824
825 int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable)
826 {
827 nx_nic_req_t req;
828 u64 word;
829 int rv = 0;
830
831 if (!!(adapter->flags & NETXEN_NIC_BRIDGE_ENABLED) == enable)
832 return rv;
833
834 memset(&req, 0, sizeof(nx_nic_req_t));
835
836 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
837
838 word = NX_NIC_H2C_OPCODE_CONFIG_BRIDGING |
839 ((u64)adapter->portnum << 16);
840 req.req_hdr = cpu_to_le64(word);
841
842 req.words[0] = cpu_to_le64(enable);
843
844 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
845 if (rv != 0) {
846 printk(KERN_ERR "ERROR. Could not send "
847 "configure bridge mode request\n");
848 }
849
850 adapter->flags ^= NETXEN_NIC_BRIDGE_ENABLED;
851
852 return rv;
853 }
854
855
856 #define RSS_HASHTYPE_IP_TCP 0x3
857
858 int netxen_config_rss(struct netxen_adapter *adapter, int enable)
859 {
860 nx_nic_req_t req;
861 u64 word;
862 int i, rv;
863
864 u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
865 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
866 0x255b0ec26d5a56daULL };
867
868
869 memset(&req, 0, sizeof(nx_nic_req_t));
870 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
871
872 word = NX_NIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
873 req.req_hdr = cpu_to_le64(word);
874
875 /*
876 * RSS request:
877 * bits 3-0: hash_method
878 * 5-4: hash_type_ipv4
879 * 7-6: hash_type_ipv6
880 * 8: enable
881 * 9: use indirection table
882 * 47-10: reserved
883 * 63-48: indirection table mask
884 */
885 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
886 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
887 ((u64)(enable & 0x1) << 8) |
888 ((0x7ULL) << 48);
889 req.words[0] = cpu_to_le64(word);
890 for (i = 0; i < 5; i++)
891 req.words[i+1] = cpu_to_le64(key[i]);
892
893
894 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
895 if (rv != 0) {
896 printk(KERN_ERR "%s: could not configure RSS\n",
897 adapter->netdev->name);
898 }
899
900 return rv;
901 }
902
903 int netxen_config_ipaddr(struct netxen_adapter *adapter, u32 ip, int cmd)
904 {
905 nx_nic_req_t req;
906 u64 word;
907 int rv;
908
909 memset(&req, 0, sizeof(nx_nic_req_t));
910 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
911
912 word = NX_NIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
913 req.req_hdr = cpu_to_le64(word);
914
915 req.words[0] = cpu_to_le64(cmd);
916 req.words[1] = cpu_to_le64(ip);
917
918 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
919 if (rv != 0) {
920 printk(KERN_ERR "%s: could not notify %s IP 0x%x reuqest\n",
921 adapter->netdev->name,
922 (cmd == NX_IP_UP) ? "Add" : "Remove", ip);
923 }
924 return rv;
925 }
926
927 int netxen_linkevent_request(struct netxen_adapter *adapter, int enable)
928 {
929 nx_nic_req_t req;
930 u64 word;
931 int rv;
932
933 memset(&req, 0, sizeof(nx_nic_req_t));
934 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
935
936 word = NX_NIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
937 req.req_hdr = cpu_to_le64(word);
938 req.words[0] = cpu_to_le64(enable | (enable << 8));
939
940 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
941 if (rv != 0) {
942 printk(KERN_ERR "%s: could not configure link notification\n",
943 adapter->netdev->name);
944 }
945
946 return rv;
947 }
948
949 int netxen_send_lro_cleanup(struct netxen_adapter *adapter)
950 {
951 nx_nic_req_t req;
952 u64 word;
953 int rv;
954
955 memset(&req, 0, sizeof(nx_nic_req_t));
956 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
957
958 word = NX_NIC_H2C_OPCODE_LRO_REQUEST |
959 ((u64)adapter->portnum << 16) |
960 ((u64)NX_NIC_LRO_REQUEST_CLEANUP << 56) ;
961
962 req.req_hdr = cpu_to_le64(word);
963
964 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
965 if (rv != 0) {
966 printk(KERN_ERR "%s: could not cleanup lro flows\n",
967 adapter->netdev->name);
968 }
969 return rv;
970 }
971
972 /*
973 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
974 * @returns 0 on success, negative on failure
975 */
976
977 #define MTU_FUDGE_FACTOR 100
978
979 int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
980 {
981 struct netxen_adapter *adapter = netdev_priv(netdev);
982 int max_mtu;
983 int rc = 0;
984
985 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
986 max_mtu = P3_MAX_MTU;
987 else
988 max_mtu = P2_MAX_MTU;
989
990 if (mtu > max_mtu) {
991 printk(KERN_ERR "%s: mtu > %d bytes unsupported\n",
992 netdev->name, max_mtu);
993 return -EINVAL;
994 }
995
996 if (adapter->set_mtu)
997 rc = adapter->set_mtu(adapter, mtu);
998
999 if (!rc)
1000 netdev->mtu = mtu;
1001
1002 return rc;
1003 }
1004
1005 static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
1006 int size, __le32 * buf)
1007 {
1008 int i, v, addr;
1009 __le32 *ptr32;
1010
1011 addr = base;
1012 ptr32 = buf;
1013 for (i = 0; i < size / sizeof(u32); i++) {
1014 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
1015 return -1;
1016 *ptr32 = cpu_to_le32(v);
1017 ptr32++;
1018 addr += sizeof(u32);
1019 }
1020 if ((char *)buf + size > (char *)ptr32) {
1021 __le32 local;
1022 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
1023 return -1;
1024 local = cpu_to_le32(v);
1025 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
1026 }
1027
1028 return 0;
1029 }
1030
1031 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
1032 {
1033 __le32 *pmac = (__le32 *) mac;
1034 u32 offset;
1035
1036 offset = NX_FW_MAC_ADDR_OFFSET + (adapter->portnum * sizeof(u64));
1037
1038 if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1)
1039 return -1;
1040
1041 if (*mac == cpu_to_le64(~0ULL)) {
1042
1043 offset = NX_OLD_MAC_ADDR_OFFSET +
1044 (adapter->portnum * sizeof(u64));
1045
1046 if (netxen_get_flash_block(adapter,
1047 offset, sizeof(u64), pmac) == -1)
1048 return -1;
1049
1050 if (*mac == cpu_to_le64(~0ULL))
1051 return -1;
1052 }
1053 return 0;
1054 }
1055
1056 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
1057 {
1058 uint32_t crbaddr, mac_hi, mac_lo;
1059 int pci_func = adapter->ahw.pci_func;
1060
1061 crbaddr = CRB_MAC_BLOCK_START +
1062 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
1063
1064 mac_lo = NXRD32(adapter, crbaddr);
1065 mac_hi = NXRD32(adapter, crbaddr+4);
1066
1067 if (pci_func & 1)
1068 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
1069 else
1070 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
1071
1072 return 0;
1073 }
1074
1075 /*
1076 * Changes the CRB window to the specified window.
1077 */
1078 static void
1079 netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, u32 wndw)
1080 {
1081 void __iomem *offset;
1082 u32 tmp;
1083 int count = 0;
1084 uint8_t func = adapter->ahw.pci_func;
1085
1086 if (adapter->curr_window == wndw)
1087 return;
1088 /*
1089 * Move the CRB window.
1090 * We need to write to the "direct access" region of PCI
1091 * to avoid a race condition where the window register has
1092 * not been successfully written across CRB before the target
1093 * register address is received by PCI. The direct region bypasses
1094 * the CRB bus.
1095 */
1096 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1097 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
1098
1099 if (wndw & 0x1)
1100 wndw = NETXEN_WINDOW_ONE;
1101
1102 writel(wndw, offset);
1103
1104 /* MUST make sure window is set before we forge on... */
1105 while ((tmp = readl(offset)) != wndw) {
1106 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
1107 "registered properly: 0x%08x.\n",
1108 netxen_nic_driver_name, __func__, tmp);
1109 mdelay(1);
1110 if (count >= 10)
1111 break;
1112 count++;
1113 }
1114
1115 if (wndw == NETXEN_WINDOW_ONE)
1116 adapter->curr_window = 1;
1117 else
1118 adapter->curr_window = 0;
1119 }
1120
1121 /*
1122 * Return -1 if off is not valid,
1123 * 1 if window access is needed. 'off' is set to offset from
1124 * CRB space in 128M pci map
1125 * 0 if no window access is needed. 'off' is set to 2M addr
1126 * In: 'off' is offset from base in 128M pci map
1127 */
1128 static int
1129 netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter, ulong *off)
1130 {
1131 crb_128M_2M_sub_block_map_t *m;
1132
1133
1134 if (*off >= NETXEN_CRB_MAX)
1135 return -1;
1136
1137 if (*off >= NETXEN_PCI_CAMQM && (*off < NETXEN_PCI_CAMQM_2M_END)) {
1138 *off = (*off - NETXEN_PCI_CAMQM) + NETXEN_PCI_CAMQM_2M_BASE +
1139 (ulong)adapter->ahw.pci_base0;
1140 return 0;
1141 }
1142
1143 if (*off < NETXEN_PCI_CRBSPACE)
1144 return -1;
1145
1146 *off -= NETXEN_PCI_CRBSPACE;
1147
1148 /*
1149 * Try direct map
1150 */
1151 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
1152
1153 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
1154 *off = *off + m->start_2M - m->start_128M +
1155 (ulong)adapter->ahw.pci_base0;
1156 return 0;
1157 }
1158
1159 /*
1160 * Not in direct map, use crb window
1161 */
1162 return 1;
1163 }
1164
1165 /*
1166 * In: 'off' is offset from CRB space in 128M pci map
1167 * Out: 'off' is 2M pci map addr
1168 * side effect: lock crb window
1169 */
1170 static void
1171 netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong *off)
1172 {
1173 u32 win_read;
1174
1175 adapter->crb_win = CRB_HI(*off);
1176 writel(adapter->crb_win, (adapter->ahw.pci_base0 + CRB_WINDOW_2M));
1177 /*
1178 * Read back value to make sure write has gone through before trying
1179 * to use it.
1180 */
1181 win_read = readl(adapter->ahw.pci_base0 + CRB_WINDOW_2M);
1182 if (win_read != adapter->crb_win) {
1183 printk(KERN_ERR "%s: Written crbwin (0x%x) != "
1184 "Read crbwin (0x%x), off=0x%lx\n",
1185 __func__, adapter->crb_win, win_read, *off);
1186 }
1187 *off = (*off & MASK(16)) + CRB_INDIRECT_2M +
1188 (ulong)adapter->ahw.pci_base0;
1189 }
1190
1191 static int
1192 netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, ulong off, u32 data)
1193 {
1194 unsigned long flags;
1195 void __iomem *addr;
1196
1197 if (ADDR_IN_WINDOW1(off))
1198 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1199 else
1200 addr = pci_base_offset(adapter, off);
1201
1202 BUG_ON(!addr);
1203
1204 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1205 read_lock(&adapter->adapter_lock);
1206 writel(data, addr);
1207 read_unlock(&adapter->adapter_lock);
1208 } else { /* Window 0 */
1209 write_lock_irqsave(&adapter->adapter_lock, flags);
1210 addr = pci_base_offset(adapter, off);
1211 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1212 writel(data, addr);
1213 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1214 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1215 }
1216
1217 return 0;
1218 }
1219
1220 static u32
1221 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off)
1222 {
1223 unsigned long flags;
1224 void __iomem *addr;
1225 u32 data;
1226
1227 if (ADDR_IN_WINDOW1(off))
1228 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1229 else
1230 addr = pci_base_offset(adapter, off);
1231
1232 BUG_ON(!addr);
1233
1234 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1235 read_lock(&adapter->adapter_lock);
1236 data = readl(addr);
1237 read_unlock(&adapter->adapter_lock);
1238 } else { /* Window 0 */
1239 write_lock_irqsave(&adapter->adapter_lock, flags);
1240 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1241 data = readl(addr);
1242 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1243 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1244 }
1245
1246 return data;
1247 }
1248
1249 static int
1250 netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, ulong off, u32 data)
1251 {
1252 unsigned long flags;
1253 int rv;
1254
1255 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off);
1256
1257 if (rv == -1) {
1258 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1259 __func__, off);
1260 dump_stack();
1261 return -1;
1262 }
1263
1264 if (rv == 1) {
1265 write_lock_irqsave(&adapter->adapter_lock, flags);
1266 crb_win_lock(adapter);
1267 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1268 writel(data, (void __iomem *)off);
1269 crb_win_unlock(adapter);
1270 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1271 } else
1272 writel(data, (void __iomem *)off);
1273
1274
1275 return 0;
1276 }
1277
1278 static u32
1279 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off)
1280 {
1281 unsigned long flags;
1282 int rv;
1283 u32 data;
1284
1285 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off);
1286
1287 if (rv == -1) {
1288 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1289 __func__, off);
1290 dump_stack();
1291 return -1;
1292 }
1293
1294 if (rv == 1) {
1295 write_lock_irqsave(&adapter->adapter_lock, flags);
1296 crb_win_lock(adapter);
1297 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1298 data = readl((void __iomem *)off);
1299 crb_win_unlock(adapter);
1300 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1301 } else
1302 data = readl((void __iomem *)off);
1303
1304 return data;
1305 }
1306
1307 static int netxen_pci_set_window_warning_count;
1308
1309 static unsigned long
1310 netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1311 unsigned long long addr)
1312 {
1313 void __iomem *offset;
1314 int window;
1315 unsigned long long qdr_max;
1316 uint8_t func = adapter->ahw.pci_func;
1317
1318 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1319 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1320 } else {
1321 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1322 }
1323
1324 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1325 /* DDR network side */
1326 addr -= NETXEN_ADDR_DDR_NET;
1327 window = (addr >> 25) & 0x3ff;
1328 if (adapter->ahw.ddr_mn_window != window) {
1329 adapter->ahw.ddr_mn_window = window;
1330 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1331 NETXEN_PCIX_PH_REG(PCIE_MN_WINDOW_REG(func)));
1332 writel(window, offset);
1333 /* MUST make sure window is set before we forge on... */
1334 readl(offset);
1335 }
1336 addr -= (window * NETXEN_WINDOW_ONE);
1337 addr += NETXEN_PCI_DDR_NET;
1338 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1339 addr -= NETXEN_ADDR_OCM0;
1340 addr += NETXEN_PCI_OCM0;
1341 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1342 addr -= NETXEN_ADDR_OCM1;
1343 addr += NETXEN_PCI_OCM1;
1344 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1345 /* QDR network side */
1346 addr -= NETXEN_ADDR_QDR_NET;
1347 window = (addr >> 22) & 0x3f;
1348 if (adapter->ahw.qdr_sn_window != window) {
1349 adapter->ahw.qdr_sn_window = window;
1350 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1351 NETXEN_PCIX_PH_REG(PCIE_SN_WINDOW_REG(func)));
1352 writel((window << 22), offset);
1353 /* MUST make sure window is set before we forge on... */
1354 readl(offset);
1355 }
1356 addr -= (window * 0x400000);
1357 addr += NETXEN_PCI_QDR_NET;
1358 } else {
1359 /*
1360 * peg gdb frequently accesses memory that doesn't exist,
1361 * this limits the chit chat so debugging isn't slowed down.
1362 */
1363 if ((netxen_pci_set_window_warning_count++ < 8)
1364 || (netxen_pci_set_window_warning_count % 64 == 0))
1365 printk("%s: Warning:netxen_nic_pci_set_window()"
1366 " Unknown address range!\n",
1367 netxen_nic_driver_name);
1368 addr = -1UL;
1369 }
1370 return addr;
1371 }
1372
1373 /* window 1 registers only */
1374 static void netxen_nic_io_write_128M(struct netxen_adapter *adapter,
1375 void __iomem *addr, u32 data)
1376 {
1377 read_lock(&adapter->adapter_lock);
1378 writel(data, addr);
1379 read_unlock(&adapter->adapter_lock);
1380 }
1381
1382 static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter,
1383 void __iomem *addr)
1384 {
1385 u32 val;
1386
1387 read_lock(&adapter->adapter_lock);
1388 val = readl(addr);
1389 read_unlock(&adapter->adapter_lock);
1390
1391 return val;
1392 }
1393
1394 static void netxen_nic_io_write_2M(struct netxen_adapter *adapter,
1395 void __iomem *addr, u32 data)
1396 {
1397 writel(data, addr);
1398 }
1399
1400 static u32 netxen_nic_io_read_2M(struct netxen_adapter *adapter,
1401 void __iomem *addr)
1402 {
1403 return readl(addr);
1404 }
1405
1406 void __iomem *
1407 netxen_get_ioaddr(struct netxen_adapter *adapter, u32 offset)
1408 {
1409 ulong off = offset;
1410
1411 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1412 if (offset < NETXEN_CRB_PCIX_HOST2 &&
1413 offset > NETXEN_CRB_PCIX_HOST)
1414 return PCI_OFFSET_SECOND_RANGE(adapter, offset);
1415 return NETXEN_CRB_NORMALIZE(adapter, offset);
1416 }
1417
1418 BUG_ON(netxen_nic_pci_get_crb_addr_2M(adapter, &off));
1419 return (void __iomem *)off;
1420 }
1421
1422 static unsigned long
1423 netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1424 unsigned long long addr)
1425 {
1426 int window;
1427 u32 win_read;
1428
1429 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1430 /* DDR network side */
1431 window = MN_WIN(addr);
1432 adapter->ahw.ddr_mn_window = window;
1433 NXWR32(adapter, adapter->ahw.mn_win_crb, window);
1434 win_read = NXRD32(adapter, adapter->ahw.mn_win_crb);
1435 if ((win_read << 17) != window) {
1436 printk(KERN_INFO "Written MNwin (0x%x) != "
1437 "Read MNwin (0x%x)\n", window, win_read);
1438 }
1439 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_DDR_NET;
1440 } else if (ADDR_IN_RANGE(addr,
1441 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1442 if ((addr & 0x00ff800) == 0xff800) {
1443 printk("%s: QM access not handled.\n", __func__);
1444 addr = -1UL;
1445 }
1446
1447 window = OCM_WIN(addr);
1448 adapter->ahw.ddr_mn_window = window;
1449 NXWR32(adapter, adapter->ahw.mn_win_crb, window);
1450 win_read = NXRD32(adapter, adapter->ahw.mn_win_crb);
1451 if ((win_read >> 7) != window) {
1452 printk(KERN_INFO "%s: Written OCMwin (0x%x) != "
1453 "Read OCMwin (0x%x)\n",
1454 __func__, window, win_read);
1455 }
1456 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_OCM0_2M;
1457
1458 } else if (ADDR_IN_RANGE(addr,
1459 NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX_P3)) {
1460 /* QDR network side */
1461 window = MS_WIN(addr);
1462 adapter->ahw.qdr_sn_window = window;
1463 NXWR32(adapter, adapter->ahw.ms_win_crb, window);
1464 win_read = NXRD32(adapter, adapter->ahw.ms_win_crb);
1465 if (win_read != window) {
1466 printk(KERN_INFO "%s: Written MSwin (0x%x) != "
1467 "Read MSwin (0x%x)\n",
1468 __func__, window, win_read);
1469 }
1470 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_QDR_NET;
1471
1472 } else {
1473 /*
1474 * peg gdb frequently accesses memory that doesn't exist,
1475 * this limits the chit chat so debugging isn't slowed down.
1476 */
1477 if ((netxen_pci_set_window_warning_count++ < 8)
1478 || (netxen_pci_set_window_warning_count%64 == 0)) {
1479 printk("%s: Warning:%s Unknown address range!\n",
1480 __func__, netxen_nic_driver_name);
1481 }
1482 addr = -1UL;
1483 }
1484 return addr;
1485 }
1486
1487 #define MAX_CTL_CHECK 1000
1488
1489 static int
1490 netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1491 u64 off, void *data, int size)
1492 {
1493 unsigned long flags;
1494 int i, j, ret = 0, loop, sz[2], off0;
1495 uint32_t temp;
1496 uint64_t off8, tmpw, word[2] = {0, 0};
1497 void __iomem *mem_crb;
1498
1499 if (size != 8)
1500 return -EIO;
1501
1502 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1503 NETXEN_ADDR_QDR_NET_MAX_P2)) {
1504 mem_crb = pci_base_offset(adapter, NETXEN_CRB_QDR_NET);
1505 goto correct;
1506 }
1507
1508 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1509 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1510 goto correct;
1511 }
1512
1513 return -EIO;
1514
1515 correct:
1516 off8 = off & 0xfffffff8;
1517 off0 = off & 0x7;
1518 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1519 sz[1] = size - sz[0];
1520 loop = ((off0 + size - 1) >> 3) + 1;
1521
1522 if ((size != 8) || (off0 != 0)) {
1523 for (i = 0; i < loop; i++) {
1524 if (adapter->pci_mem_read(adapter,
1525 off8 + (i << 3), &word[i], 8))
1526 return -1;
1527 }
1528 }
1529
1530 switch (size) {
1531 case 1:
1532 tmpw = *((uint8_t *)data);
1533 break;
1534 case 2:
1535 tmpw = *((uint16_t *)data);
1536 break;
1537 case 4:
1538 tmpw = *((uint32_t *)data);
1539 break;
1540 case 8:
1541 default:
1542 tmpw = *((uint64_t *)data);
1543 break;
1544 }
1545 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1546 word[0] |= tmpw << (off0 * 8);
1547
1548 if (loop == 2) {
1549 word[1] &= ~(~0ULL << (sz[1] * 8));
1550 word[1] |= tmpw >> (sz[0] * 8);
1551 }
1552
1553 write_lock_irqsave(&adapter->adapter_lock, flags);
1554 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1555
1556 for (i = 0; i < loop; i++) {
1557 writel((uint32_t)(off8 + (i << 3)),
1558 (mem_crb+MIU_TEST_AGT_ADDR_LO));
1559 writel(0,
1560 (mem_crb+MIU_TEST_AGT_ADDR_HI));
1561 writel(word[i] & 0xffffffff,
1562 (mem_crb+MIU_TEST_AGT_WRDATA_LO));
1563 writel((word[i] >> 32) & 0xffffffff,
1564 (mem_crb+MIU_TEST_AGT_WRDATA_HI));
1565 writel(MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1566 (mem_crb+MIU_TEST_AGT_CTRL));
1567 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1568 (mem_crb+MIU_TEST_AGT_CTRL));
1569
1570 for (j = 0; j < MAX_CTL_CHECK; j++) {
1571 temp = readl(
1572 (mem_crb+MIU_TEST_AGT_CTRL));
1573 if ((temp & MIU_TA_CTL_BUSY) == 0)
1574 break;
1575 }
1576
1577 if (j >= MAX_CTL_CHECK) {
1578 if (printk_ratelimit())
1579 dev_err(&adapter->pdev->dev,
1580 "failed to write through agent\n");
1581 ret = -1;
1582 break;
1583 }
1584 }
1585
1586 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1587 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1588 return ret;
1589 }
1590
1591 static int
1592 netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1593 u64 off, void *data, int size)
1594 {
1595 unsigned long flags;
1596 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1597 uint32_t temp;
1598 uint64_t off8, val, word[2] = {0, 0};
1599 void __iomem *mem_crb;
1600
1601 if (size != 8)
1602 return -EIO;
1603
1604 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1605 NETXEN_ADDR_QDR_NET_MAX_P2)) {
1606 mem_crb = pci_base_offset(adapter, NETXEN_CRB_QDR_NET);
1607 goto correct;
1608 }
1609
1610 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1611 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1612 goto correct;
1613 }
1614
1615 return -EIO;
1616
1617 correct:
1618 off8 = off & 0xfffffff8;
1619 off0[0] = off & 0x7;
1620 off0[1] = 0;
1621 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1622 sz[1] = size - sz[0];
1623 loop = ((off0[0] + size - 1) >> 3) + 1;
1624
1625 write_lock_irqsave(&adapter->adapter_lock, flags);
1626 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1627
1628 for (i = 0; i < loop; i++) {
1629 writel((uint32_t)(off8 + (i << 3)),
1630 (mem_crb+MIU_TEST_AGT_ADDR_LO));
1631 writel(0,
1632 (mem_crb+MIU_TEST_AGT_ADDR_HI));
1633 writel(MIU_TA_CTL_ENABLE,
1634 (mem_crb+MIU_TEST_AGT_CTRL));
1635 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE,
1636 (mem_crb+MIU_TEST_AGT_CTRL));
1637
1638 for (j = 0; j < MAX_CTL_CHECK; j++) {
1639 temp = readl(
1640 (mem_crb+MIU_TEST_AGT_CTRL));
1641 if ((temp & MIU_TA_CTL_BUSY) == 0)
1642 break;
1643 }
1644
1645 if (j >= MAX_CTL_CHECK) {
1646 if (printk_ratelimit())
1647 dev_err(&adapter->pdev->dev,
1648 "failed to read through agent\n");
1649 break;
1650 }
1651
1652 start = off0[i] >> 2;
1653 end = (off0[i] + sz[i] - 1) >> 2;
1654 for (k = start; k <= end; k++) {
1655 word[i] |= ((uint64_t) readl(
1656 (mem_crb +
1657 MIU_TEST_AGT_RDDATA(k))) << (32*k));
1658 }
1659 }
1660
1661 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1662 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1663
1664 if (j >= MAX_CTL_CHECK)
1665 return -1;
1666
1667 if (sz[0] == 8) {
1668 val = word[0];
1669 } else {
1670 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1671 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1672 }
1673
1674 switch (size) {
1675 case 1:
1676 *(uint8_t *)data = val;
1677 break;
1678 case 2:
1679 *(uint16_t *)data = val;
1680 break;
1681 case 4:
1682 *(uint32_t *)data = val;
1683 break;
1684 case 8:
1685 *(uint64_t *)data = val;
1686 break;
1687 }
1688 return 0;
1689 }
1690
1691 static int
1692 netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1693 u64 off, void *data, int size)
1694 {
1695 int i, j, ret = 0, loop, sz[2], off0;
1696 uint32_t temp;
1697 uint64_t off8, tmpw, word[2] = {0, 0};
1698 void __iomem *mem_crb;
1699
1700 if (size != 8)
1701 return -EIO;
1702
1703 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1704 NETXEN_ADDR_QDR_NET_MAX_P3)) {
1705 mem_crb = netxen_get_ioaddr(adapter, NETXEN_CRB_QDR_NET);
1706 goto correct;
1707 }
1708
1709 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1710 mem_crb = netxen_get_ioaddr(adapter, NETXEN_CRB_DDR_NET);
1711 goto correct;
1712 }
1713
1714 return -EIO;
1715
1716 correct:
1717 off8 = off & 0xfffffff8;
1718 off0 = off & 0x7;
1719 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1720 sz[1] = size - sz[0];
1721 loop = ((off0 + size - 1) >> 3) + 1;
1722
1723 if ((size != 8) || (off0 != 0)) {
1724 for (i = 0; i < loop; i++) {
1725 if (adapter->pci_mem_read(adapter,
1726 off8 + (i << 3), &word[i], 8))
1727 return -1;
1728 }
1729 }
1730
1731 switch (size) {
1732 case 1:
1733 tmpw = *((uint8_t *)data);
1734 break;
1735 case 2:
1736 tmpw = *((uint16_t *)data);
1737 break;
1738 case 4:
1739 tmpw = *((uint32_t *)data);
1740 break;
1741 case 8:
1742 default:
1743 tmpw = *((uint64_t *)data);
1744 break;
1745 }
1746
1747 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1748 word[0] |= tmpw << (off0 * 8);
1749
1750 if (loop == 2) {
1751 word[1] &= ~(~0ULL << (sz[1] * 8));
1752 word[1] |= tmpw >> (sz[0] * 8);
1753 }
1754
1755 /*
1756 * don't lock here - write_wx gets the lock if each time
1757 * write_lock_irqsave(&adapter->adapter_lock, flags);
1758 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1759 */
1760
1761 for (i = 0; i < loop; i++) {
1762 writel(off8 + (i << 3), mem_crb+MIU_TEST_AGT_ADDR_LO);
1763 writel(0, mem_crb+MIU_TEST_AGT_ADDR_HI);
1764 writel(word[i] & 0xffffffff, mem_crb+MIU_TEST_AGT_WRDATA_LO);
1765 writel((word[i] >> 32) & 0xffffffff,
1766 mem_crb+MIU_TEST_AGT_WRDATA_HI);
1767 writel((MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE),
1768 mem_crb+MIU_TEST_AGT_CTRL);
1769 writel(MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE,
1770 mem_crb+MIU_TEST_AGT_CTRL);
1771
1772 for (j = 0; j < MAX_CTL_CHECK; j++) {
1773 temp = readl(mem_crb + MIU_TEST_AGT_CTRL);
1774 if ((temp & MIU_TA_CTL_BUSY) == 0)
1775 break;
1776 }
1777
1778 if (j >= MAX_CTL_CHECK) {
1779 if (printk_ratelimit())
1780 dev_err(&adapter->pdev->dev,
1781 "failed to write through agent\n");
1782 ret = -1;
1783 break;
1784 }
1785 }
1786
1787 /*
1788 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1789 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1790 */
1791 return ret;
1792 }
1793
1794 static int
1795 netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1796 u64 off, void *data, int size)
1797 {
1798 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1799 uint32_t temp;
1800 uint64_t off8, val, word[2] = {0, 0};
1801 void __iomem *mem_crb;
1802
1803 if (size != 8)
1804 return -EIO;
1805
1806 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1807 NETXEN_ADDR_QDR_NET_MAX_P3)) {
1808 mem_crb = netxen_get_ioaddr(adapter, NETXEN_CRB_QDR_NET);
1809 goto correct;
1810 }
1811
1812 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1813 mem_crb = netxen_get_ioaddr(adapter, NETXEN_CRB_DDR_NET);
1814 goto correct;
1815 }
1816
1817 return -EIO;
1818
1819 correct:
1820 off8 = off & 0xfffffff8;
1821 off0[0] = off & 0x7;
1822 off0[1] = 0;
1823 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1824 sz[1] = size - sz[0];
1825 loop = ((off0[0] + size - 1) >> 3) + 1;
1826
1827 /*
1828 * don't lock here - write_wx gets the lock if each time
1829 * write_lock_irqsave(&adapter->adapter_lock, flags);
1830 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1831 */
1832
1833 for (i = 0; i < loop; i++) {
1834 writel(off8 + (i << 3), mem_crb + MIU_TEST_AGT_ADDR_LO);
1835 writel(0, mem_crb + MIU_TEST_AGT_ADDR_HI);
1836 writel(MIU_TA_CTL_ENABLE, mem_crb + MIU_TEST_AGT_CTRL);
1837 writel(MIU_TA_CTL_START | MIU_TA_CTL_ENABLE,
1838 mem_crb + MIU_TEST_AGT_CTRL);
1839
1840 for (j = 0; j < MAX_CTL_CHECK; j++) {
1841 temp = readl(mem_crb + MIU_TEST_AGT_CTRL);
1842 if ((temp & MIU_TA_CTL_BUSY) == 0)
1843 break;
1844 }
1845
1846 if (j >= MAX_CTL_CHECK) {
1847 if (printk_ratelimit())
1848 dev_err(&adapter->pdev->dev,
1849 "failed to read through agent\n");
1850 break;
1851 }
1852
1853 start = off0[i] >> 2;
1854 end = (off0[i] + sz[i] - 1) >> 2;
1855 for (k = start; k <= end; k++) {
1856 temp = readl(mem_crb + MIU_TEST_AGT_RDDATA(k));
1857 word[i] |= ((uint64_t)temp << (32 * k));
1858 }
1859 }
1860
1861 /*
1862 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1863 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1864 */
1865
1866 if (j >= MAX_CTL_CHECK)
1867 return -1;
1868
1869 if (sz[0] == 8) {
1870 val = word[0];
1871 } else {
1872 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1873 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1874 }
1875
1876 switch (size) {
1877 case 1:
1878 *(uint8_t *)data = val;
1879 break;
1880 case 2:
1881 *(uint16_t *)data = val;
1882 break;
1883 case 4:
1884 *(uint32_t *)data = val;
1885 break;
1886 case 8:
1887 *(uint64_t *)data = val;
1888 break;
1889 }
1890 return 0;
1891 }
1892
1893 void
1894 netxen_setup_hwops(struct netxen_adapter *adapter)
1895 {
1896 adapter->init_port = netxen_niu_xg_init_port;
1897 adapter->stop_port = netxen_niu_disable_xg_port;
1898
1899 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1900 adapter->crb_read = netxen_nic_hw_read_wx_128M,
1901 adapter->crb_write = netxen_nic_hw_write_wx_128M,
1902 adapter->pci_set_window = netxen_nic_pci_set_window_128M,
1903 adapter->pci_mem_read = netxen_nic_pci_mem_read_128M,
1904 adapter->pci_mem_write = netxen_nic_pci_mem_write_128M,
1905 adapter->io_read = netxen_nic_io_read_128M,
1906 adapter->io_write = netxen_nic_io_write_128M,
1907
1908 adapter->macaddr_set = netxen_p2_nic_set_mac_addr;
1909 adapter->set_multi = netxen_p2_nic_set_multi;
1910 adapter->set_mtu = netxen_nic_set_mtu_xgb;
1911 adapter->set_promisc = netxen_p2_nic_set_promisc;
1912
1913 } else {
1914 adapter->crb_read = netxen_nic_hw_read_wx_2M,
1915 adapter->crb_write = netxen_nic_hw_write_wx_2M,
1916 adapter->pci_set_window = netxen_nic_pci_set_window_2M,
1917 adapter->pci_mem_read = netxen_nic_pci_mem_read_2M,
1918 adapter->pci_mem_write = netxen_nic_pci_mem_write_2M,
1919 adapter->io_read = netxen_nic_io_read_2M,
1920 adapter->io_write = netxen_nic_io_write_2M,
1921
1922 adapter->set_mtu = nx_fw_cmd_set_mtu;
1923 adapter->set_promisc = netxen_p3_nic_set_promisc;
1924 adapter->macaddr_set = netxen_p3_nic_set_mac_addr;
1925 adapter->set_multi = netxen_p3_nic_set_multi;
1926
1927 adapter->phy_read = nx_fw_cmd_query_phy;
1928 adapter->phy_write = nx_fw_cmd_set_phy;
1929 }
1930 }
1931
1932 int netxen_nic_get_board_info(struct netxen_adapter *adapter)
1933 {
1934 int offset, board_type, magic;
1935 struct pci_dev *pdev = adapter->pdev;
1936
1937 offset = NX_FW_MAGIC_OFFSET;
1938 if (netxen_rom_fast_read(adapter, offset, &magic))
1939 return -EIO;
1940
1941 if (magic != NETXEN_BDINFO_MAGIC) {
1942 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1943 magic);
1944 return -EIO;
1945 }
1946
1947 offset = NX_BRDTYPE_OFFSET;
1948 if (netxen_rom_fast_read(adapter, offset, &board_type))
1949 return -EIO;
1950
1951 adapter->ahw.board_type = board_type;
1952
1953 if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) {
1954 u32 gpio = NXRD32(adapter, NETXEN_ROMUSB_GLB_PAD_GPIO_I);
1955 if ((gpio & 0x8000) == 0)
1956 board_type = NETXEN_BRDTYPE_P3_10G_TP;
1957 }
1958
1959 switch (board_type) {
1960 case NETXEN_BRDTYPE_P2_SB35_4G:
1961 adapter->ahw.port_type = NETXEN_NIC_GBE;
1962 break;
1963 case NETXEN_BRDTYPE_P2_SB31_10G:
1964 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
1965 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
1966 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
1967 case NETXEN_BRDTYPE_P3_HMEZ:
1968 case NETXEN_BRDTYPE_P3_XG_LOM:
1969 case NETXEN_BRDTYPE_P3_10G_CX4:
1970 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
1971 case NETXEN_BRDTYPE_P3_IMEZ:
1972 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
1973 case NETXEN_BRDTYPE_P3_10G_SFP_CT:
1974 case NETXEN_BRDTYPE_P3_10G_SFP_QT:
1975 case NETXEN_BRDTYPE_P3_10G_XFP:
1976 case NETXEN_BRDTYPE_P3_10000_BASE_T:
1977 adapter->ahw.port_type = NETXEN_NIC_XGBE;
1978 break;
1979 case NETXEN_BRDTYPE_P1_BD:
1980 case NETXEN_BRDTYPE_P1_SB:
1981 case NETXEN_BRDTYPE_P1_SMAX:
1982 case NETXEN_BRDTYPE_P1_SOCK:
1983 case NETXEN_BRDTYPE_P3_REF_QG:
1984 case NETXEN_BRDTYPE_P3_4_GB:
1985 case NETXEN_BRDTYPE_P3_4_GB_MM:
1986 adapter->ahw.port_type = NETXEN_NIC_GBE;
1987 break;
1988 case NETXEN_BRDTYPE_P3_10G_TP:
1989 adapter->ahw.port_type = (adapter->portnum < 2) ?
1990 NETXEN_NIC_XGBE : NETXEN_NIC_GBE;
1991 break;
1992 default:
1993 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1994 adapter->ahw.port_type = NETXEN_NIC_XGBE;
1995 break;
1996 }
1997
1998 return 0;
1999 }
2000
2001 /* NIU access sections */
2002
2003 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
2004 {
2005 new_mtu += MTU_FUDGE_FACTOR;
2006 NXWR32(adapter, NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
2007 new_mtu);
2008 return 0;
2009 }
2010
2011 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
2012 {
2013 new_mtu += MTU_FUDGE_FACTOR;
2014 if (adapter->physical_port == 0)
2015 NXWR32(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu);
2016 else
2017 NXWR32(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu);
2018 return 0;
2019 }
2020
2021 void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
2022 {
2023 __u32 status;
2024 __u32 autoneg;
2025 __u32 port_mode;
2026
2027 if (!netif_carrier_ok(adapter->netdev)) {
2028 adapter->link_speed = 0;
2029 adapter->link_duplex = -1;
2030 adapter->link_autoneg = AUTONEG_ENABLE;
2031 return;
2032 }
2033
2034 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
2035 port_mode = NXRD32(adapter, NETXEN_PORT_MODE_ADDR);
2036 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
2037 adapter->link_speed = SPEED_1000;
2038 adapter->link_duplex = DUPLEX_FULL;
2039 adapter->link_autoneg = AUTONEG_DISABLE;
2040 return;
2041 }
2042
2043 if (adapter->phy_read
2044 && adapter->phy_read(adapter,
2045 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
2046 &status) == 0) {
2047 if (netxen_get_phy_link(status)) {
2048 switch (netxen_get_phy_speed(status)) {
2049 case 0:
2050 adapter->link_speed = SPEED_10;
2051 break;
2052 case 1:
2053 adapter->link_speed = SPEED_100;
2054 break;
2055 case 2:
2056 adapter->link_speed = SPEED_1000;
2057 break;
2058 default:
2059 adapter->link_speed = 0;
2060 break;
2061 }
2062 switch (netxen_get_phy_duplex(status)) {
2063 case 0:
2064 adapter->link_duplex = DUPLEX_HALF;
2065 break;
2066 case 1:
2067 adapter->link_duplex = DUPLEX_FULL;
2068 break;
2069 default:
2070 adapter->link_duplex = -1;
2071 break;
2072 }
2073 if (adapter->phy_read
2074 && adapter->phy_read(adapter,
2075 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
2076 &autoneg) != 0)
2077 adapter->link_autoneg = autoneg;
2078 } else
2079 goto link_down;
2080 } else {
2081 link_down:
2082 adapter->link_speed = 0;
2083 adapter->link_duplex = -1;
2084 }
2085 }
2086 }
2087
2088 int
2089 netxen_nic_wol_supported(struct netxen_adapter *adapter)
2090 {
2091 u32 wol_cfg;
2092
2093 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
2094 return 0;
2095
2096 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV);
2097 if (wol_cfg & (1UL << adapter->portnum)) {
2098 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG);
2099 if (wol_cfg & (1 << adapter->portnum))
2100 return 1;
2101 }
2102
2103 return 0;
2104 }
Linux ARM platform port for MOXA ART SoC