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initial commit with v2.6.32.60
[linux-2.6.32.60-moxart.git] / drivers / net / smsc911x.c
blobb496fa6811e897554cab3c3fb43c8d52358f5be3
1 /***************************************************************************
2 *
3 * Copyright (C) 2004-2008 SMSC
4 * Copyright (C) 2005-2008 ARM
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 *
20 ***************************************************************************
21 * Rewritten, heavily based on smsc911x simple driver by SMSC.
22 * Partly uses io macros from smc91x.c by Nicolas Pitre
23 *
24 * Supported devices:
25 * LAN9115, LAN9116, LAN9117, LAN9118
26 * LAN9215, LAN9216, LAN9217, LAN9218
27 * LAN9210, LAN9211
28 * LAN9220, LAN9221
29 *
30 */
31
32 #include <linux/crc32.h>
33 #include <linux/delay.h>
34 #include <linux/errno.h>
35 #include <linux/etherdevice.h>
36 #include <linux/ethtool.h>
37 #include <linux/init.h>
38 #include <linux/ioport.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/netdevice.h>
42 #include <linux/platform_device.h>
43 #include <linux/sched.h>
44 #include <linux/slab.h>
45 #include <linux/timer.h>
46 #include <linux/bug.h>
47 #include <linux/bitops.h>
48 #include <linux/irq.h>
49 #include <linux/io.h>
50 #include <linux/swab.h>
51 #include <linux/phy.h>
52 #include <linux/smsc911x.h>
53 #include <linux/device.h>
54 #include "smsc911x.h"
55
56 #define SMSC_CHIPNAME "smsc911x"
57 #define SMSC_MDIONAME "smsc911x-mdio"
58 #define SMSC_DRV_VERSION "2008-10-21"
59
60 MODULE_LICENSE("GPL");
61 MODULE_VERSION(SMSC_DRV_VERSION);
62
63 #if USE_DEBUG > 0
64 static int debug = 16;
65 #else
66 static int debug = 3;
67 #endif
68
69 module_param(debug, int, 0);
70 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
71
72 struct smsc911x_data {
73 void __iomem *ioaddr;
74
75 unsigned int idrev;
76
77 /* used to decide which workarounds apply */
78 unsigned int generation;
79
80 /* device configuration (copied from platform_data during probe) */
81 struct smsc911x_platform_config config;
82
83 /* This needs to be acquired before calling any of below:
84 * smsc911x_mac_read(), smsc911x_mac_write()
85 */
86 spinlock_t mac_lock;
87
88 /* spinlock to ensure register accesses are serialised */
89 spinlock_t dev_lock;
90
91 struct phy_device *phy_dev;
92 struct mii_bus *mii_bus;
93 int phy_irq[PHY_MAX_ADDR];
94 unsigned int using_extphy;
95 int last_duplex;
96 int last_carrier;
97
98 u32 msg_enable;
99 unsigned int gpio_setting;
100 unsigned int gpio_orig_setting;
101 struct net_device *dev;
102 struct napi_struct napi;
103
104 unsigned int software_irq_signal;
105
106 #ifdef USE_PHY_WORK_AROUND
107 #define MIN_PACKET_SIZE (64)
108 char loopback_tx_pkt[MIN_PACKET_SIZE];
109 char loopback_rx_pkt[MIN_PACKET_SIZE];
110 unsigned int resetcount;
111 #endif
112
113 /* Members for Multicast filter workaround */
114 unsigned int multicast_update_pending;
115 unsigned int set_bits_mask;
116 unsigned int clear_bits_mask;
117 unsigned int hashhi;
118 unsigned int hashlo;
119 };
120
121 static inline u32 __smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
122 {
123 if (pdata->config.flags & SMSC911X_USE_32BIT)
124 return readl(pdata->ioaddr + reg);
125
126 if (pdata->config.flags & SMSC911X_USE_16BIT)
127 return ((readw(pdata->ioaddr + reg) & 0xFFFF) |
128 ((readw(pdata->ioaddr + reg + 2) & 0xFFFF) << 16));
129
130 BUG();
131 return 0;
132 }
133
134 static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
135 {
136 u32 data;
137 unsigned long flags;
138
139 spin_lock_irqsave(&pdata->dev_lock, flags);
140 data = __smsc911x_reg_read(pdata, reg);
141 spin_unlock_irqrestore(&pdata->dev_lock, flags);
142
143 return data;
144 }
145
146 static inline void __smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
147 u32 val)
148 {
149 if (pdata->config.flags & SMSC911X_USE_32BIT) {
150 writel(val, pdata->ioaddr + reg);
151 return;
152 }
153
154 if (pdata->config.flags & SMSC911X_USE_16BIT) {
155 writew(val & 0xFFFF, pdata->ioaddr + reg);
156 writew((val >> 16) & 0xFFFF, pdata->ioaddr + reg + 2);
157 return;
158 }
159
160 BUG();
161 }
162
163 static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
164 u32 val)
165 {
166 unsigned long flags;
167
168 spin_lock_irqsave(&pdata->dev_lock, flags);
169 __smsc911x_reg_write(pdata, reg, val);
170 spin_unlock_irqrestore(&pdata->dev_lock, flags);
171 }
172
173 /* Writes a packet to the TX_DATA_FIFO */
174 static inline void
175 smsc911x_tx_writefifo(struct smsc911x_data *pdata, unsigned int *buf,
176 unsigned int wordcount)
177 {
178 unsigned long flags;
179
180 spin_lock_irqsave(&pdata->dev_lock, flags);
181
182 if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
183 while (wordcount--)
184 __smsc911x_reg_write(pdata, TX_DATA_FIFO,
185 swab32(*buf++));
186 goto out;
187 }
188
189 if (pdata->config.flags & SMSC911X_USE_32BIT) {
190 writesl(pdata->ioaddr + TX_DATA_FIFO, buf, wordcount);
191 goto out;
192 }
193
194 if (pdata->config.flags & SMSC911X_USE_16BIT) {
195 while (wordcount--)
196 __smsc911x_reg_write(pdata, TX_DATA_FIFO, *buf++);
197 goto out;
198 }
199
200 BUG();
201 out:
202 spin_unlock_irqrestore(&pdata->dev_lock, flags);
203 }
204
205 /* Reads a packet out of the RX_DATA_FIFO */
206 static inline void
207 smsc911x_rx_readfifo(struct smsc911x_data *pdata, unsigned int *buf,
208 unsigned int wordcount)
209 {
210 unsigned long flags;
211
212 spin_lock_irqsave(&pdata->dev_lock, flags);
213
214 if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
215 while (wordcount--)
216 *buf++ = swab32(__smsc911x_reg_read(pdata,
217 RX_DATA_FIFO));
218 goto out;
219 }
220
221 if (pdata->config.flags & SMSC911X_USE_32BIT) {
222 readsl(pdata->ioaddr + RX_DATA_FIFO, buf, wordcount);
223 goto out;
224 }
225
226 if (pdata->config.flags & SMSC911X_USE_16BIT) {
227 while (wordcount--)
228 *buf++ = __smsc911x_reg_read(pdata, RX_DATA_FIFO);
229 goto out;
230 }
231
232 BUG();
233 out:
234 spin_unlock_irqrestore(&pdata->dev_lock, flags);
235 }
236
237 /* waits for MAC not busy, with timeout. Only called by smsc911x_mac_read
238 * and smsc911x_mac_write, so assumes mac_lock is held */
239 static int smsc911x_mac_complete(struct smsc911x_data *pdata)
240 {
241 int i;
242 u32 val;
243
244 SMSC_ASSERT_MAC_LOCK(pdata);
245
246 for (i = 0; i < 40; i++) {
247 val = smsc911x_reg_read(pdata, MAC_CSR_CMD);
248 if (!(val & MAC_CSR_CMD_CSR_BUSY_))
249 return 0;
250 }
251 SMSC_WARNING(HW, "Timed out waiting for MAC not BUSY. "
252 "MAC_CSR_CMD: 0x%08X", val);
253 return -EIO;
254 }
255
256 /* Fetches a MAC register value. Assumes mac_lock is acquired */
257 static u32 smsc911x_mac_read(struct smsc911x_data *pdata, unsigned int offset)
258 {
259 unsigned int temp;
260
261 SMSC_ASSERT_MAC_LOCK(pdata);
262
263 temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
264 if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
265 SMSC_WARNING(HW, "MAC busy at entry");
266 return 0xFFFFFFFF;
267 }
268
269 /* Send the MAC cmd */
270 smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
271 MAC_CSR_CMD_CSR_BUSY_ | MAC_CSR_CMD_R_NOT_W_));
272
273 /* Workaround for hardware read-after-write restriction */
274 temp = smsc911x_reg_read(pdata, BYTE_TEST);
275
276 /* Wait for the read to complete */
277 if (likely(smsc911x_mac_complete(pdata) == 0))
278 return smsc911x_reg_read(pdata, MAC_CSR_DATA);
279
280 SMSC_WARNING(HW, "MAC busy after read");
281 return 0xFFFFFFFF;
282 }
283
284 /* Set a mac register, mac_lock must be acquired before calling */
285 static void smsc911x_mac_write(struct smsc911x_data *pdata,
286 unsigned int offset, u32 val)
287 {
288 unsigned int temp;
289
290 SMSC_ASSERT_MAC_LOCK(pdata);
291
292 temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
293 if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
294 SMSC_WARNING(HW,
295 "smsc911x_mac_write failed, MAC busy at entry");
296 return;
297 }
298
299 /* Send data to write */
300 smsc911x_reg_write(pdata, MAC_CSR_DATA, val);
301
302 /* Write the actual data */
303 smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
304 MAC_CSR_CMD_CSR_BUSY_));
305
306 /* Workaround for hardware read-after-write restriction */
307 temp = smsc911x_reg_read(pdata, BYTE_TEST);
308
309 /* Wait for the write to complete */
310 if (likely(smsc911x_mac_complete(pdata) == 0))
311 return;
312
313 SMSC_WARNING(HW,
314 "smsc911x_mac_write failed, MAC busy after write");
315 }
316
317 /* Get a phy register */
318 static int smsc911x_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
319 {
320 struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
321 unsigned long flags;
322 unsigned int addr;
323 int i, reg;
324
325 spin_lock_irqsave(&pdata->mac_lock, flags);
326
327 /* Confirm MII not busy */
328 if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
329 SMSC_WARNING(HW,
330 "MII is busy in smsc911x_mii_read???");
331 reg = -EIO;
332 goto out;
333 }
334
335 /* Set the address, index & direction (read from PHY) */
336 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6);
337 smsc911x_mac_write(pdata, MII_ACC, addr);
338
339 /* Wait for read to complete w/ timeout */
340 for (i = 0; i < 100; i++)
341 if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
342 reg = smsc911x_mac_read(pdata, MII_DATA);
343 goto out;
344 }
345
346 SMSC_WARNING(HW, "Timed out waiting for MII read to finish");
347 reg = -EIO;
348
349 out:
350 spin_unlock_irqrestore(&pdata->mac_lock, flags);
351 return reg;
352 }
353
354 /* Set a phy register */
355 static int smsc911x_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
356 u16 val)
357 {
358 struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
359 unsigned long flags;
360 unsigned int addr;
361 int i, reg;
362
363 spin_lock_irqsave(&pdata->mac_lock, flags);
364
365 /* Confirm MII not busy */
366 if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
367 SMSC_WARNING(HW,
368 "MII is busy in smsc911x_mii_write???");
369 reg = -EIO;
370 goto out;
371 }
372
373 /* Put the data to write in the MAC */
374 smsc911x_mac_write(pdata, MII_DATA, val);
375
376 /* Set the address, index & direction (write to PHY) */
377 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
378 MII_ACC_MII_WRITE_;
379 smsc911x_mac_write(pdata, MII_ACC, addr);
380
381 /* Wait for write to complete w/ timeout */
382 for (i = 0; i < 100; i++)
383 if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
384 reg = 0;
385 goto out;
386 }
387
388 SMSC_WARNING(HW, "Timed out waiting for MII write to finish");
389 reg = -EIO;
390
391 out:
392 spin_unlock_irqrestore(&pdata->mac_lock, flags);
393 return reg;
394 }
395
396 /* Switch to external phy. Assumes tx and rx are stopped. */
397 static void smsc911x_phy_enable_external(struct smsc911x_data *pdata)
398 {
399 unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
400
401 /* Disable phy clocks to the MAC */
402 hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
403 hwcfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_;
404 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
405 udelay(10); /* Enough time for clocks to stop */
406
407 /* Switch to external phy */
408 hwcfg |= HW_CFG_EXT_PHY_EN_;
409 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
410
411 /* Enable phy clocks to the MAC */
412 hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
413 hwcfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_;
414 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
415 udelay(10); /* Enough time for clocks to restart */
416
417 hwcfg |= HW_CFG_SMI_SEL_;
418 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
419 }
420
421 /* Autodetects and enables external phy if present on supported chips.
422 * autodetection can be overridden by specifying SMSC911X_FORCE_INTERNAL_PHY
423 * or SMSC911X_FORCE_EXTERNAL_PHY in the platform_data flags. */
424 static void smsc911x_phy_initialise_external(struct smsc911x_data *pdata)
425 {
426 unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
427
428 if (pdata->config.flags & SMSC911X_FORCE_INTERNAL_PHY) {
429 SMSC_TRACE(HW, "Forcing internal PHY");
430 pdata->using_extphy = 0;
431 } else if (pdata->config.flags & SMSC911X_FORCE_EXTERNAL_PHY) {
432 SMSC_TRACE(HW, "Forcing external PHY");
433 smsc911x_phy_enable_external(pdata);
434 pdata->using_extphy = 1;
435 } else if (hwcfg & HW_CFG_EXT_PHY_DET_) {
436 SMSC_TRACE(HW, "HW_CFG EXT_PHY_DET set, using external PHY");
437 smsc911x_phy_enable_external(pdata);
438 pdata->using_extphy = 1;
439 } else {
440 SMSC_TRACE(HW, "HW_CFG EXT_PHY_DET clear, using internal PHY");
441 pdata->using_extphy = 0;
442 }
443 }
444
445 /* Fetches a tx status out of the status fifo */
446 static unsigned int smsc911x_tx_get_txstatus(struct smsc911x_data *pdata)
447 {
448 unsigned int result =
449 smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TSUSED_;
450
451 if (result != 0)
452 result = smsc911x_reg_read(pdata, TX_STATUS_FIFO);
453
454 return result;
455 }
456
457 /* Fetches the next rx status */
458 static unsigned int smsc911x_rx_get_rxstatus(struct smsc911x_data *pdata)
459 {
460 unsigned int result =
461 smsc911x_reg_read(pdata, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED_;
462
463 if (result != 0)
464 result = smsc911x_reg_read(pdata, RX_STATUS_FIFO);
465
466 return result;
467 }
468
469 #ifdef USE_PHY_WORK_AROUND
470 static int smsc911x_phy_check_loopbackpkt(struct smsc911x_data *pdata)
471 {
472 unsigned int tries;
473 u32 wrsz;
474 u32 rdsz;
475 ulong bufp;
476
477 for (tries = 0; tries < 10; tries++) {
478 unsigned int txcmd_a;
479 unsigned int txcmd_b;
480 unsigned int status;
481 unsigned int pktlength;
482 unsigned int i;
483
484 /* Zero-out rx packet memory */
485 memset(pdata->loopback_rx_pkt, 0, MIN_PACKET_SIZE);
486
487 /* Write tx packet to 118 */
488 txcmd_a = (u32)((ulong)pdata->loopback_tx_pkt & 0x03) << 16;
489 txcmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
490 txcmd_a |= MIN_PACKET_SIZE;
491
492 txcmd_b = MIN_PACKET_SIZE << 16 | MIN_PACKET_SIZE;
493
494 smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_a);
495 smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_b);
496
497 bufp = (ulong)pdata->loopback_tx_pkt & (~0x3);
498 wrsz = MIN_PACKET_SIZE + 3;
499 wrsz += (u32)((ulong)pdata->loopback_tx_pkt & 0x3);
500 wrsz >>= 2;
501
502 smsc911x_tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
503
504 /* Wait till transmit is done */
505 i = 60;
506 do {
507 udelay(5);
508 status = smsc911x_tx_get_txstatus(pdata);
509 } while ((i--) && (!status));
510
511 if (!status) {
512 SMSC_WARNING(HW, "Failed to transmit "
513 "during loopback test");
514 continue;
515 }
516 if (status & TX_STS_ES_) {
517 SMSC_WARNING(HW, "Transmit encountered "
518 "errors during loopback test");
519 continue;
520 }
521
522 /* Wait till receive is done */
523 i = 60;
524 do {
525 udelay(5);
526 status = smsc911x_rx_get_rxstatus(pdata);
527 } while ((i--) && (!status));
528
529 if (!status) {
530 SMSC_WARNING(HW,
531 "Failed to receive during loopback test");
532 continue;
533 }
534 if (status & RX_STS_ES_) {
535 SMSC_WARNING(HW, "Receive encountered "
536 "errors during loopback test");
537 continue;
538 }
539
540 pktlength = ((status & 0x3FFF0000UL) >> 16);
541 bufp = (ulong)pdata->loopback_rx_pkt;
542 rdsz = pktlength + 3;
543 rdsz += (u32)((ulong)pdata->loopback_rx_pkt & 0x3);
544 rdsz >>= 2;
545
546 smsc911x_rx_readfifo(pdata, (unsigned int *)bufp, rdsz);
547
548 if (pktlength != (MIN_PACKET_SIZE + 4)) {
549 SMSC_WARNING(HW, "Unexpected packet size "
550 "during loop back test, size=%d, will retry",
551 pktlength);
552 } else {
553 unsigned int j;
554 int mismatch = 0;
555 for (j = 0; j < MIN_PACKET_SIZE; j++) {
556 if (pdata->loopback_tx_pkt[j]
557 != pdata->loopback_rx_pkt[j]) {
558 mismatch = 1;
559 break;
560 }
561 }
562 if (!mismatch) {
563 SMSC_TRACE(HW, "Successfully verified "
564 "loopback packet");
565 return 0;
566 } else {
567 SMSC_WARNING(HW, "Data mismatch "
568 "during loop back test, will retry");
569 }
570 }
571 }
572
573 return -EIO;
574 }
575
576 static int smsc911x_phy_reset(struct smsc911x_data *pdata)
577 {
578 struct phy_device *phy_dev = pdata->phy_dev;
579 unsigned int temp;
580 unsigned int i = 100000;
581
582 BUG_ON(!phy_dev);
583 BUG_ON(!phy_dev->bus);
584
585 SMSC_TRACE(HW, "Performing PHY BCR Reset");
586 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, BMCR_RESET);
587 do {
588 msleep(1);
589 temp = smsc911x_mii_read(phy_dev->bus, phy_dev->addr,
590 MII_BMCR);
591 } while ((i--) && (temp & BMCR_RESET));
592
593 if (temp & BMCR_RESET) {
594 SMSC_WARNING(HW, "PHY reset failed to complete.");
595 return -EIO;
596 }
597 /* Extra delay required because the phy may not be completed with
598 * its reset when BMCR_RESET is cleared. Specs say 256 uS is
599 * enough delay but using 1ms here to be safe */
600 msleep(1);
601
602 return 0;
603 }
604
605 static int smsc911x_phy_loopbacktest(struct net_device *dev)
606 {
607 struct smsc911x_data *pdata = netdev_priv(dev);
608 struct phy_device *phy_dev = pdata->phy_dev;
609 int result = -EIO;
610 unsigned int i, val;
611 unsigned long flags;
612
613 /* Initialise tx packet using broadcast destination address */
614 memset(pdata->loopback_tx_pkt, 0xff, ETH_ALEN);
615
616 /* Use incrementing source address */
617 for (i = 6; i < 12; i++)
618 pdata->loopback_tx_pkt[i] = (char)i;
619
620 /* Set length type field */
621 pdata->loopback_tx_pkt[12] = 0x00;
622 pdata->loopback_tx_pkt[13] = 0x00;
623
624 for (i = 14; i < MIN_PACKET_SIZE; i++)
625 pdata->loopback_tx_pkt[i] = (char)i;
626
627 val = smsc911x_reg_read(pdata, HW_CFG);
628 val &= HW_CFG_TX_FIF_SZ_;
629 val |= HW_CFG_SF_;
630 smsc911x_reg_write(pdata, HW_CFG, val);
631
632 smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
633 smsc911x_reg_write(pdata, RX_CFG,
634 (u32)((ulong)pdata->loopback_rx_pkt & 0x03) << 8);
635
636 for (i = 0; i < 10; i++) {
637 /* Set PHY to 10/FD, no ANEG, and loopback mode */
638 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR,
639 BMCR_LOOPBACK | BMCR_FULLDPLX);
640
641 /* Enable MAC tx/rx, FD */
642 spin_lock_irqsave(&pdata->mac_lock, flags);
643 smsc911x_mac_write(pdata, MAC_CR, MAC_CR_FDPX_
644 | MAC_CR_TXEN_ | MAC_CR_RXEN_);
645 spin_unlock_irqrestore(&pdata->mac_lock, flags);
646
647 if (smsc911x_phy_check_loopbackpkt(pdata) == 0) {
648 result = 0;
649 break;
650 }
651 pdata->resetcount++;
652
653 /* Disable MAC rx */
654 spin_lock_irqsave(&pdata->mac_lock, flags);
655 smsc911x_mac_write(pdata, MAC_CR, 0);
656 spin_unlock_irqrestore(&pdata->mac_lock, flags);
657
658 smsc911x_phy_reset(pdata);
659 }
660
661 /* Disable MAC */
662 spin_lock_irqsave(&pdata->mac_lock, flags);
663 smsc911x_mac_write(pdata, MAC_CR, 0);
664 spin_unlock_irqrestore(&pdata->mac_lock, flags);
665
666 /* Cancel PHY loopback mode */
667 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, 0);
668
669 smsc911x_reg_write(pdata, TX_CFG, 0);
670 smsc911x_reg_write(pdata, RX_CFG, 0);
671
672 return result;
673 }
674 #endif /* USE_PHY_WORK_AROUND */
675
676 static void smsc911x_phy_update_flowcontrol(struct smsc911x_data *pdata)
677 {
678 struct phy_device *phy_dev = pdata->phy_dev;
679 u32 afc = smsc911x_reg_read(pdata, AFC_CFG);
680 u32 flow;
681 unsigned long flags;
682
683 if (phy_dev->duplex == DUPLEX_FULL) {
684 u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
685 u16 rmtadv = phy_read(phy_dev, MII_LPA);
686 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
687
688 if (cap & FLOW_CTRL_RX)
689 flow = 0xFFFF0002;
690 else
691 flow = 0;
692
693 if (cap & FLOW_CTRL_TX)
694 afc |= 0xF;
695 else
696 afc &= ~0xF;
697
698 SMSC_TRACE(HW, "rx pause %s, tx pause %s",
699 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
700 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
701 } else {
702 SMSC_TRACE(HW, "half duplex");
703 flow = 0;
704 afc |= 0xF;
705 }
706
707 spin_lock_irqsave(&pdata->mac_lock, flags);
708 smsc911x_mac_write(pdata, FLOW, flow);
709 spin_unlock_irqrestore(&pdata->mac_lock, flags);
710
711 smsc911x_reg_write(pdata, AFC_CFG, afc);
712 }
713
714 /* Update link mode if anything has changed. Called periodically when the
715 * PHY is in polling mode, even if nothing has changed. */
716 static void smsc911x_phy_adjust_link(struct net_device *dev)
717 {
718 struct smsc911x_data *pdata = netdev_priv(dev);
719 struct phy_device *phy_dev = pdata->phy_dev;
720 unsigned long flags;
721 int carrier;
722
723 if (phy_dev->duplex != pdata->last_duplex) {
724 unsigned int mac_cr;
725 SMSC_TRACE(HW, "duplex state has changed");
726
727 spin_lock_irqsave(&pdata->mac_lock, flags);
728 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
729 if (phy_dev->duplex) {
730 SMSC_TRACE(HW,
731 "configuring for full duplex mode");
732 mac_cr |= MAC_CR_FDPX_;
733 } else {
734 SMSC_TRACE(HW,
735 "configuring for half duplex mode");
736 mac_cr &= ~MAC_CR_FDPX_;
737 }
738 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
739 spin_unlock_irqrestore(&pdata->mac_lock, flags);
740
741 smsc911x_phy_update_flowcontrol(pdata);
742 pdata->last_duplex = phy_dev->duplex;
743 }
744
745 carrier = netif_carrier_ok(dev);
746 if (carrier != pdata->last_carrier) {
747 SMSC_TRACE(HW, "carrier state has changed");
748 if (carrier) {
749 SMSC_TRACE(HW, "configuring for carrier OK");
750 if ((pdata->gpio_orig_setting & GPIO_CFG_LED1_EN_) &&
751 (!pdata->using_extphy)) {
752 /* Restore orginal GPIO configuration */
753 pdata->gpio_setting = pdata->gpio_orig_setting;
754 smsc911x_reg_write(pdata, GPIO_CFG,
755 pdata->gpio_setting);
756 }
757 } else {
758 SMSC_TRACE(HW, "configuring for no carrier");
759 /* Check global setting that LED1
760 * usage is 10/100 indicator */
761 pdata->gpio_setting = smsc911x_reg_read(pdata,
762 GPIO_CFG);
763 if ((pdata->gpio_setting & GPIO_CFG_LED1_EN_)
764 && (!pdata->using_extphy)) {
765 /* Force 10/100 LED off, after saving
766 * orginal GPIO configuration */
767 pdata->gpio_orig_setting = pdata->gpio_setting;
768
769 pdata->gpio_setting &= ~GPIO_CFG_LED1_EN_;
770 pdata->gpio_setting |= (GPIO_CFG_GPIOBUF0_
771 | GPIO_CFG_GPIODIR0_
772 | GPIO_CFG_GPIOD0_);
773 smsc911x_reg_write(pdata, GPIO_CFG,
774 pdata->gpio_setting);
775 }
776 }
777 pdata->last_carrier = carrier;
778 }
779 }
780
781 static int smsc911x_mii_probe(struct net_device *dev)
782 {
783 struct smsc911x_data *pdata = netdev_priv(dev);
784 struct phy_device *phydev = NULL;
785 int phy_addr;
786
787 /* find the first phy */
788 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
789 if (pdata->mii_bus->phy_map[phy_addr]) {
790 phydev = pdata->mii_bus->phy_map[phy_addr];
791 SMSC_TRACE(PROBE, "PHY %d: addr %d, phy_id 0x%08X",
792 phy_addr, phydev->addr, phydev->phy_id);
793 break;
794 }
795 }
796
797 if (!phydev) {
798 pr_err("%s: no PHY found\n", dev->name);
799 return -ENODEV;
800 }
801
802 phydev = phy_connect(dev, dev_name(&phydev->dev),
803 &smsc911x_phy_adjust_link, 0, pdata->config.phy_interface);
804
805 if (IS_ERR(phydev)) {
806 pr_err("%s: Could not attach to PHY\n", dev->name);
807 return PTR_ERR(phydev);
808 }
809
810 pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
811 dev->name, phydev->drv->name,
812 dev_name(&phydev->dev), phydev->irq);
813
814 /* mask with MAC supported features */
815 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
816 SUPPORTED_Asym_Pause);
817 phydev->advertising = phydev->supported;
818
819 pdata->phy_dev = phydev;
820 pdata->last_duplex = -1;
821 pdata->last_carrier = -1;
822
823 #ifdef USE_PHY_WORK_AROUND
824 if (smsc911x_phy_loopbacktest(dev) < 0) {
825 SMSC_WARNING(HW, "Failed Loop Back Test");
826 return -ENODEV;
827 }
828 SMSC_TRACE(HW, "Passed Loop Back Test");
829 #endif /* USE_PHY_WORK_AROUND */
830
831 SMSC_TRACE(HW, "phy initialised succesfully");
832 return 0;
833 }
834
835 static int __devinit smsc911x_mii_init(struct platform_device *pdev,
836 struct net_device *dev)
837 {
838 struct smsc911x_data *pdata = netdev_priv(dev);
839 int err = -ENXIO, i;
840
841 pdata->mii_bus = mdiobus_alloc();
842 if (!pdata->mii_bus) {
843 err = -ENOMEM;
844 goto err_out_1;
845 }
846
847 pdata->mii_bus->name = SMSC_MDIONAME;
848 snprintf(pdata->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id);
849 pdata->mii_bus->priv = pdata;
850 pdata->mii_bus->read = smsc911x_mii_read;
851 pdata->mii_bus->write = smsc911x_mii_write;
852 pdata->mii_bus->irq = pdata->phy_irq;
853 for (i = 0; i < PHY_MAX_ADDR; ++i)
854 pdata->mii_bus->irq[i] = PHY_POLL;
855
856 pdata->mii_bus->parent = &pdev->dev;
857
858 switch (pdata->idrev & 0xFFFF0000) {
859 case 0x01170000:
860 case 0x01150000:
861 case 0x117A0000:
862 case 0x115A0000:
863 /* External PHY supported, try to autodetect */
864 smsc911x_phy_initialise_external(pdata);
865 break;
866 default:
867 SMSC_TRACE(HW, "External PHY is not supported, "
868 "using internal PHY");
869 pdata->using_extphy = 0;
870 break;
871 }
872
873 if (!pdata->using_extphy) {
874 /* Mask all PHYs except ID 1 (internal) */
875 pdata->mii_bus->phy_mask = ~(1 << 1);
876 }
877
878 if (mdiobus_register(pdata->mii_bus)) {
879 SMSC_WARNING(PROBE, "Error registering mii bus");
880 goto err_out_free_bus_2;
881 }
882
883 if (smsc911x_mii_probe(dev) < 0) {
884 SMSC_WARNING(PROBE, "Error registering mii bus");
885 goto err_out_unregister_bus_3;
886 }
887
888 return 0;
889
890 err_out_unregister_bus_3:
891 mdiobus_unregister(pdata->mii_bus);
892 err_out_free_bus_2:
893 mdiobus_free(pdata->mii_bus);
894 err_out_1:
895 return err;
896 }
897
898 /* Gets the number of tx statuses in the fifo */
899 static unsigned int smsc911x_tx_get_txstatcount(struct smsc911x_data *pdata)
900 {
901 return (smsc911x_reg_read(pdata, TX_FIFO_INF)
902 & TX_FIFO_INF_TSUSED_) >> 16;
903 }
904
905 /* Reads tx statuses and increments counters where necessary */
906 static void smsc911x_tx_update_txcounters(struct net_device *dev)
907 {
908 struct smsc911x_data *pdata = netdev_priv(dev);
909 unsigned int tx_stat;
910
911 while ((tx_stat = smsc911x_tx_get_txstatus(pdata)) != 0) {
912 if (unlikely(tx_stat & 0x80000000)) {
913 /* In this driver the packet tag is used as the packet
914 * length. Since a packet length can never reach the
915 * size of 0x8000, this bit is reserved. It is worth
916 * noting that the "reserved bit" in the warning above
917 * does not reference a hardware defined reserved bit
918 * but rather a driver defined one.
919 */
920 SMSC_WARNING(HW,
921 "Packet tag reserved bit is high");
922 } else {
923 if (unlikely(tx_stat & TX_STS_ES_)) {
924 dev->stats.tx_errors++;
925 } else {
926 dev->stats.tx_packets++;
927 dev->stats.tx_bytes += (tx_stat >> 16);
928 }
929 if (unlikely(tx_stat & TX_STS_EXCESS_COL_)) {
930 dev->stats.collisions += 16;
931 dev->stats.tx_aborted_errors += 1;
932 } else {
933 dev->stats.collisions +=
934 ((tx_stat >> 3) & 0xF);
935 }
936 if (unlikely(tx_stat & TX_STS_LOST_CARRIER_))
937 dev->stats.tx_carrier_errors += 1;
938 if (unlikely(tx_stat & TX_STS_LATE_COL_)) {
939 dev->stats.collisions++;
940 dev->stats.tx_aborted_errors++;
941 }
942 }
943 }
944 }
945
946 /* Increments the Rx error counters */
947 static void
948 smsc911x_rx_counterrors(struct net_device *dev, unsigned int rxstat)
949 {
950 int crc_err = 0;
951
952 if (unlikely(rxstat & RX_STS_ES_)) {
953 dev->stats.rx_errors++;
954 if (unlikely(rxstat & RX_STS_CRC_ERR_)) {
955 dev->stats.rx_crc_errors++;
956 crc_err = 1;
957 }
958 }
959 if (likely(!crc_err)) {
960 if (unlikely((rxstat & RX_STS_FRAME_TYPE_) &&
961 (rxstat & RX_STS_LENGTH_ERR_)))
962 dev->stats.rx_length_errors++;
963 if (rxstat & RX_STS_MCAST_)
964 dev->stats.multicast++;
965 }
966 }
967
968 /* Quickly dumps bad packets */
969 static void
970 smsc911x_rx_fastforward(struct smsc911x_data *pdata, unsigned int pktbytes)
971 {
972 unsigned int pktwords = (pktbytes + NET_IP_ALIGN + 3) >> 2;
973
974 if (likely(pktwords >= 4)) {
975 unsigned int timeout = 500;
976 unsigned int val;
977 smsc911x_reg_write(pdata, RX_DP_CTRL, RX_DP_CTRL_RX_FFWD_);
978 do {
979 udelay(1);
980 val = smsc911x_reg_read(pdata, RX_DP_CTRL);
981 } while ((val & RX_DP_CTRL_RX_FFWD_) && --timeout);
982
983 if (unlikely(timeout == 0))
984 SMSC_WARNING(HW, "Timed out waiting for "
985 "RX FFWD to finish, RX_DP_CTRL: 0x%08X", val);
986 } else {
987 unsigned int temp;
988 while (pktwords--)
989 temp = smsc911x_reg_read(pdata, RX_DATA_FIFO);
990 }
991 }
992
993 /* NAPI poll function */
994 static int smsc911x_poll(struct napi_struct *napi, int budget)
995 {
996 struct smsc911x_data *pdata =
997 container_of(napi, struct smsc911x_data, napi);
998 struct net_device *dev = pdata->dev;
999 int npackets = 0;
1000
1001 while (npackets < budget) {
1002 unsigned int pktlength;
1003 unsigned int pktwords;
1004 struct sk_buff *skb;
1005 unsigned int rxstat = smsc911x_rx_get_rxstatus(pdata);
1006
1007 if (!rxstat) {
1008 unsigned int temp;
1009 /* We processed all packets available. Tell NAPI it can
1010 * stop polling then re-enable rx interrupts */
1011 smsc911x_reg_write(pdata, INT_STS, INT_STS_RSFL_);
1012 napi_complete(napi);
1013 temp = smsc911x_reg_read(pdata, INT_EN);
1014 temp |= INT_EN_RSFL_EN_;
1015 smsc911x_reg_write(pdata, INT_EN, temp);
1016 break;
1017 }
1018
1019 /* Count packet for NAPI scheduling, even if it has an error.
1020 * Error packets still require cycles to discard */
1021 npackets++;
1022
1023 pktlength = ((rxstat & 0x3FFF0000) >> 16);
1024 pktwords = (pktlength + NET_IP_ALIGN + 3) >> 2;
1025 smsc911x_rx_counterrors(dev, rxstat);
1026
1027 if (unlikely(rxstat & RX_STS_ES_)) {
1028 SMSC_WARNING(RX_ERR,
1029 "Discarding packet with error bit set");
1030 /* Packet has an error, discard it and continue with
1031 * the next */
1032 smsc911x_rx_fastforward(pdata, pktwords);
1033 dev->stats.rx_dropped++;
1034 continue;
1035 }
1036
1037 skb = netdev_alloc_skb(dev, pktlength + NET_IP_ALIGN);
1038 if (unlikely(!skb)) {
1039 SMSC_WARNING(RX_ERR,
1040 "Unable to allocate skb for rx packet");
1041 /* Drop the packet and stop this polling iteration */
1042 smsc911x_rx_fastforward(pdata, pktwords);
1043 dev->stats.rx_dropped++;
1044 break;
1045 }
1046
1047 skb->data = skb->head;
1048 skb_reset_tail_pointer(skb);
1049
1050 /* Align IP on 16B boundary */
1051 skb_reserve(skb, NET_IP_ALIGN);
1052 skb_put(skb, pktlength - 4);
1053 smsc911x_rx_readfifo(pdata, (unsigned int *)skb->head,
1054 pktwords);
1055 skb->protocol = eth_type_trans(skb, dev);
1056 skb->ip_summed = CHECKSUM_NONE;
1057 netif_receive_skb(skb);
1058
1059 /* Update counters */
1060 dev->stats.rx_packets++;
1061 dev->stats.rx_bytes += (pktlength - 4);
1062 }
1063
1064 /* Return total received packets */
1065 return npackets;
1066 }
1067
1068 /* Returns hash bit number for given MAC address
1069 * Example:
1070 * 01 00 5E 00 00 01 -> returns bit number 31 */
1071 static unsigned int smsc911x_hash(char addr[ETH_ALEN])
1072 {
1073 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
1074 }
1075
1076 static void smsc911x_rx_multicast_update(struct smsc911x_data *pdata)
1077 {
1078 /* Performs the multicast & mac_cr update. This is called when
1079 * safe on the current hardware, and with the mac_lock held */
1080 unsigned int mac_cr;
1081
1082 SMSC_ASSERT_MAC_LOCK(pdata);
1083
1084 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
1085 mac_cr |= pdata->set_bits_mask;
1086 mac_cr &= ~(pdata->clear_bits_mask);
1087 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
1088 smsc911x_mac_write(pdata, HASHH, pdata->hashhi);
1089 smsc911x_mac_write(pdata, HASHL, pdata->hashlo);
1090 SMSC_TRACE(HW, "maccr 0x%08X, HASHH 0x%08X, HASHL 0x%08X",
1091 mac_cr, pdata->hashhi, pdata->hashlo);
1092 }
1093
1094 static void smsc911x_rx_multicast_update_workaround(struct smsc911x_data *pdata)
1095 {
1096 unsigned int mac_cr;
1097
1098 /* This function is only called for older LAN911x devices
1099 * (revA or revB), where MAC_CR, HASHH and HASHL should not
1100 * be modified during Rx - newer devices immediately update the
1101 * registers.
1102 *
1103 * This is called from interrupt context */
1104
1105 spin_lock(&pdata->mac_lock);
1106
1107 /* Check Rx has stopped */
1108 if (smsc911x_mac_read(pdata, MAC_CR) & MAC_CR_RXEN_)
1109 SMSC_WARNING(DRV, "Rx not stopped");
1110
1111 /* Perform the update - safe to do now Rx has stopped */
1112 smsc911x_rx_multicast_update(pdata);
1113
1114 /* Re-enable Rx */
1115 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
1116 mac_cr |= MAC_CR_RXEN_;
1117 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
1118
1119 pdata->multicast_update_pending = 0;
1120
1121 spin_unlock(&pdata->mac_lock);
1122 }
1123
1124 static int smsc911x_soft_reset(struct smsc911x_data *pdata)
1125 {
1126 unsigned int timeout;
1127 unsigned int temp;
1128
1129 /* Reset the LAN911x */
1130 smsc911x_reg_write(pdata, HW_CFG, HW_CFG_SRST_);
1131 timeout = 10;
1132 do {
1133 udelay(10);
1134 temp = smsc911x_reg_read(pdata, HW_CFG);
1135 } while ((--timeout) && (temp & HW_CFG_SRST_));
1136
1137 if (unlikely(temp & HW_CFG_SRST_)) {
1138 SMSC_WARNING(DRV, "Failed to complete reset");
1139 return -EIO;
1140 }
1141 return 0;
1142 }
1143
1144 /* Sets the device MAC address to dev_addr, called with mac_lock held */
1145 static void
1146 smsc911x_set_hw_mac_address(struct smsc911x_data *pdata, u8 dev_addr[6])
1147 {
1148 u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
1149 u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
1150 (dev_addr[1] << 8) | dev_addr[0];
1151
1152 SMSC_ASSERT_MAC_LOCK(pdata);
1153
1154 smsc911x_mac_write(pdata, ADDRH, mac_high16);
1155 smsc911x_mac_write(pdata, ADDRL, mac_low32);
1156 }
1157
1158 static int smsc911x_open(struct net_device *dev)
1159 {
1160 struct smsc911x_data *pdata = netdev_priv(dev);
1161 unsigned int timeout;
1162 unsigned int temp;
1163 unsigned int intcfg;
1164
1165 /* if the phy is not yet registered, retry later*/
1166 if (!pdata->phy_dev) {
1167 SMSC_WARNING(HW, "phy_dev is NULL");
1168 return -EAGAIN;
1169 }
1170
1171 if (!is_valid_ether_addr(dev->dev_addr)) {
1172 SMSC_WARNING(HW, "dev_addr is not a valid MAC address");
1173 return -EADDRNOTAVAIL;
1174 }
1175
1176 /* Reset the LAN911x */
1177 if (smsc911x_soft_reset(pdata)) {
1178 SMSC_WARNING(HW, "soft reset failed");
1179 return -EIO;
1180 }
1181
1182 smsc911x_reg_write(pdata, HW_CFG, 0x00050000);
1183 smsc911x_reg_write(pdata, AFC_CFG, 0x006E3740);
1184
1185 /* Make sure EEPROM has finished loading before setting GPIO_CFG */
1186 timeout = 50;
1187 while ((smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) &&
1188 --timeout) {
1189 udelay(10);
1190 }
1191
1192 if (unlikely(timeout == 0))
1193 SMSC_WARNING(IFUP,
1194 "Timed out waiting for EEPROM busy bit to clear");
1195
1196 smsc911x_reg_write(pdata, GPIO_CFG, 0x70070000);
1197
1198 /* The soft reset above cleared the device's MAC address,
1199 * restore it from local copy (set in probe) */
1200 spin_lock_irq(&pdata->mac_lock);
1201 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
1202 spin_unlock_irq(&pdata->mac_lock);
1203
1204 /* Initialise irqs, but leave all sources disabled */
1205 smsc911x_reg_write(pdata, INT_EN, 0);
1206 smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
1207
1208 /* Set interrupt deassertion to 100uS */
1209 intcfg = ((10 << 24) | INT_CFG_IRQ_EN_);
1210
1211 if (pdata->config.irq_polarity) {
1212 SMSC_TRACE(IFUP, "irq polarity: active high");
1213 intcfg |= INT_CFG_IRQ_POL_;
1214 } else {
1215 SMSC_TRACE(IFUP, "irq polarity: active low");
1216 }
1217
1218 if (pdata->config.irq_type) {
1219 SMSC_TRACE(IFUP, "irq type: push-pull");
1220 intcfg |= INT_CFG_IRQ_TYPE_;
1221 } else {
1222 SMSC_TRACE(IFUP, "irq type: open drain");
1223 }
1224
1225 smsc911x_reg_write(pdata, INT_CFG, intcfg);
1226
1227 SMSC_TRACE(IFUP, "Testing irq handler using IRQ %d", dev->irq);
1228 pdata->software_irq_signal = 0;
1229 smp_wmb();
1230
1231 temp = smsc911x_reg_read(pdata, INT_EN);
1232 temp |= INT_EN_SW_INT_EN_;
1233 smsc911x_reg_write(pdata, INT_EN, temp);
1234
1235 timeout = 1000;
1236 while (timeout--) {
1237 if (pdata->software_irq_signal)
1238 break;
1239 msleep(1);
1240 }
1241
1242 if (!pdata->software_irq_signal) {
1243 dev_warn(&dev->dev, "ISR failed signaling test (IRQ %d)\n",
1244 dev->irq);
1245 return -ENODEV;
1246 }
1247 SMSC_TRACE(IFUP, "IRQ handler passed test using IRQ %d", dev->irq);
1248
1249 dev_info(&dev->dev, "SMSC911x/921x identified at %#08lx, IRQ: %d\n",
1250 (unsigned long)pdata->ioaddr, dev->irq);
1251
1252 /* Reset the last known duplex and carrier */
1253 pdata->last_duplex = -1;
1254 pdata->last_carrier = -1;
1255
1256 /* Bring the PHY up */
1257 phy_start(pdata->phy_dev);
1258
1259 temp = smsc911x_reg_read(pdata, HW_CFG);
1260 /* Preserve TX FIFO size and external PHY configuration */
1261 temp &= (HW_CFG_TX_FIF_SZ_|0x00000FFF);
1262 temp |= HW_CFG_SF_;
1263 smsc911x_reg_write(pdata, HW_CFG, temp);
1264
1265 temp = smsc911x_reg_read(pdata, FIFO_INT);
1266 temp |= FIFO_INT_TX_AVAIL_LEVEL_;
1267 temp &= ~(FIFO_INT_RX_STS_LEVEL_);
1268 smsc911x_reg_write(pdata, FIFO_INT, temp);
1269
1270 /* set RX Data offset to 2 bytes for alignment */
1271 smsc911x_reg_write(pdata, RX_CFG, (2 << 8));
1272
1273 /* enable NAPI polling before enabling RX interrupts */
1274 napi_enable(&pdata->napi);
1275
1276 temp = smsc911x_reg_read(pdata, INT_EN);
1277 temp |= (INT_EN_TDFA_EN_ | INT_EN_RSFL_EN_ | INT_EN_RXSTOP_INT_EN_);
1278 smsc911x_reg_write(pdata, INT_EN, temp);
1279
1280 spin_lock_irq(&pdata->mac_lock);
1281 temp = smsc911x_mac_read(pdata, MAC_CR);
1282 temp |= (MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_);
1283 smsc911x_mac_write(pdata, MAC_CR, temp);
1284 spin_unlock_irq(&pdata->mac_lock);
1285
1286 smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
1287
1288 netif_start_queue(dev);
1289 return 0;
1290 }
1291
1292 /* Entry point for stopping the interface */
1293 static int smsc911x_stop(struct net_device *dev)
1294 {
1295 struct smsc911x_data *pdata = netdev_priv(dev);
1296 unsigned int temp;
1297
1298 /* Disable all device interrupts */
1299 temp = smsc911x_reg_read(pdata, INT_CFG);
1300 temp &= ~INT_CFG_IRQ_EN_;
1301 smsc911x_reg_write(pdata, INT_CFG, temp);
1302
1303 /* Stop Tx and Rx polling */
1304 netif_stop_queue(dev);
1305 napi_disable(&pdata->napi);
1306
1307 /* At this point all Rx and Tx activity is stopped */
1308 dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
1309 smsc911x_tx_update_txcounters(dev);
1310
1311 /* Bring the PHY down */
1312 if (pdata->phy_dev)
1313 phy_stop(pdata->phy_dev);
1314
1315 SMSC_TRACE(IFDOWN, "Interface stopped");
1316 return 0;
1317 }
1318
1319 /* Entry point for transmitting a packet */
1320 static int smsc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
1321 {
1322 struct smsc911x_data *pdata = netdev_priv(dev);
1323 unsigned int freespace;
1324 unsigned int tx_cmd_a;
1325 unsigned int tx_cmd_b;
1326 unsigned int temp;
1327 u32 wrsz;
1328 ulong bufp;
1329
1330 freespace = smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TDFREE_;
1331
1332 if (unlikely(freespace < TX_FIFO_LOW_THRESHOLD))
1333 SMSC_WARNING(TX_ERR,
1334 "Tx data fifo low, space available: %d", freespace);
1335
1336 /* Word alignment adjustment */
1337 tx_cmd_a = (u32)((ulong)skb->data & 0x03) << 16;
1338 tx_cmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
1339 tx_cmd_a |= (unsigned int)skb->len;
1340
1341 tx_cmd_b = ((unsigned int)skb->len) << 16;
1342 tx_cmd_b |= (unsigned int)skb->len;
1343
1344 smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_a);
1345 smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_b);
1346
1347 bufp = (ulong)skb->data & (~0x3);
1348 wrsz = (u32)skb->len + 3;
1349 wrsz += (u32)((ulong)skb->data & 0x3);
1350 wrsz >>= 2;
1351
1352 smsc911x_tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
1353 freespace -= (skb->len + 32);
1354 dev_kfree_skb(skb);
1355 dev->trans_start = jiffies;
1356
1357 if (unlikely(smsc911x_tx_get_txstatcount(pdata) >= 30))
1358 smsc911x_tx_update_txcounters(dev);
1359
1360 if (freespace < TX_FIFO_LOW_THRESHOLD) {
1361 netif_stop_queue(dev);
1362 temp = smsc911x_reg_read(pdata, FIFO_INT);
1363 temp &= 0x00FFFFFF;
1364 temp |= 0x32000000;
1365 smsc911x_reg_write(pdata, FIFO_INT, temp);
1366 }
1367
1368 return NETDEV_TX_OK;
1369 }
1370
1371 /* Entry point for getting status counters */
1372 static struct net_device_stats *smsc911x_get_stats(struct net_device *dev)
1373 {
1374 struct smsc911x_data *pdata = netdev_priv(dev);
1375 smsc911x_tx_update_txcounters(dev);
1376 dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
1377 return &dev->stats;
1378 }
1379
1380 /* Entry point for setting addressing modes */
1381 static void smsc911x_set_multicast_list(struct net_device *dev)
1382 {
1383 struct smsc911x_data *pdata = netdev_priv(dev);
1384 unsigned long flags;
1385
1386 if (dev->flags & IFF_PROMISC) {
1387 /* Enabling promiscuous mode */
1388 pdata->set_bits_mask = MAC_CR_PRMS_;
1389 pdata->clear_bits_mask = (MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
1390 pdata->hashhi = 0;
1391 pdata->hashlo = 0;
1392 } else if (dev->flags & IFF_ALLMULTI) {
1393 /* Enabling all multicast mode */
1394 pdata->set_bits_mask = MAC_CR_MCPAS_;
1395 pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_HPFILT_);
1396 pdata->hashhi = 0;
1397 pdata->hashlo = 0;
1398 } else if (dev->mc_count > 0) {
1399 /* Enabling specific multicast addresses */
1400 unsigned int hash_high = 0;
1401 unsigned int hash_low = 0;
1402 unsigned int count = 0;
1403 struct dev_mc_list *mc_list = dev->mc_list;
1404
1405 pdata->set_bits_mask = MAC_CR_HPFILT_;
1406 pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_);
1407
1408 while (mc_list) {
1409 count++;
1410 if ((mc_list->dmi_addrlen) == ETH_ALEN) {
1411 unsigned int bitnum =
1412 smsc911x_hash(mc_list->dmi_addr);
1413 unsigned int mask = 0x01 << (bitnum & 0x1F);
1414 if (bitnum & 0x20)
1415 hash_high |= mask;
1416 else
1417 hash_low |= mask;
1418 } else {
1419 SMSC_WARNING(DRV, "dmi_addrlen != 6");
1420 }
1421 mc_list = mc_list->next;
1422 }
1423 if (count != (unsigned int)dev->mc_count)
1424 SMSC_WARNING(DRV, "mc_count != dev->mc_count");
1425
1426 pdata->hashhi = hash_high;
1427 pdata->hashlo = hash_low;
1428 } else {
1429 /* Enabling local MAC address only */
1430 pdata->set_bits_mask = 0;
1431 pdata->clear_bits_mask =
1432 (MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
1433 pdata->hashhi = 0;
1434 pdata->hashlo = 0;
1435 }
1436
1437 spin_lock_irqsave(&pdata->mac_lock, flags);
1438
1439 if (pdata->generation <= 1) {
1440 /* Older hardware revision - cannot change these flags while
1441 * receiving data */
1442 if (!pdata->multicast_update_pending) {
1443 unsigned int temp;
1444 SMSC_TRACE(HW, "scheduling mcast update");
1445 pdata->multicast_update_pending = 1;
1446
1447 /* Request the hardware to stop, then perform the
1448 * update when we get an RX_STOP interrupt */
1449 temp = smsc911x_mac_read(pdata, MAC_CR);
1450 temp &= ~(MAC_CR_RXEN_);
1451 smsc911x_mac_write(pdata, MAC_CR, temp);
1452 } else {
1453 /* There is another update pending, this should now
1454 * use the newer values */
1455 }
1456 } else {
1457 /* Newer hardware revision - can write immediately */
1458 smsc911x_rx_multicast_update(pdata);
1459 }
1460
1461 spin_unlock_irqrestore(&pdata->mac_lock, flags);
1462 }
1463
1464 static irqreturn_t smsc911x_irqhandler(int irq, void *dev_id)
1465 {
1466 struct net_device *dev = dev_id;
1467 struct smsc911x_data *pdata = netdev_priv(dev);
1468 u32 intsts = smsc911x_reg_read(pdata, INT_STS);
1469 u32 inten = smsc911x_reg_read(pdata, INT_EN);
1470 int serviced = IRQ_NONE;
1471 u32 temp;
1472
1473 if (unlikely(intsts & inten & INT_STS_SW_INT_)) {
1474 temp = smsc911x_reg_read(pdata, INT_EN);
1475 temp &= (~INT_EN_SW_INT_EN_);
1476 smsc911x_reg_write(pdata, INT_EN, temp);
1477 smsc911x_reg_write(pdata, INT_STS, INT_STS_SW_INT_);
1478 pdata->software_irq_signal = 1;
1479 smp_wmb();
1480 serviced = IRQ_HANDLED;
1481 }
1482
1483 if (unlikely(intsts & inten & INT_STS_RXSTOP_INT_)) {
1484 /* Called when there is a multicast update scheduled and
1485 * it is now safe to complete the update */
1486 SMSC_TRACE(INTR, "RX Stop interrupt");
1487 smsc911x_reg_write(pdata, INT_STS, INT_STS_RXSTOP_INT_);
1488 if (pdata->multicast_update_pending)
1489 smsc911x_rx_multicast_update_workaround(pdata);
1490 serviced = IRQ_HANDLED;
1491 }
1492
1493 if (intsts & inten & INT_STS_TDFA_) {
1494 temp = smsc911x_reg_read(pdata, FIFO_INT);
1495 temp |= FIFO_INT_TX_AVAIL_LEVEL_;
1496 smsc911x_reg_write(pdata, FIFO_INT, temp);
1497 smsc911x_reg_write(pdata, INT_STS, INT_STS_TDFA_);
1498 netif_wake_queue(dev);
1499 serviced = IRQ_HANDLED;
1500 }
1501
1502 if (unlikely(intsts & inten & INT_STS_RXE_)) {
1503 SMSC_TRACE(INTR, "RX Error interrupt");
1504 smsc911x_reg_write(pdata, INT_STS, INT_STS_RXE_);
1505 serviced = IRQ_HANDLED;
1506 }
1507
1508 if (likely(intsts & inten & INT_STS_RSFL_)) {
1509 if (likely(napi_schedule_prep(&pdata->napi))) {
1510 /* Disable Rx interrupts */
1511 temp = smsc911x_reg_read(pdata, INT_EN);
1512 temp &= (~INT_EN_RSFL_EN_);
1513 smsc911x_reg_write(pdata, INT_EN, temp);
1514 /* Schedule a NAPI poll */
1515 __napi_schedule(&pdata->napi);
1516 } else {
1517 SMSC_WARNING(RX_ERR,
1518 "napi_schedule_prep failed");
1519 }
1520 serviced = IRQ_HANDLED;
1521 }
1522
1523 return serviced;
1524 }
1525
1526 #ifdef CONFIG_NET_POLL_CONTROLLER
1527 static void smsc911x_poll_controller(struct net_device *dev)
1528 {
1529 disable_irq(dev->irq);
1530 smsc911x_irqhandler(0, dev);
1531 enable_irq(dev->irq);
1532 }
1533 #endif /* CONFIG_NET_POLL_CONTROLLER */
1534
1535 static int smsc911x_set_mac_address(struct net_device *dev, void *p)
1536 {
1537 struct smsc911x_data *pdata = netdev_priv(dev);
1538 struct sockaddr *addr = p;
1539
1540 /* On older hardware revisions we cannot change the mac address
1541 * registers while receiving data. Newer devices can safely change
1542 * this at any time. */
1543 if (pdata->generation <= 1 && netif_running(dev))
1544 return -EBUSY;
1545
1546 if (!is_valid_ether_addr(addr->sa_data))
1547 return -EADDRNOTAVAIL;
1548
1549 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
1550
1551 spin_lock_irq(&pdata->mac_lock);
1552 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
1553 spin_unlock_irq(&pdata->mac_lock);
1554
1555 dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
1556
1557 return 0;
1558 }
1559
1560 /* Standard ioctls for mii-tool */
1561 static int smsc911x_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1562 {
1563 struct smsc911x_data *pdata = netdev_priv(dev);
1564
1565 if (!netif_running(dev) || !pdata->phy_dev)
1566 return -EINVAL;
1567
1568 return phy_mii_ioctl(pdata->phy_dev, if_mii(ifr), cmd);
1569 }
1570
1571 static int
1572 smsc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1573 {
1574 struct smsc911x_data *pdata = netdev_priv(dev);
1575
1576 cmd->maxtxpkt = 1;
1577 cmd->maxrxpkt = 1;
1578 return phy_ethtool_gset(pdata->phy_dev, cmd);
1579 }
1580
1581 static int
1582 smsc911x_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1583 {
1584 struct smsc911x_data *pdata = netdev_priv(dev);
1585
1586 return phy_ethtool_sset(pdata->phy_dev, cmd);
1587 }
1588
1589 static void smsc911x_ethtool_getdrvinfo(struct net_device *dev,
1590 struct ethtool_drvinfo *info)
1591 {
1592 strlcpy(info->driver, SMSC_CHIPNAME, sizeof(info->driver));
1593 strlcpy(info->version, SMSC_DRV_VERSION, sizeof(info->version));
1594 strlcpy(info->bus_info, dev_name(dev->dev.parent),
1595 sizeof(info->bus_info));
1596 }
1597
1598 static int smsc911x_ethtool_nwayreset(struct net_device *dev)
1599 {
1600 struct smsc911x_data *pdata = netdev_priv(dev);
1601
1602 return phy_start_aneg(pdata->phy_dev);
1603 }
1604
1605 static u32 smsc911x_ethtool_getmsglevel(struct net_device *dev)
1606 {
1607 struct smsc911x_data *pdata = netdev_priv(dev);
1608 return pdata->msg_enable;
1609 }
1610
1611 static void smsc911x_ethtool_setmsglevel(struct net_device *dev, u32 level)
1612 {
1613 struct smsc911x_data *pdata = netdev_priv(dev);
1614 pdata->msg_enable = level;
1615 }
1616
1617 static int smsc911x_ethtool_getregslen(struct net_device *dev)
1618 {
1619 return (((E2P_DATA - ID_REV) / 4 + 1) + (WUCSR - MAC_CR) + 1 + 32) *
1620 sizeof(u32);
1621 }
1622
1623 static void
1624 smsc911x_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
1625 void *buf)
1626 {
1627 struct smsc911x_data *pdata = netdev_priv(dev);
1628 struct phy_device *phy_dev = pdata->phy_dev;
1629 unsigned long flags;
1630 unsigned int i;
1631 unsigned int j = 0;
1632 u32 *data = buf;
1633
1634 regs->version = pdata->idrev;
1635 for (i = ID_REV; i <= E2P_DATA; i += (sizeof(u32)))
1636 data[j++] = smsc911x_reg_read(pdata, i);
1637
1638 for (i = MAC_CR; i <= WUCSR; i++) {
1639 spin_lock_irqsave(&pdata->mac_lock, flags);
1640 data[j++] = smsc911x_mac_read(pdata, i);
1641 spin_unlock_irqrestore(&pdata->mac_lock, flags);
1642 }
1643
1644 for (i = 0; i <= 31; i++)
1645 data[j++] = smsc911x_mii_read(phy_dev->bus, phy_dev->addr, i);
1646 }
1647
1648 static void smsc911x_eeprom_enable_access(struct smsc911x_data *pdata)
1649 {
1650 unsigned int temp = smsc911x_reg_read(pdata, GPIO_CFG);
1651 temp &= ~GPIO_CFG_EEPR_EN_;
1652 smsc911x_reg_write(pdata, GPIO_CFG, temp);
1653 msleep(1);
1654 }
1655
1656 static int smsc911x_eeprom_send_cmd(struct smsc911x_data *pdata, u32 op)
1657 {
1658 int timeout = 100;
1659 u32 e2cmd;
1660
1661 SMSC_TRACE(DRV, "op 0x%08x", op);
1662 if (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
1663 SMSC_WARNING(DRV, "Busy at start");
1664 return -EBUSY;
1665 }
1666
1667 e2cmd = op | E2P_CMD_EPC_BUSY_;
1668 smsc911x_reg_write(pdata, E2P_CMD, e2cmd);
1669
1670 do {
1671 msleep(1);
1672 e2cmd = smsc911x_reg_read(pdata, E2P_CMD);
1673 } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
1674
1675 if (!timeout) {
1676 SMSC_TRACE(DRV, "TIMED OUT");
1677 return -EAGAIN;
1678 }
1679
1680 if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
1681 SMSC_TRACE(DRV, "Error occured during eeprom operation");
1682 return -EINVAL;
1683 }
1684
1685 return 0;
1686 }
1687
1688 static int smsc911x_eeprom_read_location(struct smsc911x_data *pdata,
1689 u8 address, u8 *data)
1690 {
1691 u32 op = E2P_CMD_EPC_CMD_READ_ | address;
1692 int ret;
1693
1694 SMSC_TRACE(DRV, "address 0x%x", address);
1695 ret = smsc911x_eeprom_send_cmd(pdata, op);
1696
1697 if (!ret)
1698 data[address] = smsc911x_reg_read(pdata, E2P_DATA);
1699
1700 return ret;
1701 }
1702
1703 static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata,
1704 u8 address, u8 data)
1705 {
1706 u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
1707 u32 temp;
1708 int ret;
1709
1710 SMSC_TRACE(DRV, "address 0x%x, data 0x%x", address, data);
1711 ret = smsc911x_eeprom_send_cmd(pdata, op);
1712
1713 if (!ret) {
1714 op = E2P_CMD_EPC_CMD_WRITE_ | address;
1715 smsc911x_reg_write(pdata, E2P_DATA, (u32)data);
1716
1717 /* Workaround for hardware read-after-write restriction */
1718 temp = smsc911x_reg_read(pdata, BYTE_TEST);
1719
1720 ret = smsc911x_eeprom_send_cmd(pdata, op);
1721 }
1722
1723 return ret;
1724 }
1725
1726 static int smsc911x_ethtool_get_eeprom_len(struct net_device *dev)
1727 {
1728 return SMSC911X_EEPROM_SIZE;
1729 }
1730
1731 static int smsc911x_ethtool_get_eeprom(struct net_device *dev,
1732 struct ethtool_eeprom *eeprom, u8 *data)
1733 {
1734 struct smsc911x_data *pdata = netdev_priv(dev);
1735 u8 eeprom_data[SMSC911X_EEPROM_SIZE];
1736 int len;
1737 int i;
1738
1739 smsc911x_eeprom_enable_access(pdata);
1740
1741 len = min(eeprom->len, SMSC911X_EEPROM_SIZE);
1742 for (i = 0; i < len; i++) {
1743 int ret = smsc911x_eeprom_read_location(pdata, i, eeprom_data);
1744 if (ret < 0) {
1745 eeprom->len = 0;
1746 return ret;
1747 }
1748 }
1749
1750 memcpy(data, &eeprom_data[eeprom->offset], len);
1751 eeprom->len = len;
1752 return 0;
1753 }
1754
1755 static int smsc911x_ethtool_set_eeprom(struct net_device *dev,
1756 struct ethtool_eeprom *eeprom, u8 *data)
1757 {
1758 int ret;
1759 struct smsc911x_data *pdata = netdev_priv(dev);
1760
1761 smsc911x_eeprom_enable_access(pdata);
1762 smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWEN_);
1763 ret = smsc911x_eeprom_write_location(pdata, eeprom->offset, *data);
1764 smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWDS_);
1765
1766 /* Single byte write, according to man page */
1767 eeprom->len = 1;
1768
1769 return ret;
1770 }
1771
1772 static const struct ethtool_ops smsc911x_ethtool_ops = {
1773 .get_settings = smsc911x_ethtool_getsettings,
1774 .set_settings = smsc911x_ethtool_setsettings,
1775 .get_link = ethtool_op_get_link,
1776 .get_drvinfo = smsc911x_ethtool_getdrvinfo,
1777 .nway_reset = smsc911x_ethtool_nwayreset,
1778 .get_msglevel = smsc911x_ethtool_getmsglevel,
1779 .set_msglevel = smsc911x_ethtool_setmsglevel,
1780 .get_regs_len = smsc911x_ethtool_getregslen,
1781 .get_regs = smsc911x_ethtool_getregs,
1782 .get_eeprom_len = smsc911x_ethtool_get_eeprom_len,
1783 .get_eeprom = smsc911x_ethtool_get_eeprom,
1784 .set_eeprom = smsc911x_ethtool_set_eeprom,
1785 };
1786
1787 static const struct net_device_ops smsc911x_netdev_ops = {
1788 .ndo_open = smsc911x_open,
1789 .ndo_stop = smsc911x_stop,
1790 .ndo_start_xmit = smsc911x_hard_start_xmit,
1791 .ndo_get_stats = smsc911x_get_stats,
1792 .ndo_set_multicast_list = smsc911x_set_multicast_list,
1793 .ndo_do_ioctl = smsc911x_do_ioctl,
1794 .ndo_change_mtu = eth_change_mtu,
1795 .ndo_validate_addr = eth_validate_addr,
1796 .ndo_set_mac_address = smsc911x_set_mac_address,
1797 #ifdef CONFIG_NET_POLL_CONTROLLER
1798 .ndo_poll_controller = smsc911x_poll_controller,
1799 #endif
1800 };
1801
1802 /* copies the current mac address from hardware to dev->dev_addr */
1803 static void __devinit smsc911x_read_mac_address(struct net_device *dev)
1804 {
1805 struct smsc911x_data *pdata = netdev_priv(dev);
1806 u32 mac_high16 = smsc911x_mac_read(pdata, ADDRH);
1807 u32 mac_low32 = smsc911x_mac_read(pdata, ADDRL);
1808
1809 dev->dev_addr[0] = (u8)(mac_low32);
1810 dev->dev_addr[1] = (u8)(mac_low32 >> 8);
1811 dev->dev_addr[2] = (u8)(mac_low32 >> 16);
1812 dev->dev_addr[3] = (u8)(mac_low32 >> 24);
1813 dev->dev_addr[4] = (u8)(mac_high16);
1814 dev->dev_addr[5] = (u8)(mac_high16 >> 8);
1815 }
1816
1817 /* Initializing private device structures, only called from probe */
1818 static int __devinit smsc911x_init(struct net_device *dev)
1819 {
1820 struct smsc911x_data *pdata = netdev_priv(dev);
1821 unsigned int byte_test;
1822
1823 SMSC_TRACE(PROBE, "Driver Parameters:");
1824 SMSC_TRACE(PROBE, "LAN base: 0x%08lX",
1825 (unsigned long)pdata->ioaddr);
1826 SMSC_TRACE(PROBE, "IRQ: %d", dev->irq);
1827 SMSC_TRACE(PROBE, "PHY will be autodetected.");
1828
1829 spin_lock_init(&pdata->dev_lock);
1830
1831 if (pdata->ioaddr == 0) {
1832 SMSC_WARNING(PROBE, "pdata->ioaddr: 0x00000000");
1833 return -ENODEV;
1834 }
1835
1836 /* Check byte ordering */
1837 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
1838 SMSC_TRACE(PROBE, "BYTE_TEST: 0x%08X", byte_test);
1839 if (byte_test == 0x43218765) {
1840 SMSC_TRACE(PROBE, "BYTE_TEST looks swapped, "
1841 "applying WORD_SWAP");
1842 smsc911x_reg_write(pdata, WORD_SWAP, 0xffffffff);
1843
1844 /* 1 dummy read of BYTE_TEST is needed after a write to
1845 * WORD_SWAP before its contents are valid */
1846 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
1847
1848 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
1849 }
1850
1851 if (byte_test != 0x87654321) {
1852 SMSC_WARNING(DRV, "BYTE_TEST: 0x%08X", byte_test);
1853 if (((byte_test >> 16) & 0xFFFF) == (byte_test & 0xFFFF)) {
1854 SMSC_WARNING(PROBE,
1855 "top 16 bits equal to bottom 16 bits");
1856 SMSC_TRACE(PROBE, "This may mean the chip is set "
1857 "for 32 bit while the bus is reading 16 bit");
1858 }
1859 return -ENODEV;
1860 }
1861
1862 /* Default generation to zero (all workarounds apply) */
1863 pdata->generation = 0;
1864
1865 pdata->idrev = smsc911x_reg_read(pdata, ID_REV);
1866 switch (pdata->idrev & 0xFFFF0000) {
1867 case 0x01180000:
1868 case 0x01170000:
1869 case 0x01160000:
1870 case 0x01150000:
1871 /* LAN911[5678] family */
1872 pdata->generation = pdata->idrev & 0x0000FFFF;
1873 break;
1874
1875 case 0x118A0000:
1876 case 0x117A0000:
1877 case 0x116A0000:
1878 case 0x115A0000:
1879 /* LAN921[5678] family */
1880 pdata->generation = 3;
1881 break;
1882
1883 case 0x92100000:
1884 case 0x92110000:
1885 case 0x92200000:
1886 case 0x92210000:
1887 /* LAN9210/LAN9211/LAN9220/LAN9221 */
1888 pdata->generation = 4;
1889 break;
1890
1891 default:
1892 SMSC_WARNING(PROBE, "LAN911x not identified, idrev: 0x%08X",
1893 pdata->idrev);
1894 return -ENODEV;
1895 }
1896
1897 SMSC_TRACE(PROBE, "LAN911x identified, idrev: 0x%08X, generation: %d",
1898 pdata->idrev, pdata->generation);
1899
1900 if (pdata->generation == 0)
1901 SMSC_WARNING(PROBE,
1902 "This driver is not intended for this chip revision");
1903
1904 /* workaround for platforms without an eeprom, where the mac address
1905 * is stored elsewhere and set by the bootloader. This saves the
1906 * mac address before resetting the device */
1907 if (pdata->config.flags & SMSC911X_SAVE_MAC_ADDRESS)
1908 smsc911x_read_mac_address(dev);
1909
1910 /* Reset the LAN911x */
1911 if (smsc911x_soft_reset(pdata))
1912 return -ENODEV;
1913
1914 /* Disable all interrupt sources until we bring the device up */
1915 smsc911x_reg_write(pdata, INT_EN, 0);
1916
1917 ether_setup(dev);
1918 dev->flags |= IFF_MULTICAST;
1919 netif_napi_add(dev, &pdata->napi, smsc911x_poll, SMSC_NAPI_WEIGHT);
1920 dev->netdev_ops = &smsc911x_netdev_ops;
1921 dev->ethtool_ops = &smsc911x_ethtool_ops;
1922
1923 return 0;
1924 }
1925
1926 static int __devexit smsc911x_drv_remove(struct platform_device *pdev)
1927 {
1928 struct net_device *dev;
1929 struct smsc911x_data *pdata;
1930 struct resource *res;
1931
1932 dev = platform_get_drvdata(pdev);
1933 BUG_ON(!dev);
1934 pdata = netdev_priv(dev);
1935 BUG_ON(!pdata);
1936 BUG_ON(!pdata->ioaddr);
1937 BUG_ON(!pdata->phy_dev);
1938
1939 SMSC_TRACE(IFDOWN, "Stopping driver.");
1940
1941 phy_disconnect(pdata->phy_dev);
1942 pdata->phy_dev = NULL;
1943 mdiobus_unregister(pdata->mii_bus);
1944 mdiobus_free(pdata->mii_bus);
1945
1946 platform_set_drvdata(pdev, NULL);
1947 unregister_netdev(dev);
1948 free_irq(dev->irq, dev);
1949 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1950 "smsc911x-memory");
1951 if (!res)
1952 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1953
1954 release_mem_region(res->start, resource_size(res));
1955
1956 iounmap(pdata->ioaddr);
1957
1958 free_netdev(dev);
1959
1960 return 0;
1961 }
1962
1963 static int __devinit smsc911x_drv_probe(struct platform_device *pdev)
1964 {
1965 struct net_device *dev;
1966 struct smsc911x_data *pdata;
1967 struct smsc911x_platform_config *config = pdev->dev.platform_data;
1968 struct resource *res, *irq_res;
1969 unsigned int intcfg = 0;
1970 int res_size, irq_flags;
1971 int retval;
1972
1973 pr_info("%s: Driver version %s.\n", SMSC_CHIPNAME, SMSC_DRV_VERSION);
1974
1975 /* platform data specifies irq & dynamic bus configuration */
1976 if (!pdev->dev.platform_data) {
1977 pr_warning("%s: platform_data not provided\n", SMSC_CHIPNAME);
1978 retval = -ENODEV;
1979 goto out_0;
1980 }
1981
1982 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1983 "smsc911x-memory");
1984 if (!res)
1985 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1986 if (!res) {
1987 pr_warning("%s: Could not allocate resource.\n",
1988 SMSC_CHIPNAME);
1989 retval = -ENODEV;
1990 goto out_0;
1991 }
1992 res_size = resource_size(res);
1993
1994 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1995 if (!irq_res) {
1996 pr_warning("%s: Could not allocate irq resource.\n",
1997 SMSC_CHIPNAME);
1998 retval = -ENODEV;
1999 goto out_0;
2000 }
2001
2002 if (!request_mem_region(res->start, res_size, SMSC_CHIPNAME)) {
2003 retval = -EBUSY;
2004 goto out_0;
2005 }
2006
2007 dev = alloc_etherdev(sizeof(struct smsc911x_data));
2008 if (!dev) {
2009 pr_warning("%s: Could not allocate device.\n", SMSC_CHIPNAME);
2010 retval = -ENOMEM;
2011 goto out_release_io_1;
2012 }
2013
2014 SET_NETDEV_DEV(dev, &pdev->dev);
2015
2016 pdata = netdev_priv(dev);
2017
2018 dev->irq = irq_res->start;
2019 irq_flags = irq_res->flags & IRQF_TRIGGER_MASK;
2020 pdata->ioaddr = ioremap_nocache(res->start, res_size);
2021
2022 /* copy config parameters across to pdata */
2023 memcpy(&pdata->config, config, sizeof(pdata->config));
2024
2025 pdata->dev = dev;
2026 pdata->msg_enable = ((1 << debug) - 1);
2027
2028 if (pdata->ioaddr == NULL) {
2029 SMSC_WARNING(PROBE,
2030 "Error smsc911x base address invalid");
2031 retval = -ENOMEM;
2032 goto out_free_netdev_2;
2033 }
2034
2035 retval = smsc911x_init(dev);
2036 if (retval < 0)
2037 goto out_unmap_io_3;
2038
2039 /* configure irq polarity and type before connecting isr */
2040 if (pdata->config.irq_polarity == SMSC911X_IRQ_POLARITY_ACTIVE_HIGH)
2041 intcfg |= INT_CFG_IRQ_POL_;
2042
2043 if (pdata->config.irq_type == SMSC911X_IRQ_TYPE_PUSH_PULL)
2044 intcfg |= INT_CFG_IRQ_TYPE_;
2045
2046 smsc911x_reg_write(pdata, INT_CFG, intcfg);
2047
2048 /* Ensure interrupts are globally disabled before connecting ISR */
2049 smsc911x_reg_write(pdata, INT_EN, 0);
2050 smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
2051
2052 retval = request_irq(dev->irq, smsc911x_irqhandler,
2053 irq_flags | IRQF_SHARED, dev->name, dev);
2054 if (retval) {
2055 SMSC_WARNING(PROBE,
2056 "Unable to claim requested irq: %d", dev->irq);
2057 goto out_unmap_io_3;
2058 }
2059
2060 platform_set_drvdata(pdev, dev);
2061
2062 retval = register_netdev(dev);
2063 if (retval) {
2064 SMSC_WARNING(PROBE,
2065 "Error %i registering device", retval);
2066 goto out_unset_drvdata_4;
2067 } else {
2068 SMSC_TRACE(PROBE, "Network interface: \"%s\"", dev->name);
2069 }
2070
2071 spin_lock_init(&pdata->mac_lock);
2072
2073 retval = smsc911x_mii_init(pdev, dev);
2074 if (retval) {
2075 SMSC_WARNING(PROBE,
2076 "Error %i initialising mii", retval);
2077 goto out_unregister_netdev_5;
2078 }
2079
2080 spin_lock_irq(&pdata->mac_lock);
2081
2082 /* Check if mac address has been specified when bringing interface up */
2083 if (is_valid_ether_addr(dev->dev_addr)) {
2084 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
2085 SMSC_TRACE(PROBE, "MAC Address is specified by configuration");
2086 } else {
2087 /* Try reading mac address from device. if EEPROM is present
2088 * it will already have been set */
2089 smsc911x_read_mac_address(dev);
2090
2091 if (is_valid_ether_addr(dev->dev_addr)) {
2092 /* eeprom values are valid so use them */
2093 SMSC_TRACE(PROBE,
2094 "Mac Address is read from LAN911x EEPROM");
2095 } else {
2096 /* eeprom values are invalid, generate random MAC */
2097 random_ether_addr(dev->dev_addr);
2098 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
2099 SMSC_TRACE(PROBE,
2100 "MAC Address is set to random_ether_addr");
2101 }
2102 }
2103
2104 spin_unlock_irq(&pdata->mac_lock);
2105
2106 dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
2107
2108 return 0;
2109
2110 out_unregister_netdev_5:
2111 unregister_netdev(dev);
2112 out_unset_drvdata_4:
2113 platform_set_drvdata(pdev, NULL);
2114 free_irq(dev->irq, dev);
2115 out_unmap_io_3:
2116 iounmap(pdata->ioaddr);
2117 out_free_netdev_2:
2118 free_netdev(dev);
2119 out_release_io_1:
2120 release_mem_region(res->start, resource_size(res));
2121 out_0:
2122 return retval;
2123 }
2124
2125 #ifdef CONFIG_PM
2126 /* This implementation assumes the devices remains powered on its VDDVARIO
2127 * pins during suspend. */
2128
2129 /* TODO: implement freeze/thaw callbacks for hibernation.*/
2130
2131 static int smsc911x_suspend(struct device *dev)
2132 {
2133 struct net_device *ndev = dev_get_drvdata(dev);
2134 struct smsc911x_data *pdata = netdev_priv(ndev);
2135
2136 /* enable wake on LAN, energy detection and the external PME
2137 * signal. */
2138 smsc911x_reg_write(pdata, PMT_CTRL,
2139 PMT_CTRL_PM_MODE_D1_ | PMT_CTRL_WOL_EN_ |
2140 PMT_CTRL_ED_EN_ | PMT_CTRL_PME_EN_);
2141
2142 return 0;
2143 }
2144
2145 static int smsc911x_resume(struct device *dev)
2146 {
2147 struct net_device *ndev = dev_get_drvdata(dev);
2148 struct smsc911x_data *pdata = netdev_priv(ndev);
2149 unsigned int to = 100;
2150
2151 /* Note 3.11 from the datasheet:
2152 * "When the LAN9220 is in a power saving state, a write of any
2153 * data to the BYTE_TEST register will wake-up the device."
2154 */
2155 smsc911x_reg_write(pdata, BYTE_TEST, 0);
2156
2157 /* poll the READY bit in PMT_CTRL. Any other access to the device is
2158 * forbidden while this bit isn't set. Try for 100ms and return -EIO
2159 * if it failed. */
2160 while (!(smsc911x_reg_read(pdata, PMT_CTRL) & PMT_CTRL_READY_) && --to)
2161 udelay(1000);
2162
2163 return (to == 0) ? -EIO : 0;
2164 }
2165
2166 static struct dev_pm_ops smsc911x_pm_ops = {
2167 .suspend = smsc911x_suspend,
2168 .resume = smsc911x_resume,
2169 };
2170
2171 #define SMSC911X_PM_OPS (&smsc911x_pm_ops)
2172
2173 #else
2174 #define SMSC911X_PM_OPS NULL
2175 #endif
2176
2177 static struct platform_driver smsc911x_driver = {
2178 .probe = smsc911x_drv_probe,
2179 .remove = __devexit_p(smsc911x_drv_remove),
2180 .driver = {
2181 .name = SMSC_CHIPNAME,
2182 .owner = THIS_MODULE,
2183 .pm = SMSC911X_PM_OPS,
2184 },
2185 };
2186
2187 /* Entry point for loading the module */
2188 static int __init smsc911x_init_module(void)
2189 {
2190 return platform_driver_register(&smsc911x_driver);
2191 }
2192
2193 /* entry point for unloading the module */
2194 static void __exit smsc911x_cleanup_module(void)
2195 {
2196 platform_driver_unregister(&smsc911x_driver);
2197 }
2198
2199 module_init(smsc911x_init_module);
2200 module_exit(smsc911x_cleanup_module);
Linux ARM platform port for MOXA ART SoC