?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
initial commit with v2.6.32.60
[linux-2.6.32.60-moxart.git] / drivers / net / wireless / ath / ath9k / main.c
blob31be89b646d27e89f82761a7687ab69f35ee298c
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/nl80211.h>
18 #include "ath9k.h"
19
20 static char *dev_info = "ath9k";
21
22 MODULE_AUTHOR("Atheros Communications");
23 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
24 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
25 MODULE_LICENSE("Dual BSD/GPL");
26
27 static int modparam_nohwcrypt;
28 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
29 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
30
31 /* We use the hw_value as an index into our private channel structure */
32
33 #define CHAN2G(_freq, _idx) { \
34 .center_freq = (_freq), \
35 .hw_value = (_idx), \
36 .max_power = 20, \
37 }
38
39 #define CHAN5G(_freq, _idx) { \
40 .band = IEEE80211_BAND_5GHZ, \
41 .center_freq = (_freq), \
42 .hw_value = (_idx), \
43 .max_power = 20, \
44 }
45
46 /* Some 2 GHz radios are actually tunable on 2312-2732
47 * on 5 MHz steps, we support the channels which we know
48 * we have calibration data for all cards though to make
49 * this static */
50 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
51 CHAN2G(2412, 0), /* Channel 1 */
52 CHAN2G(2417, 1), /* Channel 2 */
53 CHAN2G(2422, 2), /* Channel 3 */
54 CHAN2G(2427, 3), /* Channel 4 */
55 CHAN2G(2432, 4), /* Channel 5 */
56 CHAN2G(2437, 5), /* Channel 6 */
57 CHAN2G(2442, 6), /* Channel 7 */
58 CHAN2G(2447, 7), /* Channel 8 */
59 CHAN2G(2452, 8), /* Channel 9 */
60 CHAN2G(2457, 9), /* Channel 10 */
61 CHAN2G(2462, 10), /* Channel 11 */
62 CHAN2G(2467, 11), /* Channel 12 */
63 CHAN2G(2472, 12), /* Channel 13 */
64 CHAN2G(2484, 13), /* Channel 14 */
65 };
66
67 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
68 * on 5 MHz steps, we support the channels which we know
69 * we have calibration data for all cards though to make
70 * this static */
71 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
72 /* _We_ call this UNII 1 */
73 CHAN5G(5180, 14), /* Channel 36 */
74 CHAN5G(5200, 15), /* Channel 40 */
75 CHAN5G(5220, 16), /* Channel 44 */
76 CHAN5G(5240, 17), /* Channel 48 */
77 /* _We_ call this UNII 2 */
78 CHAN5G(5260, 18), /* Channel 52 */
79 CHAN5G(5280, 19), /* Channel 56 */
80 CHAN5G(5300, 20), /* Channel 60 */
81 CHAN5G(5320, 21), /* Channel 64 */
82 /* _We_ call this "Middle band" */
83 CHAN5G(5500, 22), /* Channel 100 */
84 CHAN5G(5520, 23), /* Channel 104 */
85 CHAN5G(5540, 24), /* Channel 108 */
86 CHAN5G(5560, 25), /* Channel 112 */
87 CHAN5G(5580, 26), /* Channel 116 */
88 CHAN5G(5600, 27), /* Channel 120 */
89 CHAN5G(5620, 28), /* Channel 124 */
90 CHAN5G(5640, 29), /* Channel 128 */
91 CHAN5G(5660, 30), /* Channel 132 */
92 CHAN5G(5680, 31), /* Channel 136 */
93 CHAN5G(5700, 32), /* Channel 140 */
94 /* _We_ call this UNII 3 */
95 CHAN5G(5745, 33), /* Channel 149 */
96 CHAN5G(5765, 34), /* Channel 153 */
97 CHAN5G(5785, 35), /* Channel 157 */
98 CHAN5G(5805, 36), /* Channel 161 */
99 CHAN5G(5825, 37), /* Channel 165 */
100 };
101
102 static void ath_cache_conf_rate(struct ath_softc *sc,
103 struct ieee80211_conf *conf)
104 {
105 switch (conf->channel->band) {
106 case IEEE80211_BAND_2GHZ:
107 if (conf_is_ht20(conf))
108 sc->cur_rate_table =
109 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
110 else if (conf_is_ht40_minus(conf))
111 sc->cur_rate_table =
112 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
113 else if (conf_is_ht40_plus(conf))
114 sc->cur_rate_table =
115 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
116 else
117 sc->cur_rate_table =
118 sc->hw_rate_table[ATH9K_MODE_11G];
119 break;
120 case IEEE80211_BAND_5GHZ:
121 if (conf_is_ht20(conf))
122 sc->cur_rate_table =
123 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
124 else if (conf_is_ht40_minus(conf))
125 sc->cur_rate_table =
126 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
127 else if (conf_is_ht40_plus(conf))
128 sc->cur_rate_table =
129 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
130 else
131 sc->cur_rate_table =
132 sc->hw_rate_table[ATH9K_MODE_11A];
133 break;
134 default:
135 BUG_ON(1);
136 break;
137 }
138 }
139
140 static void ath_update_txpow(struct ath_softc *sc)
141 {
142 struct ath_hw *ah = sc->sc_ah;
143 u32 txpow;
144
145 if (sc->curtxpow != sc->config.txpowlimit) {
146 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
147 /* read back in case value is clamped */
148 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
149 sc->curtxpow = txpow;
150 }
151 }
152
153 static u8 parse_mpdudensity(u8 mpdudensity)
154 {
155 /*
156 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
157 * 0 for no restriction
158 * 1 for 1/4 us
159 * 2 for 1/2 us
160 * 3 for 1 us
161 * 4 for 2 us
162 * 5 for 4 us
163 * 6 for 8 us
164 * 7 for 16 us
165 */
166 switch (mpdudensity) {
167 case 0:
168 return 0;
169 case 1:
170 case 2:
171 case 3:
172 /* Our lower layer calculations limit our precision to
173 1 microsecond */
174 return 1;
175 case 4:
176 return 2;
177 case 5:
178 return 4;
179 case 6:
180 return 8;
181 case 7:
182 return 16;
183 default:
184 return 0;
185 }
186 }
187
188 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
189 {
190 const struct ath_rate_table *rate_table = NULL;
191 struct ieee80211_supported_band *sband;
192 struct ieee80211_rate *rate;
193 int i, maxrates;
194
195 switch (band) {
196 case IEEE80211_BAND_2GHZ:
197 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
198 break;
199 case IEEE80211_BAND_5GHZ:
200 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
201 break;
202 default:
203 break;
204 }
205
206 if (rate_table == NULL)
207 return;
208
209 sband = &sc->sbands[band];
210 rate = sc->rates[band];
211
212 if (rate_table->rate_cnt > ATH_RATE_MAX)
213 maxrates = ATH_RATE_MAX;
214 else
215 maxrates = rate_table->rate_cnt;
216
217 for (i = 0; i < maxrates; i++) {
218 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
219 rate[i].hw_value = rate_table->info[i].ratecode;
220 if (rate_table->info[i].short_preamble) {
221 rate[i].hw_value_short = rate_table->info[i].ratecode |
222 rate_table->info[i].short_preamble;
223 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
224 }
225 sband->n_bitrates++;
226
227 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
228 rate[i].bitrate / 10, rate[i].hw_value);
229 }
230 }
231
232 static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
233 struct ieee80211_hw *hw)
234 {
235 struct ieee80211_channel *curchan = hw->conf.channel;
236 struct ath9k_channel *channel;
237 u8 chan_idx;
238
239 chan_idx = curchan->hw_value;
240 channel = &sc->sc_ah->channels[chan_idx];
241 ath9k_update_ichannel(sc, hw, channel);
242 return channel;
243 }
244
245 /*
246 * Set/change channels. If the channel is really being changed, it's done
247 * by reseting the chip. To accomplish this we must first cleanup any pending
248 * DMA, then restart stuff.
249 */
250 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
251 struct ath9k_channel *hchan)
252 {
253 struct ath_hw *ah = sc->sc_ah;
254 bool fastcc = true, stopped;
255 struct ieee80211_channel *channel = hw->conf.channel;
256 int r;
257
258 if (sc->sc_flags & SC_OP_INVALID)
259 return -EIO;
260
261 ath9k_ps_wakeup(sc);
262
263 /*
264 * This is only performed if the channel settings have
265 * actually changed.
266 *
267 * To switch channels clear any pending DMA operations;
268 * wait long enough for the RX fifo to drain, reset the
269 * hardware at the new frequency, and then re-enable
270 * the relevant bits of the h/w.
271 */
272 ath9k_hw_set_interrupts(ah, 0);
273 ath_drain_all_txq(sc, false);
274 stopped = ath_stoprecv(sc);
275
276 /* XXX: do not flush receive queue here. We don't want
277 * to flush data frames already in queue because of
278 * changing channel. */
279
280 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
281 fastcc = false;
282
283 DPRINTF(sc, ATH_DBG_CONFIG,
284 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
285 sc->sc_ah->curchan->channel,
286 channel->center_freq, sc->tx_chan_width);
287
288 spin_lock_bh(&sc->sc_resetlock);
289
290 r = ath9k_hw_reset(ah, hchan, fastcc);
291 if (r) {
292 DPRINTF(sc, ATH_DBG_FATAL,
293 "Unable to reset channel (%u Mhz) "
294 "reset status %d\n",
295 channel->center_freq, r);
296 spin_unlock_bh(&sc->sc_resetlock);
297 goto ps_restore;
298 }
299 spin_unlock_bh(&sc->sc_resetlock);
300
301 sc->sc_flags &= ~SC_OP_FULL_RESET;
302
303 if (ath_startrecv(sc) != 0) {
304 DPRINTF(sc, ATH_DBG_FATAL,
305 "Unable to restart recv logic\n");
306 r = -EIO;
307 goto ps_restore;
308 }
309
310 ath_cache_conf_rate(sc, &hw->conf);
311 ath_update_txpow(sc);
312 ath9k_hw_set_interrupts(ah, sc->imask);
313
314 ps_restore:
315 ath9k_ps_restore(sc);
316 return r;
317 }
318
319 /*
320 * This routine performs the periodic noise floor calibration function
321 * that is used to adjust and optimize the chip performance. This
322 * takes environmental changes (location, temperature) into account.
323 * When the task is complete, it reschedules itself depending on the
324 * appropriate interval that was calculated.
325 */
326 static void ath_ani_calibrate(unsigned long data)
327 {
328 struct ath_softc *sc = (struct ath_softc *)data;
329 struct ath_hw *ah = sc->sc_ah;
330 bool longcal = false;
331 bool shortcal = false;
332 bool aniflag = false;
333 unsigned int timestamp = jiffies_to_msecs(jiffies);
334 u32 cal_interval, short_cal_interval;
335
336 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
337 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
338
339 /*
340 * don't calibrate when we're scanning.
341 * we are most likely not on our home channel.
342 */
343 spin_lock(&sc->ani_lock);
344 if (sc->sc_flags & SC_OP_SCANNING)
345 goto set_timer;
346
347 /* Only calibrate if awake */
348 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
349 goto set_timer;
350
351 ath9k_ps_wakeup(sc);
352
353 /* Long calibration runs independently of short calibration. */
354 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
355 longcal = true;
356 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
357 sc->ani.longcal_timer = timestamp;
358 }
359
360 /* Short calibration applies only while caldone is false */
361 if (!sc->ani.caldone) {
362 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
363 shortcal = true;
364 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
365 sc->ani.shortcal_timer = timestamp;
366 sc->ani.resetcal_timer = timestamp;
367 }
368 } else {
369 if ((timestamp - sc->ani.resetcal_timer) >=
370 ATH_RESTART_CALINTERVAL) {
371 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
372 if (sc->ani.caldone)
373 sc->ani.resetcal_timer = timestamp;
374 }
375 }
376
377 /* Verify whether we must check ANI */
378 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
379 aniflag = true;
380 sc->ani.checkani_timer = timestamp;
381 }
382
383 /* Skip all processing if there's nothing to do. */
384 if (longcal || shortcal || aniflag) {
385 /* Call ANI routine if necessary */
386 if (aniflag)
387 ath9k_hw_ani_monitor(ah, ah->curchan);
388
389 /* Perform calibration if necessary */
390 if (longcal || shortcal) {
391 sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
392 sc->rx_chainmask, longcal);
393
394 if (longcal)
395 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
396 ah->curchan);
397
398 DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
399 ah->curchan->channel, ah->curchan->channelFlags,
400 sc->ani.noise_floor);
401 }
402 }
403
404 ath9k_ps_restore(sc);
405
406 set_timer:
407 spin_unlock(&sc->ani_lock);
408 /*
409 * Set timer interval based on previous results.
410 * The interval must be the shortest necessary to satisfy ANI,
411 * short calibration and long calibration.
412 */
413 cal_interval = ATH_LONG_CALINTERVAL;
414 if (sc->sc_ah->config.enable_ani)
415 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
416 if (!sc->ani.caldone)
417 cal_interval = min(cal_interval, (u32)short_cal_interval);
418
419 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
420 }
421
422 static void ath_start_ani(struct ath_softc *sc)
423 {
424 unsigned long timestamp = jiffies_to_msecs(jiffies);
425
426 sc->ani.longcal_timer = timestamp;
427 sc->ani.shortcal_timer = timestamp;
428 sc->ani.checkani_timer = timestamp;
429
430 mod_timer(&sc->ani.timer,
431 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
432 }
433
434 /*
435 * Update tx/rx chainmask. For legacy association,
436 * hard code chainmask to 1x1, for 11n association, use
437 * the chainmask configuration, for bt coexistence, use
438 * the chainmask configuration even in legacy mode.
439 */
440 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
441 {
442 if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
443 (sc->btcoex_info.btcoex_scheme != ATH_BTCOEX_CFG_NONE)) {
444 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
445 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
446 } else {
447 sc->tx_chainmask = 1;
448 sc->rx_chainmask = 1;
449 }
450
451 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
452 sc->tx_chainmask, sc->rx_chainmask);
453 }
454
455 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
456 {
457 struct ath_node *an;
458
459 an = (struct ath_node *)sta->drv_priv;
460
461 if (sc->sc_flags & SC_OP_TXAGGR) {
462 ath_tx_node_init(sc, an);
463 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
464 sta->ht_cap.ampdu_factor);
465 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
466 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
467 }
468 }
469
470 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
471 {
472 struct ath_node *an = (struct ath_node *)sta->drv_priv;
473
474 if (sc->sc_flags & SC_OP_TXAGGR)
475 ath_tx_node_cleanup(sc, an);
476 }
477
478 static void ath9k_tasklet(unsigned long data)
479 {
480 struct ath_softc *sc = (struct ath_softc *)data;
481 u32 status = sc->intrstatus;
482
483 ath9k_ps_wakeup(sc);
484
485 if (status & ATH9K_INT_FATAL) {
486 ath_reset(sc, false);
487 ath9k_ps_restore(sc);
488 return;
489 }
490
491 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
492 spin_lock_bh(&sc->rx.rxflushlock);
493 ath_rx_tasklet(sc, 0);
494 spin_unlock_bh(&sc->rx.rxflushlock);
495 }
496
497 if (status & ATH9K_INT_TX)
498 ath_tx_tasklet(sc);
499
500 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
501 /*
502 * TSF sync does not look correct; remain awake to sync with
503 * the next Beacon.
504 */
505 DPRINTF(sc, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
506 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
507 }
508
509 if (sc->btcoex_info.btcoex_scheme == ATH_BTCOEX_CFG_3WIRE)
510 if (status & ATH9K_INT_GENTIMER)
511 ath_gen_timer_isr(sc->sc_ah);
512
513 /* re-enable hardware interrupt */
514 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
515 ath9k_ps_restore(sc);
516 }
517
518 irqreturn_t ath_isr(int irq, void *dev)
519 {
520 #define SCHED_INTR ( \
521 ATH9K_INT_FATAL | \
522 ATH9K_INT_RXORN | \
523 ATH9K_INT_RXEOL | \
524 ATH9K_INT_RX | \
525 ATH9K_INT_TX | \
526 ATH9K_INT_BMISS | \
527 ATH9K_INT_CST | \
528 ATH9K_INT_TSFOOR | \
529 ATH9K_INT_GENTIMER)
530
531 struct ath_softc *sc = dev;
532 struct ath_hw *ah = sc->sc_ah;
533 enum ath9k_int status;
534 bool sched = false;
535
536 /*
537 * The hardware is not ready/present, don't
538 * touch anything. Note this can happen early
539 * on if the IRQ is shared.
540 */
541 if (sc->sc_flags & SC_OP_INVALID)
542 return IRQ_NONE;
543
544
545 /* shared irq, not for us */
546
547 if (!ath9k_hw_intrpend(ah))
548 return IRQ_NONE;
549
550 /*
551 * Figure out the reason(s) for the interrupt. Note
552 * that the hal returns a pseudo-ISR that may include
553 * bits we haven't explicitly enabled so we mask the
554 * value to insure we only process bits we requested.
555 */
556 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
557 status &= sc->imask; /* discard unasked-for bits */
558
559 /*
560 * If there are no status bits set, then this interrupt was not
561 * for me (should have been caught above).
562 */
563 if (!status)
564 return IRQ_NONE;
565
566 /* Cache the status */
567 sc->intrstatus = status;
568
569 if (status & SCHED_INTR)
570 sched = true;
571
572 /*
573 * If a FATAL or RXORN interrupt is received, we have to reset the
574 * chip immediately.
575 */
576 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
577 goto chip_reset;
578
579 if (status & ATH9K_INT_SWBA)
580 tasklet_schedule(&sc->bcon_tasklet);
581
582 if (status & ATH9K_INT_TXURN)
583 ath9k_hw_updatetxtriglevel(ah, true);
584
585 if (status & ATH9K_INT_MIB) {
586 /*
587 * Disable interrupts until we service the MIB
588 * interrupt; otherwise it will continue to
589 * fire.
590 */
591 ath9k_hw_set_interrupts(ah, 0);
592 /*
593 * Let the hal handle the event. We assume
594 * it will clear whatever condition caused
595 * the interrupt.
596 */
597 ath9k_hw_procmibevent(ah);
598 ath9k_hw_set_interrupts(ah, sc->imask);
599 }
600
601 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
602 if (status & ATH9K_INT_TIM_TIMER) {
603 /* Clear RxAbort bit so that we can
604 * receive frames */
605 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
606 ath9k_hw_setrxabort(sc->sc_ah, 0);
607 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
608 }
609
610 chip_reset:
611
612 ath_debug_stat_interrupt(sc, status);
613
614 if (sched) {
615 /* turn off every interrupt except SWBA */
616 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
617 tasklet_schedule(&sc->intr_tq);
618 }
619
620 return IRQ_HANDLED;
621
622 #undef SCHED_INTR
623 }
624
625 static u32 ath_get_extchanmode(struct ath_softc *sc,
626 struct ieee80211_channel *chan,
627 enum nl80211_channel_type channel_type)
628 {
629 u32 chanmode = 0;
630
631 switch (chan->band) {
632 case IEEE80211_BAND_2GHZ:
633 switch(channel_type) {
634 case NL80211_CHAN_NO_HT:
635 case NL80211_CHAN_HT20:
636 chanmode = CHANNEL_G_HT20;
637 break;
638 case NL80211_CHAN_HT40PLUS:
639 chanmode = CHANNEL_G_HT40PLUS;
640 break;
641 case NL80211_CHAN_HT40MINUS:
642 chanmode = CHANNEL_G_HT40MINUS;
643 break;
644 }
645 break;
646 case IEEE80211_BAND_5GHZ:
647 switch(channel_type) {
648 case NL80211_CHAN_NO_HT:
649 case NL80211_CHAN_HT20:
650 chanmode = CHANNEL_A_HT20;
651 break;
652 case NL80211_CHAN_HT40PLUS:
653 chanmode = CHANNEL_A_HT40PLUS;
654 break;
655 case NL80211_CHAN_HT40MINUS:
656 chanmode = CHANNEL_A_HT40MINUS;
657 break;
658 }
659 break;
660 default:
661 break;
662 }
663
664 return chanmode;
665 }
666
667 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
668 struct ath9k_keyval *hk, const u8 *addr,
669 bool authenticator)
670 {
671 const u8 *key_rxmic;
672 const u8 *key_txmic;
673
674 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
675 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
676
677 if (addr == NULL) {
678 /*
679 * Group key installation - only two key cache entries are used
680 * regardless of splitmic capability since group key is only
681 * used either for TX or RX.
682 */
683 if (authenticator) {
684 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
685 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
686 } else {
687 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
688 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
689 }
690 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
691 }
692 if (!sc->splitmic) {
693 /* TX and RX keys share the same key cache entry. */
694 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
695 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
696 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
697 }
698
699 /* Separate key cache entries for TX and RX */
700
701 /* TX key goes at first index, RX key at +32. */
702 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
703 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
704 /* TX MIC entry failed. No need to proceed further */
705 DPRINTF(sc, ATH_DBG_FATAL,
706 "Setting TX MIC Key Failed\n");
707 return 0;
708 }
709
710 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
711 /* XXX delete tx key on failure? */
712 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
713 }
714
715 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
716 {
717 int i;
718
719 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
720 if (test_bit(i, sc->keymap) ||
721 test_bit(i + 64, sc->keymap))
722 continue; /* At least one part of TKIP key allocated */
723 if (sc->splitmic &&
724 (test_bit(i + 32, sc->keymap) ||
725 test_bit(i + 64 + 32, sc->keymap)))
726 continue; /* At least one part of TKIP key allocated */
727
728 /* Found a free slot for a TKIP key */
729 return i;
730 }
731 return -1;
732 }
733
734 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
735 {
736 int i;
737
738 /* First, try to find slots that would not be available for TKIP. */
739 if (sc->splitmic) {
740 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
741 if (!test_bit(i, sc->keymap) &&
742 (test_bit(i + 32, sc->keymap) ||
743 test_bit(i + 64, sc->keymap) ||
744 test_bit(i + 64 + 32, sc->keymap)))
745 return i;
746 if (!test_bit(i + 32, sc->keymap) &&
747 (test_bit(i, sc->keymap) ||
748 test_bit(i + 64, sc->keymap) ||
749 test_bit(i + 64 + 32, sc->keymap)))
750 return i + 32;
751 if (!test_bit(i + 64, sc->keymap) &&
752 (test_bit(i , sc->keymap) ||
753 test_bit(i + 32, sc->keymap) ||
754 test_bit(i + 64 + 32, sc->keymap)))
755 return i + 64;
756 if (!test_bit(i + 64 + 32, sc->keymap) &&
757 (test_bit(i, sc->keymap) ||
758 test_bit(i + 32, sc->keymap) ||
759 test_bit(i + 64, sc->keymap)))
760 return i + 64 + 32;
761 }
762 } else {
763 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
764 if (!test_bit(i, sc->keymap) &&
765 test_bit(i + 64, sc->keymap))
766 return i;
767 if (test_bit(i, sc->keymap) &&
768 !test_bit(i + 64, sc->keymap))
769 return i + 64;
770 }
771 }
772
773 /* No partially used TKIP slots, pick any available slot */
774 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
775 /* Do not allow slots that could be needed for TKIP group keys
776 * to be used. This limitation could be removed if we know that
777 * TKIP will not be used. */
778 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
779 continue;
780 if (sc->splitmic) {
781 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
782 continue;
783 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
784 continue;
785 }
786
787 if (!test_bit(i, sc->keymap))
788 return i; /* Found a free slot for a key */
789 }
790
791 /* No free slot found */
792 return -1;
793 }
794
795 static int ath_key_config(struct ath_softc *sc,
796 struct ieee80211_vif *vif,
797 struct ieee80211_sta *sta,
798 struct ieee80211_key_conf *key)
799 {
800 struct ath9k_keyval hk;
801 const u8 *mac = NULL;
802 int ret = 0;
803 int idx;
804
805 memset(&hk, 0, sizeof(hk));
806
807 switch (key->alg) {
808 case ALG_WEP:
809 hk.kv_type = ATH9K_CIPHER_WEP;
810 break;
811 case ALG_TKIP:
812 hk.kv_type = ATH9K_CIPHER_TKIP;
813 break;
814 case ALG_CCMP:
815 hk.kv_type = ATH9K_CIPHER_AES_CCM;
816 break;
817 default:
818 return -EOPNOTSUPP;
819 }
820
821 hk.kv_len = key->keylen;
822 memcpy(hk.kv_val, key->key, key->keylen);
823
824 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
825 /* For now, use the default keys for broadcast keys. This may
826 * need to change with virtual interfaces. */
827 idx = key->keyidx;
828 } else if (key->keyidx) {
829 if (WARN_ON(!sta))
830 return -EOPNOTSUPP;
831 mac = sta->addr;
832
833 if (vif->type != NL80211_IFTYPE_AP) {
834 /* Only keyidx 0 should be used with unicast key, but
835 * allow this for client mode for now. */
836 idx = key->keyidx;
837 } else
838 return -EIO;
839 } else {
840 if (WARN_ON(!sta))
841 return -EOPNOTSUPP;
842 mac = sta->addr;
843
844 if (key->alg == ALG_TKIP)
845 idx = ath_reserve_key_cache_slot_tkip(sc);
846 else
847 idx = ath_reserve_key_cache_slot(sc);
848 if (idx < 0)
849 return -ENOSPC; /* no free key cache entries */
850 }
851
852 if (key->alg == ALG_TKIP)
853 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
854 vif->type == NL80211_IFTYPE_AP);
855 else
856 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
857
858 if (!ret)
859 return -EIO;
860
861 set_bit(idx, sc->keymap);
862 if (key->alg == ALG_TKIP) {
863 set_bit(idx + 64, sc->keymap);
864 if (sc->splitmic) {
865 set_bit(idx + 32, sc->keymap);
866 set_bit(idx + 64 + 32, sc->keymap);
867 }
868 }
869
870 return idx;
871 }
872
873 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
874 {
875 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
876 if (key->hw_key_idx < IEEE80211_WEP_NKID)
877 return;
878
879 clear_bit(key->hw_key_idx, sc->keymap);
880 if (key->alg != ALG_TKIP)
881 return;
882
883 clear_bit(key->hw_key_idx + 64, sc->keymap);
884 if (sc->splitmic) {
885 clear_bit(key->hw_key_idx + 32, sc->keymap);
886 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
887 }
888 }
889
890 static void setup_ht_cap(struct ath_softc *sc,
891 struct ieee80211_sta_ht_cap *ht_info)
892 {
893 u8 tx_streams, rx_streams;
894
895 ht_info->ht_supported = true;
896 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
897 IEEE80211_HT_CAP_SM_PS |
898 IEEE80211_HT_CAP_SGI_40 |
899 IEEE80211_HT_CAP_DSSSCCK40;
900
901 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
902 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
903
904 /* set up supported mcs set */
905 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
906 tx_streams = !(sc->tx_chainmask & (sc->tx_chainmask - 1)) ? 1 : 2;
907 rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2;
908
909 if (tx_streams != rx_streams) {
910 DPRINTF(sc, ATH_DBG_CONFIG, "TX streams %d, RX streams: %d\n",
911 tx_streams, rx_streams);
912 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
913 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
914 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
915 }
916
917 ht_info->mcs.rx_mask[0] = 0xff;
918 if (rx_streams >= 2)
919 ht_info->mcs.rx_mask[1] = 0xff;
920
921 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
922 }
923
924 static void ath9k_bss_assoc_info(struct ath_softc *sc,
925 struct ieee80211_vif *vif,
926 struct ieee80211_bss_conf *bss_conf)
927 {
928
929 if (bss_conf->assoc) {
930 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
931 bss_conf->aid, sc->curbssid);
932
933 /* New association, store aid */
934 sc->curaid = bss_conf->aid;
935 ath9k_hw_write_associd(sc);
936
937 /*
938 * Request a re-configuration of Beacon related timers
939 * on the receipt of the first Beacon frame (i.e.,
940 * after time sync with the AP).
941 */
942 sc->sc_flags |= SC_OP_BEACON_SYNC;
943
944 /* Configure the beacon */
945 ath_beacon_config(sc, vif);
946
947 /* Reset rssi stats */
948 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
949
950 ath_start_ani(sc);
951 } else {
952 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
953 sc->curaid = 0;
954 /* Stop ANI */
955 del_timer_sync(&sc->ani.timer);
956 }
957 }
958
959 /********************************/
960 /* LED functions */
961 /********************************/
962
963 static void ath_led_blink_work(struct work_struct *work)
964 {
965 struct ath_softc *sc = container_of(work, struct ath_softc,
966 ath_led_blink_work.work);
967
968 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
969 return;
970
971 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
972 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
973 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
974 else
975 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
976 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
977
978 ieee80211_queue_delayed_work(sc->hw,
979 &sc->ath_led_blink_work,
980 (sc->sc_flags & SC_OP_LED_ON) ?
981 msecs_to_jiffies(sc->led_off_duration) :
982 msecs_to_jiffies(sc->led_on_duration));
983
984 sc->led_on_duration = sc->led_on_cnt ?
985 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
986 ATH_LED_ON_DURATION_IDLE;
987 sc->led_off_duration = sc->led_off_cnt ?
988 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
989 ATH_LED_OFF_DURATION_IDLE;
990 sc->led_on_cnt = sc->led_off_cnt = 0;
991 if (sc->sc_flags & SC_OP_LED_ON)
992 sc->sc_flags &= ~SC_OP_LED_ON;
993 else
994 sc->sc_flags |= SC_OP_LED_ON;
995 }
996
997 static void ath_led_brightness(struct led_classdev *led_cdev,
998 enum led_brightness brightness)
999 {
1000 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
1001 struct ath_softc *sc = led->sc;
1002
1003 switch (brightness) {
1004 case LED_OFF:
1005 if (led->led_type == ATH_LED_ASSOC ||
1006 led->led_type == ATH_LED_RADIO) {
1007 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
1008 (led->led_type == ATH_LED_RADIO));
1009 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1010 if (led->led_type == ATH_LED_RADIO)
1011 sc->sc_flags &= ~SC_OP_LED_ON;
1012 } else {
1013 sc->led_off_cnt++;
1014 }
1015 break;
1016 case LED_FULL:
1017 if (led->led_type == ATH_LED_ASSOC) {
1018 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
1019 ieee80211_queue_delayed_work(sc->hw,
1020 &sc->ath_led_blink_work, 0);
1021 } else if (led->led_type == ATH_LED_RADIO) {
1022 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
1023 sc->sc_flags |= SC_OP_LED_ON;
1024 } else {
1025 sc->led_on_cnt++;
1026 }
1027 break;
1028 default:
1029 break;
1030 }
1031 }
1032
1033 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1034 char *trigger)
1035 {
1036 int ret;
1037
1038 led->sc = sc;
1039 led->led_cdev.name = led->name;
1040 led->led_cdev.default_trigger = trigger;
1041 led->led_cdev.brightness_set = ath_led_brightness;
1042
1043 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1044 if (ret)
1045 DPRINTF(sc, ATH_DBG_FATAL,
1046 "Failed to register led:%s", led->name);
1047 else
1048 led->registered = 1;
1049 return ret;
1050 }
1051
1052 static void ath_unregister_led(struct ath_led *led)
1053 {
1054 if (led->registered) {
1055 led_classdev_unregister(&led->led_cdev);
1056 led->registered = 0;
1057 }
1058 }
1059
1060 static void ath_deinit_leds(struct ath_softc *sc)
1061 {
1062 ath_unregister_led(&sc->assoc_led);
1063 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1064 ath_unregister_led(&sc->tx_led);
1065 ath_unregister_led(&sc->rx_led);
1066 ath_unregister_led(&sc->radio_led);
1067 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1068 }
1069
1070 static void ath_init_leds(struct ath_softc *sc)
1071 {
1072 char *trigger;
1073 int ret;
1074
1075 if (AR_SREV_9287(sc->sc_ah))
1076 sc->sc_ah->led_pin = ATH_LED_PIN_9287;
1077 else
1078 sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
1079
1080 /* Configure gpio 1 for output */
1081 ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
1082 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1083 /* LED off, active low */
1084 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1085
1086 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1087
1088 trigger = ieee80211_get_radio_led_name(sc->hw);
1089 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1090 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1091 ret = ath_register_led(sc, &sc->radio_led, trigger);
1092 sc->radio_led.led_type = ATH_LED_RADIO;
1093 if (ret)
1094 goto fail;
1095
1096 trigger = ieee80211_get_assoc_led_name(sc->hw);
1097 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1098 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1099 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1100 sc->assoc_led.led_type = ATH_LED_ASSOC;
1101 if (ret)
1102 goto fail;
1103
1104 trigger = ieee80211_get_tx_led_name(sc->hw);
1105 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1106 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1107 ret = ath_register_led(sc, &sc->tx_led, trigger);
1108 sc->tx_led.led_type = ATH_LED_TX;
1109 if (ret)
1110 goto fail;
1111
1112 trigger = ieee80211_get_rx_led_name(sc->hw);
1113 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1114 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1115 ret = ath_register_led(sc, &sc->rx_led, trigger);
1116 sc->rx_led.led_type = ATH_LED_RX;
1117 if (ret)
1118 goto fail;
1119
1120 return;
1121
1122 fail:
1123 cancel_delayed_work_sync(&sc->ath_led_blink_work);
1124 ath_deinit_leds(sc);
1125 }
1126
1127 void ath_radio_enable(struct ath_softc *sc)
1128 {
1129 struct ath_hw *ah = sc->sc_ah;
1130 struct ieee80211_channel *channel = sc->hw->conf.channel;
1131 int r;
1132
1133 ath9k_ps_wakeup(sc);
1134 ath9k_hw_configpcipowersave(ah, 0, 0);
1135
1136 if (!ah->curchan)
1137 ah->curchan = ath_get_curchannel(sc, sc->hw);
1138
1139 spin_lock_bh(&sc->sc_resetlock);
1140 r = ath9k_hw_reset(ah, ah->curchan, false);
1141 if (r) {
1142 DPRINTF(sc, ATH_DBG_FATAL,
1143 "Unable to reset channel %u (%uMhz) ",
1144 "reset status %d\n",
1145 channel->center_freq, r);
1146 }
1147 spin_unlock_bh(&sc->sc_resetlock);
1148
1149 ath_update_txpow(sc);
1150 if (ath_startrecv(sc) != 0) {
1151 DPRINTF(sc, ATH_DBG_FATAL,
1152 "Unable to restart recv logic\n");
1153 return;
1154 }
1155
1156 if (sc->sc_flags & SC_OP_BEACONS)
1157 ath_beacon_config(sc, NULL); /* restart beacons */
1158
1159 /* Re-Enable interrupts */
1160 ath9k_hw_set_interrupts(ah, sc->imask);
1161
1162 /* Enable LED */
1163 ath9k_hw_cfg_output(ah, ah->led_pin,
1164 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1165 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
1166
1167 ieee80211_wake_queues(sc->hw);
1168 ath9k_ps_restore(sc);
1169 }
1170
1171 void ath_radio_disable(struct ath_softc *sc)
1172 {
1173 struct ath_hw *ah = sc->sc_ah;
1174 struct ieee80211_channel *channel = sc->hw->conf.channel;
1175 int r;
1176
1177 ath9k_ps_wakeup(sc);
1178 ieee80211_stop_queues(sc->hw);
1179
1180 /* Disable LED */
1181 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
1182 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
1183
1184 /* Disable interrupts */
1185 ath9k_hw_set_interrupts(ah, 0);
1186
1187 ath_drain_all_txq(sc, false); /* clear pending tx frames */
1188 ath_stoprecv(sc); /* turn off frame recv */
1189 ath_flushrecv(sc); /* flush recv queue */
1190
1191 if (!ah->curchan)
1192 ah->curchan = ath_get_curchannel(sc, sc->hw);
1193
1194 spin_lock_bh(&sc->sc_resetlock);
1195 r = ath9k_hw_reset(ah, ah->curchan, false);
1196 if (r) {
1197 DPRINTF(sc, ATH_DBG_FATAL,
1198 "Unable to reset channel %u (%uMhz) "
1199 "reset status %d\n",
1200 channel->center_freq, r);
1201 }
1202 spin_unlock_bh(&sc->sc_resetlock);
1203
1204 ath9k_hw_phy_disable(ah);
1205 ath9k_hw_configpcipowersave(ah, 1, 1);
1206 ath9k_ps_restore(sc);
1207 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1208 }
1209
1210 /*******************/
1211 /* Rfkill */
1212 /*******************/
1213
1214 static bool ath_is_rfkill_set(struct ath_softc *sc)
1215 {
1216 struct ath_hw *ah = sc->sc_ah;
1217
1218 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1219 ah->rfkill_polarity;
1220 }
1221
1222 static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
1223 {
1224 struct ath_wiphy *aphy = hw->priv;
1225 struct ath_softc *sc = aphy->sc;
1226 bool blocked = !!ath_is_rfkill_set(sc);
1227
1228 wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
1229 }
1230
1231 static void ath_start_rfkill_poll(struct ath_softc *sc)
1232 {
1233 struct ath_hw *ah = sc->sc_ah;
1234
1235 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1236 wiphy_rfkill_start_polling(sc->hw->wiphy);
1237 }
1238
1239 void ath_cleanup(struct ath_softc *sc)
1240 {
1241 ath_detach(sc);
1242 free_irq(sc->irq, sc);
1243 ath_bus_cleanup(sc);
1244 kfree(sc->sec_wiphy);
1245 ieee80211_free_hw(sc->hw);
1246 }
1247
1248 void ath_detach(struct ath_softc *sc)
1249 {
1250 struct ieee80211_hw *hw = sc->hw;
1251 int i = 0;
1252
1253 ath9k_ps_wakeup(sc);
1254
1255 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1256
1257 ath_deinit_leds(sc);
1258 wiphy_rfkill_stop_polling(sc->hw->wiphy);
1259
1260 for (i = 0; i < sc->num_sec_wiphy; i++) {
1261 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1262 if (aphy == NULL)
1263 continue;
1264 sc->sec_wiphy[i] = NULL;
1265 ieee80211_unregister_hw(aphy->hw);
1266 ieee80211_free_hw(aphy->hw);
1267 }
1268 ieee80211_unregister_hw(hw);
1269 ath_rx_cleanup(sc);
1270 ath_tx_cleanup(sc);
1271
1272 tasklet_kill(&sc->intr_tq);
1273 tasklet_kill(&sc->bcon_tasklet);
1274
1275 if (!(sc->sc_flags & SC_OP_INVALID))
1276 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1277
1278 /* cleanup tx queues */
1279 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1280 if (ATH_TXQ_SETUP(sc, i))
1281 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1282
1283 if ((sc->btcoex_info.no_stomp_timer) &&
1284 sc->btcoex_info.btcoex_scheme == ATH_BTCOEX_CFG_3WIRE)
1285 ath_gen_timer_free(sc->sc_ah, sc->btcoex_info.no_stomp_timer);
1286
1287 ath9k_hw_detach(sc->sc_ah);
1288 sc->sc_ah = NULL;
1289 ath9k_exit_debug(sc);
1290 }
1291
1292 static int ath9k_reg_notifier(struct wiphy *wiphy,
1293 struct regulatory_request *request)
1294 {
1295 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1296 struct ath_wiphy *aphy = hw->priv;
1297 struct ath_softc *sc = aphy->sc;
1298 struct ath_regulatory *reg = &sc->common.regulatory;
1299
1300 return ath_reg_notifier_apply(wiphy, request, reg);
1301 }
1302
1303 /*
1304 * Initialize and fill ath_softc, ath_sofct is the
1305 * "Software Carrier" struct. Historically it has existed
1306 * to allow the separation between hardware specific
1307 * variables (now in ath_hw) and driver specific variables.
1308 */
1309 static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid)
1310 {
1311 struct ath_hw *ah = NULL;
1312 int r = 0, i;
1313 int csz = 0;
1314
1315 /* XXX: hardware will not be ready until ath_open() being called */
1316 sc->sc_flags |= SC_OP_INVALID;
1317
1318 if (ath9k_init_debug(sc) < 0)
1319 printk(KERN_ERR "Unable to create debugfs files\n");
1320
1321 spin_lock_init(&sc->wiphy_lock);
1322 spin_lock_init(&sc->sc_resetlock);
1323 spin_lock_init(&sc->sc_serial_rw);
1324 spin_lock_init(&sc->ani_lock);
1325 spin_lock_init(&sc->sc_pm_lock);
1326 mutex_init(&sc->mutex);
1327 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1328 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1329 (unsigned long)sc);
1330
1331 /*
1332 * Cache line size is used to size and align various
1333 * structures used to communicate with the hardware.
1334 */
1335 ath_read_cachesize(sc, &csz);
1336 /* XXX assert csz is non-zero */
1337 sc->common.cachelsz = csz << 2; /* convert to bytes */
1338
1339 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
1340 if (!ah) {
1341 r = -ENOMEM;
1342 goto bad_no_ah;
1343 }
1344
1345 ah->ah_sc = sc;
1346 ah->hw_version.devid = devid;
1347 ah->hw_version.subsysid = subsysid;
1348 sc->sc_ah = ah;
1349
1350 r = ath9k_hw_init(ah);
1351 if (r) {
1352 DPRINTF(sc, ATH_DBG_FATAL,
1353 "Unable to initialize hardware; "
1354 "initialization status: %d\n", r);
1355 goto bad;
1356 }
1357
1358 /* Get the hardware key cache size. */
1359 sc->keymax = ah->caps.keycache_size;
1360 if (sc->keymax > ATH_KEYMAX) {
1361 DPRINTF(sc, ATH_DBG_ANY,
1362 "Warning, using only %u entries in %u key cache\n",
1363 ATH_KEYMAX, sc->keymax);
1364 sc->keymax = ATH_KEYMAX;
1365 }
1366
1367 /*
1368 * Reset the key cache since some parts do not
1369 * reset the contents on initial power up.
1370 */
1371 for (i = 0; i < sc->keymax; i++)
1372 ath9k_hw_keyreset(ah, (u16) i);
1373
1374 /* default to MONITOR mode */
1375 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1376
1377 /* Setup rate tables */
1378
1379 ath_rate_attach(sc);
1380 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1381 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1382
1383 /*
1384 * Allocate hardware transmit queues: one queue for
1385 * beacon frames and one data queue for each QoS
1386 * priority. Note that the hal handles reseting
1387 * these queues at the needed time.
1388 */
1389 sc->beacon.beaconq = ath_beaconq_setup(ah);
1390 if (sc->beacon.beaconq == -1) {
1391 DPRINTF(sc, ATH_DBG_FATAL,
1392 "Unable to setup a beacon xmit queue\n");
1393 r = -EIO;
1394 goto bad2;
1395 }
1396 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1397 if (sc->beacon.cabq == NULL) {
1398 DPRINTF(sc, ATH_DBG_FATAL,
1399 "Unable to setup CAB xmit queue\n");
1400 r = -EIO;
1401 goto bad2;
1402 }
1403
1404 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1405 ath_cabq_update(sc);
1406
1407 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1408 sc->tx.hwq_map[i] = -1;
1409
1410 /* Setup data queues */
1411 /* NB: ensure BK queue is the lowest priority h/w queue */
1412 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1413 DPRINTF(sc, ATH_DBG_FATAL,
1414 "Unable to setup xmit queue for BK traffic\n");
1415 r = -EIO;
1416 goto bad2;
1417 }
1418
1419 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1420 DPRINTF(sc, ATH_DBG_FATAL,
1421 "Unable to setup xmit queue for BE traffic\n");
1422 r = -EIO;
1423 goto bad2;
1424 }
1425 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1426 DPRINTF(sc, ATH_DBG_FATAL,
1427 "Unable to setup xmit queue for VI traffic\n");
1428 r = -EIO;
1429 goto bad2;
1430 }
1431 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1432 DPRINTF(sc, ATH_DBG_FATAL,
1433 "Unable to setup xmit queue for VO traffic\n");
1434 r = -EIO;
1435 goto bad2;
1436 }
1437
1438 /* Initializes the noise floor to a reasonable default value.
1439 * Later on this will be updated during ANI processing. */
1440
1441 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1442 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1443
1444 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1445 ATH9K_CIPHER_TKIP, NULL)) {
1446 /*
1447 * Whether we should enable h/w TKIP MIC.
1448 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1449 * report WMM capable, so it's always safe to turn on
1450 * TKIP MIC in this case.
1451 */
1452 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1453 0, 1, NULL);
1454 }
1455
1456 /*
1457 * Check whether the separate key cache entries
1458 * are required to handle both tx+rx MIC keys.
1459 * With split mic keys the number of stations is limited
1460 * to 27 otherwise 59.
1461 */
1462 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1463 ATH9K_CIPHER_TKIP, NULL)
1464 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1465 ATH9K_CIPHER_MIC, NULL)
1466 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1467 0, NULL))
1468 sc->splitmic = 1;
1469
1470 /* turn on mcast key search if possible */
1471 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1472 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1473 1, NULL);
1474
1475 sc->config.txpowlimit = ATH_TXPOWER_MAX;
1476
1477 /* 11n Capabilities */
1478 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1479 sc->sc_flags |= SC_OP_TXAGGR;
1480 sc->sc_flags |= SC_OP_RXAGGR;
1481 }
1482
1483 sc->tx_chainmask = ah->caps.tx_chainmask;
1484 sc->rx_chainmask = ah->caps.rx_chainmask;
1485
1486 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1487 sc->rx.defant = ath9k_hw_getdefantenna(ah);
1488
1489 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1490 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
1491
1492 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
1493
1494 /* initialize beacon slots */
1495 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1496 sc->beacon.bslot[i] = NULL;
1497 sc->beacon.bslot_aphy[i] = NULL;
1498 }
1499
1500 /* setup channels and rates */
1501
1502 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1503 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1504 sc->rates[IEEE80211_BAND_2GHZ];
1505 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1506 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1507 ARRAY_SIZE(ath9k_2ghz_chantable);
1508
1509 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1510 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1511 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1512 sc->rates[IEEE80211_BAND_5GHZ];
1513 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1514 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1515 ARRAY_SIZE(ath9k_5ghz_chantable);
1516 }
1517
1518 if (sc->btcoex_info.btcoex_scheme != ATH_BTCOEX_CFG_NONE) {
1519 r = ath9k_hw_btcoex_init(ah);
1520 if (r)
1521 goto bad2;
1522 }
1523
1524 return 0;
1525 bad2:
1526 /* cleanup tx queues */
1527 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1528 if (ATH_TXQ_SETUP(sc, i))
1529 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1530 bad:
1531 ath9k_hw_detach(ah);
1532 sc->sc_ah = NULL;
1533 bad_no_ah:
1534 ath9k_exit_debug(sc);
1535
1536 return r;
1537 }
1538
1539 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1540 {
1541 struct ath_hw *ah = sc->sc_ah;
1542
1543 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1544 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1545 IEEE80211_HW_SIGNAL_DBM |
1546 IEEE80211_HW_SUPPORTS_PS |
1547 IEEE80211_HW_PS_NULLFUNC_STACK |
1548 IEEE80211_HW_REPORTS_TX_ACK_STATUS |
1549 IEEE80211_HW_SPECTRUM_MGMT;
1550
1551 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
1552 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
1553
1554 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1555 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1556
1557 hw->wiphy->interface_modes =
1558 BIT(NL80211_IFTYPE_AP) |
1559 BIT(NL80211_IFTYPE_STATION) |
1560 BIT(NL80211_IFTYPE_ADHOC) |
1561 BIT(NL80211_IFTYPE_MESH_POINT);
1562
1563 if (AR_SREV_5416(ah))
1564 hw->wiphy->ps_default = false;
1565 else
1566 hw->wiphy->ps_default = true;
1567
1568 hw->queues = 4;
1569 hw->max_rates = 4;
1570 hw->channel_change_time = 5000;
1571 hw->max_listen_interval = 10;
1572 /* Hardware supports 10 but we use 4 */
1573 hw->max_rate_tries = 4;
1574 hw->sta_data_size = sizeof(struct ath_node);
1575 hw->vif_data_size = sizeof(struct ath_vif);
1576
1577 hw->rate_control_algorithm = "ath9k_rate_control";
1578
1579 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1580 &sc->sbands[IEEE80211_BAND_2GHZ];
1581 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1582 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1583 &sc->sbands[IEEE80211_BAND_5GHZ];
1584 }
1585
1586 /* Device driver core initialization */
1587 int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid)
1588 {
1589 struct ieee80211_hw *hw = sc->hw;
1590 int error = 0, i;
1591 struct ath_regulatory *reg;
1592
1593 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1594
1595 error = ath_init_softc(devid, sc, subsysid);
1596 if (error != 0)
1597 return error;
1598
1599 /* get mac address from hardware and set in mac80211 */
1600
1601 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1602
1603 ath_set_hw_capab(sc, hw);
1604
1605 error = ath_regd_init(&sc->common.regulatory, sc->hw->wiphy,
1606 ath9k_reg_notifier);
1607 if (error)
1608 return error;
1609
1610 reg = &sc->common.regulatory;
1611
1612 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1613 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1614 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1615 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1616 }
1617
1618 /* initialize tx/rx engine */
1619 error = ath_tx_init(sc, ATH_TXBUF);
1620 if (error != 0)
1621 goto error_attach;
1622
1623 error = ath_rx_init(sc, ATH_RXBUF);
1624 if (error != 0)
1625 goto error_attach;
1626
1627 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1628 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1629 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1630
1631 error = ieee80211_register_hw(hw);
1632
1633 if (!ath_is_world_regd(reg)) {
1634 error = regulatory_hint(hw->wiphy, reg->alpha2);
1635 if (error)
1636 goto error_attach;
1637 }
1638
1639 /* Initialize LED control */
1640 ath_init_leds(sc);
1641
1642 ath_start_rfkill_poll(sc);
1643
1644 return 0;
1645
1646 error_attach:
1647 /* cleanup tx queues */
1648 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1649 if (ATH_TXQ_SETUP(sc, i))
1650 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1651
1652 ath9k_hw_detach(sc->sc_ah);
1653 sc->sc_ah = NULL;
1654 ath9k_exit_debug(sc);
1655
1656 return error;
1657 }
1658
1659 int ath_reset(struct ath_softc *sc, bool retry_tx)
1660 {
1661 struct ath_hw *ah = sc->sc_ah;
1662 struct ieee80211_hw *hw = sc->hw;
1663 int r;
1664
1665 ath9k_hw_set_interrupts(ah, 0);
1666 ath_drain_all_txq(sc, retry_tx);
1667 ath_stoprecv(sc);
1668 ath_flushrecv(sc);
1669
1670 spin_lock_bh(&sc->sc_resetlock);
1671 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1672 if (r)
1673 DPRINTF(sc, ATH_DBG_FATAL,
1674 "Unable to reset hardware; reset status %d\n", r);
1675 spin_unlock_bh(&sc->sc_resetlock);
1676
1677 if (ath_startrecv(sc) != 0)
1678 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1679
1680 /*
1681 * We may be doing a reset in response to a request
1682 * that changes the channel so update any state that
1683 * might change as a result.
1684 */
1685 ath_cache_conf_rate(sc, &hw->conf);
1686
1687 ath_update_txpow(sc);
1688
1689 if (sc->sc_flags & SC_OP_BEACONS)
1690 ath_beacon_config(sc, NULL); /* restart beacons */
1691
1692 ath9k_hw_set_interrupts(ah, sc->imask);
1693
1694 if (retry_tx) {
1695 int i;
1696 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1697 if (ATH_TXQ_SETUP(sc, i)) {
1698 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1699 ath_txq_schedule(sc, &sc->tx.txq[i]);
1700 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1701 }
1702 }
1703 }
1704
1705 return r;
1706 }
1707
1708 /*
1709 * This function will allocate both the DMA descriptor structure, and the
1710 * buffers it contains. These are used to contain the descriptors used
1711 * by the system.
1712 */
1713 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1714 struct list_head *head, const char *name,
1715 int nbuf, int ndesc)
1716 {
1717 #define DS2PHYS(_dd, _ds) \
1718 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1719 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1720 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1721
1722 struct ath_desc *ds;
1723 struct ath_buf *bf;
1724 int i, bsize, error;
1725
1726 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1727 name, nbuf, ndesc);
1728
1729 INIT_LIST_HEAD(head);
1730 /* ath_desc must be a multiple of DWORDs */
1731 if ((sizeof(struct ath_desc) % 4) != 0) {
1732 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1733 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1734 error = -ENOMEM;
1735 goto fail;
1736 }
1737
1738 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1739
1740 /*
1741 * Need additional DMA memory because we can't use
1742 * descriptors that cross the 4K page boundary. Assume
1743 * one skipped descriptor per 4K page.
1744 */
1745 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1746 u32 ndesc_skipped =
1747 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1748 u32 dma_len;
1749
1750 while (ndesc_skipped) {
1751 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1752 dd->dd_desc_len += dma_len;
1753
1754 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1755 };
1756 }
1757
1758 /* allocate descriptors */
1759 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1760 &dd->dd_desc_paddr, GFP_KERNEL);
1761 if (dd->dd_desc == NULL) {
1762 error = -ENOMEM;
1763 goto fail;
1764 }
1765 ds = dd->dd_desc;
1766 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1767 name, ds, (u32) dd->dd_desc_len,
1768 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1769
1770 /* allocate buffers */
1771 bsize = sizeof(struct ath_buf) * nbuf;
1772 bf = kzalloc(bsize, GFP_KERNEL);
1773 if (bf == NULL) {
1774 error = -ENOMEM;
1775 goto fail2;
1776 }
1777 dd->dd_bufptr = bf;
1778
1779 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1780 bf->bf_desc = ds;
1781 bf->bf_daddr = DS2PHYS(dd, ds);
1782
1783 if (!(sc->sc_ah->caps.hw_caps &
1784 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1785 /*
1786 * Skip descriptor addresses which can cause 4KB
1787 * boundary crossing (addr + length) with a 32 dword
1788 * descriptor fetch.
1789 */
1790 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1791 ASSERT((caddr_t) bf->bf_desc <
1792 ((caddr_t) dd->dd_desc +
1793 dd->dd_desc_len));
1794
1795 ds += ndesc;
1796 bf->bf_desc = ds;
1797 bf->bf_daddr = DS2PHYS(dd, ds);
1798 }
1799 }
1800 list_add_tail(&bf->list, head);
1801 }
1802 return 0;
1803 fail2:
1804 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1805 dd->dd_desc_paddr);
1806 fail:
1807 memset(dd, 0, sizeof(*dd));
1808 return error;
1809 #undef ATH_DESC_4KB_BOUND_CHECK
1810 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1811 #undef DS2PHYS
1812 }
1813
1814 void ath_descdma_cleanup(struct ath_softc *sc,
1815 struct ath_descdma *dd,
1816 struct list_head *head)
1817 {
1818 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1819 dd->dd_desc_paddr);
1820
1821 INIT_LIST_HEAD(head);
1822 kfree(dd->dd_bufptr);
1823 memset(dd, 0, sizeof(*dd));
1824 }
1825
1826 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1827 {
1828 int qnum;
1829
1830 switch (queue) {
1831 case 0:
1832 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1833 break;
1834 case 1:
1835 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1836 break;
1837 case 2:
1838 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1839 break;
1840 case 3:
1841 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1842 break;
1843 default:
1844 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1845 break;
1846 }
1847
1848 return qnum;
1849 }
1850
1851 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1852 {
1853 int qnum;
1854
1855 switch (queue) {
1856 case ATH9K_WME_AC_VO:
1857 qnum = 0;
1858 break;
1859 case ATH9K_WME_AC_VI:
1860 qnum = 1;
1861 break;
1862 case ATH9K_WME_AC_BE:
1863 qnum = 2;
1864 break;
1865 case ATH9K_WME_AC_BK:
1866 qnum = 3;
1867 break;
1868 default:
1869 qnum = -1;
1870 break;
1871 }
1872
1873 return qnum;
1874 }
1875
1876 /* XXX: Remove me once we don't depend on ath9k_channel for all
1877 * this redundant data */
1878 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1879 struct ath9k_channel *ichan)
1880 {
1881 struct ieee80211_channel *chan = hw->conf.channel;
1882 struct ieee80211_conf *conf = &hw->conf;
1883
1884 ichan->channel = chan->center_freq;
1885 ichan->chan = chan;
1886
1887 if (chan->band == IEEE80211_BAND_2GHZ) {
1888 ichan->chanmode = CHANNEL_G;
1889 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
1890 } else {
1891 ichan->chanmode = CHANNEL_A;
1892 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1893 }
1894
1895 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1896
1897 if (conf_is_ht(conf)) {
1898 if (conf_is_ht40(conf))
1899 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1900
1901 ichan->chanmode = ath_get_extchanmode(sc, chan,
1902 conf->channel_type);
1903 }
1904 }
1905
1906 /**********************/
1907 /* mac80211 callbacks */
1908 /**********************/
1909
1910 static int ath9k_start(struct ieee80211_hw *hw)
1911 {
1912 struct ath_wiphy *aphy = hw->priv;
1913 struct ath_softc *sc = aphy->sc;
1914 struct ieee80211_channel *curchan = hw->conf.channel;
1915 struct ath9k_channel *init_channel;
1916 int r;
1917
1918 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1919 "initial channel: %d MHz\n", curchan->center_freq);
1920
1921 ath9k_ps_wakeup(sc);
1922
1923 mutex_lock(&sc->mutex);
1924
1925 if (ath9k_wiphy_started(sc)) {
1926 if (sc->chan_idx == curchan->hw_value) {
1927 /*
1928 * Already on the operational channel, the new wiphy
1929 * can be marked active.
1930 */
1931 aphy->state = ATH_WIPHY_ACTIVE;
1932 ieee80211_wake_queues(hw);
1933 } else {
1934 /*
1935 * Another wiphy is on another channel, start the new
1936 * wiphy in paused state.
1937 */
1938 aphy->state = ATH_WIPHY_PAUSED;
1939 ieee80211_stop_queues(hw);
1940 }
1941 mutex_unlock(&sc->mutex);
1942 return 0;
1943 }
1944 aphy->state = ATH_WIPHY_ACTIVE;
1945
1946 /* setup initial channel */
1947
1948 sc->chan_idx = curchan->hw_value;
1949
1950 init_channel = ath_get_curchannel(sc, hw);
1951
1952 /* Reset SERDES registers */
1953 ath9k_hw_configpcipowersave(sc->sc_ah, 0, 0);
1954
1955 /*
1956 * The basic interface to setting the hardware in a good
1957 * state is ``reset''. On return the hardware is known to
1958 * be powered up and with interrupts disabled. This must
1959 * be followed by initialization of the appropriate bits
1960 * and then setup of the interrupt mask.
1961 */
1962 spin_lock_bh(&sc->sc_resetlock);
1963 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1964 if (r) {
1965 DPRINTF(sc, ATH_DBG_FATAL,
1966 "Unable to reset hardware; reset status %d "
1967 "(freq %u MHz)\n", r,
1968 curchan->center_freq);
1969 spin_unlock_bh(&sc->sc_resetlock);
1970 goto mutex_unlock;
1971 }
1972 spin_unlock_bh(&sc->sc_resetlock);
1973
1974 /*
1975 * This is needed only to setup initial state
1976 * but it's best done after a reset.
1977 */
1978 ath_update_txpow(sc);
1979
1980 /*
1981 * Setup the hardware after reset:
1982 * The receive engine is set going.
1983 * Frame transmit is handled entirely
1984 * in the frame output path; there's nothing to do
1985 * here except setup the interrupt mask.
1986 */
1987 if (ath_startrecv(sc) != 0) {
1988 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1989 r = -EIO;
1990 goto mutex_unlock;
1991 }
1992
1993 /* Setup our intr mask. */
1994 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
1995 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1996 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1997
1998 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
1999 sc->imask |= ATH9K_INT_GTT;
2000
2001 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2002 sc->imask |= ATH9K_INT_CST;
2003
2004 ath_cache_conf_rate(sc, &hw->conf);
2005
2006 sc->sc_flags &= ~SC_OP_INVALID;
2007
2008 /* Disable BMISS interrupt when we're not associated */
2009 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2010 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2011
2012 ieee80211_wake_queues(hw);
2013
2014 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
2015
2016 if ((sc->btcoex_info.btcoex_scheme != ATH_BTCOEX_CFG_NONE) &&
2017 !(sc->sc_flags & SC_OP_BTCOEX_ENABLED)) {
2018 ath_btcoex_set_weight(&sc->btcoex_info, AR_BT_COEX_WGHT,
2019 AR_STOMP_LOW_WLAN_WGHT);
2020 ath9k_hw_btcoex_enable(sc->sc_ah);
2021
2022 ath_pcie_aspm_disable(sc);
2023 if (sc->btcoex_info.btcoex_scheme == ATH_BTCOEX_CFG_3WIRE)
2024 ath_btcoex_timer_resume(sc, &sc->btcoex_info);
2025 }
2026
2027 mutex_unlock:
2028 mutex_unlock(&sc->mutex);
2029
2030 ath9k_ps_restore(sc);
2031
2032 return r;
2033 }
2034
2035 static int ath9k_tx(struct ieee80211_hw *hw,
2036 struct sk_buff *skb)
2037 {
2038 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2039 struct ath_wiphy *aphy = hw->priv;
2040 struct ath_softc *sc = aphy->sc;
2041 struct ath_tx_control txctl;
2042 int hdrlen, padsize;
2043
2044 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2045 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2046 "%d\n", wiphy_name(hw->wiphy), aphy->state);
2047 goto exit;
2048 }
2049
2050 if (sc->ps_enabled) {
2051 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2052 /*
2053 * mac80211 does not set PM field for normal data frames, so we
2054 * need to update that based on the current PS mode.
2055 */
2056 if (ieee80211_is_data(hdr->frame_control) &&
2057 !ieee80211_is_nullfunc(hdr->frame_control) &&
2058 !ieee80211_has_pm(hdr->frame_control)) {
2059 DPRINTF(sc, ATH_DBG_PS, "Add PM=1 for a TX frame "
2060 "while in PS mode\n");
2061 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2062 }
2063 }
2064
2065 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2066 /*
2067 * We are using PS-Poll and mac80211 can request TX while in
2068 * power save mode. Need to wake up hardware for the TX to be
2069 * completed and if needed, also for RX of buffered frames.
2070 */
2071 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2072 ath9k_ps_wakeup(sc);
2073 ath9k_hw_setrxabort(sc->sc_ah, 0);
2074 if (ieee80211_is_pspoll(hdr->frame_control)) {
2075 DPRINTF(sc, ATH_DBG_PS, "Sending PS-Poll to pick a "
2076 "buffered frame\n");
2077 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2078 } else {
2079 DPRINTF(sc, ATH_DBG_PS, "Wake up to complete TX\n");
2080 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2081 }
2082 /*
2083 * The actual restore operation will happen only after
2084 * the sc_flags bit is cleared. We are just dropping
2085 * the ps_usecount here.
2086 */
2087 ath9k_ps_restore(sc);
2088 }
2089
2090 memset(&txctl, 0, sizeof(struct ath_tx_control));
2091
2092 /*
2093 * As a temporary workaround, assign seq# here; this will likely need
2094 * to be cleaned up to work better with Beacon transmission and virtual
2095 * BSSes.
2096 */
2097 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2098 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2099 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2100 sc->tx.seq_no += 0x10;
2101 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2102 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2103 }
2104
2105 /* Add the padding after the header if this is not already done */
2106 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2107 if (hdrlen & 3) {
2108 padsize = hdrlen % 4;
2109 if (skb_headroom(skb) < padsize)
2110 return -1;
2111 skb_push(skb, padsize);
2112 memmove(skb->data, skb->data + padsize, hdrlen);
2113 }
2114
2115 /* Check if a tx queue is available */
2116
2117 txctl.txq = ath_test_get_txq(sc, skb);
2118 if (!txctl.txq)
2119 goto exit;
2120
2121 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2122
2123 if (ath_tx_start(hw, skb, &txctl) != 0) {
2124 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2125 goto exit;
2126 }
2127
2128 return 0;
2129 exit:
2130 dev_kfree_skb_any(skb);
2131 return 0;
2132 }
2133
2134 static void ath9k_stop(struct ieee80211_hw *hw)
2135 {
2136 struct ath_wiphy *aphy = hw->priv;
2137 struct ath_softc *sc = aphy->sc;
2138
2139 mutex_lock(&sc->mutex);
2140
2141 aphy->state = ATH_WIPHY_INACTIVE;
2142
2143 cancel_delayed_work_sync(&sc->ath_led_blink_work);
2144 cancel_delayed_work_sync(&sc->tx_complete_work);
2145
2146 if (!sc->num_sec_wiphy) {
2147 cancel_delayed_work_sync(&sc->wiphy_work);
2148 cancel_work_sync(&sc->chan_work);
2149 }
2150
2151 if (sc->sc_flags & SC_OP_INVALID) {
2152 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2153 mutex_unlock(&sc->mutex);
2154 return;
2155 }
2156
2157 if (ath9k_wiphy_started(sc)) {
2158 mutex_unlock(&sc->mutex);
2159 return; /* another wiphy still in use */
2160 }
2161
2162 /* Ensure HW is awake when we try to shut it down. */
2163 ath9k_ps_wakeup(sc);
2164
2165 if (sc->sc_flags & SC_OP_BTCOEX_ENABLED) {
2166 ath9k_hw_btcoex_disable(sc->sc_ah);
2167 if (sc->btcoex_info.btcoex_scheme == ATH_BTCOEX_CFG_3WIRE)
2168 ath_btcoex_timer_pause(sc, &sc->btcoex_info);
2169 }
2170
2171 /* make sure h/w will not generate any interrupt
2172 * before setting the invalid flag. */
2173 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2174
2175 if (!(sc->sc_flags & SC_OP_INVALID)) {
2176 ath_drain_all_txq(sc, false);
2177 ath_stoprecv(sc);
2178 ath9k_hw_phy_disable(sc->sc_ah);
2179 } else
2180 sc->rx.rxlink = NULL;
2181
2182 /* disable HAL and put h/w to sleep */
2183 ath9k_hw_disable(sc->sc_ah);
2184 ath9k_hw_configpcipowersave(sc->sc_ah, 1, 1);
2185 ath9k_ps_restore(sc);
2186
2187 /* Finally, put the chip in FULL SLEEP mode */
2188 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
2189
2190 sc->sc_flags |= SC_OP_INVALID;
2191
2192 mutex_unlock(&sc->mutex);
2193
2194 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2195 }
2196
2197 static int ath9k_add_interface(struct ieee80211_hw *hw,
2198 struct ieee80211_if_init_conf *conf)
2199 {
2200 struct ath_wiphy *aphy = hw->priv;
2201 struct ath_softc *sc = aphy->sc;
2202 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2203 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2204 int ret = 0;
2205
2206 mutex_lock(&sc->mutex);
2207
2208 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2209 sc->nvifs > 0) {
2210 ret = -ENOBUFS;
2211 goto out;
2212 }
2213
2214 switch (conf->type) {
2215 case NL80211_IFTYPE_STATION:
2216 ic_opmode = NL80211_IFTYPE_STATION;
2217 break;
2218 case NL80211_IFTYPE_ADHOC:
2219 case NL80211_IFTYPE_AP:
2220 case NL80211_IFTYPE_MESH_POINT:
2221 if (sc->nbcnvifs >= ATH_BCBUF) {
2222 ret = -ENOBUFS;
2223 goto out;
2224 }
2225 ic_opmode = conf->type;
2226 break;
2227 default:
2228 DPRINTF(sc, ATH_DBG_FATAL,
2229 "Interface type %d not yet supported\n", conf->type);
2230 ret = -EOPNOTSUPP;
2231 goto out;
2232 }
2233
2234 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
2235
2236 /* Set the VIF opmode */
2237 avp->av_opmode = ic_opmode;
2238 avp->av_bslot = -1;
2239
2240 sc->nvifs++;
2241
2242 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2243 ath9k_set_bssid_mask(hw);
2244
2245 if (sc->nvifs > 1)
2246 goto out; /* skip global settings for secondary vif */
2247
2248 if (ic_opmode == NL80211_IFTYPE_AP) {
2249 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2250 sc->sc_flags |= SC_OP_TSF_RESET;
2251 }
2252
2253 /* Set the device opmode */
2254 sc->sc_ah->opmode = ic_opmode;
2255
2256 /*
2257 * Enable MIB interrupts when there are hardware phy counters.
2258 * Note we only do this (at the moment) for station mode.
2259 */
2260 if ((conf->type == NL80211_IFTYPE_STATION) ||
2261 (conf->type == NL80211_IFTYPE_ADHOC) ||
2262 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
2263 sc->imask |= ATH9K_INT_MIB;
2264 sc->imask |= ATH9K_INT_TSFOOR;
2265 }
2266
2267 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2268
2269 if (conf->type == NL80211_IFTYPE_AP ||
2270 conf->type == NL80211_IFTYPE_ADHOC ||
2271 conf->type == NL80211_IFTYPE_MONITOR)
2272 ath_start_ani(sc);
2273
2274 out:
2275 mutex_unlock(&sc->mutex);
2276 return ret;
2277 }
2278
2279 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2280 struct ieee80211_if_init_conf *conf)
2281 {
2282 struct ath_wiphy *aphy = hw->priv;
2283 struct ath_softc *sc = aphy->sc;
2284 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2285 int i;
2286
2287 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2288
2289 mutex_lock(&sc->mutex);
2290
2291 /* Stop ANI */
2292 del_timer_sync(&sc->ani.timer);
2293
2294 /* Reclaim beacon resources */
2295 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2296 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2297 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
2298 ath9k_ps_wakeup(sc);
2299 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2300 ath9k_ps_restore(sc);
2301 }
2302
2303 ath_beacon_return(sc, avp);
2304 sc->sc_flags &= ~SC_OP_BEACONS;
2305
2306 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2307 if (sc->beacon.bslot[i] == conf->vif) {
2308 printk(KERN_DEBUG "%s: vif had allocated beacon "
2309 "slot\n", __func__);
2310 sc->beacon.bslot[i] = NULL;
2311 sc->beacon.bslot_aphy[i] = NULL;
2312 }
2313 }
2314
2315 sc->nvifs--;
2316
2317 mutex_unlock(&sc->mutex);
2318 }
2319
2320 void ath9k_enable_ps(struct ath_softc *sc)
2321 {
2322 sc->ps_enabled = true;
2323 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2324 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2325 sc->imask |= ATH9K_INT_TIM_TIMER;
2326 ath9k_hw_set_interrupts(sc->sc_ah,
2327 sc->imask);
2328 }
2329 }
2330 ath9k_hw_setrxabort(sc->sc_ah, 1);
2331 }
2332
2333 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2334 {
2335 struct ath_wiphy *aphy = hw->priv;
2336 struct ath_softc *sc = aphy->sc;
2337 struct ieee80211_conf *conf = &hw->conf;
2338 struct ath_hw *ah = sc->sc_ah;
2339 bool all_wiphys_idle = false, disable_radio = false;
2340
2341 mutex_lock(&sc->mutex);
2342
2343 /* Leave this as the first check */
2344 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
2345
2346 spin_lock_bh(&sc->wiphy_lock);
2347 all_wiphys_idle = ath9k_all_wiphys_idle(sc);
2348 spin_unlock_bh(&sc->wiphy_lock);
2349
2350 if (conf->flags & IEEE80211_CONF_IDLE){
2351 if (all_wiphys_idle)
2352 disable_radio = true;
2353 }
2354 else if (all_wiphys_idle) {
2355 ath_radio_enable(sc);
2356 DPRINTF(sc, ATH_DBG_CONFIG,
2357 "not-idle: enabling radio\n");
2358 }
2359 }
2360
2361 if (changed & IEEE80211_CONF_CHANGE_PS) {
2362 if (conf->flags & IEEE80211_CONF_PS) {
2363 sc->sc_flags |= SC_OP_PS_ENABLED;
2364 if ((sc->sc_flags & SC_OP_NULLFUNC_COMPLETED)) {
2365 sc->sc_flags &= ~SC_OP_NULLFUNC_COMPLETED;
2366 ath9k_enable_ps(sc);
2367 }
2368 } else {
2369 sc->ps_enabled = false;
2370 sc->sc_flags &= ~(SC_OP_PS_ENABLED |
2371 SC_OP_NULLFUNC_COMPLETED);
2372 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2373 if (!(ah->caps.hw_caps &
2374 ATH9K_HW_CAP_AUTOSLEEP)) {
2375 ath9k_hw_setrxabort(sc->sc_ah, 0);
2376 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2377 SC_OP_WAIT_FOR_CAB |
2378 SC_OP_WAIT_FOR_PSPOLL_DATA |
2379 SC_OP_WAIT_FOR_TX_ACK);
2380 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2381 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2382 ath9k_hw_set_interrupts(sc->sc_ah,
2383 sc->imask);
2384 }
2385 }
2386 }
2387 }
2388
2389 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2390 struct ieee80211_channel *curchan = hw->conf.channel;
2391 int pos = curchan->hw_value;
2392
2393 aphy->chan_idx = pos;
2394 aphy->chan_is_ht = conf_is_ht(conf);
2395
2396 if (aphy->state == ATH_WIPHY_SCAN ||
2397 aphy->state == ATH_WIPHY_ACTIVE)
2398 ath9k_wiphy_pause_all_forced(sc, aphy);
2399 else {
2400 /*
2401 * Do not change operational channel based on a paused
2402 * wiphy changes.
2403 */
2404 goto skip_chan_change;
2405 }
2406
2407 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2408 curchan->center_freq);
2409
2410 /* XXX: remove me eventualy */
2411 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2412
2413 ath_update_chainmask(sc, conf_is_ht(conf));
2414
2415 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2416 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2417 mutex_unlock(&sc->mutex);
2418 return -EINVAL;
2419 }
2420 }
2421
2422 skip_chan_change:
2423 if (changed & IEEE80211_CONF_CHANGE_POWER)
2424 sc->config.txpowlimit = 2 * conf->power_level;
2425
2426 if (disable_radio) {
2427 DPRINTF(sc, ATH_DBG_CONFIG, "idle: disabling radio\n");
2428 ath_radio_disable(sc);
2429 }
2430
2431 mutex_unlock(&sc->mutex);
2432
2433 return 0;
2434 }
2435
2436 #define SUPPORTED_FILTERS \
2437 (FIF_PROMISC_IN_BSS | \
2438 FIF_ALLMULTI | \
2439 FIF_CONTROL | \
2440 FIF_PSPOLL | \
2441 FIF_OTHER_BSS | \
2442 FIF_BCN_PRBRESP_PROMISC | \
2443 FIF_FCSFAIL)
2444
2445 /* FIXME: sc->sc_full_reset ? */
2446 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2447 unsigned int changed_flags,
2448 unsigned int *total_flags,
2449 u64 multicast)
2450 {
2451 struct ath_wiphy *aphy = hw->priv;
2452 struct ath_softc *sc = aphy->sc;
2453 u32 rfilt;
2454
2455 changed_flags &= SUPPORTED_FILTERS;
2456 *total_flags &= SUPPORTED_FILTERS;
2457
2458 sc->rx.rxfilter = *total_flags;
2459 ath9k_ps_wakeup(sc);
2460 rfilt = ath_calcrxfilter(sc);
2461 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2462 ath9k_ps_restore(sc);
2463
2464 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", rfilt);
2465 }
2466
2467 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2468 struct ieee80211_vif *vif,
2469 enum sta_notify_cmd cmd,
2470 struct ieee80211_sta *sta)
2471 {
2472 struct ath_wiphy *aphy = hw->priv;
2473 struct ath_softc *sc = aphy->sc;
2474
2475 if (!(sc->sc_flags & SC_OP_TXAGGR))
2476 return;
2477
2478 switch (cmd) {
2479 case STA_NOTIFY_ADD:
2480 ath_node_attach(sc, sta);
2481 break;
2482 case STA_NOTIFY_REMOVE:
2483 ath_node_detach(sc, sta);
2484 break;
2485 default:
2486 break;
2487 }
2488 }
2489
2490 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2491 const struct ieee80211_tx_queue_params *params)
2492 {
2493 struct ath_wiphy *aphy = hw->priv;
2494 struct ath_softc *sc = aphy->sc;
2495 struct ath9k_tx_queue_info qi;
2496 int ret = 0, qnum;
2497
2498 if (queue >= WME_NUM_AC)
2499 return 0;
2500
2501 mutex_lock(&sc->mutex);
2502
2503 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2504
2505 qi.tqi_aifs = params->aifs;
2506 qi.tqi_cwmin = params->cw_min;
2507 qi.tqi_cwmax = params->cw_max;
2508 qi.tqi_burstTime = params->txop;
2509 qnum = ath_get_hal_qnum(queue, sc);
2510
2511 DPRINTF(sc, ATH_DBG_CONFIG,
2512 "Configure tx [queue/halq] [%d/%d], "
2513 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2514 queue, qnum, params->aifs, params->cw_min,
2515 params->cw_max, params->txop);
2516
2517 ret = ath_txq_update(sc, qnum, &qi);
2518 if (ret)
2519 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2520
2521 mutex_unlock(&sc->mutex);
2522
2523 return ret;
2524 }
2525
2526 static int ath9k_set_key(struct ieee80211_hw *hw,
2527 enum set_key_cmd cmd,
2528 struct ieee80211_vif *vif,
2529 struct ieee80211_sta *sta,
2530 struct ieee80211_key_conf *key)
2531 {
2532 struct ath_wiphy *aphy = hw->priv;
2533 struct ath_softc *sc = aphy->sc;
2534 int ret = 0;
2535
2536 if (modparam_nohwcrypt)
2537 return -ENOSPC;
2538
2539 mutex_lock(&sc->mutex);
2540 ath9k_ps_wakeup(sc);
2541 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
2542
2543 switch (cmd) {
2544 case SET_KEY:
2545 ret = ath_key_config(sc, vif, sta, key);
2546 if (ret >= 0) {
2547 key->hw_key_idx = ret;
2548 /* push IV and Michael MIC generation to stack */
2549 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2550 if (key->alg == ALG_TKIP)
2551 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2552 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2553 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2554 ret = 0;
2555 }
2556 break;
2557 case DISABLE_KEY:
2558 ath_key_delete(sc, key);
2559 break;
2560 default:
2561 ret = -EINVAL;
2562 }
2563
2564 ath9k_ps_restore(sc);
2565 mutex_unlock(&sc->mutex);
2566
2567 return ret;
2568 }
2569
2570 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2571 struct ieee80211_vif *vif,
2572 struct ieee80211_bss_conf *bss_conf,
2573 u32 changed)
2574 {
2575 struct ath_wiphy *aphy = hw->priv;
2576 struct ath_softc *sc = aphy->sc;
2577 struct ath_hw *ah = sc->sc_ah;
2578 struct ath_vif *avp = (void *)vif->drv_priv;
2579 u32 rfilt = 0;
2580 int error, i;
2581
2582 mutex_lock(&sc->mutex);
2583
2584 /*
2585 * TODO: Need to decide which hw opmode to use for
2586 * multi-interface cases
2587 * XXX: This belongs into add_interface!
2588 */
2589 if (vif->type == NL80211_IFTYPE_AP &&
2590 ah->opmode != NL80211_IFTYPE_AP) {
2591 ah->opmode = NL80211_IFTYPE_STATION;
2592 ath9k_hw_setopmode(ah);
2593 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2594 sc->curaid = 0;
2595 ath9k_hw_write_associd(sc);
2596 /* Request full reset to get hw opmode changed properly */
2597 sc->sc_flags |= SC_OP_FULL_RESET;
2598 }
2599
2600 if ((changed & BSS_CHANGED_BSSID) &&
2601 !is_zero_ether_addr(bss_conf->bssid)) {
2602 switch (vif->type) {
2603 case NL80211_IFTYPE_STATION:
2604 case NL80211_IFTYPE_ADHOC:
2605 case NL80211_IFTYPE_MESH_POINT:
2606 /* Set BSSID */
2607 memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
2608 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2609 sc->curaid = 0;
2610 ath9k_hw_write_associd(sc);
2611
2612 /* Set aggregation protection mode parameters */
2613 sc->config.ath_aggr_prot = 0;
2614
2615 DPRINTF(sc, ATH_DBG_CONFIG,
2616 "RX filter 0x%x bssid %pM aid 0x%x\n",
2617 rfilt, sc->curbssid, sc->curaid);
2618
2619 /* need to reconfigure the beacon */
2620 sc->sc_flags &= ~SC_OP_BEACONS ;
2621
2622 break;
2623 default:
2624 break;
2625 }
2626 }
2627
2628 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2629 (vif->type == NL80211_IFTYPE_AP) ||
2630 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2631 if ((changed & BSS_CHANGED_BEACON) ||
2632 (changed & BSS_CHANGED_BEACON_ENABLED &&
2633 bss_conf->enable_beacon)) {
2634 /*
2635 * Allocate and setup the beacon frame.
2636 *
2637 * Stop any previous beacon DMA. This may be
2638 * necessary, for example, when an ibss merge
2639 * causes reconfiguration; we may be called
2640 * with beacon transmission active.
2641 */
2642 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2643
2644 error = ath_beacon_alloc(aphy, vif);
2645 if (!error)
2646 ath_beacon_config(sc, vif);
2647 }
2648 }
2649
2650 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2651 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2652 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2653 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2654 ath9k_hw_keysetmac(sc->sc_ah,
2655 (u16)i,
2656 sc->curbssid);
2657 }
2658
2659 /* Only legacy IBSS for now */
2660 if (vif->type == NL80211_IFTYPE_ADHOC)
2661 ath_update_chainmask(sc, 0);
2662
2663 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2664 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2665 bss_conf->use_short_preamble);
2666 if (bss_conf->use_short_preamble)
2667 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2668 else
2669 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2670 }
2671
2672 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2673 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2674 bss_conf->use_cts_prot);
2675 if (bss_conf->use_cts_prot &&
2676 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2677 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2678 else
2679 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2680 }
2681
2682 if (changed & BSS_CHANGED_ASSOC) {
2683 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2684 bss_conf->assoc);
2685 ath9k_bss_assoc_info(sc, vif, bss_conf);
2686 }
2687
2688 /*
2689 * The HW TSF has to be reset when the beacon interval changes.
2690 * We set the flag here, and ath_beacon_config_ap() would take this
2691 * into account when it gets called through the subsequent
2692 * config_interface() call - with IFCC_BEACON in the changed field.
2693 */
2694
2695 if (changed & BSS_CHANGED_BEACON_INT) {
2696 sc->sc_flags |= SC_OP_TSF_RESET;
2697 sc->beacon_interval = bss_conf->beacon_int;
2698 }
2699
2700 mutex_unlock(&sc->mutex);
2701 }
2702
2703 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2704 {
2705 u64 tsf;
2706 struct ath_wiphy *aphy = hw->priv;
2707 struct ath_softc *sc = aphy->sc;
2708
2709 mutex_lock(&sc->mutex);
2710 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2711 mutex_unlock(&sc->mutex);
2712
2713 return tsf;
2714 }
2715
2716 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2717 {
2718 struct ath_wiphy *aphy = hw->priv;
2719 struct ath_softc *sc = aphy->sc;
2720
2721 mutex_lock(&sc->mutex);
2722 ath9k_hw_settsf64(sc->sc_ah, tsf);
2723 mutex_unlock(&sc->mutex);
2724 }
2725
2726 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2727 {
2728 struct ath_wiphy *aphy = hw->priv;
2729 struct ath_softc *sc = aphy->sc;
2730
2731 mutex_lock(&sc->mutex);
2732 ath9k_hw_reset_tsf(sc->sc_ah);
2733 mutex_unlock(&sc->mutex);
2734 }
2735
2736 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2737 enum ieee80211_ampdu_mlme_action action,
2738 struct ieee80211_sta *sta,
2739 u16 tid, u16 *ssn)
2740 {
2741 struct ath_wiphy *aphy = hw->priv;
2742 struct ath_softc *sc = aphy->sc;
2743 int ret = 0;
2744
2745 switch (action) {
2746 case IEEE80211_AMPDU_RX_START:
2747 if (!(sc->sc_flags & SC_OP_RXAGGR))
2748 ret = -ENOTSUPP;
2749 break;
2750 case IEEE80211_AMPDU_RX_STOP:
2751 break;
2752 case IEEE80211_AMPDU_TX_START:
2753 ath9k_ps_wakeup(sc);
2754 ath_tx_aggr_start(sc, sta, tid, ssn);
2755 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2756 ath9k_ps_restore(sc);
2757 break;
2758 case IEEE80211_AMPDU_TX_STOP:
2759 ath9k_ps_wakeup(sc);
2760 ath_tx_aggr_stop(sc, sta, tid);
2761 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2762 ath9k_ps_restore(sc);
2763 break;
2764 case IEEE80211_AMPDU_TX_OPERATIONAL:
2765 ath9k_ps_wakeup(sc);
2766 ath_tx_aggr_resume(sc, sta, tid);
2767 ath9k_ps_restore(sc);
2768 break;
2769 default:
2770 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2771 }
2772
2773 return ret;
2774 }
2775
2776 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2777 {
2778 struct ath_wiphy *aphy = hw->priv;
2779 struct ath_softc *sc = aphy->sc;
2780
2781 mutex_lock(&sc->mutex);
2782 if (ath9k_wiphy_scanning(sc)) {
2783 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2784 "same time\n");
2785 /*
2786 * Do not allow the concurrent scanning state for now. This
2787 * could be improved with scanning control moved into ath9k.
2788 */
2789 mutex_unlock(&sc->mutex);
2790 return;
2791 }
2792
2793 aphy->state = ATH_WIPHY_SCAN;
2794 ath9k_wiphy_pause_all_forced(sc, aphy);
2795
2796 spin_lock_bh(&sc->ani_lock);
2797 sc->sc_flags |= SC_OP_SCANNING;
2798 spin_unlock_bh(&sc->ani_lock);
2799 mutex_unlock(&sc->mutex);
2800 }
2801
2802 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2803 {
2804 struct ath_wiphy *aphy = hw->priv;
2805 struct ath_softc *sc = aphy->sc;
2806
2807 mutex_lock(&sc->mutex);
2808 spin_lock_bh(&sc->ani_lock);
2809 aphy->state = ATH_WIPHY_ACTIVE;
2810 sc->sc_flags &= ~SC_OP_SCANNING;
2811 sc->sc_flags |= SC_OP_FULL_RESET;
2812 spin_unlock_bh(&sc->ani_lock);
2813 ath_beacon_config(sc, NULL);
2814 mutex_unlock(&sc->mutex);
2815 }
2816
2817 struct ieee80211_ops ath9k_ops = {
2818 .tx = ath9k_tx,
2819 .start = ath9k_start,
2820 .stop = ath9k_stop,
2821 .add_interface = ath9k_add_interface,
2822 .remove_interface = ath9k_remove_interface,
2823 .config = ath9k_config,
2824 .configure_filter = ath9k_configure_filter,
2825 .sta_notify = ath9k_sta_notify,
2826 .conf_tx = ath9k_conf_tx,
2827 .bss_info_changed = ath9k_bss_info_changed,
2828 .set_key = ath9k_set_key,
2829 .get_tsf = ath9k_get_tsf,
2830 .set_tsf = ath9k_set_tsf,
2831 .reset_tsf = ath9k_reset_tsf,
2832 .ampdu_action = ath9k_ampdu_action,
2833 .sw_scan_start = ath9k_sw_scan_start,
2834 .sw_scan_complete = ath9k_sw_scan_complete,
2835 .rfkill_poll = ath9k_rfkill_poll_state,
2836 };
2837
2838 static struct {
2839 u32 version;
2840 const char * name;
2841 } ath_mac_bb_names[] = {
2842 { AR_SREV_VERSION_5416_PCI, "5416" },
2843 { AR_SREV_VERSION_5416_PCIE, "5418" },
2844 { AR_SREV_VERSION_9100, "9100" },
2845 { AR_SREV_VERSION_9160, "9160" },
2846 { AR_SREV_VERSION_9280, "9280" },
2847 { AR_SREV_VERSION_9285, "9285" },
2848 { AR_SREV_VERSION_9287, "9287" }
2849 };
2850
2851 static struct {
2852 u16 version;
2853 const char * name;
2854 } ath_rf_names[] = {
2855 { 0, "5133" },
2856 { AR_RAD5133_SREV_MAJOR, "5133" },
2857 { AR_RAD5122_SREV_MAJOR, "5122" },
2858 { AR_RAD2133_SREV_MAJOR, "2133" },
2859 { AR_RAD2122_SREV_MAJOR, "2122" }
2860 };
2861
2862 /*
2863 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2864 */
2865 const char *
2866 ath_mac_bb_name(u32 mac_bb_version)
2867 {
2868 int i;
2869
2870 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2871 if (ath_mac_bb_names[i].version == mac_bb_version) {
2872 return ath_mac_bb_names[i].name;
2873 }
2874 }
2875
2876 return "????";
2877 }
2878
2879 /*
2880 * Return the RF name. "????" is returned if the RF is unknown.
2881 */
2882 const char *
2883 ath_rf_name(u16 rf_version)
2884 {
2885 int i;
2886
2887 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2888 if (ath_rf_names[i].version == rf_version) {
2889 return ath_rf_names[i].name;
2890 }
2891 }
2892
2893 return "????";
2894 }
2895
2896 static int __init ath9k_init(void)
2897 {
2898 int error;
2899
2900 /* Register rate control algorithm */
2901 error = ath_rate_control_register();
2902 if (error != 0) {
2903 printk(KERN_ERR
2904 "ath9k: Unable to register rate control "
2905 "algorithm: %d\n",
2906 error);
2907 goto err_out;
2908 }
2909
2910 error = ath9k_debug_create_root();
2911 if (error) {
2912 printk(KERN_ERR
2913 "ath9k: Unable to create debugfs root: %d\n",
2914 error);
2915 goto err_rate_unregister;
2916 }
2917
2918 error = ath_pci_init();
2919 if (error < 0) {
2920 printk(KERN_ERR
2921 "ath9k: No PCI devices found, driver not installed.\n");
2922 error = -ENODEV;
2923 goto err_remove_root;
2924 }
2925
2926 error = ath_ahb_init();
2927 if (error < 0) {
2928 error = -ENODEV;
2929 goto err_pci_exit;
2930 }
2931
2932 return 0;
2933
2934 err_pci_exit:
2935 ath_pci_exit();
2936
2937 err_remove_root:
2938 ath9k_debug_remove_root();
2939 err_rate_unregister:
2940 ath_rate_control_unregister();
2941 err_out:
2942 return error;
2943 }
2944 module_init(ath9k_init);
2945
2946 static void __exit ath9k_exit(void)
2947 {
2948 ath_ahb_exit();
2949 ath_pci_exit();
2950 ath9k_debug_remove_root();
2951 ath_rate_control_unregister();
2952 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2953 }
2954 module_exit(ath9k_exit);
Linux ARM platform port for MOXA ART SoC