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initial commit with v2.6.32.60
[linux-2.6.32.60-moxart.git] / drivers / net / wireless / b43 / main.c
blob94dae56310e604538afd9f7307c86420d77ef0f0
1 /*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005-2009 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 SDIO support
12 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
13
14 Some parts of the code in this file are derived from the ipw2200
15 driver Copyright(c) 2003 - 2004 Intel Corporation.
16
17 This program is free software; you can redistribute it and/or modify
18 it under the terms of the GNU General Public License as published by
19 the Free Software Foundation; either version 2 of the License, or
20 (at your option) any later version.
21
22 This program is distributed in the hope that it will be useful,
23 but WITHOUT ANY WARRANTY; without even the implied warranty of
24 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 GNU General Public License for more details.
26
27 You should have received a copy of the GNU General Public License
28 along with this program; see the file COPYING. If not, write to
29 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
30 Boston, MA 02110-1301, USA.
31
32 */
33
34 #include <linux/delay.h>
35 #include <linux/init.h>
36 #include <linux/moduleparam.h>
37 #include <linux/if_arp.h>
38 #include <linux/etherdevice.h>
39 #include <linux/firmware.h>
40 #include <linux/wireless.h>
41 #include <linux/workqueue.h>
42 #include <linux/skbuff.h>
43 #include <linux/io.h>
44 #include <linux/dma-mapping.h>
45 #include <asm/unaligned.h>
46
47 #include "b43.h"
48 #include "main.h"
49 #include "debugfs.h"
50 #include "phy_common.h"
51 #include "phy_g.h"
52 #include "phy_n.h"
53 #include "dma.h"
54 #include "pio.h"
55 #include "sysfs.h"
56 #include "xmit.h"
57 #include "lo.h"
58 #include "pcmcia.h"
59 #include "sdio.h"
60 #include <linux/mmc/sdio_func.h>
61
62 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
63 MODULE_AUTHOR("Martin Langer");
64 MODULE_AUTHOR("Stefano Brivio");
65 MODULE_AUTHOR("Michael Buesch");
66 MODULE_AUTHOR("Gábor Stefanik");
67 MODULE_LICENSE("GPL");
68
69 MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
70
71
72 static int modparam_bad_frames_preempt;
73 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
74 MODULE_PARM_DESC(bad_frames_preempt,
75 "enable(1) / disable(0) Bad Frames Preemption");
76
77 static char modparam_fwpostfix[16];
78 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
79 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
80
81 static int modparam_hwpctl;
82 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
83 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
84
85 static int modparam_nohwcrypt;
86 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
87 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
88
89 static int modparam_hwtkip;
90 module_param_named(hwtkip, modparam_hwtkip, int, 0444);
91 MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
92
93 static int modparam_qos = 1;
94 module_param_named(qos, modparam_qos, int, 0444);
95 MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
96
97 static int modparam_btcoex = 1;
98 module_param_named(btcoex, modparam_btcoex, int, 0444);
99 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
100
101 int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
102 module_param_named(verbose, b43_modparam_verbose, int, 0644);
103 MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
104
105 int b43_modparam_pio = B43_PIO_DEFAULT;
106 module_param_named(pio, b43_modparam_pio, int, 0644);
107 MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO");
108
109 static const struct ssb_device_id b43_ssb_tbl[] = {
110 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
111 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
112 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
113 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
114 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
115 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
116 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
117 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
118 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
119 SSB_DEVTABLE_END
120 };
121
122 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
123
124 /* Channel and ratetables are shared for all devices.
125 * They can't be const, because ieee80211 puts some precalculated
126 * data in there. This data is the same for all devices, so we don't
127 * get concurrency issues */
128 #define RATETAB_ENT(_rateid, _flags) \
129 { \
130 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
131 .hw_value = (_rateid), \
132 .flags = (_flags), \
133 }
134
135 /*
136 * NOTE: When changing this, sync with xmit.c's
137 * b43_plcp_get_bitrate_idx_* functions!
138 */
139 static struct ieee80211_rate __b43_ratetable[] = {
140 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
141 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
142 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
143 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
144 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
145 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
146 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
147 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
148 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
149 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
150 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
151 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
152 };
153
154 #define b43_a_ratetable (__b43_ratetable + 4)
155 #define b43_a_ratetable_size 8
156 #define b43_b_ratetable (__b43_ratetable + 0)
157 #define b43_b_ratetable_size 4
158 #define b43_g_ratetable (__b43_ratetable + 0)
159 #define b43_g_ratetable_size 12
160
161 #define CHAN4G(_channel, _freq, _flags) { \
162 .band = IEEE80211_BAND_2GHZ, \
163 .center_freq = (_freq), \
164 .hw_value = (_channel), \
165 .flags = (_flags), \
166 .max_antenna_gain = 0, \
167 .max_power = 30, \
168 }
169 static struct ieee80211_channel b43_2ghz_chantable[] = {
170 CHAN4G(1, 2412, 0),
171 CHAN4G(2, 2417, 0),
172 CHAN4G(3, 2422, 0),
173 CHAN4G(4, 2427, 0),
174 CHAN4G(5, 2432, 0),
175 CHAN4G(6, 2437, 0),
176 CHAN4G(7, 2442, 0),
177 CHAN4G(8, 2447, 0),
178 CHAN4G(9, 2452, 0),
179 CHAN4G(10, 2457, 0),
180 CHAN4G(11, 2462, 0),
181 CHAN4G(12, 2467, 0),
182 CHAN4G(13, 2472, 0),
183 CHAN4G(14, 2484, 0),
184 };
185 #undef CHAN4G
186
187 #define CHAN5G(_channel, _flags) { \
188 .band = IEEE80211_BAND_5GHZ, \
189 .center_freq = 5000 + (5 * (_channel)), \
190 .hw_value = (_channel), \
191 .flags = (_flags), \
192 .max_antenna_gain = 0, \
193 .max_power = 30, \
194 }
195 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
196 CHAN5G(32, 0), CHAN5G(34, 0),
197 CHAN5G(36, 0), CHAN5G(38, 0),
198 CHAN5G(40, 0), CHAN5G(42, 0),
199 CHAN5G(44, 0), CHAN5G(46, 0),
200 CHAN5G(48, 0), CHAN5G(50, 0),
201 CHAN5G(52, 0), CHAN5G(54, 0),
202 CHAN5G(56, 0), CHAN5G(58, 0),
203 CHAN5G(60, 0), CHAN5G(62, 0),
204 CHAN5G(64, 0), CHAN5G(66, 0),
205 CHAN5G(68, 0), CHAN5G(70, 0),
206 CHAN5G(72, 0), CHAN5G(74, 0),
207 CHAN5G(76, 0), CHAN5G(78, 0),
208 CHAN5G(80, 0), CHAN5G(82, 0),
209 CHAN5G(84, 0), CHAN5G(86, 0),
210 CHAN5G(88, 0), CHAN5G(90, 0),
211 CHAN5G(92, 0), CHAN5G(94, 0),
212 CHAN5G(96, 0), CHAN5G(98, 0),
213 CHAN5G(100, 0), CHAN5G(102, 0),
214 CHAN5G(104, 0), CHAN5G(106, 0),
215 CHAN5G(108, 0), CHAN5G(110, 0),
216 CHAN5G(112, 0), CHAN5G(114, 0),
217 CHAN5G(116, 0), CHAN5G(118, 0),
218 CHAN5G(120, 0), CHAN5G(122, 0),
219 CHAN5G(124, 0), CHAN5G(126, 0),
220 CHAN5G(128, 0), CHAN5G(130, 0),
221 CHAN5G(132, 0), CHAN5G(134, 0),
222 CHAN5G(136, 0), CHAN5G(138, 0),
223 CHAN5G(140, 0), CHAN5G(142, 0),
224 CHAN5G(144, 0), CHAN5G(145, 0),
225 CHAN5G(146, 0), CHAN5G(147, 0),
226 CHAN5G(148, 0), CHAN5G(149, 0),
227 CHAN5G(150, 0), CHAN5G(151, 0),
228 CHAN5G(152, 0), CHAN5G(153, 0),
229 CHAN5G(154, 0), CHAN5G(155, 0),
230 CHAN5G(156, 0), CHAN5G(157, 0),
231 CHAN5G(158, 0), CHAN5G(159, 0),
232 CHAN5G(160, 0), CHAN5G(161, 0),
233 CHAN5G(162, 0), CHAN5G(163, 0),
234 CHAN5G(164, 0), CHAN5G(165, 0),
235 CHAN5G(166, 0), CHAN5G(168, 0),
236 CHAN5G(170, 0), CHAN5G(172, 0),
237 CHAN5G(174, 0), CHAN5G(176, 0),
238 CHAN5G(178, 0), CHAN5G(180, 0),
239 CHAN5G(182, 0), CHAN5G(184, 0),
240 CHAN5G(186, 0), CHAN5G(188, 0),
241 CHAN5G(190, 0), CHAN5G(192, 0),
242 CHAN5G(194, 0), CHAN5G(196, 0),
243 CHAN5G(198, 0), CHAN5G(200, 0),
244 CHAN5G(202, 0), CHAN5G(204, 0),
245 CHAN5G(206, 0), CHAN5G(208, 0),
246 CHAN5G(210, 0), CHAN5G(212, 0),
247 CHAN5G(214, 0), CHAN5G(216, 0),
248 CHAN5G(218, 0), CHAN5G(220, 0),
249 CHAN5G(222, 0), CHAN5G(224, 0),
250 CHAN5G(226, 0), CHAN5G(228, 0),
251 };
252
253 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
254 CHAN5G(34, 0), CHAN5G(36, 0),
255 CHAN5G(38, 0), CHAN5G(40, 0),
256 CHAN5G(42, 0), CHAN5G(44, 0),
257 CHAN5G(46, 0), CHAN5G(48, 0),
258 CHAN5G(52, 0), CHAN5G(56, 0),
259 CHAN5G(60, 0), CHAN5G(64, 0),
260 CHAN5G(100, 0), CHAN5G(104, 0),
261 CHAN5G(108, 0), CHAN5G(112, 0),
262 CHAN5G(116, 0), CHAN5G(120, 0),
263 CHAN5G(124, 0), CHAN5G(128, 0),
264 CHAN5G(132, 0), CHAN5G(136, 0),
265 CHAN5G(140, 0), CHAN5G(149, 0),
266 CHAN5G(153, 0), CHAN5G(157, 0),
267 CHAN5G(161, 0), CHAN5G(165, 0),
268 CHAN5G(184, 0), CHAN5G(188, 0),
269 CHAN5G(192, 0), CHAN5G(196, 0),
270 CHAN5G(200, 0), CHAN5G(204, 0),
271 CHAN5G(208, 0), CHAN5G(212, 0),
272 CHAN5G(216, 0),
273 };
274 #undef CHAN5G
275
276 static struct ieee80211_supported_band b43_band_5GHz_nphy = {
277 .band = IEEE80211_BAND_5GHZ,
278 .channels = b43_5ghz_nphy_chantable,
279 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
280 .bitrates = b43_a_ratetable,
281 .n_bitrates = b43_a_ratetable_size,
282 };
283
284 static struct ieee80211_supported_band b43_band_5GHz_aphy = {
285 .band = IEEE80211_BAND_5GHZ,
286 .channels = b43_5ghz_aphy_chantable,
287 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
288 .bitrates = b43_a_ratetable,
289 .n_bitrates = b43_a_ratetable_size,
290 };
291
292 static struct ieee80211_supported_band b43_band_2GHz = {
293 .band = IEEE80211_BAND_2GHZ,
294 .channels = b43_2ghz_chantable,
295 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
296 .bitrates = b43_g_ratetable,
297 .n_bitrates = b43_g_ratetable_size,
298 };
299
300 static void b43_wireless_core_exit(struct b43_wldev *dev);
301 static int b43_wireless_core_init(struct b43_wldev *dev);
302 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
303 static int b43_wireless_core_start(struct b43_wldev *dev);
304
305 static int b43_ratelimit(struct b43_wl *wl)
306 {
307 if (!wl || !wl->current_dev)
308 return 1;
309 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
310 return 1;
311 /* We are up and running.
312 * Ratelimit the messages to avoid DoS over the net. */
313 return net_ratelimit();
314 }
315
316 void b43info(struct b43_wl *wl, const char *fmt, ...)
317 {
318 va_list args;
319
320 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
321 return;
322 if (!b43_ratelimit(wl))
323 return;
324 va_start(args, fmt);
325 printk(KERN_INFO "b43-%s: ",
326 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
327 vprintk(fmt, args);
328 va_end(args);
329 }
330
331 void b43err(struct b43_wl *wl, const char *fmt, ...)
332 {
333 va_list args;
334
335 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
336 return;
337 if (!b43_ratelimit(wl))
338 return;
339 va_start(args, fmt);
340 printk(KERN_ERR "b43-%s ERROR: ",
341 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
342 vprintk(fmt, args);
343 va_end(args);
344 }
345
346 void b43warn(struct b43_wl *wl, const char *fmt, ...)
347 {
348 va_list args;
349
350 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
351 return;
352 if (!b43_ratelimit(wl))
353 return;
354 va_start(args, fmt);
355 printk(KERN_WARNING "b43-%s warning: ",
356 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
357 vprintk(fmt, args);
358 va_end(args);
359 }
360
361 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
362 {
363 va_list args;
364
365 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
366 return;
367 va_start(args, fmt);
368 printk(KERN_DEBUG "b43-%s debug: ",
369 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
370 vprintk(fmt, args);
371 va_end(args);
372 }
373
374 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
375 {
376 u32 macctl;
377
378 B43_WARN_ON(offset % 4 != 0);
379
380 macctl = b43_read32(dev, B43_MMIO_MACCTL);
381 if (macctl & B43_MACCTL_BE)
382 val = swab32(val);
383
384 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
385 mmiowb();
386 b43_write32(dev, B43_MMIO_RAM_DATA, val);
387 }
388
389 static inline void b43_shm_control_word(struct b43_wldev *dev,
390 u16 routing, u16 offset)
391 {
392 u32 control;
393
394 /* "offset" is the WORD offset. */
395 control = routing;
396 control <<= 16;
397 control |= offset;
398 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
399 }
400
401 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
402 {
403 u32 ret;
404
405 if (routing == B43_SHM_SHARED) {
406 B43_WARN_ON(offset & 0x0001);
407 if (offset & 0x0003) {
408 /* Unaligned access */
409 b43_shm_control_word(dev, routing, offset >> 2);
410 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
411 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
412 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
413
414 goto out;
415 }
416 offset >>= 2;
417 }
418 b43_shm_control_word(dev, routing, offset);
419 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
420 out:
421 return ret;
422 }
423
424 u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
425 {
426 u16 ret;
427
428 if (routing == B43_SHM_SHARED) {
429 B43_WARN_ON(offset & 0x0001);
430 if (offset & 0x0003) {
431 /* Unaligned access */
432 b43_shm_control_word(dev, routing, offset >> 2);
433 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
434
435 goto out;
436 }
437 offset >>= 2;
438 }
439 b43_shm_control_word(dev, routing, offset);
440 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
441 out:
442 return ret;
443 }
444
445 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
446 {
447 if (routing == B43_SHM_SHARED) {
448 B43_WARN_ON(offset & 0x0001);
449 if (offset & 0x0003) {
450 /* Unaligned access */
451 b43_shm_control_word(dev, routing, offset >> 2);
452 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
453 value & 0xFFFF);
454 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
455 b43_write16(dev, B43_MMIO_SHM_DATA,
456 (value >> 16) & 0xFFFF);
457 return;
458 }
459 offset >>= 2;
460 }
461 b43_shm_control_word(dev, routing, offset);
462 b43_write32(dev, B43_MMIO_SHM_DATA, value);
463 }
464
465 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
466 {
467 if (routing == B43_SHM_SHARED) {
468 B43_WARN_ON(offset & 0x0001);
469 if (offset & 0x0003) {
470 /* Unaligned access */
471 b43_shm_control_word(dev, routing, offset >> 2);
472 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
473 return;
474 }
475 offset >>= 2;
476 }
477 b43_shm_control_word(dev, routing, offset);
478 b43_write16(dev, B43_MMIO_SHM_DATA, value);
479 }
480
481 /* Read HostFlags */
482 u64 b43_hf_read(struct b43_wldev *dev)
483 {
484 u64 ret;
485
486 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
487 ret <<= 16;
488 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
489 ret <<= 16;
490 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
491
492 return ret;
493 }
494
495 /* Write HostFlags */
496 void b43_hf_write(struct b43_wldev *dev, u64 value)
497 {
498 u16 lo, mi, hi;
499
500 lo = (value & 0x00000000FFFFULL);
501 mi = (value & 0x0000FFFF0000ULL) >> 16;
502 hi = (value & 0xFFFF00000000ULL) >> 32;
503 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
504 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
505 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
506 }
507
508 /* Read the firmware capabilities bitmask (Opensource firmware only) */
509 static u16 b43_fwcapa_read(struct b43_wldev *dev)
510 {
511 B43_WARN_ON(!dev->fw.opensource);
512 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
513 }
514
515 void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
516 {
517 u32 low, high;
518
519 B43_WARN_ON(dev->dev->id.revision < 3);
520
521 /* The hardware guarantees us an atomic read, if we
522 * read the low register first. */
523 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
524 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
525
526 *tsf = high;
527 *tsf <<= 32;
528 *tsf |= low;
529 }
530
531 static void b43_time_lock(struct b43_wldev *dev)
532 {
533 u32 macctl;
534
535 macctl = b43_read32(dev, B43_MMIO_MACCTL);
536 macctl |= B43_MACCTL_TBTTHOLD;
537 b43_write32(dev, B43_MMIO_MACCTL, macctl);
538 /* Commit the write */
539 b43_read32(dev, B43_MMIO_MACCTL);
540 }
541
542 static void b43_time_unlock(struct b43_wldev *dev)
543 {
544 u32 macctl;
545
546 macctl = b43_read32(dev, B43_MMIO_MACCTL);
547 macctl &= ~B43_MACCTL_TBTTHOLD;
548 b43_write32(dev, B43_MMIO_MACCTL, macctl);
549 /* Commit the write */
550 b43_read32(dev, B43_MMIO_MACCTL);
551 }
552
553 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
554 {
555 u32 low, high;
556
557 B43_WARN_ON(dev->dev->id.revision < 3);
558
559 low = tsf;
560 high = (tsf >> 32);
561 /* The hardware guarantees us an atomic write, if we
562 * write the low register first. */
563 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
564 mmiowb();
565 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
566 mmiowb();
567 }
568
569 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
570 {
571 b43_time_lock(dev);
572 b43_tsf_write_locked(dev, tsf);
573 b43_time_unlock(dev);
574 }
575
576 static
577 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
578 {
579 static const u8 zero_addr[ETH_ALEN] = { 0 };
580 u16 data;
581
582 if (!mac)
583 mac = zero_addr;
584
585 offset |= 0x0020;
586 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
587
588 data = mac[0];
589 data |= mac[1] << 8;
590 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
591 data = mac[2];
592 data |= mac[3] << 8;
593 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
594 data = mac[4];
595 data |= mac[5] << 8;
596 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
597 }
598
599 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
600 {
601 const u8 *mac;
602 const u8 *bssid;
603 u8 mac_bssid[ETH_ALEN * 2];
604 int i;
605 u32 tmp;
606
607 bssid = dev->wl->bssid;
608 mac = dev->wl->mac_addr;
609
610 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
611
612 memcpy(mac_bssid, mac, ETH_ALEN);
613 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
614
615 /* Write our MAC address and BSSID to template ram */
616 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
617 tmp = (u32) (mac_bssid[i + 0]);
618 tmp |= (u32) (mac_bssid[i + 1]) << 8;
619 tmp |= (u32) (mac_bssid[i + 2]) << 16;
620 tmp |= (u32) (mac_bssid[i + 3]) << 24;
621 b43_ram_write(dev, 0x20 + i, tmp);
622 }
623 }
624
625 static void b43_upload_card_macaddress(struct b43_wldev *dev)
626 {
627 b43_write_mac_bssid_templates(dev);
628 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
629 }
630
631 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
632 {
633 /* slot_time is in usec. */
634 /* This test used to exit for all but a G PHY. */
635 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
636 return;
637 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
638 /* Shared memory location 0x0010 is the slot time and should be
639 * set to slot_time; however, this register is initially 0 and changing
640 * the value adversely affects the transmit rate for BCM4311
641 * devices. Until this behavior is unterstood, delete this step
642 *
643 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
644 */
645 }
646
647 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
648 {
649 b43_set_slot_time(dev, 9);
650 }
651
652 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
653 {
654 b43_set_slot_time(dev, 20);
655 }
656
657 /* DummyTransmission function, as documented on
658 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
659 */
660 void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
661 {
662 struct b43_phy *phy = &dev->phy;
663 unsigned int i, max_loop;
664 u16 value;
665 u32 buffer[5] = {
666 0x00000000,
667 0x00D40000,
668 0x00000000,
669 0x01000000,
670 0x00000000,
671 };
672
673 if (ofdm) {
674 max_loop = 0x1E;
675 buffer[0] = 0x000201CC;
676 } else {
677 max_loop = 0xFA;
678 buffer[0] = 0x000B846E;
679 }
680
681 for (i = 0; i < 5; i++)
682 b43_ram_write(dev, i * 4, buffer[i]);
683
684 b43_write16(dev, 0x0568, 0x0000);
685 if (dev->dev->id.revision < 11)
686 b43_write16(dev, 0x07C0, 0x0000);
687 else
688 b43_write16(dev, 0x07C0, 0x0100);
689 value = (ofdm ? 0x41 : 0x40);
690 b43_write16(dev, 0x050C, value);
691 if ((phy->type == B43_PHYTYPE_N) || (phy->type == B43_PHYTYPE_LP))
692 b43_write16(dev, 0x0514, 0x1A02);
693 b43_write16(dev, 0x0508, 0x0000);
694 b43_write16(dev, 0x050A, 0x0000);
695 b43_write16(dev, 0x054C, 0x0000);
696 b43_write16(dev, 0x056A, 0x0014);
697 b43_write16(dev, 0x0568, 0x0826);
698 b43_write16(dev, 0x0500, 0x0000);
699 if (!pa_on && (phy->type == B43_PHYTYPE_N)) {
700 //SPEC TODO
701 }
702
703 switch (phy->type) {
704 case B43_PHYTYPE_N:
705 b43_write16(dev, 0x0502, 0x00D0);
706 break;
707 case B43_PHYTYPE_LP:
708 b43_write16(dev, 0x0502, 0x0050);
709 break;
710 default:
711 b43_write16(dev, 0x0502, 0x0030);
712 }
713
714 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
715 b43_radio_write16(dev, 0x0051, 0x0017);
716 for (i = 0x00; i < max_loop; i++) {
717 value = b43_read16(dev, 0x050E);
718 if (value & 0x0080)
719 break;
720 udelay(10);
721 }
722 for (i = 0x00; i < 0x0A; i++) {
723 value = b43_read16(dev, 0x050E);
724 if (value & 0x0400)
725 break;
726 udelay(10);
727 }
728 for (i = 0x00; i < 0x19; i++) {
729 value = b43_read16(dev, 0x0690);
730 if (!(value & 0x0100))
731 break;
732 udelay(10);
733 }
734 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
735 b43_radio_write16(dev, 0x0051, 0x0037);
736 }
737
738 static void key_write(struct b43_wldev *dev,
739 u8 index, u8 algorithm, const u8 *key)
740 {
741 unsigned int i;
742 u32 offset;
743 u16 value;
744 u16 kidx;
745
746 /* Key index/algo block */
747 kidx = b43_kidx_to_fw(dev, index);
748 value = ((kidx << 4) | algorithm);
749 b43_shm_write16(dev, B43_SHM_SHARED,
750 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
751
752 /* Write the key to the Key Table Pointer offset */
753 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
754 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
755 value = key[i];
756 value |= (u16) (key[i + 1]) << 8;
757 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
758 }
759 }
760
761 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
762 {
763 u32 addrtmp[2] = { 0, 0, };
764 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
765
766 if (b43_new_kidx_api(dev))
767 pairwise_keys_start = B43_NR_GROUP_KEYS;
768
769 B43_WARN_ON(index < pairwise_keys_start);
770 /* We have four default TX keys and possibly four default RX keys.
771 * Physical mac 0 is mapped to physical key 4 or 8, depending
772 * on the firmware version.
773 * So we must adjust the index here.
774 */
775 index -= pairwise_keys_start;
776 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
777
778 if (addr) {
779 addrtmp[0] = addr[0];
780 addrtmp[0] |= ((u32) (addr[1]) << 8);
781 addrtmp[0] |= ((u32) (addr[2]) << 16);
782 addrtmp[0] |= ((u32) (addr[3]) << 24);
783 addrtmp[1] = addr[4];
784 addrtmp[1] |= ((u32) (addr[5]) << 8);
785 }
786
787 /* Receive match transmitter address (RCMTA) mechanism */
788 b43_shm_write32(dev, B43_SHM_RCMTA,
789 (index * 2) + 0, addrtmp[0]);
790 b43_shm_write16(dev, B43_SHM_RCMTA,
791 (index * 2) + 1, addrtmp[1]);
792 }
793
794 /* The ucode will use phase1 key with TEK key to decrypt rx packets.
795 * When a packet is received, the iv32 is checked.
796 * - if it doesn't the packet is returned without modification (and software
797 * decryption can be done). That's what happen when iv16 wrap.
798 * - if it does, the rc4 key is computed, and decryption is tried.
799 * Either it will success and B43_RX_MAC_DEC is returned,
800 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
801 * and the packet is not usable (it got modified by the ucode).
802 * So in order to never have B43_RX_MAC_DECERR, we should provide
803 * a iv32 and phase1key that match. Because we drop packets in case of
804 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
805 * packets will be lost without higher layer knowing (ie no resync possible
806 * until next wrap).
807 *
808 * NOTE : this should support 50 key like RCMTA because
809 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
810 */
811 static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
812 u16 *phase1key)
813 {
814 unsigned int i;
815 u32 offset;
816 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
817
818 if (!modparam_hwtkip)
819 return;
820
821 if (b43_new_kidx_api(dev))
822 pairwise_keys_start = B43_NR_GROUP_KEYS;
823
824 B43_WARN_ON(index < pairwise_keys_start);
825 /* We have four default TX keys and possibly four default RX keys.
826 * Physical mac 0 is mapped to physical key 4 or 8, depending
827 * on the firmware version.
828 * So we must adjust the index here.
829 */
830 index -= pairwise_keys_start;
831 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
832
833 if (b43_debug(dev, B43_DBG_KEYS)) {
834 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
835 index, iv32);
836 }
837 /* Write the key to the RX tkip shared mem */
838 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
839 for (i = 0; i < 10; i += 2) {
840 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
841 phase1key ? phase1key[i / 2] : 0);
842 }
843 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
844 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
845 }
846
847 static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
848 struct ieee80211_key_conf *keyconf, const u8 *addr,
849 u32 iv32, u16 *phase1key)
850 {
851 struct b43_wl *wl = hw_to_b43_wl(hw);
852 struct b43_wldev *dev;
853 int index = keyconf->hw_key_idx;
854
855 if (B43_WARN_ON(!modparam_hwtkip))
856 return;
857
858 /* This is only called from the RX path through mac80211, where
859 * our mutex is already locked. */
860 B43_WARN_ON(!mutex_is_locked(&wl->mutex));
861 dev = wl->current_dev;
862 B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
863
864 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
865
866 rx_tkip_phase1_write(dev, index, iv32, phase1key);
867 keymac_write(dev, index, addr);
868 }
869
870 static void do_key_write(struct b43_wldev *dev,
871 u8 index, u8 algorithm,
872 const u8 *key, size_t key_len, const u8 *mac_addr)
873 {
874 u8 buf[B43_SEC_KEYSIZE] = { 0, };
875 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
876
877 if (b43_new_kidx_api(dev))
878 pairwise_keys_start = B43_NR_GROUP_KEYS;
879
880 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
881 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
882
883 if (index >= pairwise_keys_start)
884 keymac_write(dev, index, NULL); /* First zero out mac. */
885 if (algorithm == B43_SEC_ALGO_TKIP) {
886 /*
887 * We should provide an initial iv32, phase1key pair.
888 * We could start with iv32=0 and compute the corresponding
889 * phase1key, but this means calling ieee80211_get_tkip_key
890 * with a fake skb (or export other tkip function).
891 * Because we are lazy we hope iv32 won't start with
892 * 0xffffffff and let's b43_op_update_tkip_key provide a
893 * correct pair.
894 */
895 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
896 } else if (index >= pairwise_keys_start) /* clear it */
897 rx_tkip_phase1_write(dev, index, 0, NULL);
898 if (key)
899 memcpy(buf, key, key_len);
900 key_write(dev, index, algorithm, buf);
901 if (index >= pairwise_keys_start)
902 keymac_write(dev, index, mac_addr);
903
904 dev->key[index].algorithm = algorithm;
905 }
906
907 static int b43_key_write(struct b43_wldev *dev,
908 int index, u8 algorithm,
909 const u8 *key, size_t key_len,
910 const u8 *mac_addr,
911 struct ieee80211_key_conf *keyconf)
912 {
913 int i;
914 int pairwise_keys_start;
915
916 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
917 * - Temporal Encryption Key (128 bits)
918 * - Temporal Authenticator Tx MIC Key (64 bits)
919 * - Temporal Authenticator Rx MIC Key (64 bits)
920 *
921 * Hardware only store TEK
922 */
923 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
924 key_len = 16;
925 if (key_len > B43_SEC_KEYSIZE)
926 return -EINVAL;
927 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
928 /* Check that we don't already have this key. */
929 B43_WARN_ON(dev->key[i].keyconf == keyconf);
930 }
931 if (index < 0) {
932 /* Pairwise key. Get an empty slot for the key. */
933 if (b43_new_kidx_api(dev))
934 pairwise_keys_start = B43_NR_GROUP_KEYS;
935 else
936 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
937 for (i = pairwise_keys_start;
938 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
939 i++) {
940 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
941 if (!dev->key[i].keyconf) {
942 /* found empty */
943 index = i;
944 break;
945 }
946 }
947 if (index < 0) {
948 b43warn(dev->wl, "Out of hardware key memory\n");
949 return -ENOSPC;
950 }
951 } else
952 B43_WARN_ON(index > 3);
953
954 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
955 if ((index <= 3) && !b43_new_kidx_api(dev)) {
956 /* Default RX key */
957 B43_WARN_ON(mac_addr);
958 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
959 }
960 keyconf->hw_key_idx = index;
961 dev->key[index].keyconf = keyconf;
962
963 return 0;
964 }
965
966 static int b43_key_clear(struct b43_wldev *dev, int index)
967 {
968 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
969 return -EINVAL;
970 do_key_write(dev, index, B43_SEC_ALGO_NONE,
971 NULL, B43_SEC_KEYSIZE, NULL);
972 if ((index <= 3) && !b43_new_kidx_api(dev)) {
973 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
974 NULL, B43_SEC_KEYSIZE, NULL);
975 }
976 dev->key[index].keyconf = NULL;
977
978 return 0;
979 }
980
981 static void b43_clear_keys(struct b43_wldev *dev)
982 {
983 int i, count;
984
985 if (b43_new_kidx_api(dev))
986 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
987 else
988 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
989 for (i = 0; i < count; i++)
990 b43_key_clear(dev, i);
991 }
992
993 static void b43_dump_keymemory(struct b43_wldev *dev)
994 {
995 unsigned int i, index, count, offset, pairwise_keys_start;
996 u8 mac[ETH_ALEN];
997 u16 algo;
998 u32 rcmta0;
999 u16 rcmta1;
1000 u64 hf;
1001 struct b43_key *key;
1002
1003 if (!b43_debug(dev, B43_DBG_KEYS))
1004 return;
1005
1006 hf = b43_hf_read(dev);
1007 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
1008 !!(hf & B43_HF_USEDEFKEYS));
1009 if (b43_new_kidx_api(dev)) {
1010 pairwise_keys_start = B43_NR_GROUP_KEYS;
1011 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1012 } else {
1013 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1014 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1015 }
1016 for (index = 0; index < count; index++) {
1017 key = &(dev->key[index]);
1018 printk(KERN_DEBUG "Key slot %02u: %s",
1019 index, (key->keyconf == NULL) ? " " : "*");
1020 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1021 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1022 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1023 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1024 }
1025
1026 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1027 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1028 printk(" Algo: %04X/%02X", algo, key->algorithm);
1029
1030 if (index >= pairwise_keys_start) {
1031 if (key->algorithm == B43_SEC_ALGO_TKIP) {
1032 printk(" TKIP: ");
1033 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1034 for (i = 0; i < 14; i += 2) {
1035 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1036 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1037 }
1038 }
1039 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
1040 ((index - pairwise_keys_start) * 2) + 0);
1041 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
1042 ((index - pairwise_keys_start) * 2) + 1);
1043 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1044 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
1045 printk(" MAC: %pM", mac);
1046 } else
1047 printk(" DEFAULT KEY");
1048 printk("\n");
1049 }
1050 }
1051
1052 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1053 {
1054 u32 macctl;
1055 u16 ucstat;
1056 bool hwps;
1057 bool awake;
1058 int i;
1059
1060 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1061 (ps_flags & B43_PS_DISABLED));
1062 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1063
1064 if (ps_flags & B43_PS_ENABLED) {
1065 hwps = 1;
1066 } else if (ps_flags & B43_PS_DISABLED) {
1067 hwps = 0;
1068 } else {
1069 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1070 // and thus is not an AP and we are associated, set bit 25
1071 }
1072 if (ps_flags & B43_PS_AWAKE) {
1073 awake = 1;
1074 } else if (ps_flags & B43_PS_ASLEEP) {
1075 awake = 0;
1076 } else {
1077 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1078 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1079 // successful, set bit26
1080 }
1081
1082 /* FIXME: For now we force awake-on and hwps-off */
1083 hwps = 0;
1084 awake = 1;
1085
1086 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1087 if (hwps)
1088 macctl |= B43_MACCTL_HWPS;
1089 else
1090 macctl &= ~B43_MACCTL_HWPS;
1091 if (awake)
1092 macctl |= B43_MACCTL_AWAKE;
1093 else
1094 macctl &= ~B43_MACCTL_AWAKE;
1095 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1096 /* Commit write */
1097 b43_read32(dev, B43_MMIO_MACCTL);
1098 if (awake && dev->dev->id.revision >= 5) {
1099 /* Wait for the microcode to wake up. */
1100 for (i = 0; i < 100; i++) {
1101 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1102 B43_SHM_SH_UCODESTAT);
1103 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1104 break;
1105 udelay(10);
1106 }
1107 }
1108 }
1109
1110 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1111 {
1112 u32 tmslow;
1113 u32 macctl;
1114
1115 flags |= B43_TMSLOW_PHYCLKEN;
1116 flags |= B43_TMSLOW_PHYRESET;
1117 ssb_device_enable(dev->dev, flags);
1118 msleep(2); /* Wait for the PLL to turn on. */
1119
1120 /* Now take the PHY out of Reset again */
1121 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
1122 tmslow |= SSB_TMSLOW_FGC;
1123 tmslow &= ~B43_TMSLOW_PHYRESET;
1124 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1125 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1126 msleep(1);
1127 tmslow &= ~SSB_TMSLOW_FGC;
1128 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1129 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1130 msleep(1);
1131
1132 /* Turn Analog ON, but only if we already know the PHY-type.
1133 * This protects against very early setup where we don't know the
1134 * PHY-type, yet. wireless_core_reset will be called once again later,
1135 * when we know the PHY-type. */
1136 if (dev->phy.ops)
1137 dev->phy.ops->switch_analog(dev, 1);
1138
1139 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1140 macctl &= ~B43_MACCTL_GMODE;
1141 if (flags & B43_TMSLOW_GMODE)
1142 macctl |= B43_MACCTL_GMODE;
1143 macctl |= B43_MACCTL_IHR_ENABLED;
1144 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1145 }
1146
1147 static void handle_irq_transmit_status(struct b43_wldev *dev)
1148 {
1149 u32 v0, v1;
1150 u16 tmp;
1151 struct b43_txstatus stat;
1152
1153 while (1) {
1154 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1155 if (!(v0 & 0x00000001))
1156 break;
1157 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1158
1159 stat.cookie = (v0 >> 16);
1160 stat.seq = (v1 & 0x0000FFFF);
1161 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1162 tmp = (v0 & 0x0000FFFF);
1163 stat.frame_count = ((tmp & 0xF000) >> 12);
1164 stat.rts_count = ((tmp & 0x0F00) >> 8);
1165 stat.supp_reason = ((tmp & 0x001C) >> 2);
1166 stat.pm_indicated = !!(tmp & 0x0080);
1167 stat.intermediate = !!(tmp & 0x0040);
1168 stat.for_ampdu = !!(tmp & 0x0020);
1169 stat.acked = !!(tmp & 0x0002);
1170
1171 b43_handle_txstatus(dev, &stat);
1172 }
1173 }
1174
1175 static void drain_txstatus_queue(struct b43_wldev *dev)
1176 {
1177 u32 dummy;
1178
1179 if (dev->dev->id.revision < 5)
1180 return;
1181 /* Read all entries from the microcode TXstatus FIFO
1182 * and throw them away.
1183 */
1184 while (1) {
1185 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1186 if (!(dummy & 0x00000001))
1187 break;
1188 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1189 }
1190 }
1191
1192 static u32 b43_jssi_read(struct b43_wldev *dev)
1193 {
1194 u32 val = 0;
1195
1196 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1197 val <<= 16;
1198 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1199
1200 return val;
1201 }
1202
1203 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1204 {
1205 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1206 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1207 }
1208
1209 static void b43_generate_noise_sample(struct b43_wldev *dev)
1210 {
1211 b43_jssi_write(dev, 0x7F7F7F7F);
1212 b43_write32(dev, B43_MMIO_MACCMD,
1213 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1214 }
1215
1216 static void b43_calculate_link_quality(struct b43_wldev *dev)
1217 {
1218 /* Top half of Link Quality calculation. */
1219
1220 if (dev->phy.type != B43_PHYTYPE_G)
1221 return;
1222 if (dev->noisecalc.calculation_running)
1223 return;
1224 dev->noisecalc.calculation_running = 1;
1225 dev->noisecalc.nr_samples = 0;
1226
1227 b43_generate_noise_sample(dev);
1228 }
1229
1230 static void handle_irq_noise(struct b43_wldev *dev)
1231 {
1232 struct b43_phy_g *phy = dev->phy.g;
1233 u16 tmp;
1234 u8 noise[4];
1235 u8 i, j;
1236 s32 average;
1237
1238 /* Bottom half of Link Quality calculation. */
1239
1240 if (dev->phy.type != B43_PHYTYPE_G)
1241 return;
1242
1243 /* Possible race condition: It might be possible that the user
1244 * changed to a different channel in the meantime since we
1245 * started the calculation. We ignore that fact, since it's
1246 * not really that much of a problem. The background noise is
1247 * an estimation only anyway. Slightly wrong results will get damped
1248 * by the averaging of the 8 sample rounds. Additionally the
1249 * value is shortlived. So it will be replaced by the next noise
1250 * calculation round soon. */
1251
1252 B43_WARN_ON(!dev->noisecalc.calculation_running);
1253 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1254 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1255 noise[2] == 0x7F || noise[3] == 0x7F)
1256 goto generate_new;
1257
1258 /* Get the noise samples. */
1259 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1260 i = dev->noisecalc.nr_samples;
1261 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1262 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1263 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1264 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1265 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1266 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1267 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1268 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1269 dev->noisecalc.nr_samples++;
1270 if (dev->noisecalc.nr_samples == 8) {
1271 /* Calculate the Link Quality by the noise samples. */
1272 average = 0;
1273 for (i = 0; i < 8; i++) {
1274 for (j = 0; j < 4; j++)
1275 average += dev->noisecalc.samples[i][j];
1276 }
1277 average /= (8 * 4);
1278 average *= 125;
1279 average += 64;
1280 average /= 128;
1281 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1282 tmp = (tmp / 128) & 0x1F;
1283 if (tmp >= 8)
1284 average += 2;
1285 else
1286 average -= 25;
1287 if (tmp == 8)
1288 average -= 72;
1289 else
1290 average -= 48;
1291
1292 dev->stats.link_noise = average;
1293 dev->noisecalc.calculation_running = 0;
1294 return;
1295 }
1296 generate_new:
1297 b43_generate_noise_sample(dev);
1298 }
1299
1300 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1301 {
1302 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
1303 ///TODO: PS TBTT
1304 } else {
1305 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1306 b43_power_saving_ctl_bits(dev, 0);
1307 }
1308 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
1309 dev->dfq_valid = 1;
1310 }
1311
1312 static void handle_irq_atim_end(struct b43_wldev *dev)
1313 {
1314 if (dev->dfq_valid) {
1315 b43_write32(dev, B43_MMIO_MACCMD,
1316 b43_read32(dev, B43_MMIO_MACCMD)
1317 | B43_MACCMD_DFQ_VALID);
1318 dev->dfq_valid = 0;
1319 }
1320 }
1321
1322 static void handle_irq_pmq(struct b43_wldev *dev)
1323 {
1324 u32 tmp;
1325
1326 //TODO: AP mode.
1327
1328 while (1) {
1329 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1330 if (!(tmp & 0x00000008))
1331 break;
1332 }
1333 /* 16bit write is odd, but correct. */
1334 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1335 }
1336
1337 static void b43_write_template_common(struct b43_wldev *dev,
1338 const u8 *data, u16 size,
1339 u16 ram_offset,
1340 u16 shm_size_offset, u8 rate)
1341 {
1342 u32 i, tmp;
1343 struct b43_plcp_hdr4 plcp;
1344
1345 plcp.data = 0;
1346 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1347 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1348 ram_offset += sizeof(u32);
1349 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1350 * So leave the first two bytes of the next write blank.
1351 */
1352 tmp = (u32) (data[0]) << 16;
1353 tmp |= (u32) (data[1]) << 24;
1354 b43_ram_write(dev, ram_offset, tmp);
1355 ram_offset += sizeof(u32);
1356 for (i = 2; i < size; i += sizeof(u32)) {
1357 tmp = (u32) (data[i + 0]);
1358 if (i + 1 < size)
1359 tmp |= (u32) (data[i + 1]) << 8;
1360 if (i + 2 < size)
1361 tmp |= (u32) (data[i + 2]) << 16;
1362 if (i + 3 < size)
1363 tmp |= (u32) (data[i + 3]) << 24;
1364 b43_ram_write(dev, ram_offset + i - 2, tmp);
1365 }
1366 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1367 size + sizeof(struct b43_plcp_hdr6));
1368 }
1369
1370 /* Check if the use of the antenna that ieee80211 told us to
1371 * use is possible. This will fall back to DEFAULT.
1372 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1373 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1374 u8 antenna_nr)
1375 {
1376 u8 antenna_mask;
1377
1378 if (antenna_nr == 0) {
1379 /* Zero means "use default antenna". That's always OK. */
1380 return 0;
1381 }
1382
1383 /* Get the mask of available antennas. */
1384 if (dev->phy.gmode)
1385 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
1386 else
1387 antenna_mask = dev->dev->bus->sprom.ant_available_a;
1388
1389 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1390 /* This antenna is not available. Fall back to default. */
1391 return 0;
1392 }
1393
1394 return antenna_nr;
1395 }
1396
1397 /* Convert a b43 antenna number value to the PHY TX control value. */
1398 static u16 b43_antenna_to_phyctl(int antenna)
1399 {
1400 switch (antenna) {
1401 case B43_ANTENNA0:
1402 return B43_TXH_PHY_ANT0;
1403 case B43_ANTENNA1:
1404 return B43_TXH_PHY_ANT1;
1405 case B43_ANTENNA2:
1406 return B43_TXH_PHY_ANT2;
1407 case B43_ANTENNA3:
1408 return B43_TXH_PHY_ANT3;
1409 case B43_ANTENNA_AUTO0:
1410 case B43_ANTENNA_AUTO1:
1411 return B43_TXH_PHY_ANT01AUTO;
1412 }
1413 B43_WARN_ON(1);
1414 return 0;
1415 }
1416
1417 static void b43_write_beacon_template(struct b43_wldev *dev,
1418 u16 ram_offset,
1419 u16 shm_size_offset)
1420 {
1421 unsigned int i, len, variable_len;
1422 const struct ieee80211_mgmt *bcn;
1423 const u8 *ie;
1424 bool tim_found = 0;
1425 unsigned int rate;
1426 u16 ctl;
1427 int antenna;
1428 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1429
1430 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1431 len = min((size_t) dev->wl->current_beacon->len,
1432 0x200 - sizeof(struct b43_plcp_hdr6));
1433 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
1434
1435 b43_write_template_common(dev, (const u8 *)bcn,
1436 len, ram_offset, shm_size_offset, rate);
1437
1438 /* Write the PHY TX control parameters. */
1439 antenna = B43_ANTENNA_DEFAULT;
1440 antenna = b43_antenna_to_phyctl(antenna);
1441 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1442 /* We can't send beacons with short preamble. Would get PHY errors. */
1443 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1444 ctl &= ~B43_TXH_PHY_ANT;
1445 ctl &= ~B43_TXH_PHY_ENC;
1446 ctl |= antenna;
1447 if (b43_is_cck_rate(rate))
1448 ctl |= B43_TXH_PHY_ENC_CCK;
1449 else
1450 ctl |= B43_TXH_PHY_ENC_OFDM;
1451 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1452
1453 /* Find the position of the TIM and the DTIM_period value
1454 * and write them to SHM. */
1455 ie = bcn->u.beacon.variable;
1456 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1457 for (i = 0; i < variable_len - 2; ) {
1458 uint8_t ie_id, ie_len;
1459
1460 ie_id = ie[i];
1461 ie_len = ie[i + 1];
1462 if (ie_id == 5) {
1463 u16 tim_position;
1464 u16 dtim_period;
1465 /* This is the TIM Information Element */
1466
1467 /* Check whether the ie_len is in the beacon data range. */
1468 if (variable_len < ie_len + 2 + i)
1469 break;
1470 /* A valid TIM is at least 4 bytes long. */
1471 if (ie_len < 4)
1472 break;
1473 tim_found = 1;
1474
1475 tim_position = sizeof(struct b43_plcp_hdr6);
1476 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1477 tim_position += i;
1478
1479 dtim_period = ie[i + 3];
1480
1481 b43_shm_write16(dev, B43_SHM_SHARED,
1482 B43_SHM_SH_TIMBPOS, tim_position);
1483 b43_shm_write16(dev, B43_SHM_SHARED,
1484 B43_SHM_SH_DTIMPER, dtim_period);
1485 break;
1486 }
1487 i += ie_len + 2;
1488 }
1489 if (!tim_found) {
1490 /*
1491 * If ucode wants to modify TIM do it behind the beacon, this
1492 * will happen, for example, when doing mesh networking.
1493 */
1494 b43_shm_write16(dev, B43_SHM_SHARED,
1495 B43_SHM_SH_TIMBPOS,
1496 len + sizeof(struct b43_plcp_hdr6));
1497 b43_shm_write16(dev, B43_SHM_SHARED,
1498 B43_SHM_SH_DTIMPER, 0);
1499 }
1500 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
1501 }
1502
1503 static void b43_upload_beacon0(struct b43_wldev *dev)
1504 {
1505 struct b43_wl *wl = dev->wl;
1506
1507 if (wl->beacon0_uploaded)
1508 return;
1509 b43_write_beacon_template(dev, 0x68, 0x18);
1510 wl->beacon0_uploaded = 1;
1511 }
1512
1513 static void b43_upload_beacon1(struct b43_wldev *dev)
1514 {
1515 struct b43_wl *wl = dev->wl;
1516
1517 if (wl->beacon1_uploaded)
1518 return;
1519 b43_write_beacon_template(dev, 0x468, 0x1A);
1520 wl->beacon1_uploaded = 1;
1521 }
1522
1523 static void handle_irq_beacon(struct b43_wldev *dev)
1524 {
1525 struct b43_wl *wl = dev->wl;
1526 u32 cmd, beacon0_valid, beacon1_valid;
1527
1528 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1529 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) &&
1530 !b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
1531 return;
1532
1533 /* This is the bottom half of the asynchronous beacon update. */
1534
1535 /* Ignore interrupt in the future. */
1536 dev->irq_mask &= ~B43_IRQ_BEACON;
1537
1538 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1539 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1540 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1541
1542 /* Schedule interrupt manually, if busy. */
1543 if (beacon0_valid && beacon1_valid) {
1544 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1545 dev->irq_mask |= B43_IRQ_BEACON;
1546 return;
1547 }
1548
1549 if (unlikely(wl->beacon_templates_virgin)) {
1550 /* We never uploaded a beacon before.
1551 * Upload both templates now, but only mark one valid. */
1552 wl->beacon_templates_virgin = 0;
1553 b43_upload_beacon0(dev);
1554 b43_upload_beacon1(dev);
1555 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1556 cmd |= B43_MACCMD_BEACON0_VALID;
1557 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1558 } else {
1559 if (!beacon0_valid) {
1560 b43_upload_beacon0(dev);
1561 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1562 cmd |= B43_MACCMD_BEACON0_VALID;
1563 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1564 } else if (!beacon1_valid) {
1565 b43_upload_beacon1(dev);
1566 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1567 cmd |= B43_MACCMD_BEACON1_VALID;
1568 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1569 }
1570 }
1571 }
1572
1573 static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1574 {
1575 u32 old_irq_mask = dev->irq_mask;
1576
1577 /* update beacon right away or defer to irq */
1578 handle_irq_beacon(dev);
1579 if (old_irq_mask != dev->irq_mask) {
1580 /* The handler updated the IRQ mask. */
1581 B43_WARN_ON(!dev->irq_mask);
1582 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1583 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1584 } else {
1585 /* Device interrupts are currently disabled. That means
1586 * we just ran the hardirq handler and scheduled the
1587 * IRQ thread. The thread will write the IRQ mask when
1588 * it finished, so there's nothing to do here. Writing
1589 * the mask _here_ would incorrectly re-enable IRQs. */
1590 }
1591 }
1592 }
1593
1594 static void b43_beacon_update_trigger_work(struct work_struct *work)
1595 {
1596 struct b43_wl *wl = container_of(work, struct b43_wl,
1597 beacon_update_trigger);
1598 struct b43_wldev *dev;
1599
1600 mutex_lock(&wl->mutex);
1601 dev = wl->current_dev;
1602 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1603 if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) {
1604 /* wl->mutex is enough. */
1605 b43_do_beacon_update_trigger_work(dev);
1606 mmiowb();
1607 } else {
1608 spin_lock_irq(&wl->hardirq_lock);
1609 b43_do_beacon_update_trigger_work(dev);
1610 mmiowb();
1611 spin_unlock_irq(&wl->hardirq_lock);
1612 }
1613 }
1614 mutex_unlock(&wl->mutex);
1615 }
1616
1617 /* Asynchronously update the packet templates in template RAM.
1618 * Locking: Requires wl->mutex to be locked. */
1619 static void b43_update_templates(struct b43_wl *wl)
1620 {
1621 struct sk_buff *beacon;
1622
1623 /* This is the top half of the ansynchronous beacon update.
1624 * The bottom half is the beacon IRQ.
1625 * Beacon update must be asynchronous to avoid sending an
1626 * invalid beacon. This can happen for example, if the firmware
1627 * transmits a beacon while we are updating it. */
1628
1629 /* We could modify the existing beacon and set the aid bit in
1630 * the TIM field, but that would probably require resizing and
1631 * moving of data within the beacon template.
1632 * Simply request a new beacon and let mac80211 do the hard work. */
1633 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1634 if (unlikely(!beacon))
1635 return;
1636
1637 if (wl->current_beacon)
1638 dev_kfree_skb_any(wl->current_beacon);
1639 wl->current_beacon = beacon;
1640 wl->beacon0_uploaded = 0;
1641 wl->beacon1_uploaded = 0;
1642 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
1643 }
1644
1645 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1646 {
1647 b43_time_lock(dev);
1648 if (dev->dev->id.revision >= 3) {
1649 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1650 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1651 } else {
1652 b43_write16(dev, 0x606, (beacon_int >> 6));
1653 b43_write16(dev, 0x610, beacon_int);
1654 }
1655 b43_time_unlock(dev);
1656 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1657 }
1658
1659 static void b43_handle_firmware_panic(struct b43_wldev *dev)
1660 {
1661 u16 reason;
1662
1663 /* Read the register that contains the reason code for the panic. */
1664 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1665 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1666
1667 switch (reason) {
1668 default:
1669 b43dbg(dev->wl, "The panic reason is unknown.\n");
1670 /* fallthrough */
1671 case B43_FWPANIC_DIE:
1672 /* Do not restart the controller or firmware.
1673 * The device is nonfunctional from now on.
1674 * Restarting would result in this panic to trigger again,
1675 * so we avoid that recursion. */
1676 break;
1677 case B43_FWPANIC_RESTART:
1678 b43_controller_restart(dev, "Microcode panic");
1679 break;
1680 }
1681 }
1682
1683 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1684 {
1685 unsigned int i, cnt;
1686 u16 reason, marker_id, marker_line;
1687 __le16 *buf;
1688
1689 /* The proprietary firmware doesn't have this IRQ. */
1690 if (!dev->fw.opensource)
1691 return;
1692
1693 /* Read the register that contains the reason code for this IRQ. */
1694 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1695
1696 switch (reason) {
1697 case B43_DEBUGIRQ_PANIC:
1698 b43_handle_firmware_panic(dev);
1699 break;
1700 case B43_DEBUGIRQ_DUMP_SHM:
1701 if (!B43_DEBUG)
1702 break; /* Only with driver debugging enabled. */
1703 buf = kmalloc(4096, GFP_ATOMIC);
1704 if (!buf) {
1705 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1706 goto out;
1707 }
1708 for (i = 0; i < 4096; i += 2) {
1709 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1710 buf[i / 2] = cpu_to_le16(tmp);
1711 }
1712 b43info(dev->wl, "Shared memory dump:\n");
1713 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1714 16, 2, buf, 4096, 1);
1715 kfree(buf);
1716 break;
1717 case B43_DEBUGIRQ_DUMP_REGS:
1718 if (!B43_DEBUG)
1719 break; /* Only with driver debugging enabled. */
1720 b43info(dev->wl, "Microcode register dump:\n");
1721 for (i = 0, cnt = 0; i < 64; i++) {
1722 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1723 if (cnt == 0)
1724 printk(KERN_INFO);
1725 printk("r%02u: 0x%04X ", i, tmp);
1726 cnt++;
1727 if (cnt == 6) {
1728 printk("\n");
1729 cnt = 0;
1730 }
1731 }
1732 printk("\n");
1733 break;
1734 case B43_DEBUGIRQ_MARKER:
1735 if (!B43_DEBUG)
1736 break; /* Only with driver debugging enabled. */
1737 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1738 B43_MARKER_ID_REG);
1739 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1740 B43_MARKER_LINE_REG);
1741 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1742 "at line number %u\n",
1743 marker_id, marker_line);
1744 break;
1745 default:
1746 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1747 reason);
1748 }
1749 out:
1750 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1751 b43_shm_write16(dev, B43_SHM_SCRATCH,
1752 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
1753 }
1754
1755 static void b43_do_interrupt_thread(struct b43_wldev *dev)
1756 {
1757 u32 reason;
1758 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1759 u32 merged_dma_reason = 0;
1760 int i;
1761
1762 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1763 return;
1764
1765 reason = dev->irq_reason;
1766 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1767 dma_reason[i] = dev->dma_reason[i];
1768 merged_dma_reason |= dma_reason[i];
1769 }
1770
1771 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1772 b43err(dev->wl, "MAC transmission error\n");
1773
1774 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1775 b43err(dev->wl, "PHY transmission error\n");
1776 rmb();
1777 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1778 atomic_set(&dev->phy.txerr_cnt,
1779 B43_PHY_TX_BADNESS_LIMIT);
1780 b43err(dev->wl, "Too many PHY TX errors, "
1781 "restarting the controller\n");
1782 b43_controller_restart(dev, "PHY TX errors");
1783 }
1784 }
1785
1786 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1787 B43_DMAIRQ_NONFATALMASK))) {
1788 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1789 b43err(dev->wl, "Fatal DMA error: "
1790 "0x%08X, 0x%08X, 0x%08X, "
1791 "0x%08X, 0x%08X, 0x%08X\n",
1792 dma_reason[0], dma_reason[1],
1793 dma_reason[2], dma_reason[3],
1794 dma_reason[4], dma_reason[5]);
1795 b43err(dev->wl, "This device does not support DMA "
1796 "on your system. Please use PIO instead.\n");
1797 /* Fall back to PIO transfers if we get fatal DMA errors! */
1798 dev->use_pio = 1;
1799 b43_controller_restart(dev, "DMA error");
1800 return;
1801 }
1802 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1803 b43err(dev->wl, "DMA error: "
1804 "0x%08X, 0x%08X, 0x%08X, "
1805 "0x%08X, 0x%08X, 0x%08X\n",
1806 dma_reason[0], dma_reason[1],
1807 dma_reason[2], dma_reason[3],
1808 dma_reason[4], dma_reason[5]);
1809 }
1810 }
1811
1812 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1813 handle_irq_ucode_debug(dev);
1814 if (reason & B43_IRQ_TBTT_INDI)
1815 handle_irq_tbtt_indication(dev);
1816 if (reason & B43_IRQ_ATIM_END)
1817 handle_irq_atim_end(dev);
1818 if (reason & B43_IRQ_BEACON)
1819 handle_irq_beacon(dev);
1820 if (reason & B43_IRQ_PMQ)
1821 handle_irq_pmq(dev);
1822 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1823 ;/* TODO */
1824 if (reason & B43_IRQ_NOISESAMPLE_OK)
1825 handle_irq_noise(dev);
1826
1827 /* Check the DMA reason registers for received data. */
1828 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1829 if (b43_using_pio_transfers(dev))
1830 b43_pio_rx(dev->pio.rx_queue);
1831 else
1832 b43_dma_rx(dev->dma.rx_ring);
1833 }
1834 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1835 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1836 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
1837 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1838 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1839
1840 if (reason & B43_IRQ_TX_OK)
1841 handle_irq_transmit_status(dev);
1842
1843 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
1844 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1845
1846 #if B43_DEBUG
1847 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
1848 dev->irq_count++;
1849 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
1850 if (reason & (1 << i))
1851 dev->irq_bit_count[i]++;
1852 }
1853 }
1854 #endif
1855 }
1856
1857 /* Interrupt thread handler. Handles device interrupts in thread context. */
1858 static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
1859 {
1860 struct b43_wldev *dev = dev_id;
1861
1862 mutex_lock(&dev->wl->mutex);
1863 b43_do_interrupt_thread(dev);
1864 mmiowb();
1865 mutex_unlock(&dev->wl->mutex);
1866
1867 return IRQ_HANDLED;
1868 }
1869
1870 static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
1871 {
1872 u32 reason;
1873
1874 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
1875 * On SDIO, this runs under wl->mutex. */
1876
1877 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1878 if (reason == 0xffffffff) /* shared IRQ */
1879 return IRQ_NONE;
1880 reason &= dev->irq_mask;
1881 if (!reason)
1882 return IRQ_HANDLED;
1883
1884 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1885 & 0x0001DC00;
1886 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1887 & 0x0000DC00;
1888 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1889 & 0x0000DC00;
1890 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1891 & 0x0001DC00;
1892 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1893 & 0x0000DC00;
1894 /* Unused ring
1895 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1896 & 0x0000DC00;
1897 */
1898
1899 /* ACK the interrupt. */
1900 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1901 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1902 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1903 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1904 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1905 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1906 /* Unused ring
1907 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1908 */
1909
1910 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
1911 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
1912 /* Save the reason bitmasks for the IRQ thread handler. */
1913 dev->irq_reason = reason;
1914
1915 return IRQ_WAKE_THREAD;
1916 }
1917
1918 /* Interrupt handler top-half. This runs with interrupts disabled. */
1919 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1920 {
1921 struct b43_wldev *dev = dev_id;
1922 irqreturn_t ret;
1923
1924 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
1925 return IRQ_NONE;
1926
1927 spin_lock(&dev->wl->hardirq_lock);
1928 ret = b43_do_interrupt(dev);
1929 mmiowb();
1930 spin_unlock(&dev->wl->hardirq_lock);
1931
1932 return ret;
1933 }
1934
1935 /* SDIO interrupt handler. This runs in process context. */
1936 static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
1937 {
1938 struct b43_wl *wl = dev->wl;
1939 irqreturn_t ret;
1940
1941 mutex_lock(&wl->mutex);
1942
1943 ret = b43_do_interrupt(dev);
1944 if (ret == IRQ_WAKE_THREAD)
1945 b43_do_interrupt_thread(dev);
1946
1947 mutex_unlock(&wl->mutex);
1948 }
1949
1950 void b43_do_release_fw(struct b43_firmware_file *fw)
1951 {
1952 release_firmware(fw->data);
1953 fw->data = NULL;
1954 fw->filename = NULL;
1955 }
1956
1957 static void b43_release_firmware(struct b43_wldev *dev)
1958 {
1959 b43_do_release_fw(&dev->fw.ucode);
1960 b43_do_release_fw(&dev->fw.pcm);
1961 b43_do_release_fw(&dev->fw.initvals);
1962 b43_do_release_fw(&dev->fw.initvals_band);
1963 }
1964
1965 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
1966 {
1967 const char text[] =
1968 "You must go to " \
1969 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
1970 "and download the correct firmware for this driver version. " \
1971 "Please carefully read all instructions on this website.\n";
1972
1973 if (error)
1974 b43err(wl, text);
1975 else
1976 b43warn(wl, text);
1977 }
1978
1979 int b43_do_request_fw(struct b43_request_fw_context *ctx,
1980 const char *name,
1981 struct b43_firmware_file *fw)
1982 {
1983 const struct firmware *blob;
1984 struct b43_fw_header *hdr;
1985 u32 size;
1986 int err;
1987
1988 if (!name) {
1989 /* Don't fetch anything. Free possibly cached firmware. */
1990 /* FIXME: We should probably keep it anyway, to save some headache
1991 * on suspend/resume with multiband devices. */
1992 b43_do_release_fw(fw);
1993 return 0;
1994 }
1995 if (fw->filename) {
1996 if ((fw->type == ctx->req_type) &&
1997 (strcmp(fw->filename, name) == 0))
1998 return 0; /* Already have this fw. */
1999 /* Free the cached firmware first. */
2000 /* FIXME: We should probably do this later after we successfully
2001 * got the new fw. This could reduce headache with multiband devices.
2002 * We could also redesign this to cache the firmware for all possible
2003 * bands all the time. */
2004 b43_do_release_fw(fw);
2005 }
2006
2007 switch (ctx->req_type) {
2008 case B43_FWTYPE_PROPRIETARY:
2009 snprintf(ctx->fwname, sizeof(ctx->fwname),
2010 "b43%s/%s.fw",
2011 modparam_fwpostfix, name);
2012 break;
2013 case B43_FWTYPE_OPENSOURCE:
2014 snprintf(ctx->fwname, sizeof(ctx->fwname),
2015 "b43-open%s/%s.fw",
2016 modparam_fwpostfix, name);
2017 break;
2018 default:
2019 B43_WARN_ON(1);
2020 return -ENOSYS;
2021 }
2022 err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev);
2023 if (err == -ENOENT) {
2024 snprintf(ctx->errors[ctx->req_type],
2025 sizeof(ctx->errors[ctx->req_type]),
2026 "Firmware file \"%s\" not found\n", ctx->fwname);
2027 return err;
2028 } else if (err) {
2029 snprintf(ctx->errors[ctx->req_type],
2030 sizeof(ctx->errors[ctx->req_type]),
2031 "Firmware file \"%s\" request failed (err=%d)\n",
2032 ctx->fwname, err);
2033 return err;
2034 }
2035 if (blob->size < sizeof(struct b43_fw_header))
2036 goto err_format;
2037 hdr = (struct b43_fw_header *)(blob->data);
2038 switch (hdr->type) {
2039 case B43_FW_TYPE_UCODE:
2040 case B43_FW_TYPE_PCM:
2041 size = be32_to_cpu(hdr->size);
2042 if (size != blob->size - sizeof(struct b43_fw_header))
2043 goto err_format;
2044 /* fallthrough */
2045 case B43_FW_TYPE_IV:
2046 if (hdr->ver != 1)
2047 goto err_format;
2048 break;
2049 default:
2050 goto err_format;
2051 }
2052
2053 fw->data = blob;
2054 fw->filename = name;
2055 fw->type = ctx->req_type;
2056
2057 return 0;
2058
2059 err_format:
2060 snprintf(ctx->errors[ctx->req_type],
2061 sizeof(ctx->errors[ctx->req_type]),
2062 "Firmware file \"%s\" format error.\n", ctx->fwname);
2063 release_firmware(blob);
2064
2065 return -EPROTO;
2066 }
2067
2068 static int b43_try_request_fw(struct b43_request_fw_context *ctx)
2069 {
2070 struct b43_wldev *dev = ctx->dev;
2071 struct b43_firmware *fw = &ctx->dev->fw;
2072 const u8 rev = ctx->dev->dev->id.revision;
2073 const char *filename;
2074 u32 tmshigh;
2075 int err;
2076
2077 /* Get microcode */
2078 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
2079 if ((rev >= 5) && (rev <= 10))
2080 filename = "ucode5";
2081 else if ((rev >= 11) && (rev <= 12))
2082 filename = "ucode11";
2083 else if (rev == 13)
2084 filename = "ucode13";
2085 else if (rev == 14)
2086 filename = "ucode14";
2087 else if (rev >= 15)
2088 filename = "ucode15";
2089 else
2090 goto err_no_ucode;
2091 err = b43_do_request_fw(ctx, filename, &fw->ucode);
2092 if (err)
2093 goto err_load;
2094
2095 /* Get PCM code */
2096 if ((rev >= 5) && (rev <= 10))
2097 filename = "pcm5";
2098 else if (rev >= 11)
2099 filename = NULL;
2100 else
2101 goto err_no_pcm;
2102 fw->pcm_request_failed = 0;
2103 err = b43_do_request_fw(ctx, filename, &fw->pcm);
2104 if (err == -ENOENT) {
2105 /* We did not find a PCM file? Not fatal, but
2106 * core rev <= 10 must do without hwcrypto then. */
2107 fw->pcm_request_failed = 1;
2108 } else if (err)
2109 goto err_load;
2110
2111 /* Get initvals */
2112 switch (dev->phy.type) {
2113 case B43_PHYTYPE_A:
2114 if ((rev >= 5) && (rev <= 10)) {
2115 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2116 filename = "a0g1initvals5";
2117 else
2118 filename = "a0g0initvals5";
2119 } else
2120 goto err_no_initvals;
2121 break;
2122 case B43_PHYTYPE_G:
2123 if ((rev >= 5) && (rev <= 10))
2124 filename = "b0g0initvals5";
2125 else if (rev >= 13)
2126 filename = "b0g0initvals13";
2127 else
2128 goto err_no_initvals;
2129 break;
2130 case B43_PHYTYPE_N:
2131 if ((rev >= 11) && (rev <= 12))
2132 filename = "n0initvals11";
2133 else
2134 goto err_no_initvals;
2135 break;
2136 case B43_PHYTYPE_LP:
2137 if (rev == 13)
2138 filename = "lp0initvals13";
2139 else if (rev == 14)
2140 filename = "lp0initvals14";
2141 else if (rev >= 15)
2142 filename = "lp0initvals15";
2143 else
2144 goto err_no_initvals;
2145 break;
2146 default:
2147 goto err_no_initvals;
2148 }
2149 err = b43_do_request_fw(ctx, filename, &fw->initvals);
2150 if (err)
2151 goto err_load;
2152
2153 /* Get bandswitch initvals */
2154 switch (dev->phy.type) {
2155 case B43_PHYTYPE_A:
2156 if ((rev >= 5) && (rev <= 10)) {
2157 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2158 filename = "a0g1bsinitvals5";
2159 else
2160 filename = "a0g0bsinitvals5";
2161 } else if (rev >= 11)
2162 filename = NULL;
2163 else
2164 goto err_no_initvals;
2165 break;
2166 case B43_PHYTYPE_G:
2167 if ((rev >= 5) && (rev <= 10))
2168 filename = "b0g0bsinitvals5";
2169 else if (rev >= 11)
2170 filename = NULL;
2171 else
2172 goto err_no_initvals;
2173 break;
2174 case B43_PHYTYPE_N:
2175 if ((rev >= 11) && (rev <= 12))
2176 filename = "n0bsinitvals11";
2177 else
2178 goto err_no_initvals;
2179 break;
2180 case B43_PHYTYPE_LP:
2181 if (rev == 13)
2182 filename = "lp0bsinitvals13";
2183 else if (rev == 14)
2184 filename = "lp0bsinitvals14";
2185 else if (rev >= 15)
2186 filename = "lp0bsinitvals15";
2187 else
2188 goto err_no_initvals;
2189 break;
2190 default:
2191 goto err_no_initvals;
2192 }
2193 err = b43_do_request_fw(ctx, filename, &fw->initvals_band);
2194 if (err)
2195 goto err_load;
2196
2197 return 0;
2198
2199 err_no_ucode:
2200 err = ctx->fatal_failure = -EOPNOTSUPP;
2201 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2202 "is required for your device (wl-core rev %u)\n", rev);
2203 goto error;
2204
2205 err_no_pcm:
2206 err = ctx->fatal_failure = -EOPNOTSUPP;
2207 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2208 "is required for your device (wl-core rev %u)\n", rev);
2209 goto error;
2210
2211 err_no_initvals:
2212 err = ctx->fatal_failure = -EOPNOTSUPP;
2213 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2214 "is required for your device (wl-core rev %u)\n", rev);
2215 goto error;
2216
2217 err_load:
2218 /* We failed to load this firmware image. The error message
2219 * already is in ctx->errors. Return and let our caller decide
2220 * what to do. */
2221 goto error;
2222
2223 error:
2224 b43_release_firmware(dev);
2225 return err;
2226 }
2227
2228 static int b43_request_firmware(struct b43_wldev *dev)
2229 {
2230 struct b43_request_fw_context *ctx;
2231 unsigned int i;
2232 int err;
2233 const char *errmsg;
2234
2235 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2236 if (!ctx)
2237 return -ENOMEM;
2238 ctx->dev = dev;
2239
2240 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2241 err = b43_try_request_fw(ctx);
2242 if (!err)
2243 goto out; /* Successfully loaded it. */
2244 err = ctx->fatal_failure;
2245 if (err)
2246 goto out;
2247
2248 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2249 err = b43_try_request_fw(ctx);
2250 if (!err)
2251 goto out; /* Successfully loaded it. */
2252 err = ctx->fatal_failure;
2253 if (err)
2254 goto out;
2255
2256 /* Could not find a usable firmware. Print the errors. */
2257 for (i = 0; i < B43_NR_FWTYPES; i++) {
2258 errmsg = ctx->errors[i];
2259 if (strlen(errmsg))
2260 b43err(dev->wl, errmsg);
2261 }
2262 b43_print_fw_helptext(dev->wl, 1);
2263 err = -ENOENT;
2264
2265 out:
2266 kfree(ctx);
2267 return err;
2268 }
2269
2270 static int b43_upload_microcode(struct b43_wldev *dev)
2271 {
2272 const size_t hdr_len = sizeof(struct b43_fw_header);
2273 const __be32 *data;
2274 unsigned int i, len;
2275 u16 fwrev, fwpatch, fwdate, fwtime;
2276 u32 tmp, macctl;
2277 int err = 0;
2278
2279 /* Jump the microcode PSM to offset 0 */
2280 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2281 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2282 macctl |= B43_MACCTL_PSM_JMP0;
2283 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2284 /* Zero out all microcode PSM registers and shared memory. */
2285 for (i = 0; i < 64; i++)
2286 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2287 for (i = 0; i < 4096; i += 2)
2288 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2289
2290 /* Upload Microcode. */
2291 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2292 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2293 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2294 for (i = 0; i < len; i++) {
2295 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2296 udelay(10);
2297 }
2298
2299 if (dev->fw.pcm.data) {
2300 /* Upload PCM data. */
2301 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2302 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2303 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2304 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2305 /* No need for autoinc bit in SHM_HW */
2306 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2307 for (i = 0; i < len; i++) {
2308 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2309 udelay(10);
2310 }
2311 }
2312
2313 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2314
2315 /* Start the microcode PSM */
2316 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2317 macctl &= ~B43_MACCTL_PSM_JMP0;
2318 macctl |= B43_MACCTL_PSM_RUN;
2319 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2320
2321 /* Wait for the microcode to load and respond */
2322 i = 0;
2323 while (1) {
2324 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2325 if (tmp == B43_IRQ_MAC_SUSPENDED)
2326 break;
2327 i++;
2328 if (i >= 20) {
2329 b43err(dev->wl, "Microcode not responding\n");
2330 b43_print_fw_helptext(dev->wl, 1);
2331 err = -ENODEV;
2332 goto error;
2333 }
2334 msleep(50);
2335 }
2336 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2337
2338 /* Get and check the revisions. */
2339 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2340 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2341 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2342 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2343
2344 if (fwrev <= 0x128) {
2345 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2346 "binary drivers older than version 4.x is unsupported. "
2347 "You must upgrade your firmware files.\n");
2348 b43_print_fw_helptext(dev->wl, 1);
2349 err = -EOPNOTSUPP;
2350 goto error;
2351 }
2352 dev->fw.rev = fwrev;
2353 dev->fw.patch = fwpatch;
2354 dev->fw.opensource = (fwdate == 0xFFFF);
2355
2356 /* Default to use-all-queues. */
2357 dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues;
2358 dev->qos_enabled = !!modparam_qos;
2359 /* Default to firmware/hardware crypto acceleration. */
2360 dev->hwcrypto_enabled = 1;
2361
2362 if (dev->fw.opensource) {
2363 u16 fwcapa;
2364
2365 /* Patchlevel info is encoded in the "time" field. */
2366 dev->fw.patch = fwtime;
2367 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2368 dev->fw.rev, dev->fw.patch);
2369
2370 fwcapa = b43_fwcapa_read(dev);
2371 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2372 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2373 /* Disable hardware crypto and fall back to software crypto. */
2374 dev->hwcrypto_enabled = 0;
2375 }
2376 if (!(fwcapa & B43_FWCAPA_QOS)) {
2377 b43info(dev->wl, "QoS not supported by firmware\n");
2378 /* Disable QoS. Tweak hw->queues to 1. It will be restored before
2379 * ieee80211_unregister to make sure the networking core can
2380 * properly free possible resources. */
2381 dev->wl->hw->queues = 1;
2382 dev->qos_enabled = 0;
2383 }
2384 } else {
2385 b43info(dev->wl, "Loading firmware version %u.%u "
2386 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2387 fwrev, fwpatch,
2388 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2389 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2390 if (dev->fw.pcm_request_failed) {
2391 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2392 "Hardware accelerated cryptography is disabled.\n");
2393 b43_print_fw_helptext(dev->wl, 0);
2394 }
2395 }
2396
2397 if (b43_is_old_txhdr_format(dev)) {
2398 /* We're over the deadline, but we keep support for old fw
2399 * until it turns out to be in major conflict with something new. */
2400 b43warn(dev->wl, "You are using an old firmware image. "
2401 "Support for old firmware will be removed soon "
2402 "(official deadline was July 2008).\n");
2403 b43_print_fw_helptext(dev->wl, 0);
2404 }
2405
2406 return 0;
2407
2408 error:
2409 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2410 macctl &= ~B43_MACCTL_PSM_RUN;
2411 macctl |= B43_MACCTL_PSM_JMP0;
2412 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2413
2414 return err;
2415 }
2416
2417 static int b43_write_initvals(struct b43_wldev *dev,
2418 const struct b43_iv *ivals,
2419 size_t count,
2420 size_t array_size)
2421 {
2422 const struct b43_iv *iv;
2423 u16 offset;
2424 size_t i;
2425 bool bit32;
2426
2427 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2428 iv = ivals;
2429 for (i = 0; i < count; i++) {
2430 if (array_size < sizeof(iv->offset_size))
2431 goto err_format;
2432 array_size -= sizeof(iv->offset_size);
2433 offset = be16_to_cpu(iv->offset_size);
2434 bit32 = !!(offset & B43_IV_32BIT);
2435 offset &= B43_IV_OFFSET_MASK;
2436 if (offset >= 0x1000)
2437 goto err_format;
2438 if (bit32) {
2439 u32 value;
2440
2441 if (array_size < sizeof(iv->data.d32))
2442 goto err_format;
2443 array_size -= sizeof(iv->data.d32);
2444
2445 value = get_unaligned_be32(&iv->data.d32);
2446 b43_write32(dev, offset, value);
2447
2448 iv = (const struct b43_iv *)((const uint8_t *)iv +
2449 sizeof(__be16) +
2450 sizeof(__be32));
2451 } else {
2452 u16 value;
2453
2454 if (array_size < sizeof(iv->data.d16))
2455 goto err_format;
2456 array_size -= sizeof(iv->data.d16);
2457
2458 value = be16_to_cpu(iv->data.d16);
2459 b43_write16(dev, offset, value);
2460
2461 iv = (const struct b43_iv *)((const uint8_t *)iv +
2462 sizeof(__be16) +
2463 sizeof(__be16));
2464 }
2465 }
2466 if (array_size)
2467 goto err_format;
2468
2469 return 0;
2470
2471 err_format:
2472 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2473 b43_print_fw_helptext(dev->wl, 1);
2474
2475 return -EPROTO;
2476 }
2477
2478 static int b43_upload_initvals(struct b43_wldev *dev)
2479 {
2480 const size_t hdr_len = sizeof(struct b43_fw_header);
2481 const struct b43_fw_header *hdr;
2482 struct b43_firmware *fw = &dev->fw;
2483 const struct b43_iv *ivals;
2484 size_t count;
2485 int err;
2486
2487 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2488 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2489 count = be32_to_cpu(hdr->size);
2490 err = b43_write_initvals(dev, ivals, count,
2491 fw->initvals.data->size - hdr_len);
2492 if (err)
2493 goto out;
2494 if (fw->initvals_band.data) {
2495 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2496 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2497 count = be32_to_cpu(hdr->size);
2498 err = b43_write_initvals(dev, ivals, count,
2499 fw->initvals_band.data->size - hdr_len);
2500 if (err)
2501 goto out;
2502 }
2503 out:
2504
2505 return err;
2506 }
2507
2508 /* Initialize the GPIOs
2509 * http://bcm-specs.sipsolutions.net/GPIO
2510 */
2511 static int b43_gpio_init(struct b43_wldev *dev)
2512 {
2513 struct ssb_bus *bus = dev->dev->bus;
2514 struct ssb_device *gpiodev, *pcidev = NULL;
2515 u32 mask, set;
2516
2517 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2518 & ~B43_MACCTL_GPOUTSMSK);
2519
2520 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2521 | 0x000F);
2522
2523 mask = 0x0000001F;
2524 set = 0x0000000F;
2525 if (dev->dev->bus->chip_id == 0x4301) {
2526 mask |= 0x0060;
2527 set |= 0x0060;
2528 }
2529 if (0 /* FIXME: conditional unknown */ ) {
2530 b43_write16(dev, B43_MMIO_GPIO_MASK,
2531 b43_read16(dev, B43_MMIO_GPIO_MASK)
2532 | 0x0100);
2533 mask |= 0x0180;
2534 set |= 0x0180;
2535 }
2536 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
2537 b43_write16(dev, B43_MMIO_GPIO_MASK,
2538 b43_read16(dev, B43_MMIO_GPIO_MASK)
2539 | 0x0200);
2540 mask |= 0x0200;
2541 set |= 0x0200;
2542 }
2543 if (dev->dev->id.revision >= 2)
2544 mask |= 0x0010; /* FIXME: This is redundant. */
2545
2546 #ifdef CONFIG_SSB_DRIVER_PCICORE
2547 pcidev = bus->pcicore.dev;
2548 #endif
2549 gpiodev = bus->chipco.dev ? : pcidev;
2550 if (!gpiodev)
2551 return 0;
2552 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2553 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2554 & mask) | set);
2555
2556 return 0;
2557 }
2558
2559 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2560 static void b43_gpio_cleanup(struct b43_wldev *dev)
2561 {
2562 struct ssb_bus *bus = dev->dev->bus;
2563 struct ssb_device *gpiodev, *pcidev = NULL;
2564
2565 #ifdef CONFIG_SSB_DRIVER_PCICORE
2566 pcidev = bus->pcicore.dev;
2567 #endif
2568 gpiodev = bus->chipco.dev ? : pcidev;
2569 if (!gpiodev)
2570 return;
2571 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2572 }
2573
2574 /* http://bcm-specs.sipsolutions.net/EnableMac */
2575 void b43_mac_enable(struct b43_wldev *dev)
2576 {
2577 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2578 u16 fwstate;
2579
2580 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2581 B43_SHM_SH_UCODESTAT);
2582 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2583 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2584 b43err(dev->wl, "b43_mac_enable(): The firmware "
2585 "should be suspended, but current state is %u\n",
2586 fwstate);
2587 }
2588 }
2589
2590 dev->mac_suspended--;
2591 B43_WARN_ON(dev->mac_suspended < 0);
2592 if (dev->mac_suspended == 0) {
2593 b43_write32(dev, B43_MMIO_MACCTL,
2594 b43_read32(dev, B43_MMIO_MACCTL)
2595 | B43_MACCTL_ENABLED);
2596 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2597 B43_IRQ_MAC_SUSPENDED);
2598 /* Commit writes */
2599 b43_read32(dev, B43_MMIO_MACCTL);
2600 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2601 b43_power_saving_ctl_bits(dev, 0);
2602 }
2603 }
2604
2605 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2606 void b43_mac_suspend(struct b43_wldev *dev)
2607 {
2608 int i;
2609 u32 tmp;
2610
2611 might_sleep();
2612 B43_WARN_ON(dev->mac_suspended < 0);
2613
2614 if (dev->mac_suspended == 0) {
2615 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2616 b43_write32(dev, B43_MMIO_MACCTL,
2617 b43_read32(dev, B43_MMIO_MACCTL)
2618 & ~B43_MACCTL_ENABLED);
2619 /* force pci to flush the write */
2620 b43_read32(dev, B43_MMIO_MACCTL);
2621 for (i = 35; i; i--) {
2622 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2623 if (tmp & B43_IRQ_MAC_SUSPENDED)
2624 goto out;
2625 udelay(10);
2626 }
2627 /* Hm, it seems this will take some time. Use msleep(). */
2628 for (i = 40; i; i--) {
2629 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2630 if (tmp & B43_IRQ_MAC_SUSPENDED)
2631 goto out;
2632 msleep(1);
2633 }
2634 b43err(dev->wl, "MAC suspend failed\n");
2635 }
2636 out:
2637 dev->mac_suspended++;
2638 }
2639
2640 static void b43_adjust_opmode(struct b43_wldev *dev)
2641 {
2642 struct b43_wl *wl = dev->wl;
2643 u32 ctl;
2644 u16 cfp_pretbtt;
2645
2646 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2647 /* Reset status to STA infrastructure mode. */
2648 ctl &= ~B43_MACCTL_AP;
2649 ctl &= ~B43_MACCTL_KEEP_CTL;
2650 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2651 ctl &= ~B43_MACCTL_KEEP_BAD;
2652 ctl &= ~B43_MACCTL_PROMISC;
2653 ctl &= ~B43_MACCTL_BEACPROMISC;
2654 ctl |= B43_MACCTL_INFRA;
2655
2656 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2657 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
2658 ctl |= B43_MACCTL_AP;
2659 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
2660 ctl &= ~B43_MACCTL_INFRA;
2661
2662 if (wl->filter_flags & FIF_CONTROL)
2663 ctl |= B43_MACCTL_KEEP_CTL;
2664 if (wl->filter_flags & FIF_FCSFAIL)
2665 ctl |= B43_MACCTL_KEEP_BAD;
2666 if (wl->filter_flags & FIF_PLCPFAIL)
2667 ctl |= B43_MACCTL_KEEP_BADPLCP;
2668 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2669 ctl |= B43_MACCTL_PROMISC;
2670 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2671 ctl |= B43_MACCTL_BEACPROMISC;
2672
2673 /* Workaround: On old hardware the HW-MAC-address-filter
2674 * doesn't work properly, so always run promisc in filter
2675 * it in software. */
2676 if (dev->dev->id.revision <= 4)
2677 ctl |= B43_MACCTL_PROMISC;
2678
2679 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2680
2681 cfp_pretbtt = 2;
2682 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2683 if (dev->dev->bus->chip_id == 0x4306 &&
2684 dev->dev->bus->chip_rev == 3)
2685 cfp_pretbtt = 100;
2686 else
2687 cfp_pretbtt = 50;
2688 }
2689 b43_write16(dev, 0x612, cfp_pretbtt);
2690
2691 /* FIXME: We don't currently implement the PMQ mechanism,
2692 * so always disable it. If we want to implement PMQ,
2693 * we need to enable it here (clear DISCPMQ) in AP mode.
2694 */
2695 if (0 /* ctl & B43_MACCTL_AP */) {
2696 b43_write32(dev, B43_MMIO_MACCTL,
2697 b43_read32(dev, B43_MMIO_MACCTL)
2698 & ~B43_MACCTL_DISCPMQ);
2699 } else {
2700 b43_write32(dev, B43_MMIO_MACCTL,
2701 b43_read32(dev, B43_MMIO_MACCTL)
2702 | B43_MACCTL_DISCPMQ);
2703 }
2704 }
2705
2706 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2707 {
2708 u16 offset;
2709
2710 if (is_ofdm) {
2711 offset = 0x480;
2712 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2713 } else {
2714 offset = 0x4C0;
2715 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2716 }
2717 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2718 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2719 }
2720
2721 static void b43_rate_memory_init(struct b43_wldev *dev)
2722 {
2723 switch (dev->phy.type) {
2724 case B43_PHYTYPE_A:
2725 case B43_PHYTYPE_G:
2726 case B43_PHYTYPE_N:
2727 case B43_PHYTYPE_LP:
2728 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2729 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2730 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2731 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2732 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2733 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2734 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2735 if (dev->phy.type == B43_PHYTYPE_A)
2736 break;
2737 /* fallthrough */
2738 case B43_PHYTYPE_B:
2739 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2740 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2741 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2742 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2743 break;
2744 default:
2745 B43_WARN_ON(1);
2746 }
2747 }
2748
2749 /* Set the default values for the PHY TX Control Words. */
2750 static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2751 {
2752 u16 ctl = 0;
2753
2754 ctl |= B43_TXH_PHY_ENC_CCK;
2755 ctl |= B43_TXH_PHY_ANT01AUTO;
2756 ctl |= B43_TXH_PHY_TXPWR;
2757
2758 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2759 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2760 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2761 }
2762
2763 /* Set the TX-Antenna for management frames sent by firmware. */
2764 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2765 {
2766 u16 ant;
2767 u16 tmp;
2768
2769 ant = b43_antenna_to_phyctl(antenna);
2770
2771 /* For ACK/CTS */
2772 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2773 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2774 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2775 /* For Probe Resposes */
2776 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2777 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2778 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2779 }
2780
2781 /* This is the opposite of b43_chip_init() */
2782 static void b43_chip_exit(struct b43_wldev *dev)
2783 {
2784 b43_phy_exit(dev);
2785 b43_gpio_cleanup(dev);
2786 /* firmware is released later */
2787 }
2788
2789 /* Initialize the chip
2790 * http://bcm-specs.sipsolutions.net/ChipInit
2791 */
2792 static int b43_chip_init(struct b43_wldev *dev)
2793 {
2794 struct b43_phy *phy = &dev->phy;
2795 int err;
2796 u32 value32, macctl;
2797 u16 value16;
2798
2799 /* Initialize the MAC control */
2800 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2801 if (dev->phy.gmode)
2802 macctl |= B43_MACCTL_GMODE;
2803 macctl |= B43_MACCTL_INFRA;
2804 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2805
2806 err = b43_request_firmware(dev);
2807 if (err)
2808 goto out;
2809 err = b43_upload_microcode(dev);
2810 if (err)
2811 goto out; /* firmware is released later */
2812
2813 err = b43_gpio_init(dev);
2814 if (err)
2815 goto out; /* firmware is released later */
2816
2817 err = b43_upload_initvals(dev);
2818 if (err)
2819 goto err_gpio_clean;
2820
2821 /* Turn the Analog on and initialize the PHY. */
2822 phy->ops->switch_analog(dev, 1);
2823 err = b43_phy_init(dev);
2824 if (err)
2825 goto err_gpio_clean;
2826
2827 /* Disable Interference Mitigation. */
2828 if (phy->ops->interf_mitigation)
2829 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
2830
2831 /* Select the antennae */
2832 if (phy->ops->set_rx_antenna)
2833 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2834 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2835
2836 if (phy->type == B43_PHYTYPE_B) {
2837 value16 = b43_read16(dev, 0x005E);
2838 value16 |= 0x0004;
2839 b43_write16(dev, 0x005E, value16);
2840 }
2841 b43_write32(dev, 0x0100, 0x01000000);
2842 if (dev->dev->id.revision < 5)
2843 b43_write32(dev, 0x010C, 0x01000000);
2844
2845 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2846 & ~B43_MACCTL_INFRA);
2847 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2848 | B43_MACCTL_INFRA);
2849
2850 /* Probe Response Timeout value */
2851 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2852 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2853
2854 /* Initially set the wireless operation mode. */
2855 b43_adjust_opmode(dev);
2856
2857 if (dev->dev->id.revision < 3) {
2858 b43_write16(dev, 0x060E, 0x0000);
2859 b43_write16(dev, 0x0610, 0x8000);
2860 b43_write16(dev, 0x0604, 0x0000);
2861 b43_write16(dev, 0x0606, 0x0200);
2862 } else {
2863 b43_write32(dev, 0x0188, 0x80000000);
2864 b43_write32(dev, 0x018C, 0x02000000);
2865 }
2866 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2867 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2868 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2869 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2870 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2871 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2872 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2873
2874 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2875 value32 |= 0x00100000;
2876 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2877
2878 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2879 dev->dev->bus->chipco.fast_pwrup_delay);
2880
2881 err = 0;
2882 b43dbg(dev->wl, "Chip initialized\n");
2883 out:
2884 return err;
2885
2886 err_gpio_clean:
2887 b43_gpio_cleanup(dev);
2888 return err;
2889 }
2890
2891 static void b43_periodic_every60sec(struct b43_wldev *dev)
2892 {
2893 const struct b43_phy_operations *ops = dev->phy.ops;
2894
2895 if (ops->pwork_60sec)
2896 ops->pwork_60sec(dev);
2897
2898 /* Force check the TX power emission now. */
2899 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
2900 }
2901
2902 static void b43_periodic_every30sec(struct b43_wldev *dev)
2903 {
2904 /* Update device statistics. */
2905 b43_calculate_link_quality(dev);
2906 }
2907
2908 static void b43_periodic_every15sec(struct b43_wldev *dev)
2909 {
2910 struct b43_phy *phy = &dev->phy;
2911 u16 wdr;
2912
2913 if (dev->fw.opensource) {
2914 /* Check if the firmware is still alive.
2915 * It will reset the watchdog counter to 0 in its idle loop. */
2916 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
2917 if (unlikely(wdr)) {
2918 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
2919 b43_controller_restart(dev, "Firmware watchdog");
2920 return;
2921 } else {
2922 b43_shm_write16(dev, B43_SHM_SCRATCH,
2923 B43_WATCHDOG_REG, 1);
2924 }
2925 }
2926
2927 if (phy->ops->pwork_15sec)
2928 phy->ops->pwork_15sec(dev);
2929
2930 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2931 wmb();
2932
2933 #if B43_DEBUG
2934 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
2935 unsigned int i;
2936
2937 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
2938 dev->irq_count / 15,
2939 dev->tx_count / 15,
2940 dev->rx_count / 15);
2941 dev->irq_count = 0;
2942 dev->tx_count = 0;
2943 dev->rx_count = 0;
2944 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
2945 if (dev->irq_bit_count[i]) {
2946 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
2947 dev->irq_bit_count[i] / 15, i, (1 << i));
2948 dev->irq_bit_count[i] = 0;
2949 }
2950 }
2951 }
2952 #endif
2953 }
2954
2955 static void do_periodic_work(struct b43_wldev *dev)
2956 {
2957 unsigned int state;
2958
2959 state = dev->periodic_state;
2960 if (state % 4 == 0)
2961 b43_periodic_every60sec(dev);
2962 if (state % 2 == 0)
2963 b43_periodic_every30sec(dev);
2964 b43_periodic_every15sec(dev);
2965 }
2966
2967 /* Periodic work locking policy:
2968 * The whole periodic work handler is protected by
2969 * wl->mutex. If another lock is needed somewhere in the
2970 * pwork callchain, it's aquired in-place, where it's needed.
2971 */
2972 static void b43_periodic_work_handler(struct work_struct *work)
2973 {
2974 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2975 periodic_work.work);
2976 struct b43_wl *wl = dev->wl;
2977 unsigned long delay;
2978
2979 mutex_lock(&wl->mutex);
2980
2981 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2982 goto out;
2983 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2984 goto out_requeue;
2985
2986 do_periodic_work(dev);
2987
2988 dev->periodic_state++;
2989 out_requeue:
2990 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2991 delay = msecs_to_jiffies(50);
2992 else
2993 delay = round_jiffies_relative(HZ * 15);
2994 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
2995 out:
2996 mutex_unlock(&wl->mutex);
2997 }
2998
2999 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
3000 {
3001 struct delayed_work *work = &dev->periodic_work;
3002
3003 dev->periodic_state = 0;
3004 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
3005 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
3006 }
3007
3008 /* Check if communication with the device works correctly. */
3009 static int b43_validate_chipaccess(struct b43_wldev *dev)
3010 {
3011 u32 v, backup0, backup4;
3012
3013 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
3014 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
3015
3016 /* Check for read/write and endianness problems. */
3017 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
3018 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
3019 goto error;
3020 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
3021 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
3022 goto error;
3023
3024 /* Check if unaligned 32bit SHM_SHARED access works properly.
3025 * However, don't bail out on failure, because it's noncritical. */
3026 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
3027 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
3028 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
3029 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
3030 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
3031 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
3032 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
3033 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
3034 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
3035 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
3036 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
3037 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
3038
3039 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3040 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
3041
3042 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
3043 /* The 32bit register shadows the two 16bit registers
3044 * with update sideeffects. Validate this. */
3045 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3046 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3047 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3048 goto error;
3049 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3050 goto error;
3051 }
3052 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3053
3054 v = b43_read32(dev, B43_MMIO_MACCTL);
3055 v |= B43_MACCTL_GMODE;
3056 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
3057 goto error;
3058
3059 return 0;
3060 error:
3061 b43err(dev->wl, "Failed to validate the chipaccess\n");
3062 return -ENODEV;
3063 }
3064
3065 static void b43_security_init(struct b43_wldev *dev)
3066 {
3067 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3068 /* KTP is a word address, but we address SHM bytewise.
3069 * So multiply by two.
3070 */
3071 dev->ktp *= 2;
3072 /* Number of RCMTA address slots */
3073 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3074 /* Clear the key memory. */
3075 b43_clear_keys(dev);
3076 }
3077
3078 #ifdef CONFIG_B43_HWRNG
3079 static int b43_rng_read(struct hwrng *rng, u32 *data)
3080 {
3081 struct b43_wl *wl = (struct b43_wl *)rng->priv;
3082 struct b43_wldev *dev;
3083 int count = -ENODEV;
3084
3085 mutex_lock(&wl->mutex);
3086 dev = wl->current_dev;
3087 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
3088 *data = b43_read16(dev, B43_MMIO_RNG);
3089 count = sizeof(u16);
3090 }
3091 mutex_unlock(&wl->mutex);
3092
3093 return count;
3094 }
3095 #endif /* CONFIG_B43_HWRNG */
3096
3097 static void b43_rng_exit(struct b43_wl *wl)
3098 {
3099 #ifdef CONFIG_B43_HWRNG
3100 if (wl->rng_initialized)
3101 hwrng_unregister(&wl->rng);
3102 #endif /* CONFIG_B43_HWRNG */
3103 }
3104
3105 static int b43_rng_init(struct b43_wl *wl)
3106 {
3107 int err = 0;
3108
3109 #ifdef CONFIG_B43_HWRNG
3110 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3111 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3112 wl->rng.name = wl->rng_name;
3113 wl->rng.data_read = b43_rng_read;
3114 wl->rng.priv = (unsigned long)wl;
3115 wl->rng_initialized = 1;
3116 err = hwrng_register(&wl->rng);
3117 if (err) {
3118 wl->rng_initialized = 0;
3119 b43err(wl, "Failed to register the random "
3120 "number generator (%d)\n", err);
3121 }
3122 #endif /* CONFIG_B43_HWRNG */
3123
3124 return err;
3125 }
3126
3127 static void b43_tx_work(struct work_struct *work)
3128 {
3129 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3130 struct b43_wldev *dev;
3131 struct sk_buff *skb;
3132 int err = 0;
3133
3134 mutex_lock(&wl->mutex);
3135 dev = wl->current_dev;
3136 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3137 mutex_unlock(&wl->mutex);
3138 return;
3139 }
3140
3141 while (skb_queue_len(&wl->tx_queue)) {
3142 skb = skb_dequeue(&wl->tx_queue);
3143
3144 if (b43_using_pio_transfers(dev))
3145 err = b43_pio_tx(dev, skb);
3146 else
3147 err = b43_dma_tx(dev, skb);
3148 if (unlikely(err))
3149 dev_kfree_skb(skb); /* Drop it */
3150 }
3151
3152 #if B43_DEBUG
3153 dev->tx_count++;
3154 #endif
3155 mutex_unlock(&wl->mutex);
3156 }
3157
3158 static int b43_op_tx(struct ieee80211_hw *hw,
3159 struct sk_buff *skb)
3160 {
3161 struct b43_wl *wl = hw_to_b43_wl(hw);
3162
3163 if (unlikely(skb->len < 2 + 2 + 6)) {
3164 /* Too short, this can't be a valid frame. */
3165 dev_kfree_skb_any(skb);
3166 return NETDEV_TX_OK;
3167 }
3168 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3169
3170 skb_queue_tail(&wl->tx_queue, skb);
3171 ieee80211_queue_work(wl->hw, &wl->tx_work);
3172
3173 return NETDEV_TX_OK;
3174 }
3175
3176 static void b43_qos_params_upload(struct b43_wldev *dev,
3177 const struct ieee80211_tx_queue_params *p,
3178 u16 shm_offset)
3179 {
3180 u16 params[B43_NR_QOSPARAMS];
3181 int bslots, tmp;
3182 unsigned int i;
3183
3184 if (!dev->qos_enabled)
3185 return;
3186
3187 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
3188
3189 memset(&params, 0, sizeof(params));
3190
3191 params[B43_QOSPARAM_TXOP] = p->txop * 32;
3192 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3193 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3194 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3195 params[B43_QOSPARAM_AIFS] = p->aifs;
3196 params[B43_QOSPARAM_BSLOTS] = bslots;
3197 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
3198
3199 for (i = 0; i < ARRAY_SIZE(params); i++) {
3200 if (i == B43_QOSPARAM_STATUS) {
3201 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3202 shm_offset + (i * 2));
3203 /* Mark the parameters as updated. */
3204 tmp |= 0x100;
3205 b43_shm_write16(dev, B43_SHM_SHARED,
3206 shm_offset + (i * 2),
3207 tmp);
3208 } else {
3209 b43_shm_write16(dev, B43_SHM_SHARED,
3210 shm_offset + (i * 2),
3211 params[i]);
3212 }
3213 }
3214 }
3215
3216 /* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3217 static const u16 b43_qos_shm_offsets[] = {
3218 /* [mac80211-queue-nr] = SHM_OFFSET, */
3219 [0] = B43_QOS_VOICE,
3220 [1] = B43_QOS_VIDEO,
3221 [2] = B43_QOS_BESTEFFORT,
3222 [3] = B43_QOS_BACKGROUND,
3223 };
3224
3225 /* Update all QOS parameters in hardware. */
3226 static void b43_qos_upload_all(struct b43_wldev *dev)
3227 {
3228 struct b43_wl *wl = dev->wl;
3229 struct b43_qos_params *params;
3230 unsigned int i;
3231
3232 if (!dev->qos_enabled)
3233 return;
3234
3235 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3236 ARRAY_SIZE(wl->qos_params));
3237
3238 b43_mac_suspend(dev);
3239 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3240 params = &(wl->qos_params[i]);
3241 b43_qos_params_upload(dev, &(params->p),
3242 b43_qos_shm_offsets[i]);
3243 }
3244 b43_mac_enable(dev);
3245 }
3246
3247 static void b43_qos_clear(struct b43_wl *wl)
3248 {
3249 struct b43_qos_params *params;
3250 unsigned int i;
3251
3252 /* Initialize QoS parameters to sane defaults. */
3253
3254 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3255 ARRAY_SIZE(wl->qos_params));
3256
3257 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3258 params = &(wl->qos_params[i]);
3259
3260 switch (b43_qos_shm_offsets[i]) {
3261 case B43_QOS_VOICE:
3262 params->p.txop = 0;
3263 params->p.aifs = 2;
3264 params->p.cw_min = 0x0001;
3265 params->p.cw_max = 0x0001;
3266 break;
3267 case B43_QOS_VIDEO:
3268 params->p.txop = 0;
3269 params->p.aifs = 2;
3270 params->p.cw_min = 0x0001;
3271 params->p.cw_max = 0x0001;
3272 break;
3273 case B43_QOS_BESTEFFORT:
3274 params->p.txop = 0;
3275 params->p.aifs = 3;
3276 params->p.cw_min = 0x0001;
3277 params->p.cw_max = 0x03FF;
3278 break;
3279 case B43_QOS_BACKGROUND:
3280 params->p.txop = 0;
3281 params->p.aifs = 7;
3282 params->p.cw_min = 0x0001;
3283 params->p.cw_max = 0x03FF;
3284 break;
3285 default:
3286 B43_WARN_ON(1);
3287 }
3288 }
3289 }
3290
3291 /* Initialize the core's QOS capabilities */
3292 static void b43_qos_init(struct b43_wldev *dev)
3293 {
3294 if (!dev->qos_enabled) {
3295 /* Disable QOS support. */
3296 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3297 b43_write16(dev, B43_MMIO_IFSCTL,
3298 b43_read16(dev, B43_MMIO_IFSCTL)
3299 & ~B43_MMIO_IFSCTL_USE_EDCF);
3300 b43dbg(dev->wl, "QoS disabled\n");
3301 return;
3302 }
3303
3304 /* Upload the current QOS parameters. */
3305 b43_qos_upload_all(dev);
3306
3307 /* Enable QOS support. */
3308 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3309 b43_write16(dev, B43_MMIO_IFSCTL,
3310 b43_read16(dev, B43_MMIO_IFSCTL)
3311 | B43_MMIO_IFSCTL_USE_EDCF);
3312 b43dbg(dev->wl, "QoS enabled\n");
3313 }
3314
3315 static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
3316 const struct ieee80211_tx_queue_params *params)
3317 {
3318 struct b43_wl *wl = hw_to_b43_wl(hw);
3319 struct b43_wldev *dev;
3320 unsigned int queue = (unsigned int)_queue;
3321 int err = -ENODEV;
3322
3323 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3324 /* Queue not available or don't support setting
3325 * params on this queue. Return success to not
3326 * confuse mac80211. */
3327 return 0;
3328 }
3329 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3330 ARRAY_SIZE(wl->qos_params));
3331
3332 mutex_lock(&wl->mutex);
3333 dev = wl->current_dev;
3334 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3335 goto out_unlock;
3336
3337 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3338 b43_mac_suspend(dev);
3339 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3340 b43_qos_shm_offsets[queue]);
3341 b43_mac_enable(dev);
3342 err = 0;
3343
3344 out_unlock:
3345 mutex_unlock(&wl->mutex);
3346
3347 return err;
3348 }
3349
3350 static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
3351 struct ieee80211_tx_queue_stats *stats)
3352 {
3353 struct b43_wl *wl = hw_to_b43_wl(hw);
3354 struct b43_wldev *dev;
3355 int err = -ENODEV;
3356
3357 mutex_lock(&wl->mutex);
3358 dev = wl->current_dev;
3359 if (dev && b43_status(dev) >= B43_STAT_STARTED) {
3360 if (b43_using_pio_transfers(dev))
3361 b43_pio_get_tx_stats(dev, stats);
3362 else
3363 b43_dma_get_tx_stats(dev, stats);
3364 err = 0;
3365 }
3366 mutex_unlock(&wl->mutex);
3367
3368 return err;
3369 }
3370
3371 static int b43_op_get_stats(struct ieee80211_hw *hw,
3372 struct ieee80211_low_level_stats *stats)
3373 {
3374 struct b43_wl *wl = hw_to_b43_wl(hw);
3375
3376 mutex_lock(&wl->mutex);
3377 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3378 mutex_unlock(&wl->mutex);
3379
3380 return 0;
3381 }
3382
3383 static u64 b43_op_get_tsf(struct ieee80211_hw *hw)
3384 {
3385 struct b43_wl *wl = hw_to_b43_wl(hw);
3386 struct b43_wldev *dev;
3387 u64 tsf;
3388
3389 mutex_lock(&wl->mutex);
3390 dev = wl->current_dev;
3391
3392 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3393 b43_tsf_read(dev, &tsf);
3394 else
3395 tsf = 0;
3396
3397 mutex_unlock(&wl->mutex);
3398
3399 return tsf;
3400 }
3401
3402 static void b43_op_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3403 {
3404 struct b43_wl *wl = hw_to_b43_wl(hw);
3405 struct b43_wldev *dev;
3406
3407 mutex_lock(&wl->mutex);
3408 dev = wl->current_dev;
3409
3410 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3411 b43_tsf_write(dev, tsf);
3412
3413 mutex_unlock(&wl->mutex);
3414 }
3415
3416 static void b43_put_phy_into_reset(struct b43_wldev *dev)
3417 {
3418 struct ssb_device *sdev = dev->dev;
3419 u32 tmslow;
3420
3421 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3422 tmslow &= ~B43_TMSLOW_GMODE;
3423 tmslow |= B43_TMSLOW_PHYRESET;
3424 tmslow |= SSB_TMSLOW_FGC;
3425 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3426 msleep(1);
3427
3428 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3429 tmslow &= ~SSB_TMSLOW_FGC;
3430 tmslow |= B43_TMSLOW_PHYRESET;
3431 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3432 msleep(1);
3433 }
3434
3435 static const char *band_to_string(enum ieee80211_band band)
3436 {
3437 switch (band) {
3438 case IEEE80211_BAND_5GHZ:
3439 return "5";
3440 case IEEE80211_BAND_2GHZ:
3441 return "2.4";
3442 default:
3443 break;
3444 }
3445 B43_WARN_ON(1);
3446 return "";
3447 }
3448
3449 /* Expects wl->mutex locked */
3450 static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
3451 {
3452 struct b43_wldev *up_dev = NULL;
3453 struct b43_wldev *down_dev;
3454 struct b43_wldev *d;
3455 int err;
3456 bool uninitialized_var(gmode);
3457 int prev_status;
3458
3459 /* Find a device and PHY which supports the band. */
3460 list_for_each_entry(d, &wl->devlist, list) {
3461 switch (chan->band) {
3462 case IEEE80211_BAND_5GHZ:
3463 if (d->phy.supports_5ghz) {
3464 up_dev = d;
3465 gmode = 0;
3466 }
3467 break;
3468 case IEEE80211_BAND_2GHZ:
3469 if (d->phy.supports_2ghz) {
3470 up_dev = d;
3471 gmode = 1;
3472 }
3473 break;
3474 default:
3475 B43_WARN_ON(1);
3476 return -EINVAL;
3477 }
3478 if (up_dev)
3479 break;
3480 }
3481 if (!up_dev) {
3482 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3483 band_to_string(chan->band));
3484 return -ENODEV;
3485 }
3486 if ((up_dev == wl->current_dev) &&
3487 (!!wl->current_dev->phy.gmode == !!gmode)) {
3488 /* This device is already running. */
3489 return 0;
3490 }
3491 b43dbg(wl, "Switching to %s-GHz band\n",
3492 band_to_string(chan->band));
3493 down_dev = wl->current_dev;
3494
3495 prev_status = b43_status(down_dev);
3496 /* Shutdown the currently running core. */
3497 if (prev_status >= B43_STAT_STARTED)
3498 down_dev = b43_wireless_core_stop(down_dev);
3499 if (prev_status >= B43_STAT_INITIALIZED)
3500 b43_wireless_core_exit(down_dev);
3501
3502 if (down_dev != up_dev) {
3503 /* We switch to a different core, so we put PHY into
3504 * RESET on the old core. */
3505 b43_put_phy_into_reset(down_dev);
3506 }
3507
3508 /* Now start the new core. */
3509 up_dev->phy.gmode = gmode;
3510 if (prev_status >= B43_STAT_INITIALIZED) {
3511 err = b43_wireless_core_init(up_dev);
3512 if (err) {
3513 b43err(wl, "Fatal: Could not initialize device for "
3514 "selected %s-GHz band\n",
3515 band_to_string(chan->band));
3516 goto init_failure;
3517 }
3518 }
3519 if (prev_status >= B43_STAT_STARTED) {
3520 err = b43_wireless_core_start(up_dev);
3521 if (err) {
3522 b43err(wl, "Fatal: Coult not start device for "
3523 "selected %s-GHz band\n",
3524 band_to_string(chan->band));
3525 b43_wireless_core_exit(up_dev);
3526 goto init_failure;
3527 }
3528 }
3529 B43_WARN_ON(b43_status(up_dev) != prev_status);
3530
3531 wl->current_dev = up_dev;
3532
3533 return 0;
3534 init_failure:
3535 /* Whoops, failed to init the new core. No core is operating now. */
3536 wl->current_dev = NULL;
3537 return err;
3538 }
3539
3540 /* Write the short and long frame retry limit values. */
3541 static void b43_set_retry_limits(struct b43_wldev *dev,
3542 unsigned int short_retry,
3543 unsigned int long_retry)
3544 {
3545 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3546 * the chip-internal counter. */
3547 short_retry = min(short_retry, (unsigned int)0xF);
3548 long_retry = min(long_retry, (unsigned int)0xF);
3549
3550 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3551 short_retry);
3552 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3553 long_retry);
3554 }
3555
3556 static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
3557 {
3558 struct b43_wl *wl = hw_to_b43_wl(hw);
3559 struct b43_wldev *dev;
3560 struct b43_phy *phy;
3561 struct ieee80211_conf *conf = &hw->conf;
3562 int antenna;
3563 int err = 0;
3564
3565 mutex_lock(&wl->mutex);
3566
3567 /* Switch the band (if necessary). This might change the active core. */
3568 err = b43_switch_band(wl, conf->channel);
3569 if (err)
3570 goto out_unlock_mutex;
3571 dev = wl->current_dev;
3572 phy = &dev->phy;
3573
3574 b43_mac_suspend(dev);
3575
3576 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3577 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3578 conf->long_frame_max_tx_count);
3579 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3580 if (!changed)
3581 goto out_mac_enable;
3582
3583 /* Switch to the requested channel.
3584 * The firmware takes care of races with the TX handler. */
3585 if (conf->channel->hw_value != phy->channel)
3586 b43_switch_channel(dev, conf->channel->hw_value);
3587
3588 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
3589
3590 /* Adjust the desired TX power level. */
3591 if (conf->power_level != 0) {
3592 if (conf->power_level != phy->desired_txpower) {
3593 phy->desired_txpower = conf->power_level;
3594 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3595 B43_TXPWR_IGNORE_TSSI);
3596 }
3597 }
3598
3599 /* Antennas for RX and management frame TX. */
3600 antenna = B43_ANTENNA_DEFAULT;
3601 b43_mgmtframe_txantenna(dev, antenna);
3602 antenna = B43_ANTENNA_DEFAULT;
3603 if (phy->ops->set_rx_antenna)
3604 phy->ops->set_rx_antenna(dev, antenna);
3605
3606 if (wl->radio_enabled != phy->radio_on) {
3607 if (wl->radio_enabled) {
3608 b43_software_rfkill(dev, false);
3609 b43info(dev->wl, "Radio turned on by software\n");
3610 if (!dev->radio_hw_enable) {
3611 b43info(dev->wl, "The hardware RF-kill button "
3612 "still turns the radio physically off. "
3613 "Press the button to turn it on.\n");
3614 }
3615 } else {
3616 b43_software_rfkill(dev, true);
3617 b43info(dev->wl, "Radio turned off by software\n");
3618 }
3619 }
3620
3621 out_mac_enable:
3622 b43_mac_enable(dev);
3623 out_unlock_mutex:
3624 mutex_unlock(&wl->mutex);
3625
3626 return err;
3627 }
3628
3629 static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
3630 {
3631 struct ieee80211_supported_band *sband =
3632 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3633 struct ieee80211_rate *rate;
3634 int i;
3635 u16 basic, direct, offset, basic_offset, rateptr;
3636
3637 for (i = 0; i < sband->n_bitrates; i++) {
3638 rate = &sband->bitrates[i];
3639
3640 if (b43_is_cck_rate(rate->hw_value)) {
3641 direct = B43_SHM_SH_CCKDIRECT;
3642 basic = B43_SHM_SH_CCKBASIC;
3643 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3644 offset &= 0xF;
3645 } else {
3646 direct = B43_SHM_SH_OFDMDIRECT;
3647 basic = B43_SHM_SH_OFDMBASIC;
3648 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3649 offset &= 0xF;
3650 }
3651
3652 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3653
3654 if (b43_is_cck_rate(rate->hw_value)) {
3655 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3656 basic_offset &= 0xF;
3657 } else {
3658 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3659 basic_offset &= 0xF;
3660 }
3661
3662 /*
3663 * Get the pointer that we need to point to
3664 * from the direct map
3665 */
3666 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3667 direct + 2 * basic_offset);
3668 /* and write it to the basic map */
3669 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3670 rateptr);
3671 }
3672 }
3673
3674 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3675 struct ieee80211_vif *vif,
3676 struct ieee80211_bss_conf *conf,
3677 u32 changed)
3678 {
3679 struct b43_wl *wl = hw_to_b43_wl(hw);
3680 struct b43_wldev *dev;
3681
3682 mutex_lock(&wl->mutex);
3683
3684 dev = wl->current_dev;
3685 if (!dev || b43_status(dev) < B43_STAT_STARTED)
3686 goto out_unlock_mutex;
3687
3688 B43_WARN_ON(wl->vif != vif);
3689
3690 if (changed & BSS_CHANGED_BSSID) {
3691 if (conf->bssid)
3692 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3693 else
3694 memset(wl->bssid, 0, ETH_ALEN);
3695 }
3696
3697 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3698 if (changed & BSS_CHANGED_BEACON &&
3699 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3700 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3701 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3702 b43_update_templates(wl);
3703
3704 if (changed & BSS_CHANGED_BSSID)
3705 b43_write_mac_bssid_templates(dev);
3706 }
3707
3708 b43_mac_suspend(dev);
3709
3710 /* Update templates for AP/mesh mode. */
3711 if (changed & BSS_CHANGED_BEACON_INT &&
3712 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3713 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3714 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3715 b43_set_beacon_int(dev, conf->beacon_int);
3716
3717 if (changed & BSS_CHANGED_BASIC_RATES)
3718 b43_update_basic_rates(dev, conf->basic_rates);
3719
3720 if (changed & BSS_CHANGED_ERP_SLOT) {
3721 if (conf->use_short_slot)
3722 b43_short_slot_timing_enable(dev);
3723 else
3724 b43_short_slot_timing_disable(dev);
3725 }
3726
3727 b43_mac_enable(dev);
3728 out_unlock_mutex:
3729 mutex_unlock(&wl->mutex);
3730 }
3731
3732 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3733 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3734 struct ieee80211_key_conf *key)
3735 {
3736 struct b43_wl *wl = hw_to_b43_wl(hw);
3737 struct b43_wldev *dev;
3738 u8 algorithm;
3739 u8 index;
3740 int err;
3741 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
3742
3743 if (modparam_nohwcrypt)
3744 return -ENOSPC; /* User disabled HW-crypto */
3745
3746 mutex_lock(&wl->mutex);
3747
3748 dev = wl->current_dev;
3749 err = -ENODEV;
3750 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3751 goto out_unlock;
3752
3753 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
3754 /* We don't have firmware for the crypto engine.
3755 * Must use software-crypto. */
3756 err = -EOPNOTSUPP;
3757 goto out_unlock;
3758 }
3759
3760 err = -EINVAL;
3761 switch (key->alg) {
3762 case ALG_WEP:
3763 if (key->keylen == WLAN_KEY_LEN_WEP40)
3764 algorithm = B43_SEC_ALGO_WEP40;
3765 else
3766 algorithm = B43_SEC_ALGO_WEP104;
3767 break;
3768 case ALG_TKIP:
3769 algorithm = B43_SEC_ALGO_TKIP;
3770 break;
3771 case ALG_CCMP:
3772 algorithm = B43_SEC_ALGO_AES;
3773 break;
3774 default:
3775 B43_WARN_ON(1);
3776 goto out_unlock;
3777 }
3778 index = (u8) (key->keyidx);
3779 if (index > 3)
3780 goto out_unlock;
3781
3782 switch (cmd) {
3783 case SET_KEY:
3784 if (algorithm == B43_SEC_ALGO_TKIP &&
3785 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
3786 !modparam_hwtkip)) {
3787 /* We support only pairwise key */
3788 err = -EOPNOTSUPP;
3789 goto out_unlock;
3790 }
3791
3792 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
3793 if (WARN_ON(!sta)) {
3794 err = -EOPNOTSUPP;
3795 goto out_unlock;
3796 }
3797 /* Pairwise key with an assigned MAC address. */
3798 err = b43_key_write(dev, -1, algorithm,
3799 key->key, key->keylen,
3800 sta->addr, key);
3801 } else {
3802 /* Group key */
3803 err = b43_key_write(dev, index, algorithm,
3804 key->key, key->keylen, NULL, key);
3805 }
3806 if (err)
3807 goto out_unlock;
3808
3809 if (algorithm == B43_SEC_ALGO_WEP40 ||
3810 algorithm == B43_SEC_ALGO_WEP104) {
3811 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3812 } else {
3813 b43_hf_write(dev,
3814 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3815 }
3816 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3817 if (algorithm == B43_SEC_ALGO_TKIP)
3818 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
3819 break;
3820 case DISABLE_KEY: {
3821 err = b43_key_clear(dev, key->hw_key_idx);
3822 if (err)
3823 goto out_unlock;
3824 break;
3825 }
3826 default:
3827 B43_WARN_ON(1);
3828 }
3829
3830 out_unlock:
3831 if (!err) {
3832 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
3833 "mac: %pM\n",
3834 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
3835 sta ? sta->addr : bcast_addr);
3836 b43_dump_keymemory(dev);
3837 }
3838 mutex_unlock(&wl->mutex);
3839
3840 return err;
3841 }
3842
3843 static void b43_op_configure_filter(struct ieee80211_hw *hw,
3844 unsigned int changed, unsigned int *fflags,
3845 u64 multicast)
3846 {
3847 struct b43_wl *wl = hw_to_b43_wl(hw);
3848 struct b43_wldev *dev;
3849
3850 mutex_lock(&wl->mutex);
3851 dev = wl->current_dev;
3852 if (!dev) {
3853 *fflags = 0;
3854 goto out_unlock;
3855 }
3856
3857 *fflags &= FIF_PROMISC_IN_BSS |
3858 FIF_ALLMULTI |
3859 FIF_FCSFAIL |
3860 FIF_PLCPFAIL |
3861 FIF_CONTROL |
3862 FIF_OTHER_BSS |
3863 FIF_BCN_PRBRESP_PROMISC;
3864
3865 changed &= FIF_PROMISC_IN_BSS |
3866 FIF_ALLMULTI |
3867 FIF_FCSFAIL |
3868 FIF_PLCPFAIL |
3869 FIF_CONTROL |
3870 FIF_OTHER_BSS |
3871 FIF_BCN_PRBRESP_PROMISC;
3872
3873 wl->filter_flags = *fflags;
3874
3875 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3876 b43_adjust_opmode(dev);
3877
3878 out_unlock:
3879 mutex_unlock(&wl->mutex);
3880 }
3881
3882 /* Locking: wl->mutex
3883 * Returns the current dev. This might be different from the passed in dev,
3884 * because the core might be gone away while we unlocked the mutex. */
3885 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
3886 {
3887 struct b43_wl *wl = dev->wl;
3888 struct b43_wldev *orig_dev;
3889 u32 mask;
3890
3891 redo:
3892 if (!dev || b43_status(dev) < B43_STAT_STARTED)
3893 return dev;
3894
3895 /* Cancel work. Unlock to avoid deadlocks. */
3896 mutex_unlock(&wl->mutex);
3897 cancel_delayed_work_sync(&dev->periodic_work);
3898 cancel_work_sync(&wl->tx_work);
3899 mutex_lock(&wl->mutex);
3900 dev = wl->current_dev;
3901 if (!dev || b43_status(dev) < B43_STAT_STARTED) {
3902 /* Whoops, aliens ate up the device while we were unlocked. */
3903 return dev;
3904 }
3905
3906 /* Disable interrupts on the device. */
3907 b43_set_status(dev, B43_STAT_INITIALIZED);
3908 if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) {
3909 /* wl->mutex is locked. That is enough. */
3910 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
3911 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
3912 } else {
3913 spin_lock_irq(&wl->hardirq_lock);
3914 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
3915 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
3916 spin_unlock_irq(&wl->hardirq_lock);
3917 }
3918 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
3919 orig_dev = dev;
3920 mutex_unlock(&wl->mutex);
3921 if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) {
3922 b43_sdio_free_irq(dev);
3923 } else {
3924 synchronize_irq(dev->dev->irq);
3925 free_irq(dev->dev->irq, dev);
3926 }
3927 mutex_lock(&wl->mutex);
3928 dev = wl->current_dev;
3929 if (!dev)
3930 return dev;
3931 if (dev != orig_dev) {
3932 if (b43_status(dev) >= B43_STAT_STARTED)
3933 goto redo;
3934 return dev;
3935 }
3936 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
3937 B43_WARN_ON(mask != 0xFFFFFFFF && mask);
3938
3939 /* Drain the TX queue */
3940 while (skb_queue_len(&wl->tx_queue))
3941 dev_kfree_skb(skb_dequeue(&wl->tx_queue));
3942
3943 b43_mac_suspend(dev);
3944 b43_leds_exit(dev);
3945 b43dbg(wl, "Wireless interface stopped\n");
3946
3947 return dev;
3948 }
3949
3950 /* Locking: wl->mutex */
3951 static int b43_wireless_core_start(struct b43_wldev *dev)
3952 {
3953 int err;
3954
3955 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3956
3957 drain_txstatus_queue(dev);
3958 if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) {
3959 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
3960 if (err) {
3961 b43err(dev->wl, "Cannot request SDIO IRQ\n");
3962 goto out;
3963 }
3964 } else {
3965 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
3966 b43_interrupt_thread_handler,
3967 IRQF_SHARED, KBUILD_MODNAME, dev);
3968 if (err) {
3969 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3970 goto out;
3971 }
3972 }
3973
3974 /* We are ready to run. */
3975 ieee80211_wake_queues(dev->wl->hw);
3976 b43_set_status(dev, B43_STAT_STARTED);
3977
3978 /* Start data flow (TX/RX). */
3979 b43_mac_enable(dev);
3980 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
3981
3982 /* Start maintainance work */
3983 b43_periodic_tasks_setup(dev);
3984
3985 b43_leds_init(dev);
3986
3987 b43dbg(dev->wl, "Wireless interface started\n");
3988 out:
3989 return err;
3990 }
3991
3992 /* Get PHY and RADIO versioning numbers */
3993 static int b43_phy_versioning(struct b43_wldev *dev)
3994 {
3995 struct b43_phy *phy = &dev->phy;
3996 u32 tmp;
3997 u8 analog_type;
3998 u8 phy_type;
3999 u8 phy_rev;
4000 u16 radio_manuf;
4001 u16 radio_ver;
4002 u16 radio_rev;
4003 int unsupported = 0;
4004
4005 /* Get PHY versioning */
4006 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
4007 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
4008 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
4009 phy_rev = (tmp & B43_PHYVER_VERSION);
4010 switch (phy_type) {
4011 case B43_PHYTYPE_A:
4012 if (phy_rev >= 4)
4013 unsupported = 1;
4014 break;
4015 case B43_PHYTYPE_B:
4016 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
4017 && phy_rev != 7)
4018 unsupported = 1;
4019 break;
4020 case B43_PHYTYPE_G:
4021 if (phy_rev > 9)
4022 unsupported = 1;
4023 break;
4024 #ifdef CONFIG_B43_NPHY
4025 case B43_PHYTYPE_N:
4026 if (phy_rev > 4)
4027 unsupported = 1;
4028 break;
4029 #endif
4030 #ifdef CONFIG_B43_PHY_LP
4031 case B43_PHYTYPE_LP:
4032 if (phy_rev > 2)
4033 unsupported = 1;
4034 break;
4035 #endif
4036 default:
4037 unsupported = 1;
4038 };
4039 if (unsupported) {
4040 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
4041 "(Analog %u, Type %u, Revision %u)\n",
4042 analog_type, phy_type, phy_rev);
4043 return -EOPNOTSUPP;
4044 }
4045 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
4046 analog_type, phy_type, phy_rev);
4047
4048 /* Get RADIO versioning */
4049 if (dev->dev->bus->chip_id == 0x4317) {
4050 if (dev->dev->bus->chip_rev == 0)
4051 tmp = 0x3205017F;
4052 else if (dev->dev->bus->chip_rev == 1)
4053 tmp = 0x4205017F;
4054 else
4055 tmp = 0x5205017F;
4056 } else {
4057 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
4058 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4059 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
4060 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
4061 }
4062 radio_manuf = (tmp & 0x00000FFF);
4063 radio_ver = (tmp & 0x0FFFF000) >> 12;
4064 radio_rev = (tmp & 0xF0000000) >> 28;
4065 if (radio_manuf != 0x17F /* Broadcom */)
4066 unsupported = 1;
4067 switch (phy_type) {
4068 case B43_PHYTYPE_A:
4069 if (radio_ver != 0x2060)
4070 unsupported = 1;
4071 if (radio_rev != 1)
4072 unsupported = 1;
4073 if (radio_manuf != 0x17F)
4074 unsupported = 1;
4075 break;
4076 case B43_PHYTYPE_B:
4077 if ((radio_ver & 0xFFF0) != 0x2050)
4078 unsupported = 1;
4079 break;
4080 case B43_PHYTYPE_G:
4081 if (radio_ver != 0x2050)
4082 unsupported = 1;
4083 break;
4084 case B43_PHYTYPE_N:
4085 if (radio_ver != 0x2055 && radio_ver != 0x2056)
4086 unsupported = 1;
4087 break;
4088 case B43_PHYTYPE_LP:
4089 if (radio_ver != 0x2062 && radio_ver != 0x2063)
4090 unsupported = 1;
4091 break;
4092 default:
4093 B43_WARN_ON(1);
4094 }
4095 if (unsupported) {
4096 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
4097 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
4098 radio_manuf, radio_ver, radio_rev);
4099 return -EOPNOTSUPP;
4100 }
4101 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
4102 radio_manuf, radio_ver, radio_rev);
4103
4104 phy->radio_manuf = radio_manuf;
4105 phy->radio_ver = radio_ver;
4106 phy->radio_rev = radio_rev;
4107
4108 phy->analog = analog_type;
4109 phy->type = phy_type;
4110 phy->rev = phy_rev;
4111
4112 return 0;
4113 }
4114
4115 static void setup_struct_phy_for_init(struct b43_wldev *dev,
4116 struct b43_phy *phy)
4117 {
4118 phy->hardware_power_control = !!modparam_hwpctl;
4119 phy->next_txpwr_check_time = jiffies;
4120 /* PHY TX errors counter. */
4121 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
4122
4123 #if B43_DEBUG
4124 phy->phy_locked = 0;
4125 phy->radio_locked = 0;
4126 #endif
4127 }
4128
4129 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4130 {
4131 dev->dfq_valid = 0;
4132
4133 /* Assume the radio is enabled. If it's not enabled, the state will
4134 * immediately get fixed on the first periodic work run. */
4135 dev->radio_hw_enable = 1;
4136
4137 /* Stats */
4138 memset(&dev->stats, 0, sizeof(dev->stats));
4139
4140 setup_struct_phy_for_init(dev, &dev->phy);
4141
4142 /* IRQ related flags */
4143 dev->irq_reason = 0;
4144 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
4145 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
4146 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
4147 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
4148
4149 dev->mac_suspended = 1;
4150
4151 /* Noise calculation context */
4152 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4153 }
4154
4155 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4156 {
4157 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
4158 u64 hf;
4159
4160 if (!modparam_btcoex)
4161 return;
4162 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
4163 return;
4164 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4165 return;
4166
4167 hf = b43_hf_read(dev);
4168 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
4169 hf |= B43_HF_BTCOEXALT;
4170 else
4171 hf |= B43_HF_BTCOEX;
4172 b43_hf_write(dev, hf);
4173 }
4174
4175 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
4176 {
4177 if (!modparam_btcoex)
4178 return;
4179 //TODO
4180 }
4181
4182 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4183 {
4184 #ifdef CONFIG_SSB_DRIVER_PCICORE
4185 struct ssb_bus *bus = dev->dev->bus;
4186 u32 tmp;
4187
4188 if (bus->pcicore.dev &&
4189 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
4190 bus->pcicore.dev->id.revision <= 5) {
4191 /* IMCFGLO timeouts workaround. */
4192 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
4193 switch (bus->bustype) {
4194 case SSB_BUSTYPE_PCI:
4195 case SSB_BUSTYPE_PCMCIA:
4196 tmp &= ~SSB_IMCFGLO_REQTO;
4197 tmp &= ~SSB_IMCFGLO_SERTO;
4198 tmp |= 0x32;
4199 break;
4200 case SSB_BUSTYPE_SSB:
4201 tmp &= ~SSB_IMCFGLO_REQTO;
4202 tmp &= ~SSB_IMCFGLO_SERTO;
4203 tmp |= 0x53;
4204 break;
4205 default:
4206 break;
4207 }
4208 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
4209 }
4210 #endif /* CONFIG_SSB_DRIVER_PCICORE */
4211 }
4212
4213 static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4214 {
4215 u16 pu_delay;
4216
4217 /* The time value is in microseconds. */
4218 if (dev->phy.type == B43_PHYTYPE_A)
4219 pu_delay = 3700;
4220 else
4221 pu_delay = 1050;
4222 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
4223 pu_delay = 500;
4224 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4225 pu_delay = max(pu_delay, (u16)2400);
4226
4227 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4228 }
4229
4230 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4231 static void b43_set_pretbtt(struct b43_wldev *dev)
4232 {
4233 u16 pretbtt;
4234
4235 /* The time value is in microseconds. */
4236 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
4237 pretbtt = 2;
4238 } else {
4239 if (dev->phy.type == B43_PHYTYPE_A)
4240 pretbtt = 120;
4241 else
4242 pretbtt = 250;
4243 }
4244 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4245 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4246 }
4247
4248 /* Shutdown a wireless core */
4249 /* Locking: wl->mutex */
4250 static void b43_wireless_core_exit(struct b43_wldev *dev)
4251 {
4252 u32 macctl;
4253
4254 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4255 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
4256 return;
4257 b43_set_status(dev, B43_STAT_UNINIT);
4258
4259 /* Stop the microcode PSM. */
4260 macctl = b43_read32(dev, B43_MMIO_MACCTL);
4261 macctl &= ~B43_MACCTL_PSM_RUN;
4262 macctl |= B43_MACCTL_PSM_JMP0;
4263 b43_write32(dev, B43_MMIO_MACCTL, macctl);
4264
4265 b43_dma_free(dev);
4266 b43_pio_free(dev);
4267 b43_chip_exit(dev);
4268 dev->phy.ops->switch_analog(dev, 0);
4269 if (dev->wl->current_beacon) {
4270 dev_kfree_skb_any(dev->wl->current_beacon);
4271 dev->wl->current_beacon = NULL;
4272 }
4273
4274 ssb_device_disable(dev->dev, 0);
4275 ssb_bus_may_powerdown(dev->dev->bus);
4276 }
4277
4278 /* Initialize a wireless core */
4279 static int b43_wireless_core_init(struct b43_wldev *dev)
4280 {
4281 struct ssb_bus *bus = dev->dev->bus;
4282 struct ssb_sprom *sprom = &bus->sprom;
4283 struct b43_phy *phy = &dev->phy;
4284 int err;
4285 u64 hf;
4286 u32 tmp;
4287
4288 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4289
4290 err = ssb_bus_powerup(bus, 0);
4291 if (err)
4292 goto out;
4293 if (!ssb_device_is_enabled(dev->dev)) {
4294 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
4295 b43_wireless_core_reset(dev, tmp);
4296 }
4297
4298 /* Reset all data structures. */
4299 setup_struct_wldev_for_init(dev);
4300 phy->ops->prepare_structs(dev);
4301
4302 /* Enable IRQ routing to this device. */
4303 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
4304
4305 b43_imcfglo_timeouts_workaround(dev);
4306 b43_bluetooth_coext_disable(dev);
4307 if (phy->ops->prepare_hardware) {
4308 err = phy->ops->prepare_hardware(dev);
4309 if (err)
4310 goto err_busdown;
4311 }
4312 err = b43_chip_init(dev);
4313 if (err)
4314 goto err_busdown;
4315 b43_shm_write16(dev, B43_SHM_SHARED,
4316 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
4317 hf = b43_hf_read(dev);
4318 if (phy->type == B43_PHYTYPE_G) {
4319 hf |= B43_HF_SYMW;
4320 if (phy->rev == 1)
4321 hf |= B43_HF_GDCW;
4322 if (sprom->boardflags_lo & B43_BFL_PACTRL)
4323 hf |= B43_HF_OFDMPABOOST;
4324 }
4325 if (phy->radio_ver == 0x2050) {
4326 if (phy->radio_rev == 6)
4327 hf |= B43_HF_4318TSSI;
4328 if (phy->radio_rev < 6)
4329 hf |= B43_HF_VCORECALC;
4330 }
4331 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4332 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
4333 #ifdef CONFIG_SSB_DRIVER_PCICORE
4334 if ((bus->bustype == SSB_BUSTYPE_PCI) &&
4335 (bus->pcicore.dev->id.revision <= 10))
4336 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
4337 #endif
4338 hf &= ~B43_HF_SKCFPUP;
4339 b43_hf_write(dev, hf);
4340
4341 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4342 B43_DEFAULT_LONG_RETRY_LIMIT);
4343 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4344 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4345
4346 /* Disable sending probe responses from firmware.
4347 * Setting the MaxTime to one usec will always trigger
4348 * a timeout, so we never send any probe resp.
4349 * A timeout of zero is infinite. */
4350 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4351
4352 b43_rate_memory_init(dev);
4353 b43_set_phytxctl_defaults(dev);
4354
4355 /* Minimum Contention Window */
4356 if (phy->type == B43_PHYTYPE_B) {
4357 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4358 } else {
4359 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4360 }
4361 /* Maximum Contention Window */
4362 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4363
4364 if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) ||
4365 (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) ||
4366 dev->use_pio) {
4367 dev->__using_pio_transfers = 1;
4368 err = b43_pio_init(dev);
4369 } else {
4370 dev->__using_pio_transfers = 0;
4371 err = b43_dma_init(dev);
4372 }
4373 if (err)
4374 goto err_chip_exit;
4375 b43_qos_init(dev);
4376 b43_set_synth_pu_delay(dev, 1);
4377 b43_bluetooth_coext_enable(dev);
4378
4379 ssb_bus_powerup(bus, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4380 b43_upload_card_macaddress(dev);
4381 b43_security_init(dev);
4382
4383 ieee80211_wake_queues(dev->wl->hw);
4384
4385 b43_set_status(dev, B43_STAT_INITIALIZED);
4386
4387 out:
4388 return err;
4389
4390 err_chip_exit:
4391 b43_chip_exit(dev);
4392 err_busdown:
4393 ssb_bus_may_powerdown(bus);
4394 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4395 return err;
4396 }
4397
4398 static int b43_op_add_interface(struct ieee80211_hw *hw,
4399 struct ieee80211_if_init_conf *conf)
4400 {
4401 struct b43_wl *wl = hw_to_b43_wl(hw);
4402 struct b43_wldev *dev;
4403 int err = -EOPNOTSUPP;
4404
4405 /* TODO: allow WDS/AP devices to coexist */
4406
4407 if (conf->type != NL80211_IFTYPE_AP &&
4408 conf->type != NL80211_IFTYPE_MESH_POINT &&
4409 conf->type != NL80211_IFTYPE_STATION &&
4410 conf->type != NL80211_IFTYPE_WDS &&
4411 conf->type != NL80211_IFTYPE_ADHOC)
4412 return -EOPNOTSUPP;
4413
4414 mutex_lock(&wl->mutex);
4415 if (wl->operating)
4416 goto out_mutex_unlock;
4417
4418 b43dbg(wl, "Adding Interface type %d\n", conf->type);
4419
4420 dev = wl->current_dev;
4421 wl->operating = 1;
4422 wl->vif = conf->vif;
4423 wl->if_type = conf->type;
4424 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
4425
4426 b43_adjust_opmode(dev);
4427 b43_set_pretbtt(dev);
4428 b43_set_synth_pu_delay(dev, 0);
4429 b43_upload_card_macaddress(dev);
4430
4431 err = 0;
4432 out_mutex_unlock:
4433 mutex_unlock(&wl->mutex);
4434
4435 return err;
4436 }
4437
4438 static void b43_op_remove_interface(struct ieee80211_hw *hw,
4439 struct ieee80211_if_init_conf *conf)
4440 {
4441 struct b43_wl *wl = hw_to_b43_wl(hw);
4442 struct b43_wldev *dev = wl->current_dev;
4443
4444 b43dbg(wl, "Removing Interface type %d\n", conf->type);
4445
4446 mutex_lock(&wl->mutex);
4447
4448 B43_WARN_ON(!wl->operating);
4449 B43_WARN_ON(wl->vif != conf->vif);
4450 wl->vif = NULL;
4451
4452 wl->operating = 0;
4453
4454 b43_adjust_opmode(dev);
4455 memset(wl->mac_addr, 0, ETH_ALEN);
4456 b43_upload_card_macaddress(dev);
4457
4458 mutex_unlock(&wl->mutex);
4459 }
4460
4461 static int b43_op_start(struct ieee80211_hw *hw)
4462 {
4463 struct b43_wl *wl = hw_to_b43_wl(hw);
4464 struct b43_wldev *dev = wl->current_dev;
4465 int did_init = 0;
4466 int err = 0;
4467
4468 /* Kill all old instance specific information to make sure
4469 * the card won't use it in the short timeframe between start
4470 * and mac80211 reconfiguring it. */
4471 memset(wl->bssid, 0, ETH_ALEN);
4472 memset(wl->mac_addr, 0, ETH_ALEN);
4473 wl->filter_flags = 0;
4474 wl->radiotap_enabled = 0;
4475 b43_qos_clear(wl);
4476 wl->beacon0_uploaded = 0;
4477 wl->beacon1_uploaded = 0;
4478 wl->beacon_templates_virgin = 1;
4479 wl->radio_enabled = 1;
4480
4481 mutex_lock(&wl->mutex);
4482
4483 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4484 err = b43_wireless_core_init(dev);
4485 if (err)
4486 goto out_mutex_unlock;
4487 did_init = 1;
4488 }
4489
4490 if (b43_status(dev) < B43_STAT_STARTED) {
4491 err = b43_wireless_core_start(dev);
4492 if (err) {
4493 if (did_init)
4494 b43_wireless_core_exit(dev);
4495 goto out_mutex_unlock;
4496 }
4497 }
4498
4499 /* XXX: only do if device doesn't support rfkill irq */
4500 wiphy_rfkill_start_polling(hw->wiphy);
4501
4502 out_mutex_unlock:
4503 mutex_unlock(&wl->mutex);
4504
4505 return err;
4506 }
4507
4508 static void b43_op_stop(struct ieee80211_hw *hw)
4509 {
4510 struct b43_wl *wl = hw_to_b43_wl(hw);
4511 struct b43_wldev *dev = wl->current_dev;
4512
4513 cancel_work_sync(&(wl->beacon_update_trigger));
4514
4515 mutex_lock(&wl->mutex);
4516 if (b43_status(dev) >= B43_STAT_STARTED) {
4517 dev = b43_wireless_core_stop(dev);
4518 if (!dev)
4519 goto out_unlock;
4520 }
4521 b43_wireless_core_exit(dev);
4522 wl->radio_enabled = 0;
4523
4524 out_unlock:
4525 mutex_unlock(&wl->mutex);
4526
4527 cancel_work_sync(&(wl->txpower_adjust_work));
4528 }
4529
4530 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4531 struct ieee80211_sta *sta, bool set)
4532 {
4533 struct b43_wl *wl = hw_to_b43_wl(hw);
4534
4535 /* FIXME: add locking */
4536 b43_update_templates(wl);
4537
4538 return 0;
4539 }
4540
4541 static void b43_op_sta_notify(struct ieee80211_hw *hw,
4542 struct ieee80211_vif *vif,
4543 enum sta_notify_cmd notify_cmd,
4544 struct ieee80211_sta *sta)
4545 {
4546 struct b43_wl *wl = hw_to_b43_wl(hw);
4547
4548 B43_WARN_ON(!vif || wl->vif != vif);
4549 }
4550
4551 static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4552 {
4553 struct b43_wl *wl = hw_to_b43_wl(hw);
4554 struct b43_wldev *dev;
4555
4556 mutex_lock(&wl->mutex);
4557 dev = wl->current_dev;
4558 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4559 /* Disable CFP update during scan on other channels. */
4560 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4561 }
4562 mutex_unlock(&wl->mutex);
4563 }
4564
4565 static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4566 {
4567 struct b43_wl *wl = hw_to_b43_wl(hw);
4568 struct b43_wldev *dev;
4569
4570 mutex_lock(&wl->mutex);
4571 dev = wl->current_dev;
4572 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4573 /* Re-enable CFP update. */
4574 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
4575 }
4576 mutex_unlock(&wl->mutex);
4577 }
4578
4579 static const struct ieee80211_ops b43_hw_ops = {
4580 .tx = b43_op_tx,
4581 .conf_tx = b43_op_conf_tx,
4582 .add_interface = b43_op_add_interface,
4583 .remove_interface = b43_op_remove_interface,
4584 .config = b43_op_config,
4585 .bss_info_changed = b43_op_bss_info_changed,
4586 .configure_filter = b43_op_configure_filter,
4587 .set_key = b43_op_set_key,
4588 .update_tkip_key = b43_op_update_tkip_key,
4589 .get_stats = b43_op_get_stats,
4590 .get_tx_stats = b43_op_get_tx_stats,
4591 .get_tsf = b43_op_get_tsf,
4592 .set_tsf = b43_op_set_tsf,
4593 .start = b43_op_start,
4594 .stop = b43_op_stop,
4595 .set_tim = b43_op_beacon_set_tim,
4596 .sta_notify = b43_op_sta_notify,
4597 .sw_scan_start = b43_op_sw_scan_start_notifier,
4598 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
4599 .rfkill_poll = b43_rfkill_poll,
4600 };
4601
4602 /* Hard-reset the chip. Do not call this directly.
4603 * Use b43_controller_restart()
4604 */
4605 static void b43_chip_reset(struct work_struct *work)
4606 {
4607 struct b43_wldev *dev =
4608 container_of(work, struct b43_wldev, restart_work);
4609 struct b43_wl *wl = dev->wl;
4610 int err = 0;
4611 int prev_status;
4612
4613 mutex_lock(&wl->mutex);
4614
4615 prev_status = b43_status(dev);
4616 /* Bring the device down... */
4617 if (prev_status >= B43_STAT_STARTED) {
4618 dev = b43_wireless_core_stop(dev);
4619 if (!dev) {
4620 err = -ENODEV;
4621 goto out;
4622 }
4623 }
4624 if (prev_status >= B43_STAT_INITIALIZED)
4625 b43_wireless_core_exit(dev);
4626
4627 /* ...and up again. */
4628 if (prev_status >= B43_STAT_INITIALIZED) {
4629 err = b43_wireless_core_init(dev);
4630 if (err)
4631 goto out;
4632 }
4633 if (prev_status >= B43_STAT_STARTED) {
4634 err = b43_wireless_core_start(dev);
4635 if (err) {
4636 b43_wireless_core_exit(dev);
4637 goto out;
4638 }
4639 }
4640 out:
4641 if (err)
4642 wl->current_dev = NULL; /* Failed to init the dev. */
4643 mutex_unlock(&wl->mutex);
4644 if (err)
4645 b43err(wl, "Controller restart FAILED\n");
4646 else
4647 b43info(wl, "Controller restarted\n");
4648 }
4649
4650 static int b43_setup_bands(struct b43_wldev *dev,
4651 bool have_2ghz_phy, bool have_5ghz_phy)
4652 {
4653 struct ieee80211_hw *hw = dev->wl->hw;
4654
4655 if (have_2ghz_phy)
4656 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4657 if (dev->phy.type == B43_PHYTYPE_N) {
4658 if (have_5ghz_phy)
4659 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4660 } else {
4661 if (have_5ghz_phy)
4662 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4663 }
4664
4665 dev->phy.supports_2ghz = have_2ghz_phy;
4666 dev->phy.supports_5ghz = have_5ghz_phy;
4667
4668 return 0;
4669 }
4670
4671 static void b43_wireless_core_detach(struct b43_wldev *dev)
4672 {
4673 /* We release firmware that late to not be required to re-request
4674 * is all the time when we reinit the core. */
4675 b43_release_firmware(dev);
4676 b43_phy_free(dev);
4677 }
4678
4679 static int b43_wireless_core_attach(struct b43_wldev *dev)
4680 {
4681 struct b43_wl *wl = dev->wl;
4682 struct ssb_bus *bus = dev->dev->bus;
4683 struct pci_dev *pdev = bus->host_pci;
4684 int err;
4685 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
4686 u32 tmp;
4687
4688 /* Do NOT do any device initialization here.
4689 * Do it in wireless_core_init() instead.
4690 * This function is for gathering basic information about the HW, only.
4691 * Also some structs may be set up here. But most likely you want to have
4692 * that in core_init(), too.
4693 */
4694
4695 err = ssb_bus_powerup(bus, 0);
4696 if (err) {
4697 b43err(wl, "Bus powerup failed\n");
4698 goto out;
4699 }
4700 /* Get the PHY type. */
4701 if (dev->dev->id.revision >= 5) {
4702 u32 tmshigh;
4703
4704 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
4705 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
4706 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
4707 } else
4708 B43_WARN_ON(1);
4709
4710 dev->phy.gmode = have_2ghz_phy;
4711 dev->phy.radio_on = 1;
4712 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4713 b43_wireless_core_reset(dev, tmp);
4714
4715 err = b43_phy_versioning(dev);
4716 if (err)
4717 goto err_powerdown;
4718 /* Check if this device supports multiband. */
4719 if (!pdev ||
4720 (pdev->device != 0x4312 &&
4721 pdev->device != 0x4319 && pdev->device != 0x4324)) {
4722 /* No multiband support. */
4723 have_2ghz_phy = 0;
4724 have_5ghz_phy = 0;
4725 switch (dev->phy.type) {
4726 case B43_PHYTYPE_A:
4727 have_5ghz_phy = 1;
4728 break;
4729 case B43_PHYTYPE_LP: //FIXME not always!
4730 #if 0 //FIXME enabling 5GHz causes a NULL pointer dereference
4731 have_5ghz_phy = 1;
4732 #endif
4733 case B43_PHYTYPE_G:
4734 case B43_PHYTYPE_N:
4735 have_2ghz_phy = 1;
4736 break;
4737 default:
4738 B43_WARN_ON(1);
4739 }
4740 }
4741 if (dev->phy.type == B43_PHYTYPE_A) {
4742 /* FIXME */
4743 b43err(wl, "IEEE 802.11a devices are unsupported\n");
4744 err = -EOPNOTSUPP;
4745 goto err_powerdown;
4746 }
4747 if (1 /* disable A-PHY */) {
4748 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
4749 if (dev->phy.type != B43_PHYTYPE_N &&
4750 dev->phy.type != B43_PHYTYPE_LP) {
4751 have_2ghz_phy = 1;
4752 have_5ghz_phy = 0;
4753 }
4754 }
4755
4756 err = b43_phy_allocate(dev);
4757 if (err)
4758 goto err_powerdown;
4759
4760 dev->phy.gmode = have_2ghz_phy;
4761 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4762 b43_wireless_core_reset(dev, tmp);
4763
4764 err = b43_validate_chipaccess(dev);
4765 if (err)
4766 goto err_phy_free;
4767 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
4768 if (err)
4769 goto err_phy_free;
4770
4771 /* Now set some default "current_dev" */
4772 if (!wl->current_dev)
4773 wl->current_dev = dev;
4774 INIT_WORK(&dev->restart_work, b43_chip_reset);
4775
4776 dev->phy.ops->switch_analog(dev, 0);
4777 ssb_device_disable(dev->dev, 0);
4778 ssb_bus_may_powerdown(bus);
4779
4780 out:
4781 return err;
4782
4783 err_phy_free:
4784 b43_phy_free(dev);
4785 err_powerdown:
4786 ssb_bus_may_powerdown(bus);
4787 return err;
4788 }
4789
4790 static void b43_one_core_detach(struct ssb_device *dev)
4791 {
4792 struct b43_wldev *wldev;
4793 struct b43_wl *wl;
4794
4795 /* Do not cancel ieee80211-workqueue based work here.
4796 * See comment in b43_remove(). */
4797
4798 wldev = ssb_get_drvdata(dev);
4799 wl = wldev->wl;
4800 b43_debugfs_remove_device(wldev);
4801 b43_wireless_core_detach(wldev);
4802 list_del(&wldev->list);
4803 wl->nr_devs--;
4804 ssb_set_drvdata(dev, NULL);
4805 kfree(wldev);
4806 }
4807
4808 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4809 {
4810 struct b43_wldev *wldev;
4811 struct pci_dev *pdev;
4812 int err = -ENOMEM;
4813
4814 if (!list_empty(&wl->devlist)) {
4815 /* We are not the first core on this chip. */
4816 pdev = dev->bus->host_pci;
4817 /* Only special chips support more than one wireless
4818 * core, although some of the other chips have more than
4819 * one wireless core as well. Check for this and
4820 * bail out early.
4821 */
4822 if (!pdev ||
4823 ((pdev->device != 0x4321) &&
4824 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
4825 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
4826 return -ENODEV;
4827 }
4828 }
4829
4830 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4831 if (!wldev)
4832 goto out;
4833
4834 wldev->use_pio = b43_modparam_pio;
4835 wldev->dev = dev;
4836 wldev->wl = wl;
4837 b43_set_status(wldev, B43_STAT_UNINIT);
4838 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
4839 INIT_LIST_HEAD(&wldev->list);
4840
4841 err = b43_wireless_core_attach(wldev);
4842 if (err)
4843 goto err_kfree_wldev;
4844
4845 list_add(&wldev->list, &wl->devlist);
4846 wl->nr_devs++;
4847 ssb_set_drvdata(dev, wldev);
4848 b43_debugfs_add_device(wldev);
4849
4850 out:
4851 return err;
4852
4853 err_kfree_wldev:
4854 kfree(wldev);
4855 return err;
4856 }
4857
4858 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
4859 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
4860 (pdev->device == _device) && \
4861 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
4862 (pdev->subsystem_device == _subdevice) )
4863
4864 static void b43_sprom_fixup(struct ssb_bus *bus)
4865 {
4866 struct pci_dev *pdev;
4867
4868 /* boardflags workarounds */
4869 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4870 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
4871 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
4872 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4873 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
4874 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
4875 if (bus->bustype == SSB_BUSTYPE_PCI) {
4876 pdev = bus->host_pci;
4877 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
4878 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
4879 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
4880 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
4881 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
4882 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
4883 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
4884 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
4885 }
4886 }
4887
4888 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4889 {
4890 struct ieee80211_hw *hw = wl->hw;
4891
4892 ssb_set_devtypedata(dev, NULL);
4893 ieee80211_free_hw(hw);
4894 }
4895
4896 static int b43_wireless_init(struct ssb_device *dev)
4897 {
4898 struct ssb_sprom *sprom = &dev->bus->sprom;
4899 struct ieee80211_hw *hw;
4900 struct b43_wl *wl;
4901 int err = -ENOMEM;
4902
4903 b43_sprom_fixup(dev->bus);
4904
4905 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4906 if (!hw) {
4907 b43err(NULL, "Could not allocate ieee80211 device\n");
4908 goto out;
4909 }
4910 wl = hw_to_b43_wl(hw);
4911
4912 /* fill hw info */
4913 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
4914 IEEE80211_HW_SIGNAL_DBM |
4915 IEEE80211_HW_NOISE_DBM;
4916
4917 hw->wiphy->interface_modes =
4918 BIT(NL80211_IFTYPE_AP) |
4919 BIT(NL80211_IFTYPE_MESH_POINT) |
4920 BIT(NL80211_IFTYPE_STATION) |
4921 BIT(NL80211_IFTYPE_WDS) |
4922 BIT(NL80211_IFTYPE_ADHOC);
4923
4924 hw->queues = modparam_qos ? 4 : 1;
4925 wl->mac80211_initially_registered_queues = hw->queues;
4926 hw->max_rates = 2;
4927 SET_IEEE80211_DEV(hw, dev->dev);
4928 if (is_valid_ether_addr(sprom->et1mac))
4929 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
4930 else
4931 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
4932
4933 /* Initialize struct b43_wl */
4934 wl->hw = hw;
4935 mutex_init(&wl->mutex);
4936 spin_lock_init(&wl->hardirq_lock);
4937 INIT_LIST_HEAD(&wl->devlist);
4938 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
4939 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
4940 INIT_WORK(&wl->tx_work, b43_tx_work);
4941 skb_queue_head_init(&wl->tx_queue);
4942
4943 ssb_set_devtypedata(dev, wl);
4944 b43info(wl, "Broadcom %04X WLAN found (core revision %u)\n",
4945 dev->bus->chip_id, dev->id.revision);
4946 err = 0;
4947 out:
4948 return err;
4949 }
4950
4951 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4952 {
4953 struct b43_wl *wl;
4954 int err;
4955 int first = 0;
4956
4957 wl = ssb_get_devtypedata(dev);
4958 if (!wl) {
4959 /* Probing the first core. Must setup common struct b43_wl */
4960 first = 1;
4961 err = b43_wireless_init(dev);
4962 if (err)
4963 goto out;
4964 wl = ssb_get_devtypedata(dev);
4965 B43_WARN_ON(!wl);
4966 }
4967 err = b43_one_core_attach(dev, wl);
4968 if (err)
4969 goto err_wireless_exit;
4970
4971 if (first) {
4972 err = ieee80211_register_hw(wl->hw);
4973 if (err)
4974 goto err_one_core_detach;
4975 b43_leds_register(wl->current_dev);
4976 b43_rng_init(wl);
4977 }
4978
4979 out:
4980 return err;
4981
4982 err_one_core_detach:
4983 b43_one_core_detach(dev);
4984 err_wireless_exit:
4985 if (first)
4986 b43_wireless_exit(dev, wl);
4987 return err;
4988 }
4989
4990 static void b43_remove(struct ssb_device *dev)
4991 {
4992 struct b43_wl *wl = ssb_get_devtypedata(dev);
4993 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4994
4995 /* We must cancel any work here before unregistering from ieee80211,
4996 * as the ieee80211 unreg will destroy the workqueue. */
4997 cancel_work_sync(&wldev->restart_work);
4998
4999 B43_WARN_ON(!wl);
5000 if (wl->current_dev == wldev) {
5001 /* Restore the queues count before unregistering, because firmware detect
5002 * might have modified it. Restoring is important, so the networking
5003 * stack can properly free resources. */
5004 wl->hw->queues = wl->mac80211_initially_registered_queues;
5005 b43_leds_stop(wldev);
5006 ieee80211_unregister_hw(wl->hw);
5007 }
5008
5009 b43_one_core_detach(dev);
5010
5011 if (list_empty(&wl->devlist)) {
5012 b43_rng_exit(wl);
5013 b43_leds_unregister(wl);
5014 /* Last core on the chip unregistered.
5015 * We can destroy common struct b43_wl.
5016 */
5017 b43_wireless_exit(dev, wl);
5018 }
5019 }
5020
5021 /* Perform a hardware reset. This can be called from any context. */
5022 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
5023 {
5024 /* Must avoid requeueing, if we are in shutdown. */
5025 if (b43_status(dev) < B43_STAT_INITIALIZED)
5026 return;
5027 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
5028 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
5029 }
5030
5031 static struct ssb_driver b43_ssb_driver = {
5032 .name = KBUILD_MODNAME,
5033 .id_table = b43_ssb_tbl,
5034 .probe = b43_probe,
5035 .remove = b43_remove,
5036 };
5037
5038 static void b43_print_driverinfo(void)
5039 {
5040 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
5041 *feat_leds = "", *feat_sdio = "";
5042
5043 #ifdef CONFIG_B43_PCI_AUTOSELECT
5044 feat_pci = "P";
5045 #endif
5046 #ifdef CONFIG_B43_PCMCIA
5047 feat_pcmcia = "M";
5048 #endif
5049 #ifdef CONFIG_B43_NPHY
5050 feat_nphy = "N";
5051 #endif
5052 #ifdef CONFIG_B43_LEDS
5053 feat_leds = "L";
5054 #endif
5055 #ifdef CONFIG_B43_SDIO
5056 feat_sdio = "S";
5057 #endif
5058 printk(KERN_INFO "Broadcom 43xx driver loaded "
5059 "[ Features: %s%s%s%s%s, Firmware-ID: "
5060 B43_SUPPORTED_FIRMWARE_ID " ]\n",
5061 feat_pci, feat_pcmcia, feat_nphy,
5062 feat_leds, feat_sdio);
5063 }
5064
5065 static int __init b43_init(void)
5066 {
5067 int err;
5068
5069 b43_debugfs_init();
5070 err = b43_pcmcia_init();
5071 if (err)
5072 goto err_dfs_exit;
5073 err = b43_sdio_init();
5074 if (err)
5075 goto err_pcmcia_exit;
5076 err = ssb_driver_register(&b43_ssb_driver);
5077 if (err)
5078 goto err_sdio_exit;
5079 b43_print_driverinfo();
5080
5081 return err;
5082
5083 err_sdio_exit:
5084 b43_sdio_exit();
5085 err_pcmcia_exit:
5086 b43_pcmcia_exit();
5087 err_dfs_exit:
5088 b43_debugfs_exit();
5089 return err;
5090 }
5091
5092 static void __exit b43_exit(void)
5093 {
5094 ssb_driver_unregister(&b43_ssb_driver);
5095 b43_sdio_exit();
5096 b43_pcmcia_exit();
5097 b43_debugfs_exit();
5098 }
5099
5100 module_init(b43_init)
5101 module_exit(b43_exit)
Linux ARM platform port for MOXA ART SoC