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initial commit with v2.6.32.60
[linux-2.6.32.60-moxart.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
blob0e56d78ffc2a714fc1ee24a757138aaef488dd95
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/pci.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/delay.h>
36 #include <linux/sched.h>
37 #include <linux/skbuff.h>
38 #include <linux/netdevice.h>
39 #include <linux/wireless.h>
40 #include <linux/firmware.h>
41 #include <linux/etherdevice.h>
42 #include <linux/if_arp.h>
43
44 #include <net/mac80211.h>
45
46 #include <asm/div64.h>
47
48 #define DRV_NAME "iwlagn"
49
50 #include "iwl-eeprom.h"
51 #include "iwl-dev.h"
52 #include "iwl-core.h"
53 #include "iwl-io.h"
54 #include "iwl-helpers.h"
55 #include "iwl-sta.h"
56 #include "iwl-calib.h"
57
58
59 /******************************************************************************
60 *
61 * module boiler plate
62 *
63 ******************************************************************************/
64
65 /*
66 * module name, copyright, version, etc.
67 */
68 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
69
70 #ifdef CONFIG_IWLWIFI_DEBUG
71 #define VD "d"
72 #else
73 #define VD
74 #endif
75
76 #ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
77 #define VS "s"
78 #else
79 #define VS
80 #endif
81
82 #define DRV_VERSION IWLWIFI_VERSION VD VS
83
84
85 MODULE_DESCRIPTION(DRV_DESCRIPTION);
86 MODULE_VERSION(DRV_VERSION);
87 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
88 MODULE_LICENSE("GPL");
89 MODULE_ALIAS("iwl4965");
90
91 /*************** STATION TABLE MANAGEMENT ****
92 * mac80211 should be examined to determine if sta_info is duplicating
93 * the functionality provided here
94 */
95
96 /**************************************************************/
97
98 /**
99 * iwl_commit_rxon - commit staging_rxon to hardware
100 *
101 * The RXON command in staging_rxon is committed to the hardware and
102 * the active_rxon structure is updated with the new data. This
103 * function correctly transitions out of the RXON_ASSOC_MSK state if
104 * a HW tune is required based on the RXON structure changes.
105 */
106 int iwl_commit_rxon(struct iwl_priv *priv)
107 {
108 /* cast away the const for active_rxon in this function */
109 struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
110 int ret;
111 bool new_assoc =
112 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
113
114 if (!iwl_is_alive(priv))
115 return -EBUSY;
116
117 /* always get timestamp with Rx frame */
118 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
119
120 ret = iwl_check_rxon_cmd(priv);
121 if (ret) {
122 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
123 return -EINVAL;
124 }
125
126 /* If we don't need to send a full RXON, we can use
127 * iwl_rxon_assoc_cmd which is used to reconfigure filter
128 * and other flags for the current radio configuration. */
129 if (!iwl_full_rxon_required(priv)) {
130 ret = iwl_send_rxon_assoc(priv);
131 if (ret) {
132 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
133 return ret;
134 }
135
136 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
137 return 0;
138 }
139
140 /* station table will be cleared */
141 priv->assoc_station_added = 0;
142
143 /* If we are currently associated and the new config requires
144 * an RXON_ASSOC and the new config wants the associated mask enabled,
145 * we must clear the associated from the active configuration
146 * before we apply the new config */
147 if (iwl_is_associated(priv) && new_assoc) {
148 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
149 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
150
151 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
152 sizeof(struct iwl_rxon_cmd),
153 &priv->active_rxon);
154
155 /* If the mask clearing failed then we set
156 * active_rxon back to what it was previously */
157 if (ret) {
158 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
159 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
160 return ret;
161 }
162 }
163
164 IWL_DEBUG_INFO(priv, "Sending RXON\n"
165 "* with%s RXON_FILTER_ASSOC_MSK\n"
166 "* channel = %d\n"
167 "* bssid = %pM\n",
168 (new_assoc ? "" : "out"),
169 le16_to_cpu(priv->staging_rxon.channel),
170 priv->staging_rxon.bssid_addr);
171
172 iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
173
174 /* Apply the new configuration
175 * RXON unassoc clears the station table in uCode, send it before
176 * we add the bcast station. If assoc bit is set, we will send RXON
177 * after having added the bcast and bssid station.
178 */
179 if (!new_assoc) {
180 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
181 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
182 if (ret) {
183 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
184 return ret;
185 }
186 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
187 }
188
189 iwl_clear_stations_table(priv);
190
191 priv->start_calib = 0;
192
193 /* Add the broadcast address so we can send broadcast frames */
194 if (iwl_rxon_add_station(priv, iwl_bcast_addr, 0) ==
195 IWL_INVALID_STATION) {
196 IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
197 return -EIO;
198 }
199
200 /* If we have set the ASSOC_MSK and we are in BSS mode then
201 * add the IWL_AP_ID to the station rate table */
202 if (new_assoc) {
203 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
204 ret = iwl_rxon_add_station(priv,
205 priv->active_rxon.bssid_addr, 1);
206 if (ret == IWL_INVALID_STATION) {
207 IWL_ERR(priv,
208 "Error adding AP address for TX.\n");
209 return -EIO;
210 }
211 priv->assoc_station_added = 1;
212 if (priv->default_wep_key &&
213 iwl_send_static_wepkey_cmd(priv, 0))
214 IWL_ERR(priv,
215 "Could not send WEP static key.\n");
216 }
217
218 /*
219 * allow CTS-to-self if possible for new association.
220 * this is relevant only for 5000 series and up,
221 * but will not damage 4965
222 */
223 priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
224
225 /* Apply the new configuration
226 * RXON assoc doesn't clear the station table in uCode,
227 */
228 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
229 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
230 if (ret) {
231 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
232 return ret;
233 }
234 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
235 }
236
237 iwl_init_sensitivity(priv);
238
239 /* If we issue a new RXON command which required a tune then we must
240 * send a new TXPOWER command or we won't be able to Tx any frames */
241 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
242 if (ret) {
243 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
244 return ret;
245 }
246
247 return 0;
248 }
249
250 void iwl_update_chain_flags(struct iwl_priv *priv)
251 {
252
253 if (priv->cfg->ops->hcmd->set_rxon_chain)
254 priv->cfg->ops->hcmd->set_rxon_chain(priv);
255 iwlcore_commit_rxon(priv);
256 }
257
258 static void iwl_clear_free_frames(struct iwl_priv *priv)
259 {
260 struct list_head *element;
261
262 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
263 priv->frames_count);
264
265 while (!list_empty(&priv->free_frames)) {
266 element = priv->free_frames.next;
267 list_del(element);
268 kfree(list_entry(element, struct iwl_frame, list));
269 priv->frames_count--;
270 }
271
272 if (priv->frames_count) {
273 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
274 priv->frames_count);
275 priv->frames_count = 0;
276 }
277 }
278
279 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
280 {
281 struct iwl_frame *frame;
282 struct list_head *element;
283 if (list_empty(&priv->free_frames)) {
284 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
285 if (!frame) {
286 IWL_ERR(priv, "Could not allocate frame!\n");
287 return NULL;
288 }
289
290 priv->frames_count++;
291 return frame;
292 }
293
294 element = priv->free_frames.next;
295 list_del(element);
296 return list_entry(element, struct iwl_frame, list);
297 }
298
299 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
300 {
301 memset(frame, 0, sizeof(*frame));
302 list_add(&frame->list, &priv->free_frames);
303 }
304
305 static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv,
306 struct ieee80211_hdr *hdr,
307 int left)
308 {
309 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
310 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
311 (priv->iw_mode != NL80211_IFTYPE_AP)))
312 return 0;
313
314 if (priv->ibss_beacon->len > left)
315 return 0;
316
317 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
318
319 return priv->ibss_beacon->len;
320 }
321
322 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
323 struct iwl_frame *frame, u8 rate)
324 {
325 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
326 unsigned int frame_size;
327
328 tx_beacon_cmd = &frame->u.beacon;
329 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
330
331 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
332 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
333
334 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
335 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
336
337 BUG_ON(frame_size > MAX_MPDU_SIZE);
338 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
339
340 if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
341 tx_beacon_cmd->tx.rate_n_flags =
342 iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
343 else
344 tx_beacon_cmd->tx.rate_n_flags =
345 iwl_hw_set_rate_n_flags(rate, 0);
346
347 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
348 TX_CMD_FLG_TSF_MSK |
349 TX_CMD_FLG_STA_RATE_MSK;
350
351 return sizeof(*tx_beacon_cmd) + frame_size;
352 }
353 static int iwl_send_beacon_cmd(struct iwl_priv *priv)
354 {
355 struct iwl_frame *frame;
356 unsigned int frame_size;
357 int rc;
358 u8 rate;
359
360 frame = iwl_get_free_frame(priv);
361
362 if (!frame) {
363 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
364 "command.\n");
365 return -ENOMEM;
366 }
367
368 rate = iwl_rate_get_lowest_plcp(priv);
369
370 frame_size = iwl_hw_get_beacon_cmd(priv, frame, rate);
371
372 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
373 &frame->u.cmd[0]);
374
375 iwl_free_frame(priv, frame);
376
377 return rc;
378 }
379
380 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
381 {
382 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
383
384 dma_addr_t addr = get_unaligned_le32(&tb->lo);
385 if (sizeof(dma_addr_t) > sizeof(u32))
386 addr |=
387 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
388
389 return addr;
390 }
391
392 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
393 {
394 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
395
396 return le16_to_cpu(tb->hi_n_len) >> 4;
397 }
398
399 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
400 dma_addr_t addr, u16 len)
401 {
402 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
403 u16 hi_n_len = len << 4;
404
405 put_unaligned_le32(addr, &tb->lo);
406 if (sizeof(dma_addr_t) > sizeof(u32))
407 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
408
409 tb->hi_n_len = cpu_to_le16(hi_n_len);
410
411 tfd->num_tbs = idx + 1;
412 }
413
414 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
415 {
416 return tfd->num_tbs & 0x1f;
417 }
418
419 /**
420 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
421 * @priv - driver private data
422 * @txq - tx queue
423 *
424 * Does NOT advance any TFD circular buffer read/write indexes
425 * Does NOT free the TFD itself (which is within circular buffer)
426 */
427 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
428 {
429 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
430 struct iwl_tfd *tfd;
431 struct pci_dev *dev = priv->pci_dev;
432 int index = txq->q.read_ptr;
433 int i;
434 int num_tbs;
435
436 tfd = &tfd_tmp[index];
437
438 /* Sanity check on number of chunks */
439 num_tbs = iwl_tfd_get_num_tbs(tfd);
440
441 if (num_tbs >= IWL_NUM_OF_TBS) {
442 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
443 /* @todo issue fatal error, it is quite serious situation */
444 return;
445 }
446
447 /* Unmap tx_cmd */
448 if (num_tbs)
449 pci_unmap_single(dev,
450 pci_unmap_addr(&txq->meta[index], mapping),
451 pci_unmap_len(&txq->meta[index], len),
452 PCI_DMA_BIDIRECTIONAL);
453
454 /* Unmap chunks, if any. */
455 for (i = 1; i < num_tbs; i++) {
456 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
457 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
458
459 if (txq->txb) {
460 dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
461 txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
462 }
463 }
464 }
465
466 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
467 struct iwl_tx_queue *txq,
468 dma_addr_t addr, u16 len,
469 u8 reset, u8 pad)
470 {
471 struct iwl_queue *q;
472 struct iwl_tfd *tfd, *tfd_tmp;
473 u32 num_tbs;
474
475 q = &txq->q;
476 tfd_tmp = (struct iwl_tfd *)txq->tfds;
477 tfd = &tfd_tmp[q->write_ptr];
478
479 if (reset)
480 memset(tfd, 0, sizeof(*tfd));
481
482 num_tbs = iwl_tfd_get_num_tbs(tfd);
483
484 /* Each TFD can point to a maximum 20 Tx buffers */
485 if (num_tbs >= IWL_NUM_OF_TBS) {
486 IWL_ERR(priv, "Error can not send more than %d chunks\n",
487 IWL_NUM_OF_TBS);
488 return -EINVAL;
489 }
490
491 BUG_ON(addr & ~DMA_BIT_MASK(36));
492 if (unlikely(addr & ~IWL_TX_DMA_MASK))
493 IWL_ERR(priv, "Unaligned address = %llx\n",
494 (unsigned long long)addr);
495
496 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
497
498 return 0;
499 }
500
501 /*
502 * Tell nic where to find circular buffer of Tx Frame Descriptors for
503 * given Tx queue, and enable the DMA channel used for that queue.
504 *
505 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
506 * channels supported in hardware.
507 */
508 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
509 struct iwl_tx_queue *txq)
510 {
511 int txq_id = txq->q.id;
512
513 /* Circular buffer (TFD queue in DRAM) physical base address */
514 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
515 txq->q.dma_addr >> 8);
516
517 return 0;
518 }
519
520 /******************************************************************************
521 *
522 * Generic RX handler implementations
523 *
524 ******************************************************************************/
525 static void iwl_rx_reply_alive(struct iwl_priv *priv,
526 struct iwl_rx_mem_buffer *rxb)
527 {
528 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
529 struct iwl_alive_resp *palive;
530 struct delayed_work *pwork;
531
532 palive = &pkt->u.alive_frame;
533
534 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
535 "0x%01X 0x%01X\n",
536 palive->is_valid, palive->ver_type,
537 palive->ver_subtype);
538
539 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
540 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
541 memcpy(&priv->card_alive_init,
542 &pkt->u.alive_frame,
543 sizeof(struct iwl_init_alive_resp));
544 pwork = &priv->init_alive_start;
545 } else {
546 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
547 memcpy(&priv->card_alive, &pkt->u.alive_frame,
548 sizeof(struct iwl_alive_resp));
549 pwork = &priv->alive_start;
550 }
551
552 /* We delay the ALIVE response by 5ms to
553 * give the HW RF Kill time to activate... */
554 if (palive->is_valid == UCODE_VALID_OK)
555 queue_delayed_work(priv->workqueue, pwork,
556 msecs_to_jiffies(5));
557 else
558 IWL_WARN(priv, "uCode did not respond OK.\n");
559 }
560
561 static void iwl_bg_beacon_update(struct work_struct *work)
562 {
563 struct iwl_priv *priv =
564 container_of(work, struct iwl_priv, beacon_update);
565 struct sk_buff *beacon;
566
567 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
568 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
569
570 if (!beacon) {
571 IWL_ERR(priv, "update beacon failed\n");
572 return;
573 }
574
575 mutex_lock(&priv->mutex);
576 /* new beacon skb is allocated every time; dispose previous.*/
577 if (priv->ibss_beacon)
578 dev_kfree_skb(priv->ibss_beacon);
579
580 priv->ibss_beacon = beacon;
581 mutex_unlock(&priv->mutex);
582
583 iwl_send_beacon_cmd(priv);
584 }
585
586 /**
587 * iwl_bg_statistics_periodic - Timer callback to queue statistics
588 *
589 * This callback is provided in order to send a statistics request.
590 *
591 * This timer function is continually reset to execute within
592 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
593 * was received. We need to ensure we receive the statistics in order
594 * to update the temperature used for calibrating the TXPOWER.
595 */
596 static void iwl_bg_statistics_periodic(unsigned long data)
597 {
598 struct iwl_priv *priv = (struct iwl_priv *)data;
599
600 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
601 return;
602
603 /* dont send host command if rf-kill is on */
604 if (!iwl_is_ready_rf(priv))
605 return;
606
607 iwl_send_statistics_request(priv, CMD_ASYNC);
608 }
609
610 static void iwl_rx_beacon_notif(struct iwl_priv *priv,
611 struct iwl_rx_mem_buffer *rxb)
612 {
613 #ifdef CONFIG_IWLWIFI_DEBUG
614 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
615 struct iwl4965_beacon_notif *beacon =
616 (struct iwl4965_beacon_notif *)pkt->u.raw;
617 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
618
619 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
620 "tsf %d %d rate %d\n",
621 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
622 beacon->beacon_notify_hdr.failure_frame,
623 le32_to_cpu(beacon->ibss_mgr_status),
624 le32_to_cpu(beacon->high_tsf),
625 le32_to_cpu(beacon->low_tsf), rate);
626 #endif
627
628 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
629 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
630 queue_work(priv->workqueue, &priv->beacon_update);
631 }
632
633 /* Handle notification from uCode that card's power state is changing
634 * due to software, hardware, or critical temperature RFKILL */
635 static void iwl_rx_card_state_notif(struct iwl_priv *priv,
636 struct iwl_rx_mem_buffer *rxb)
637 {
638 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
639 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
640 unsigned long status = priv->status;
641
642 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
643 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
644 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
645
646 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
647 RF_CARD_DISABLED)) {
648
649 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
650 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
651
652 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
653 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
654
655 if (!(flags & RXON_CARD_DISABLED)) {
656 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
657 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
658 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
659 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
660 }
661 if (flags & RF_CARD_DISABLED)
662 iwl_tt_enter_ct_kill(priv);
663 }
664 if (!(flags & RF_CARD_DISABLED))
665 iwl_tt_exit_ct_kill(priv);
666
667 if (flags & HW_CARD_DISABLED)
668 set_bit(STATUS_RF_KILL_HW, &priv->status);
669 else
670 clear_bit(STATUS_RF_KILL_HW, &priv->status);
671
672
673 if (!(flags & RXON_CARD_DISABLED))
674 iwl_scan_cancel(priv);
675
676 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
677 test_bit(STATUS_RF_KILL_HW, &priv->status)))
678 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
679 test_bit(STATUS_RF_KILL_HW, &priv->status));
680 else
681 wake_up_interruptible(&priv->wait_command_queue);
682 }
683
684 int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
685 {
686 if (src == IWL_PWR_SRC_VAUX) {
687 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
688 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
689 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
690 ~APMG_PS_CTRL_MSK_PWR_SRC);
691 } else {
692 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
693 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
694 ~APMG_PS_CTRL_MSK_PWR_SRC);
695 }
696
697 return 0;
698 }
699
700 /**
701 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
702 *
703 * Setup the RX handlers for each of the reply types sent from the uCode
704 * to the host.
705 *
706 * This function chains into the hardware specific files for them to setup
707 * any hardware specific handlers as well.
708 */
709 static void iwl_setup_rx_handlers(struct iwl_priv *priv)
710 {
711 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
712 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
713 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
714 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
715 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
716 iwl_rx_pm_debug_statistics_notif;
717 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
718
719 /*
720 * The same handler is used for both the REPLY to a discrete
721 * statistics request from the host as well as for the periodic
722 * statistics notifications (after received beacons) from the uCode.
723 */
724 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics;
725 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
726
727 iwl_setup_spectrum_handlers(priv);
728 iwl_setup_rx_scan_handlers(priv);
729
730 /* status change handler */
731 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
732
733 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
734 iwl_rx_missed_beacon_notif;
735 /* Rx handlers */
736 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
737 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
738 /* block ack */
739 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
740 /* Set up hardware specific Rx handlers */
741 priv->cfg->ops->lib->rx_handler_setup(priv);
742 }
743
744 /**
745 * iwl_rx_handle - Main entry function for receiving responses from uCode
746 *
747 * Uses the priv->rx_handlers callback function array to invoke
748 * the appropriate handlers, including command responses,
749 * frame-received notifications, and other notifications.
750 */
751 void iwl_rx_handle(struct iwl_priv *priv)
752 {
753 struct iwl_rx_mem_buffer *rxb;
754 struct iwl_rx_packet *pkt;
755 struct iwl_rx_queue *rxq = &priv->rxq;
756 u32 r, i;
757 int reclaim;
758 unsigned long flags;
759 u8 fill_rx = 0;
760 u32 count = 8;
761 int total_empty;
762
763 /* uCode's read index (stored in shared DRAM) indicates the last Rx
764 * buffer that the driver may process (last buffer filled by ucode). */
765 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
766 i = rxq->read;
767
768 /* Rx interrupt, but nothing sent from uCode */
769 if (i == r)
770 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
771
772 /* calculate total frames need to be restock after handling RX */
773 total_empty = r - priv->rxq.write_actual;
774 if (total_empty < 0)
775 total_empty += RX_QUEUE_SIZE;
776
777 if (total_empty > (RX_QUEUE_SIZE / 2))
778 fill_rx = 1;
779
780 while (i != r) {
781 rxb = rxq->queue[i];
782
783 /* If an RXB doesn't have a Rx queue slot associated with it,
784 * then a bug has been introduced in the queue refilling
785 * routines -- catch it here */
786 BUG_ON(rxb == NULL);
787
788 rxq->queue[i] = NULL;
789
790 pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
791 priv->hw_params.rx_buf_size + 256,
792 PCI_DMA_FROMDEVICE);
793 pkt = (struct iwl_rx_packet *)rxb->skb->data;
794
795 /* Reclaim a command buffer only if this packet is a response
796 * to a (driver-originated) command.
797 * If the packet (e.g. Rx frame) originated from uCode,
798 * there is no command buffer to reclaim.
799 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
800 * but apparently a few don't get set; catch them here. */
801 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
802 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
803 (pkt->hdr.cmd != REPLY_RX) &&
804 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
805 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
806 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
807 (pkt->hdr.cmd != REPLY_TX);
808
809 /* Based on type of command response or notification,
810 * handle those that need handling via function in
811 * rx_handlers table. See iwl_setup_rx_handlers() */
812 if (priv->rx_handlers[pkt->hdr.cmd]) {
813 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
814 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
815 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
816 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
817 } else {
818 /* No handling needed */
819 IWL_DEBUG_RX(priv,
820 "r %d i %d No handler needed for %s, 0x%02x\n",
821 r, i, get_cmd_string(pkt->hdr.cmd),
822 pkt->hdr.cmd);
823 }
824
825 if (reclaim) {
826 /* Invoke any callbacks, transfer the skb to caller, and
827 * fire off the (possibly) blocking iwl_send_cmd()
828 * as we reclaim the driver command queue */
829 if (rxb && rxb->skb)
830 iwl_tx_cmd_complete(priv, rxb);
831 else
832 IWL_WARN(priv, "Claim null rxb?\n");
833 }
834
835 /* For now we just don't re-use anything. We can tweak this
836 * later to try and re-use notification packets and SKBs that
837 * fail to Rx correctly */
838 if (rxb->skb != NULL) {
839 priv->alloc_rxb_skb--;
840 dev_kfree_skb_any(rxb->skb);
841 rxb->skb = NULL;
842 }
843
844 spin_lock_irqsave(&rxq->lock, flags);
845 list_add_tail(&rxb->list, &priv->rxq.rx_used);
846 spin_unlock_irqrestore(&rxq->lock, flags);
847 i = (i + 1) & RX_QUEUE_MASK;
848 /* If there are a lot of unused frames,
849 * restock the Rx queue so ucode wont assert. */
850 if (fill_rx) {
851 count++;
852 if (count >= 8) {
853 priv->rxq.read = i;
854 iwl_rx_replenish_now(priv);
855 count = 0;
856 }
857 }
858 }
859
860 /* Backtrack one entry */
861 priv->rxq.read = i;
862 if (fill_rx)
863 iwl_rx_replenish_now(priv);
864 else
865 iwl_rx_queue_restock(priv);
866 }
867
868 /* call this function to flush any scheduled tasklet */
869 static inline void iwl_synchronize_irq(struct iwl_priv *priv)
870 {
871 /* wait to make sure we flush pending tasklet*/
872 synchronize_irq(priv->pci_dev->irq);
873 tasklet_kill(&priv->irq_tasklet);
874 }
875
876 static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
877 {
878 u32 inta, handled = 0;
879 u32 inta_fh;
880 unsigned long flags;
881 #ifdef CONFIG_IWLWIFI_DEBUG
882 u32 inta_mask;
883 #endif
884
885 spin_lock_irqsave(&priv->lock, flags);
886
887 /* Ack/clear/reset pending uCode interrupts.
888 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
889 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
890 inta = iwl_read32(priv, CSR_INT);
891 iwl_write32(priv, CSR_INT, inta);
892
893 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
894 * Any new interrupts that happen after this, either while we're
895 * in this tasklet, or later, will show up in next ISR/tasklet. */
896 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
897 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
898
899 #ifdef CONFIG_IWLWIFI_DEBUG
900 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
901 /* just for debug */
902 inta_mask = iwl_read32(priv, CSR_INT_MASK);
903 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
904 inta, inta_mask, inta_fh);
905 }
906 #endif
907
908 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
909 * atomic, make sure that inta covers all the interrupts that
910 * we've discovered, even if FH interrupt came in just after
911 * reading CSR_INT. */
912 if (inta_fh & CSR49_FH_INT_RX_MASK)
913 inta |= CSR_INT_BIT_FH_RX;
914 if (inta_fh & CSR49_FH_INT_TX_MASK)
915 inta |= CSR_INT_BIT_FH_TX;
916
917 /* Now service all interrupt bits discovered above. */
918 if (inta & CSR_INT_BIT_HW_ERR) {
919 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
920
921 /* Tell the device to stop sending interrupts */
922 iwl_disable_interrupts(priv);
923
924 priv->isr_stats.hw++;
925 iwl_irq_handle_error(priv);
926
927 handled |= CSR_INT_BIT_HW_ERR;
928
929 spin_unlock_irqrestore(&priv->lock, flags);
930
931 return;
932 }
933
934 #ifdef CONFIG_IWLWIFI_DEBUG
935 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
936 /* NIC fires this, but we don't use it, redundant with WAKEUP */
937 if (inta & CSR_INT_BIT_SCD) {
938 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
939 "the frame/frames.\n");
940 priv->isr_stats.sch++;
941 }
942
943 /* Alive notification via Rx interrupt will do the real work */
944 if (inta & CSR_INT_BIT_ALIVE) {
945 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
946 priv->isr_stats.alive++;
947 }
948 }
949 #endif
950 /* Safely ignore these bits for debug checks below */
951 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
952
953 /* HW RF KILL switch toggled */
954 if (inta & CSR_INT_BIT_RF_KILL) {
955 int hw_rf_kill = 0;
956 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
957 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
958 hw_rf_kill = 1;
959
960 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
961 hw_rf_kill ? "disable radio" : "enable radio");
962
963 priv->isr_stats.rfkill++;
964
965 /* driver only loads ucode once setting the interface up.
966 * the driver allows loading the ucode even if the radio
967 * is killed. Hence update the killswitch state here. The
968 * rfkill handler will care about restarting if needed.
969 */
970 if (!test_bit(STATUS_ALIVE, &priv->status)) {
971 if (hw_rf_kill)
972 set_bit(STATUS_RF_KILL_HW, &priv->status);
973 else
974 clear_bit(STATUS_RF_KILL_HW, &priv->status);
975 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
976 }
977
978 handled |= CSR_INT_BIT_RF_KILL;
979 }
980
981 /* Chip got too hot and stopped itself */
982 if (inta & CSR_INT_BIT_CT_KILL) {
983 IWL_ERR(priv, "Microcode CT kill error detected.\n");
984 priv->isr_stats.ctkill++;
985 handled |= CSR_INT_BIT_CT_KILL;
986 }
987
988 /* Error detected by uCode */
989 if (inta & CSR_INT_BIT_SW_ERR) {
990 IWL_ERR(priv, "Microcode SW error detected. "
991 " Restarting 0x%X.\n", inta);
992 priv->isr_stats.sw++;
993 priv->isr_stats.sw_err = inta;
994 iwl_irq_handle_error(priv);
995 handled |= CSR_INT_BIT_SW_ERR;
996 }
997
998 /* uCode wakes up after power-down sleep */
999 if (inta & CSR_INT_BIT_WAKEUP) {
1000 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1001 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1002 iwl_txq_update_write_ptr(priv, &priv->txq[0]);
1003 iwl_txq_update_write_ptr(priv, &priv->txq[1]);
1004 iwl_txq_update_write_ptr(priv, &priv->txq[2]);
1005 iwl_txq_update_write_ptr(priv, &priv->txq[3]);
1006 iwl_txq_update_write_ptr(priv, &priv->txq[4]);
1007 iwl_txq_update_write_ptr(priv, &priv->txq[5]);
1008
1009 priv->isr_stats.wakeup++;
1010
1011 handled |= CSR_INT_BIT_WAKEUP;
1012 }
1013
1014 /* All uCode command responses, including Tx command responses,
1015 * Rx "responses" (frame-received notification), and other
1016 * notifications from uCode come through here*/
1017 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1018 iwl_rx_handle(priv);
1019 priv->isr_stats.rx++;
1020 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1021 }
1022
1023 if (inta & CSR_INT_BIT_FH_TX) {
1024 IWL_DEBUG_ISR(priv, "Tx interrupt\n");
1025 priv->isr_stats.tx++;
1026 handled |= CSR_INT_BIT_FH_TX;
1027 /* FH finished to write, send event */
1028 priv->ucode_write_complete = 1;
1029 wake_up_interruptible(&priv->wait_command_queue);
1030 }
1031
1032 if (inta & ~handled) {
1033 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1034 priv->isr_stats.unhandled++;
1035 }
1036
1037 if (inta & ~(priv->inta_mask)) {
1038 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1039 inta & ~priv->inta_mask);
1040 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
1041 }
1042
1043 /* Re-enable all interrupts */
1044 /* only Re-enable if diabled by irq */
1045 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1046 iwl_enable_interrupts(priv);
1047 /* Re-enable RF_KILL if it occurred */
1048 else if (handled & CSR_INT_BIT_RF_KILL)
1049 iwl_enable_rfkill_int(priv);
1050
1051 #ifdef CONFIG_IWLWIFI_DEBUG
1052 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1053 inta = iwl_read32(priv, CSR_INT);
1054 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1055 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1056 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
1057 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1058 }
1059 #endif
1060 spin_unlock_irqrestore(&priv->lock, flags);
1061 }
1062
1063 /* tasklet for iwlagn interrupt */
1064 static void iwl_irq_tasklet(struct iwl_priv *priv)
1065 {
1066 u32 inta = 0;
1067 u32 handled = 0;
1068 unsigned long flags;
1069 #ifdef CONFIG_IWLWIFI_DEBUG
1070 u32 inta_mask;
1071 #endif
1072
1073 spin_lock_irqsave(&priv->lock, flags);
1074
1075 /* Ack/clear/reset pending uCode interrupts.
1076 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1077 */
1078 iwl_write32(priv, CSR_INT, priv->inta);
1079
1080 inta = priv->inta;
1081
1082 #ifdef CONFIG_IWLWIFI_DEBUG
1083 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1084 /* just for debug */
1085 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1086 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1087 inta, inta_mask);
1088 }
1089 #endif
1090 /* saved interrupt in inta variable now we can reset priv->inta */
1091 priv->inta = 0;
1092
1093 /* Now service all interrupt bits discovered above. */
1094 if (inta & CSR_INT_BIT_HW_ERR) {
1095 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
1096
1097 /* Tell the device to stop sending interrupts */
1098 iwl_disable_interrupts(priv);
1099
1100 priv->isr_stats.hw++;
1101 iwl_irq_handle_error(priv);
1102
1103 handled |= CSR_INT_BIT_HW_ERR;
1104
1105 spin_unlock_irqrestore(&priv->lock, flags);
1106
1107 return;
1108 }
1109
1110 #ifdef CONFIG_IWLWIFI_DEBUG
1111 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1112 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1113 if (inta & CSR_INT_BIT_SCD) {
1114 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1115 "the frame/frames.\n");
1116 priv->isr_stats.sch++;
1117 }
1118
1119 /* Alive notification via Rx interrupt will do the real work */
1120 if (inta & CSR_INT_BIT_ALIVE) {
1121 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1122 priv->isr_stats.alive++;
1123 }
1124 }
1125 #endif
1126 /* Safely ignore these bits for debug checks below */
1127 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1128
1129 /* HW RF KILL switch toggled */
1130 if (inta & CSR_INT_BIT_RF_KILL) {
1131 int hw_rf_kill = 0;
1132 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1133 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1134 hw_rf_kill = 1;
1135
1136 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1137 hw_rf_kill ? "disable radio" : "enable radio");
1138
1139 priv->isr_stats.rfkill++;
1140
1141 /* driver only loads ucode once setting the interface up.
1142 * the driver allows loading the ucode even if the radio
1143 * is killed. Hence update the killswitch state here. The
1144 * rfkill handler will care about restarting if needed.
1145 */
1146 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1147 if (hw_rf_kill)
1148 set_bit(STATUS_RF_KILL_HW, &priv->status);
1149 else
1150 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1151 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1152 }
1153
1154 handled |= CSR_INT_BIT_RF_KILL;
1155 }
1156
1157 /* Chip got too hot and stopped itself */
1158 if (inta & CSR_INT_BIT_CT_KILL) {
1159 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1160 priv->isr_stats.ctkill++;
1161 handled |= CSR_INT_BIT_CT_KILL;
1162 }
1163
1164 /* Error detected by uCode */
1165 if (inta & CSR_INT_BIT_SW_ERR) {
1166 IWL_ERR(priv, "Microcode SW error detected. "
1167 " Restarting 0x%X.\n", inta);
1168 priv->isr_stats.sw++;
1169 priv->isr_stats.sw_err = inta;
1170 iwl_irq_handle_error(priv);
1171 handled |= CSR_INT_BIT_SW_ERR;
1172 }
1173
1174 /* uCode wakes up after power-down sleep */
1175 if (inta & CSR_INT_BIT_WAKEUP) {
1176 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1177 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1178 iwl_txq_update_write_ptr(priv, &priv->txq[0]);
1179 iwl_txq_update_write_ptr(priv, &priv->txq[1]);
1180 iwl_txq_update_write_ptr(priv, &priv->txq[2]);
1181 iwl_txq_update_write_ptr(priv, &priv->txq[3]);
1182 iwl_txq_update_write_ptr(priv, &priv->txq[4]);
1183 iwl_txq_update_write_ptr(priv, &priv->txq[5]);
1184
1185 priv->isr_stats.wakeup++;
1186
1187 handled |= CSR_INT_BIT_WAKEUP;
1188 }
1189
1190 /* All uCode command responses, including Tx command responses,
1191 * Rx "responses" (frame-received notification), and other
1192 * notifications from uCode come through here*/
1193 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1194 CSR_INT_BIT_RX_PERIODIC)) {
1195 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
1196 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1197 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1198 iwl_write32(priv, CSR_FH_INT_STATUS,
1199 CSR49_FH_INT_RX_MASK);
1200 }
1201 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1202 handled |= CSR_INT_BIT_RX_PERIODIC;
1203 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1204 }
1205 /* Sending RX interrupt require many steps to be done in the
1206 * the device:
1207 * 1- write interrupt to current index in ICT table.
1208 * 2- dma RX frame.
1209 * 3- update RX shared data to indicate last write index.
1210 * 4- send interrupt.
1211 * This could lead to RX race, driver could receive RX interrupt
1212 * but the shared data changes does not reflect this.
1213 * this could lead to RX race, RX periodic will solve this race
1214 */
1215 iwl_write32(priv, CSR_INT_PERIODIC_REG,
1216 CSR_INT_PERIODIC_DIS);
1217 iwl_rx_handle(priv);
1218 /* Only set RX periodic if real RX is received. */
1219 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1220 iwl_write32(priv, CSR_INT_PERIODIC_REG,
1221 CSR_INT_PERIODIC_ENA);
1222
1223 priv->isr_stats.rx++;
1224 }
1225
1226 if (inta & CSR_INT_BIT_FH_TX) {
1227 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
1228 IWL_DEBUG_ISR(priv, "Tx interrupt\n");
1229 priv->isr_stats.tx++;
1230 handled |= CSR_INT_BIT_FH_TX;
1231 /* FH finished to write, send event */
1232 priv->ucode_write_complete = 1;
1233 wake_up_interruptible(&priv->wait_command_queue);
1234 }
1235
1236 if (inta & ~handled) {
1237 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1238 priv->isr_stats.unhandled++;
1239 }
1240
1241 if (inta & ~(priv->inta_mask)) {
1242 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1243 inta & ~priv->inta_mask);
1244 }
1245
1246
1247 /* Re-enable all interrupts */
1248 /* only Re-enable if diabled by irq */
1249 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1250 iwl_enable_interrupts(priv);
1251 /* Re-enable RF_KILL if it occurred */
1252 else if (handled & CSR_INT_BIT_RF_KILL)
1253 iwl_enable_rfkill_int(priv);
1254
1255 spin_unlock_irqrestore(&priv->lock, flags);
1256
1257 }
1258
1259
1260 /******************************************************************************
1261 *
1262 * uCode download functions
1263 *
1264 ******************************************************************************/
1265
1266 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1267 {
1268 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1269 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1270 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1271 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1272 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1273 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
1274 }
1275
1276 static void iwl_nic_start(struct iwl_priv *priv)
1277 {
1278 /* Remove all resets to allow NIC to operate */
1279 iwl_write32(priv, CSR_RESET, 0);
1280 }
1281
1282
1283 /**
1284 * iwl_read_ucode - Read uCode images from disk file.
1285 *
1286 * Copy into buffers for card to fetch via bus-mastering
1287 */
1288 static int iwl_read_ucode(struct iwl_priv *priv)
1289 {
1290 struct iwl_ucode_header *ucode;
1291 int ret = -EINVAL, index;
1292 const struct firmware *ucode_raw;
1293 const char *name_pre = priv->cfg->fw_name_pre;
1294 const unsigned int api_max = priv->cfg->ucode_api_max;
1295 const unsigned int api_min = priv->cfg->ucode_api_min;
1296 char buf[25];
1297 u8 *src;
1298 size_t len;
1299 u32 api_ver, build;
1300 u32 inst_size, data_size, init_size, init_data_size, boot_size;
1301 u16 eeprom_ver;
1302
1303 /* Ask kernel firmware_class module to get the boot firmware off disk.
1304 * request_firmware() is synchronous, file is in memory on return. */
1305 for (index = api_max; index >= api_min; index--) {
1306 sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
1307 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
1308 if (ret < 0) {
1309 IWL_ERR(priv, "%s firmware file req failed: %d\n",
1310 buf, ret);
1311 if (ret == -ENOENT)
1312 continue;
1313 else
1314 goto error;
1315 } else {
1316 if (index < api_max)
1317 IWL_ERR(priv, "Loaded firmware %s, "
1318 "which is deprecated. "
1319 "Please use API v%u instead.\n",
1320 buf, api_max);
1321
1322 IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
1323 buf, ucode_raw->size);
1324 break;
1325 }
1326 }
1327
1328 if (ret < 0)
1329 goto error;
1330
1331 /* Make sure that we got at least the v1 header! */
1332 if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
1333 IWL_ERR(priv, "File size way too small!\n");
1334 ret = -EINVAL;
1335 goto err_release;
1336 }
1337
1338 /* Data from ucode file: header followed by uCode images */
1339 ucode = (struct iwl_ucode_header *)ucode_raw->data;
1340
1341 priv->ucode_ver = le32_to_cpu(ucode->ver);
1342 api_ver = IWL_UCODE_API(priv->ucode_ver);
1343 build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
1344 inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
1345 data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
1346 init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
1347 init_data_size =
1348 priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
1349 boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
1350 src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
1351
1352 /* api_ver should match the api version forming part of the
1353 * firmware filename ... but we don't check for that and only rely
1354 * on the API version read from firmware header from here on forward */
1355
1356 if (api_ver < api_min || api_ver > api_max) {
1357 IWL_ERR(priv, "Driver unable to support your firmware API. "
1358 "Driver supports v%u, firmware is v%u.\n",
1359 api_max, api_ver);
1360 priv->ucode_ver = 0;
1361 ret = -EINVAL;
1362 goto err_release;
1363 }
1364 if (api_ver != api_max)
1365 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
1366 "got v%u. New firmware can be obtained "
1367 "from http://www.intellinuxwireless.org.\n",
1368 api_max, api_ver);
1369
1370 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
1371 IWL_UCODE_MAJOR(priv->ucode_ver),
1372 IWL_UCODE_MINOR(priv->ucode_ver),
1373 IWL_UCODE_API(priv->ucode_ver),
1374 IWL_UCODE_SERIAL(priv->ucode_ver));
1375
1376 if (build)
1377 IWL_DEBUG_INFO(priv, "Build %u\n", build);
1378
1379 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
1380 IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
1381 (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
1382 ? "OTP" : "EEPROM", eeprom_ver);
1383
1384 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
1385 priv->ucode_ver);
1386 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
1387 inst_size);
1388 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
1389 data_size);
1390 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
1391 init_size);
1392 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
1393 init_data_size);
1394 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
1395 boot_size);
1396
1397 /* Verify size of file vs. image size info in file's header */
1398 if (ucode_raw->size !=
1399 priv->cfg->ops->ucode->get_header_size(api_ver) +
1400 inst_size + data_size + init_size +
1401 init_data_size + boot_size) {
1402
1403 IWL_DEBUG_INFO(priv,
1404 "uCode file size %d does not match expected size\n",
1405 (int)ucode_raw->size);
1406 ret = -EINVAL;
1407 goto err_release;
1408 }
1409
1410 /* Verify that uCode images will fit in card's SRAM */
1411 if (inst_size > priv->hw_params.max_inst_size) {
1412 IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
1413 inst_size);
1414 ret = -EINVAL;
1415 goto err_release;
1416 }
1417
1418 if (data_size > priv->hw_params.max_data_size) {
1419 IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
1420 data_size);
1421 ret = -EINVAL;
1422 goto err_release;
1423 }
1424 if (init_size > priv->hw_params.max_inst_size) {
1425 IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
1426 init_size);
1427 ret = -EINVAL;
1428 goto err_release;
1429 }
1430 if (init_data_size > priv->hw_params.max_data_size) {
1431 IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
1432 init_data_size);
1433 ret = -EINVAL;
1434 goto err_release;
1435 }
1436 if (boot_size > priv->hw_params.max_bsm_size) {
1437 IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
1438 boot_size);
1439 ret = -EINVAL;
1440 goto err_release;
1441 }
1442
1443 /* Allocate ucode buffers for card's bus-master loading ... */
1444
1445 /* Runtime instructions and 2 copies of data:
1446 * 1) unmodified from disk
1447 * 2) backup cache for save/restore during power-downs */
1448 priv->ucode_code.len = inst_size;
1449 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
1450
1451 priv->ucode_data.len = data_size;
1452 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
1453
1454 priv->ucode_data_backup.len = data_size;
1455 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1456
1457 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
1458 !priv->ucode_data_backup.v_addr)
1459 goto err_pci_alloc;
1460
1461 /* Initialization instructions and data */
1462 if (init_size && init_data_size) {
1463 priv->ucode_init.len = init_size;
1464 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
1465
1466 priv->ucode_init_data.len = init_data_size;
1467 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1468
1469 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1470 goto err_pci_alloc;
1471 }
1472
1473 /* Bootstrap (instructions only, no data) */
1474 if (boot_size) {
1475 priv->ucode_boot.len = boot_size;
1476 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
1477
1478 if (!priv->ucode_boot.v_addr)
1479 goto err_pci_alloc;
1480 }
1481
1482 /* Copy images into buffers for card's bus-master reads ... */
1483
1484 /* Runtime instructions (first block of data in file) */
1485 len = inst_size;
1486 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
1487 memcpy(priv->ucode_code.v_addr, src, len);
1488 src += len;
1489
1490 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
1491 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1492
1493 /* Runtime data (2nd block)
1494 * NOTE: Copy into backup buffer will be done in iwl_up() */
1495 len = data_size;
1496 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
1497 memcpy(priv->ucode_data.v_addr, src, len);
1498 memcpy(priv->ucode_data_backup.v_addr, src, len);
1499 src += len;
1500
1501 /* Initialization instructions (3rd block) */
1502 if (init_size) {
1503 len = init_size;
1504 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
1505 len);
1506 memcpy(priv->ucode_init.v_addr, src, len);
1507 src += len;
1508 }
1509
1510 /* Initialization data (4th block) */
1511 if (init_data_size) {
1512 len = init_data_size;
1513 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
1514 len);
1515 memcpy(priv->ucode_init_data.v_addr, src, len);
1516 src += len;
1517 }
1518
1519 /* Bootstrap instructions (5th block) */
1520 len = boot_size;
1521 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
1522 memcpy(priv->ucode_boot.v_addr, src, len);
1523
1524 /* We have our copies now, allow OS release its copies */
1525 release_firmware(ucode_raw);
1526 return 0;
1527
1528 err_pci_alloc:
1529 IWL_ERR(priv, "failed to allocate pci memory\n");
1530 ret = -ENOMEM;
1531 iwl_dealloc_ucode_pci(priv);
1532
1533 err_release:
1534 release_firmware(ucode_raw);
1535
1536 error:
1537 return ret;
1538 }
1539
1540 #ifdef CONFIG_IWLWIFI_DEBUG
1541 static const char *desc_lookup_text[] = {
1542 "OK",
1543 "FAIL",
1544 "BAD_PARAM",
1545 "BAD_CHECKSUM",
1546 "NMI_INTERRUPT_WDG",
1547 "SYSASSERT",
1548 "FATAL_ERROR",
1549 "BAD_COMMAND",
1550 "HW_ERROR_TUNE_LOCK",
1551 "HW_ERROR_TEMPERATURE",
1552 "ILLEGAL_CHAN_FREQ",
1553 "VCC_NOT_STABLE",
1554 "FH_ERROR",
1555 "NMI_INTERRUPT_HOST",
1556 "NMI_INTERRUPT_ACTION_PT",
1557 "NMI_INTERRUPT_UNKNOWN",
1558 "UCODE_VERSION_MISMATCH",
1559 "HW_ERROR_ABS_LOCK",
1560 "HW_ERROR_CAL_LOCK_FAIL",
1561 "NMI_INTERRUPT_INST_ACTION_PT",
1562 "NMI_INTERRUPT_DATA_ACTION_PT",
1563 "NMI_TRM_HW_ER",
1564 "NMI_INTERRUPT_TRM",
1565 "NMI_INTERRUPT_BREAK_POINT"
1566 "DEBUG_0",
1567 "DEBUG_1",
1568 "DEBUG_2",
1569 "DEBUG_3",
1570 "UNKNOWN"
1571 };
1572
1573 static const char *desc_lookup(int i)
1574 {
1575 int max = ARRAY_SIZE(desc_lookup_text) - 1;
1576
1577 if (i < 0 || i > max)
1578 i = max;
1579
1580 return desc_lookup_text[i];
1581 }
1582
1583 #define ERROR_START_OFFSET (1 * sizeof(u32))
1584 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
1585
1586 void iwl_dump_nic_error_log(struct iwl_priv *priv)
1587 {
1588 u32 data2, line;
1589 u32 desc, time, count, base, data1;
1590 u32 blink1, blink2, ilink1, ilink2;
1591
1592 if (priv->ucode_type == UCODE_INIT)
1593 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1594 else
1595 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1596
1597 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1598 IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
1599 return;
1600 }
1601
1602 count = iwl_read_targ_mem(priv, base);
1603
1604 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1605 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1606 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1607 priv->status, count);
1608 }
1609
1610 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1611 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1612 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1613 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1614 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1615 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1616 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1617 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1618 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1619
1620 IWL_ERR(priv, "Desc Time "
1621 "data1 data2 line\n");
1622 IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
1623 desc_lookup(desc), desc, time, data1, data2, line);
1624 IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
1625 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
1626 ilink1, ilink2);
1627
1628 }
1629
1630 #define EVENT_START_OFFSET (4 * sizeof(u32))
1631
1632 /**
1633 * iwl_print_event_log - Dump error event log to syslog
1634 *
1635 */
1636 static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1637 u32 num_events, u32 mode)
1638 {
1639 u32 i;
1640 u32 base; /* SRAM byte address of event log header */
1641 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1642 u32 ptr; /* SRAM byte address of log data */
1643 u32 ev, time, data; /* event log data */
1644
1645 if (num_events == 0)
1646 return;
1647 if (priv->ucode_type == UCODE_INIT)
1648 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1649 else
1650 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1651
1652 if (mode == 0)
1653 event_size = 2 * sizeof(u32);
1654 else
1655 event_size = 3 * sizeof(u32);
1656
1657 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1658
1659 /* "time" is actually "data" for mode 0 (no timestamp).
1660 * place event id # at far right for easier visual parsing. */
1661 for (i = 0; i < num_events; i++) {
1662 ev = iwl_read_targ_mem(priv, ptr);
1663 ptr += sizeof(u32);
1664 time = iwl_read_targ_mem(priv, ptr);
1665 ptr += sizeof(u32);
1666 if (mode == 0) {
1667 /* data, ev */
1668 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
1669 } else {
1670 data = iwl_read_targ_mem(priv, ptr);
1671 ptr += sizeof(u32);
1672 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
1673 time, data, ev);
1674 }
1675 }
1676 }
1677
1678 void iwl_dump_nic_event_log(struct iwl_priv *priv)
1679 {
1680 u32 base; /* SRAM byte address of event log header */
1681 u32 capacity; /* event log capacity in # entries */
1682 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1683 u32 num_wraps; /* # times uCode wrapped to top of log */
1684 u32 next_entry; /* index of next entry to be written by uCode */
1685 u32 size; /* # entries that we'll print */
1686
1687 if (priv->ucode_type == UCODE_INIT)
1688 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1689 else
1690 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1691
1692 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1693 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
1694 return;
1695 }
1696
1697 /* event log header */
1698 capacity = iwl_read_targ_mem(priv, base);
1699 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1700 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1701 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1702
1703 size = num_wraps ? capacity : next_entry;
1704
1705 /* bail out if nothing in log */
1706 if (size == 0) {
1707 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
1708 return;
1709 }
1710
1711 IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
1712 size, num_wraps);
1713
1714 /* if uCode has wrapped back to top of log, start at the oldest entry,
1715 * i.e the next one that uCode would fill. */
1716 if (num_wraps)
1717 iwl_print_event_log(priv, next_entry,
1718 capacity - next_entry, mode);
1719 /* (then/else) start at top of log */
1720 iwl_print_event_log(priv, 0, next_entry, mode);
1721
1722 }
1723 #endif
1724
1725 /**
1726 * iwl_alive_start - called after REPLY_ALIVE notification received
1727 * from protocol/runtime uCode (initialization uCode's
1728 * Alive gets handled by iwl_init_alive_start()).
1729 */
1730 static void iwl_alive_start(struct iwl_priv *priv)
1731 {
1732 int ret = 0;
1733
1734 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
1735
1736 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
1737 /* We had an error bringing up the hardware, so take it
1738 * all the way back down so we can try again */
1739 IWL_DEBUG_INFO(priv, "Alive failed.\n");
1740 goto restart;
1741 }
1742
1743 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
1744 * This is a paranoid check, because we would not have gotten the
1745 * "runtime" alive if code weren't properly loaded. */
1746 if (iwl_verify_ucode(priv)) {
1747 /* Runtime instruction load was bad;
1748 * take it all the way back down so we can try again */
1749 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
1750 goto restart;
1751 }
1752
1753 iwl_clear_stations_table(priv);
1754 ret = priv->cfg->ops->lib->alive_notify(priv);
1755 if (ret) {
1756 IWL_WARN(priv,
1757 "Could not complete ALIVE transition [ntf]: %d\n", ret);
1758 goto restart;
1759 }
1760
1761 /* After the ALIVE response, we can send host commands to the uCode */
1762 set_bit(STATUS_ALIVE, &priv->status);
1763
1764 if (iwl_is_rfkill(priv))
1765 return;
1766
1767 ieee80211_wake_queues(priv->hw);
1768
1769 priv->active_rate = priv->rates_mask;
1770 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1771
1772 if (iwl_is_associated(priv)) {
1773 struct iwl_rxon_cmd *active_rxon =
1774 (struct iwl_rxon_cmd *)&priv->active_rxon;
1775 /* apply any changes in staging */
1776 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
1777 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1778 } else {
1779 /* Initialize our rx_config data */
1780 iwl_connection_init_rx_config(priv, priv->iw_mode);
1781
1782 if (priv->cfg->ops->hcmd->set_rxon_chain)
1783 priv->cfg->ops->hcmd->set_rxon_chain(priv);
1784
1785 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
1786 }
1787
1788 /* Configure Bluetooth device coexistence support */
1789 iwl_send_bt_config(priv);
1790
1791 iwl_reset_run_time_calib(priv);
1792
1793 /* Configure the adapter for unassociated operation */
1794 iwlcore_commit_rxon(priv);
1795
1796 /* At this point, the NIC is initialized and operational */
1797 iwl_rf_kill_ct_config(priv);
1798
1799 iwl_leds_register(priv);
1800
1801 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
1802 set_bit(STATUS_READY, &priv->status);
1803 wake_up_interruptible(&priv->wait_command_queue);
1804
1805 iwl_power_update_mode(priv, true);
1806
1807 /* reassociate for ADHOC mode */
1808 if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
1809 struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
1810 priv->vif);
1811 if (beacon)
1812 iwl_mac_beacon_update(priv->hw, beacon);
1813 }
1814
1815
1816 if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
1817 iwl_set_mode(priv, priv->iw_mode);
1818
1819 return;
1820
1821 restart:
1822 queue_work(priv->workqueue, &priv->restart);
1823 }
1824
1825 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
1826
1827 static void __iwl_down(struct iwl_priv *priv)
1828 {
1829 unsigned long flags;
1830 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
1831
1832 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
1833
1834 if (!exit_pending)
1835 set_bit(STATUS_EXIT_PENDING, &priv->status);
1836
1837 iwl_leds_unregister(priv);
1838
1839 iwl_clear_stations_table(priv);
1840
1841 /* Unblock any waiting calls */
1842 wake_up_interruptible_all(&priv->wait_command_queue);
1843
1844 /* Wipe out the EXIT_PENDING status bit if we are not actually
1845 * exiting the module */
1846 if (!exit_pending)
1847 clear_bit(STATUS_EXIT_PENDING, &priv->status);
1848
1849 /* stop and reset the on-board processor */
1850 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1851
1852 /* tell the device to stop sending interrupts */
1853 spin_lock_irqsave(&priv->lock, flags);
1854 iwl_disable_interrupts(priv);
1855 spin_unlock_irqrestore(&priv->lock, flags);
1856 iwl_synchronize_irq(priv);
1857
1858 if (priv->mac80211_registered)
1859 ieee80211_stop_queues(priv->hw);
1860
1861 /* If we have not previously called iwl_init() then
1862 * clear all bits but the RF Kill bit and return */
1863 if (!iwl_is_init(priv)) {
1864 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
1865 STATUS_RF_KILL_HW |
1866 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
1867 STATUS_GEO_CONFIGURED |
1868 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
1869 STATUS_EXIT_PENDING;
1870 goto exit;
1871 }
1872
1873 /* ...otherwise clear out all the status bits but the RF Kill
1874 * bit and continue taking the NIC down. */
1875 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
1876 STATUS_RF_KILL_HW |
1877 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
1878 STATUS_GEO_CONFIGURED |
1879 test_bit(STATUS_FW_ERROR, &priv->status) <<
1880 STATUS_FW_ERROR |
1881 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
1882 STATUS_EXIT_PENDING;
1883
1884 /* device going down, Stop using ICT table */
1885 iwl_disable_ict(priv);
1886 spin_lock_irqsave(&priv->lock, flags);
1887 iwl_clear_bit(priv, CSR_GP_CNTRL,
1888 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1889 spin_unlock_irqrestore(&priv->lock, flags);
1890
1891 iwl_txq_ctx_stop(priv);
1892 iwl_rxq_stop(priv);
1893
1894 iwl_write_prph(priv, APMG_CLK_DIS_REG,
1895 APMG_CLK_VAL_DMA_CLK_RQT);
1896
1897 udelay(5);
1898
1899 /* FIXME: apm_ops.suspend(priv) */
1900 if (exit_pending)
1901 priv->cfg->ops->lib->apm_ops.stop(priv);
1902 else
1903 priv->cfg->ops->lib->apm_ops.reset(priv);
1904 exit:
1905 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
1906
1907 if (priv->ibss_beacon)
1908 dev_kfree_skb(priv->ibss_beacon);
1909 priv->ibss_beacon = NULL;
1910
1911 /* clear out any free frames */
1912 iwl_clear_free_frames(priv);
1913 }
1914
1915 static void iwl_down(struct iwl_priv *priv)
1916 {
1917 mutex_lock(&priv->mutex);
1918 __iwl_down(priv);
1919 mutex_unlock(&priv->mutex);
1920
1921 iwl_cancel_deferred_work(priv);
1922 }
1923
1924 #define HW_READY_TIMEOUT (50)
1925
1926 static int iwl_set_hw_ready(struct iwl_priv *priv)
1927 {
1928 int ret = 0;
1929
1930 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1931 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
1932
1933 /* See if we got it */
1934 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
1935 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
1936 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
1937 HW_READY_TIMEOUT);
1938 if (ret != -ETIMEDOUT)
1939 priv->hw_ready = true;
1940 else
1941 priv->hw_ready = false;
1942
1943 IWL_DEBUG_INFO(priv, "hardware %s\n",
1944 (priv->hw_ready == 1) ? "ready" : "not ready");
1945 return ret;
1946 }
1947
1948 static int iwl_prepare_card_hw(struct iwl_priv *priv)
1949 {
1950 int ret = 0;
1951
1952 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
1953
1954 ret = iwl_set_hw_ready(priv);
1955 if (priv->hw_ready)
1956 return ret;
1957
1958 /* If HW is not ready, prepare the conditions to check again */
1959 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1960 CSR_HW_IF_CONFIG_REG_PREPARE);
1961
1962 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
1963 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
1964 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
1965
1966 /* HW should be ready by now, check again. */
1967 if (ret != -ETIMEDOUT)
1968 iwl_set_hw_ready(priv);
1969
1970 return ret;
1971 }
1972
1973 #define MAX_HW_RESTARTS 5
1974
1975 static int __iwl_up(struct iwl_priv *priv)
1976 {
1977 int i;
1978 int ret;
1979
1980 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
1981 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
1982 return -EIO;
1983 }
1984
1985 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
1986 IWL_ERR(priv, "ucode not available for device bringup\n");
1987 return -EIO;
1988 }
1989
1990 iwl_prepare_card_hw(priv);
1991
1992 if (!priv->hw_ready) {
1993 IWL_WARN(priv, "Exit HW not ready\n");
1994 return -EIO;
1995 }
1996
1997 /* If platform's RF_KILL switch is NOT set to KILL */
1998 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
1999 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2000 else
2001 set_bit(STATUS_RF_KILL_HW, &priv->status);
2002
2003 if (iwl_is_rfkill(priv)) {
2004 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2005
2006 iwl_enable_interrupts(priv);
2007 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2008 return 0;
2009 }
2010
2011 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2012
2013 ret = iwl_hw_nic_init(priv);
2014 if (ret) {
2015 IWL_ERR(priv, "Unable to init nic\n");
2016 return ret;
2017 }
2018
2019 /* make sure rfkill handshake bits are cleared */
2020 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2021 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2022 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2023
2024 /* clear (again), then enable host interrupts */
2025 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2026 iwl_enable_interrupts(priv);
2027
2028 /* really make sure rfkill handshake bits are cleared */
2029 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2030 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2031
2032 /* Copy original ucode data image from disk into backup cache.
2033 * This will be used to initialize the on-board processor's
2034 * data SRAM for a clean start when the runtime program first loads. */
2035 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
2036 priv->ucode_data.len);
2037
2038 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2039
2040 iwl_clear_stations_table(priv);
2041
2042 /* load bootstrap state machine,
2043 * load bootstrap program into processor's memory,
2044 * prepare to load the "initialize" uCode */
2045 ret = priv->cfg->ops->lib->load_ucode(priv);
2046
2047 if (ret) {
2048 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2049 ret);
2050 continue;
2051 }
2052
2053 /* start card; "initialize" will load runtime ucode */
2054 iwl_nic_start(priv);
2055
2056 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
2057
2058 return 0;
2059 }
2060
2061 set_bit(STATUS_EXIT_PENDING, &priv->status);
2062 __iwl_down(priv);
2063 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2064
2065 /* tried to restart and config the device for as long as our
2066 * patience could withstand */
2067 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
2068 return -EIO;
2069 }
2070
2071
2072 /*****************************************************************************
2073 *
2074 * Workqueue callbacks
2075 *
2076 *****************************************************************************/
2077
2078 static void iwl_bg_init_alive_start(struct work_struct *data)
2079 {
2080 struct iwl_priv *priv =
2081 container_of(data, struct iwl_priv, init_alive_start.work);
2082
2083 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2084 return;
2085
2086 mutex_lock(&priv->mutex);
2087 priv->cfg->ops->lib->init_alive_start(priv);
2088 mutex_unlock(&priv->mutex);
2089 }
2090
2091 static void iwl_bg_alive_start(struct work_struct *data)
2092 {
2093 struct iwl_priv *priv =
2094 container_of(data, struct iwl_priv, alive_start.work);
2095
2096 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2097 return;
2098
2099 /* enable dram interrupt */
2100 iwl_reset_ict(priv);
2101
2102 mutex_lock(&priv->mutex);
2103 iwl_alive_start(priv);
2104 mutex_unlock(&priv->mutex);
2105 }
2106
2107 static void iwl_bg_run_time_calib_work(struct work_struct *work)
2108 {
2109 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2110 run_time_calib_work);
2111
2112 mutex_lock(&priv->mutex);
2113
2114 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2115 test_bit(STATUS_SCANNING, &priv->status)) {
2116 mutex_unlock(&priv->mutex);
2117 return;
2118 }
2119
2120 if (priv->start_calib) {
2121 iwl_chain_noise_calibration(priv, &priv->statistics);
2122
2123 iwl_sensitivity_calibration(priv, &priv->statistics);
2124 }
2125
2126 mutex_unlock(&priv->mutex);
2127 return;
2128 }
2129
2130 static void iwl_bg_up(struct work_struct *data)
2131 {
2132 struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
2133
2134 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2135 return;
2136
2137 mutex_lock(&priv->mutex);
2138 __iwl_up(priv);
2139 mutex_unlock(&priv->mutex);
2140 }
2141
2142 static void iwl_bg_restart(struct work_struct *data)
2143 {
2144 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
2145
2146 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2147 return;
2148
2149 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2150 mutex_lock(&priv->mutex);
2151 priv->vif = NULL;
2152 priv->is_open = 0;
2153 mutex_unlock(&priv->mutex);
2154 iwl_down(priv);
2155 ieee80211_restart_hw(priv->hw);
2156 } else {
2157 iwl_down(priv);
2158 queue_work(priv->workqueue, &priv->up);
2159 }
2160 }
2161
2162 static void iwl_bg_rx_replenish(struct work_struct *data)
2163 {
2164 struct iwl_priv *priv =
2165 container_of(data, struct iwl_priv, rx_replenish);
2166
2167 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2168 return;
2169
2170 mutex_lock(&priv->mutex);
2171 iwl_rx_replenish(priv);
2172 mutex_unlock(&priv->mutex);
2173 }
2174
2175 #define IWL_DELAY_NEXT_SCAN (HZ*2)
2176
2177 void iwl_post_associate(struct iwl_priv *priv)
2178 {
2179 struct ieee80211_conf *conf = NULL;
2180 int ret = 0;
2181 unsigned long flags;
2182
2183 if (priv->iw_mode == NL80211_IFTYPE_AP) {
2184 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
2185 return;
2186 }
2187
2188 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
2189 priv->assoc_id, priv->active_rxon.bssid_addr);
2190
2191
2192 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2193 return;
2194
2195
2196 if (!priv->vif || !priv->is_open)
2197 return;
2198
2199 iwl_scan_cancel_timeout(priv, 200);
2200
2201 conf = ieee80211_get_hw_conf(priv->hw);
2202
2203 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2204 iwlcore_commit_rxon(priv);
2205
2206 iwl_setup_rxon_timing(priv);
2207 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
2208 sizeof(priv->rxon_timing), &priv->rxon_timing);
2209 if (ret)
2210 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
2211 "Attempting to continue.\n");
2212
2213 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
2214
2215 iwl_set_rxon_ht(priv, &priv->current_ht_config);
2216
2217 if (priv->cfg->ops->hcmd->set_rxon_chain)
2218 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2219
2220 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2221
2222 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
2223 priv->assoc_id, priv->beacon_int);
2224
2225 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2226 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2227 else
2228 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2229
2230 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2231 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2232 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2233 else
2234 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2235
2236 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
2237 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2238
2239 }
2240
2241 iwlcore_commit_rxon(priv);
2242
2243 switch (priv->iw_mode) {
2244 case NL80211_IFTYPE_STATION:
2245 break;
2246
2247 case NL80211_IFTYPE_ADHOC:
2248
2249 /* assume default assoc id */
2250 priv->assoc_id = 1;
2251
2252 iwl_rxon_add_station(priv, priv->bssid, 0);
2253 iwl_send_beacon_cmd(priv);
2254
2255 break;
2256
2257 default:
2258 IWL_ERR(priv, "%s Should not be called in %d mode\n",
2259 __func__, priv->iw_mode);
2260 break;
2261 }
2262
2263 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
2264 priv->assoc_station_added = 1;
2265
2266 spin_lock_irqsave(&priv->lock, flags);
2267 iwl_activate_qos(priv, 0);
2268 spin_unlock_irqrestore(&priv->lock, flags);
2269
2270 /* the chain noise calibration will enabled PM upon completion
2271 * If chain noise has already been run, then we need to enable
2272 * power management here */
2273 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
2274 iwl_power_update_mode(priv, false);
2275
2276 /* Enable Rx differential gain and sensitivity calibrations */
2277 iwl_chain_noise_reset(priv);
2278 priv->start_calib = 1;
2279
2280 }
2281
2282 /*****************************************************************************
2283 *
2284 * mac80211 entry point functions
2285 *
2286 *****************************************************************************/
2287
2288 #define UCODE_READY_TIMEOUT (4 * HZ)
2289
2290 static int iwl_mac_start(struct ieee80211_hw *hw)
2291 {
2292 struct iwl_priv *priv = hw->priv;
2293 int ret;
2294
2295 IWL_DEBUG_MAC80211(priv, "enter\n");
2296
2297 /* we should be verifying the device is ready to be opened */
2298 mutex_lock(&priv->mutex);
2299
2300 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
2301 * ucode filename and max sizes are card-specific. */
2302
2303 if (!priv->ucode_code.len) {
2304 ret = iwl_read_ucode(priv);
2305 if (ret) {
2306 IWL_ERR(priv, "Could not read microcode: %d\n", ret);
2307 mutex_unlock(&priv->mutex);
2308 return ret;
2309 }
2310 }
2311
2312 ret = __iwl_up(priv);
2313
2314 mutex_unlock(&priv->mutex);
2315
2316 if (ret)
2317 return ret;
2318
2319 if (iwl_is_rfkill(priv))
2320 goto out;
2321
2322 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
2323
2324 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
2325 * mac80211 will not be run successfully. */
2326 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
2327 test_bit(STATUS_READY, &priv->status),
2328 UCODE_READY_TIMEOUT);
2329 if (!ret) {
2330 if (!test_bit(STATUS_READY, &priv->status)) {
2331 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
2332 jiffies_to_msecs(UCODE_READY_TIMEOUT));
2333 return -ETIMEDOUT;
2334 }
2335 }
2336
2337 out:
2338 priv->is_open = 1;
2339 IWL_DEBUG_MAC80211(priv, "leave\n");
2340 return 0;
2341 }
2342
2343 static void iwl_mac_stop(struct ieee80211_hw *hw)
2344 {
2345 struct iwl_priv *priv = hw->priv;
2346
2347 IWL_DEBUG_MAC80211(priv, "enter\n");
2348
2349 if (!priv->is_open)
2350 return;
2351
2352 priv->is_open = 0;
2353
2354 if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
2355 /* stop mac, cancel any scan request and clear
2356 * RXON_FILTER_ASSOC_MSK BIT
2357 */
2358 mutex_lock(&priv->mutex);
2359 iwl_scan_cancel_timeout(priv, 100);
2360 mutex_unlock(&priv->mutex);
2361 }
2362
2363 iwl_down(priv);
2364
2365 flush_workqueue(priv->workqueue);
2366
2367 /* User space software may expect getting rfkill changes
2368 * even if interface is down */
2369 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2370 iwl_enable_rfkill_int(priv);
2371
2372 IWL_DEBUG_MAC80211(priv, "leave\n");
2373 }
2374
2375 static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2376 {
2377 struct iwl_priv *priv = hw->priv;
2378
2379 IWL_DEBUG_MACDUMP(priv, "enter\n");
2380
2381 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
2382 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
2383
2384 if (iwl_tx_skb(priv, skb))
2385 dev_kfree_skb_any(skb);
2386
2387 IWL_DEBUG_MACDUMP(priv, "leave\n");
2388 return NETDEV_TX_OK;
2389 }
2390
2391 void iwl_config_ap(struct iwl_priv *priv)
2392 {
2393 int ret = 0;
2394 unsigned long flags;
2395
2396 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2397 return;
2398
2399 /* The following should be done only at AP bring up */
2400 if (!iwl_is_associated(priv)) {
2401
2402 /* RXON - unassoc (to set timing command) */
2403 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2404 iwlcore_commit_rxon(priv);
2405
2406 /* RXON Timing */
2407 iwl_setup_rxon_timing(priv);
2408 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
2409 sizeof(priv->rxon_timing), &priv->rxon_timing);
2410 if (ret)
2411 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
2412 "Attempting to continue.\n");
2413
2414 if (priv->cfg->ops->hcmd->set_rxon_chain)
2415 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2416
2417 /* FIXME: what should be the assoc_id for AP? */
2418 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2419 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2420 priv->staging_rxon.flags |=
2421 RXON_FLG_SHORT_PREAMBLE_MSK;
2422 else
2423 priv->staging_rxon.flags &=
2424 ~RXON_FLG_SHORT_PREAMBLE_MSK;
2425
2426 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2427 if (priv->assoc_capability &
2428 WLAN_CAPABILITY_SHORT_SLOT_TIME)
2429 priv->staging_rxon.flags |=
2430 RXON_FLG_SHORT_SLOT_MSK;
2431 else
2432 priv->staging_rxon.flags &=
2433 ~RXON_FLG_SHORT_SLOT_MSK;
2434
2435 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
2436 priv->staging_rxon.flags &=
2437 ~RXON_FLG_SHORT_SLOT_MSK;
2438 }
2439 /* restore RXON assoc */
2440 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
2441 iwlcore_commit_rxon(priv);
2442 spin_lock_irqsave(&priv->lock, flags);
2443 iwl_activate_qos(priv, 1);
2444 spin_unlock_irqrestore(&priv->lock, flags);
2445 iwl_rxon_add_station(priv, iwl_bcast_addr, 0);
2446 }
2447 iwl_send_beacon_cmd(priv);
2448
2449 /* FIXME - we need to add code here to detect a totally new
2450 * configuration, reset the AP, unassoc, rxon timing, assoc,
2451 * clear sta table, add BCAST sta... */
2452 }
2453
2454 static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
2455 struct ieee80211_key_conf *keyconf, const u8 *addr,
2456 u32 iv32, u16 *phase1key)
2457 {
2458
2459 struct iwl_priv *priv = hw->priv;
2460 IWL_DEBUG_MAC80211(priv, "enter\n");
2461
2462 iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
2463
2464 IWL_DEBUG_MAC80211(priv, "leave\n");
2465 }
2466
2467 static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2468 struct ieee80211_vif *vif,
2469 struct ieee80211_sta *sta,
2470 struct ieee80211_key_conf *key)
2471 {
2472 struct iwl_priv *priv = hw->priv;
2473 const u8 *addr;
2474 int ret;
2475 u8 sta_id;
2476 bool is_default_wep_key = false;
2477
2478 IWL_DEBUG_MAC80211(priv, "enter\n");
2479
2480 if (priv->cfg->mod_params->sw_crypto) {
2481 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
2482 return -EOPNOTSUPP;
2483 }
2484 addr = sta ? sta->addr : iwl_bcast_addr;
2485 sta_id = iwl_find_station(priv, addr);
2486 if (sta_id == IWL_INVALID_STATION) {
2487 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
2488 addr);
2489 return -EINVAL;
2490
2491 }
2492
2493 mutex_lock(&priv->mutex);
2494 iwl_scan_cancel_timeout(priv, 100);
2495 mutex_unlock(&priv->mutex);
2496
2497 /* If we are getting WEP group key and we didn't receive any key mapping
2498 * so far, we are in legacy wep mode (group key only), otherwise we are
2499 * in 1X mode.
2500 * In legacy wep mode, we use another host command to the uCode */
2501 if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
2502 priv->iw_mode != NL80211_IFTYPE_AP) {
2503 if (cmd == SET_KEY)
2504 is_default_wep_key = !priv->key_mapping_key;
2505 else
2506 is_default_wep_key =
2507 (key->hw_key_idx == HW_KEY_DEFAULT);
2508 }
2509
2510 switch (cmd) {
2511 case SET_KEY:
2512 if (is_default_wep_key)
2513 ret = iwl_set_default_wep_key(priv, key);
2514 else
2515 ret = iwl_set_dynamic_key(priv, key, sta_id);
2516
2517 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
2518 break;
2519 case DISABLE_KEY:
2520 if (is_default_wep_key)
2521 ret = iwl_remove_default_wep_key(priv, key);
2522 else
2523 ret = iwl_remove_dynamic_key(priv, key, sta_id);
2524
2525 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
2526 break;
2527 default:
2528 ret = -EINVAL;
2529 }
2530
2531 IWL_DEBUG_MAC80211(priv, "leave\n");
2532
2533 return ret;
2534 }
2535
2536 static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
2537 enum ieee80211_ampdu_mlme_action action,
2538 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
2539 {
2540 struct iwl_priv *priv = hw->priv;
2541 int ret;
2542
2543 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
2544 sta->addr, tid);
2545
2546 if (!(priv->cfg->sku & IWL_SKU_N))
2547 return -EACCES;
2548
2549 switch (action) {
2550 case IEEE80211_AMPDU_RX_START:
2551 IWL_DEBUG_HT(priv, "start Rx\n");
2552 return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
2553 case IEEE80211_AMPDU_RX_STOP:
2554 IWL_DEBUG_HT(priv, "stop Rx\n");
2555 ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
2556 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2557 return 0;
2558 else
2559 return ret;
2560 case IEEE80211_AMPDU_TX_START:
2561 IWL_DEBUG_HT(priv, "start Tx\n");
2562 return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
2563 case IEEE80211_AMPDU_TX_STOP:
2564 IWL_DEBUG_HT(priv, "stop Tx\n");
2565 ret = iwl_tx_agg_stop(priv, sta->addr, tid);
2566 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2567 return 0;
2568 else
2569 return ret;
2570 default:
2571 IWL_DEBUG_HT(priv, "unknown\n");
2572 return -EINVAL;
2573 break;
2574 }
2575 return 0;
2576 }
2577
2578 static int iwl_mac_get_stats(struct ieee80211_hw *hw,
2579 struct ieee80211_low_level_stats *stats)
2580 {
2581 struct iwl_priv *priv = hw->priv;
2582
2583 priv = hw->priv;
2584 IWL_DEBUG_MAC80211(priv, "enter\n");
2585 IWL_DEBUG_MAC80211(priv, "leave\n");
2586
2587 return 0;
2588 }
2589
2590 /*****************************************************************************
2591 *
2592 * sysfs attributes
2593 *
2594 *****************************************************************************/
2595
2596 #ifdef CONFIG_IWLWIFI_DEBUG
2597
2598 /*
2599 * The following adds a new attribute to the sysfs representation
2600 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
2601 * used for controlling the debug level.
2602 *
2603 * See the level definitions in iwl for details.
2604 *
2605 * The debug_level being managed using sysfs below is a per device debug
2606 * level that is used instead of the global debug level if it (the per
2607 * device debug level) is set.
2608 */
2609 static ssize_t show_debug_level(struct device *d,
2610 struct device_attribute *attr, char *buf)
2611 {
2612 struct iwl_priv *priv = dev_get_drvdata(d);
2613 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
2614 }
2615 static ssize_t store_debug_level(struct device *d,
2616 struct device_attribute *attr,
2617 const char *buf, size_t count)
2618 {
2619 struct iwl_priv *priv = dev_get_drvdata(d);
2620 unsigned long val;
2621 int ret;
2622
2623 ret = strict_strtoul(buf, 0, &val);
2624 if (ret)
2625 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
2626 else {
2627 priv->debug_level = val;
2628 if (iwl_alloc_traffic_mem(priv))
2629 IWL_ERR(priv,
2630 "Not enough memory to generate traffic log\n");
2631 }
2632 return strnlen(buf, count);
2633 }
2634
2635 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
2636 show_debug_level, store_debug_level);
2637
2638
2639 #endif /* CONFIG_IWLWIFI_DEBUG */
2640
2641
2642 static ssize_t show_temperature(struct device *d,
2643 struct device_attribute *attr, char *buf)
2644 {
2645 struct iwl_priv *priv = dev_get_drvdata(d);
2646
2647 if (!iwl_is_alive(priv))
2648 return -EAGAIN;
2649
2650 return sprintf(buf, "%d\n", priv->temperature);
2651 }
2652
2653 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
2654
2655 static ssize_t show_tx_power(struct device *d,
2656 struct device_attribute *attr, char *buf)
2657 {
2658 struct iwl_priv *priv = dev_get_drvdata(d);
2659
2660 if (!iwl_is_ready_rf(priv))
2661 return sprintf(buf, "off\n");
2662 else
2663 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
2664 }
2665
2666 static ssize_t store_tx_power(struct device *d,
2667 struct device_attribute *attr,
2668 const char *buf, size_t count)
2669 {
2670 struct iwl_priv *priv = dev_get_drvdata(d);
2671 unsigned long val;
2672 int ret;
2673
2674 ret = strict_strtoul(buf, 10, &val);
2675 if (ret)
2676 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
2677 else {
2678 ret = iwl_set_tx_power(priv, val, false);
2679 if (ret)
2680 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
2681 ret);
2682 else
2683 ret = count;
2684 }
2685 return ret;
2686 }
2687
2688 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
2689
2690 static ssize_t show_flags(struct device *d,
2691 struct device_attribute *attr, char *buf)
2692 {
2693 struct iwl_priv *priv = dev_get_drvdata(d);
2694
2695 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
2696 }
2697
2698 static ssize_t store_flags(struct device *d,
2699 struct device_attribute *attr,
2700 const char *buf, size_t count)
2701 {
2702 struct iwl_priv *priv = dev_get_drvdata(d);
2703 unsigned long val;
2704 u32 flags;
2705 int ret = strict_strtoul(buf, 0, &val);
2706 if (ret)
2707 return ret;
2708 flags = (u32)val;
2709
2710 mutex_lock(&priv->mutex);
2711 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
2712 /* Cancel any currently running scans... */
2713 if (iwl_scan_cancel_timeout(priv, 100))
2714 IWL_WARN(priv, "Could not cancel scan.\n");
2715 else {
2716 IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
2717 priv->staging_rxon.flags = cpu_to_le32(flags);
2718 iwlcore_commit_rxon(priv);
2719 }
2720 }
2721 mutex_unlock(&priv->mutex);
2722
2723 return count;
2724 }
2725
2726 static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
2727
2728 static ssize_t show_filter_flags(struct device *d,
2729 struct device_attribute *attr, char *buf)
2730 {
2731 struct iwl_priv *priv = dev_get_drvdata(d);
2732
2733 return sprintf(buf, "0x%04X\n",
2734 le32_to_cpu(priv->active_rxon.filter_flags));
2735 }
2736
2737 static ssize_t store_filter_flags(struct device *d,
2738 struct device_attribute *attr,
2739 const char *buf, size_t count)
2740 {
2741 struct iwl_priv *priv = dev_get_drvdata(d);
2742 unsigned long val;
2743 u32 filter_flags;
2744 int ret = strict_strtoul(buf, 0, &val);
2745 if (ret)
2746 return ret;
2747 filter_flags = (u32)val;
2748
2749 mutex_lock(&priv->mutex);
2750 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
2751 /* Cancel any currently running scans... */
2752 if (iwl_scan_cancel_timeout(priv, 100))
2753 IWL_WARN(priv, "Could not cancel scan.\n");
2754 else {
2755 IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
2756 "0x%04X\n", filter_flags);
2757 priv->staging_rxon.filter_flags =
2758 cpu_to_le32(filter_flags);
2759 iwlcore_commit_rxon(priv);
2760 }
2761 }
2762 mutex_unlock(&priv->mutex);
2763
2764 return count;
2765 }
2766
2767 static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
2768 store_filter_flags);
2769
2770
2771 static ssize_t show_statistics(struct device *d,
2772 struct device_attribute *attr, char *buf)
2773 {
2774 struct iwl_priv *priv = dev_get_drvdata(d);
2775 u32 size = sizeof(struct iwl_notif_statistics);
2776 u32 len = 0, ofs = 0;
2777 u8 *data = (u8 *)&priv->statistics;
2778 int rc = 0;
2779
2780 if (!iwl_is_alive(priv))
2781 return -EAGAIN;
2782
2783 mutex_lock(&priv->mutex);
2784 rc = iwl_send_statistics_request(priv, 0);
2785 mutex_unlock(&priv->mutex);
2786
2787 if (rc) {
2788 len = sprintf(buf,
2789 "Error sending statistics request: 0x%08X\n", rc);
2790 return len;
2791 }
2792
2793 while (size && (PAGE_SIZE - len)) {
2794 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
2795 PAGE_SIZE - len, 1);
2796 len = strlen(buf);
2797 if (PAGE_SIZE - len)
2798 buf[len++] = '\n';
2799
2800 ofs += 16;
2801 size -= min(size, 16U);
2802 }
2803
2804 return len;
2805 }
2806
2807 static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
2808
2809
2810 /*****************************************************************************
2811 *
2812 * driver setup and teardown
2813 *
2814 *****************************************************************************/
2815
2816 static void iwl_setup_deferred_work(struct iwl_priv *priv)
2817 {
2818 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
2819
2820 init_waitqueue_head(&priv->wait_command_queue);
2821
2822 INIT_WORK(&priv->up, iwl_bg_up);
2823 INIT_WORK(&priv->restart, iwl_bg_restart);
2824 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
2825 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
2826 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
2827 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
2828 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
2829
2830 iwl_setup_scan_deferred_work(priv);
2831
2832 if (priv->cfg->ops->lib->setup_deferred_work)
2833 priv->cfg->ops->lib->setup_deferred_work(priv);
2834
2835 init_timer(&priv->statistics_periodic);
2836 priv->statistics_periodic.data = (unsigned long)priv;
2837 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
2838
2839 if (!priv->cfg->use_isr_legacy)
2840 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
2841 iwl_irq_tasklet, (unsigned long)priv);
2842 else
2843 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
2844 iwl_irq_tasklet_legacy, (unsigned long)priv);
2845 }
2846
2847 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
2848 {
2849 if (priv->cfg->ops->lib->cancel_deferred_work)
2850 priv->cfg->ops->lib->cancel_deferred_work(priv);
2851
2852 cancel_delayed_work_sync(&priv->init_alive_start);
2853 cancel_delayed_work(&priv->scan_check);
2854 cancel_delayed_work(&priv->alive_start);
2855 cancel_work_sync(&priv->beacon_update);
2856 del_timer_sync(&priv->statistics_periodic);
2857 }
2858
2859 static struct attribute *iwl_sysfs_entries[] = {
2860 &dev_attr_flags.attr,
2861 &dev_attr_filter_flags.attr,
2862 &dev_attr_statistics.attr,
2863 &dev_attr_temperature.attr,
2864 &dev_attr_tx_power.attr,
2865 #ifdef CONFIG_IWLWIFI_DEBUG
2866 &dev_attr_debug_level.attr,
2867 #endif
2868 NULL
2869 };
2870
2871 static struct attribute_group iwl_attribute_group = {
2872 .name = NULL, /* put in device directory */
2873 .attrs = iwl_sysfs_entries,
2874 };
2875
2876 static struct ieee80211_ops iwl_hw_ops = {
2877 .tx = iwl_mac_tx,
2878 .start = iwl_mac_start,
2879 .stop = iwl_mac_stop,
2880 .add_interface = iwl_mac_add_interface,
2881 .remove_interface = iwl_mac_remove_interface,
2882 .config = iwl_mac_config,
2883 .configure_filter = iwl_configure_filter,
2884 .set_key = iwl_mac_set_key,
2885 .update_tkip_key = iwl_mac_update_tkip_key,
2886 .get_stats = iwl_mac_get_stats,
2887 .get_tx_stats = iwl_mac_get_tx_stats,
2888 .conf_tx = iwl_mac_conf_tx,
2889 .reset_tsf = iwl_mac_reset_tsf,
2890 .bss_info_changed = iwl_bss_info_changed,
2891 .ampdu_action = iwl_mac_ampdu_action,
2892 .hw_scan = iwl_mac_hw_scan
2893 };
2894
2895 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2896 {
2897 int err = 0;
2898 struct iwl_priv *priv;
2899 struct ieee80211_hw *hw;
2900 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
2901 unsigned long flags;
2902 u16 pci_cmd;
2903
2904 /************************
2905 * 1. Allocating HW data
2906 ************************/
2907
2908 /* Disabling hardware scan means that mac80211 will perform scans
2909 * "the hard way", rather than using device's scan. */
2910 if (cfg->mod_params->disable_hw_scan) {
2911 if (iwl_debug_level & IWL_DL_INFO)
2912 dev_printk(KERN_DEBUG, &(pdev->dev),
2913 "Disabling hw_scan\n");
2914 iwl_hw_ops.hw_scan = NULL;
2915 }
2916
2917 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
2918 if (!hw) {
2919 err = -ENOMEM;
2920 goto out;
2921 }
2922 priv = hw->priv;
2923 /* At this point both hw and priv are allocated. */
2924
2925 SET_IEEE80211_DEV(hw, &pdev->dev);
2926
2927 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
2928 priv->cfg = cfg;
2929 priv->pci_dev = pdev;
2930 priv->inta_mask = CSR_INI_SET_MASK;
2931
2932 #ifdef CONFIG_IWLWIFI_DEBUG
2933 atomic_set(&priv->restrict_refcnt, 0);
2934 #endif
2935 if (iwl_alloc_traffic_mem(priv))
2936 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
2937
2938 /**************************
2939 * 2. Initializing PCI bus
2940 **************************/
2941 if (pci_enable_device(pdev)) {
2942 err = -ENODEV;
2943 goto out_ieee80211_free_hw;
2944 }
2945
2946 pci_set_master(pdev);
2947
2948 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2949 if (!err)
2950 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2951 if (err) {
2952 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2953 if (!err)
2954 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2955 /* both attempts failed: */
2956 if (err) {
2957 IWL_WARN(priv, "No suitable DMA available.\n");
2958 goto out_pci_disable_device;
2959 }
2960 }
2961
2962 err = pci_request_regions(pdev, DRV_NAME);
2963 if (err)
2964 goto out_pci_disable_device;
2965
2966 pci_set_drvdata(pdev, priv);
2967
2968
2969 /***********************
2970 * 3. Read REV register
2971 ***********************/
2972 priv->hw_base = pci_iomap(pdev, 0, 0);
2973 if (!priv->hw_base) {
2974 err = -ENODEV;
2975 goto out_pci_release_regions;
2976 }
2977
2978 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
2979 (unsigned long long) pci_resource_len(pdev, 0));
2980 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
2981
2982 /* this spin lock will be used in apm_ops.init and EEPROM access
2983 * we should init now
2984 */
2985 spin_lock_init(&priv->reg_lock);
2986 iwl_hw_detect(priv);
2987 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
2988 priv->cfg->name, priv->hw_rev);
2989
2990 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2991 * PCI Tx retries from interfering with C3 CPU state */
2992 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2993
2994 iwl_prepare_card_hw(priv);
2995 if (!priv->hw_ready) {
2996 IWL_WARN(priv, "Failed, HW not ready\n");
2997 goto out_iounmap;
2998 }
2999
3000 /* amp init */
3001 err = priv->cfg->ops->lib->apm_ops.init(priv);
3002 if (err < 0) {
3003 IWL_ERR(priv, "Failed to init APMG\n");
3004 goto out_iounmap;
3005 }
3006 /*****************
3007 * 4. Read EEPROM
3008 *****************/
3009 /* Read the EEPROM */
3010 err = iwl_eeprom_init(priv);
3011 if (err) {
3012 IWL_ERR(priv, "Unable to init EEPROM\n");
3013 goto out_iounmap;
3014 }
3015 err = iwl_eeprom_check_version(priv);
3016 if (err)
3017 goto out_free_eeprom;
3018
3019 /* extract MAC Address */
3020 iwl_eeprom_get_mac(priv, priv->mac_addr);
3021 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
3022 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
3023
3024 /************************
3025 * 5. Setup HW constants
3026 ************************/
3027 if (iwl_set_hw_params(priv)) {
3028 IWL_ERR(priv, "failed to set hw parameters\n");
3029 goto out_free_eeprom;
3030 }
3031
3032 /*******************
3033 * 6. Setup priv
3034 *******************/
3035
3036 err = iwl_init_drv(priv);
3037 if (err)
3038 goto out_free_eeprom;
3039 /* At this point both hw and priv are initialized. */
3040
3041 /********************
3042 * 7. Setup services
3043 ********************/
3044 spin_lock_irqsave(&priv->lock, flags);
3045 iwl_disable_interrupts(priv);
3046 spin_unlock_irqrestore(&priv->lock, flags);
3047
3048 pci_enable_msi(priv->pci_dev);
3049
3050 iwl_alloc_isr_ict(priv);
3051 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
3052 IRQF_SHARED, DRV_NAME, priv);
3053 if (err) {
3054 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3055 goto out_disable_msi;
3056 }
3057 err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
3058 if (err) {
3059 IWL_ERR(priv, "failed to create sysfs device attributes\n");
3060 goto out_free_irq;
3061 }
3062
3063 iwl_setup_deferred_work(priv);
3064 iwl_setup_rx_handlers(priv);
3065
3066 /**********************************
3067 * 8. Setup and register mac80211
3068 **********************************/
3069
3070 /* enable rfkill interrupt: hw bug w/a */
3071 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3072 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3073 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3074 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3075 }
3076
3077 iwl_enable_rfkill_int(priv);
3078
3079 err = iwl_setup_mac(priv);
3080 if (err)
3081 goto out_remove_sysfs;
3082
3083 err = iwl_dbgfs_register(priv, DRV_NAME);
3084 if (err)
3085 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
3086
3087 /* If platform's RF_KILL switch is NOT set to KILL */
3088 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3089 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3090 else
3091 set_bit(STATUS_RF_KILL_HW, &priv->status);
3092
3093 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
3094 test_bit(STATUS_RF_KILL_HW, &priv->status));
3095
3096 iwl_power_initialize(priv);
3097 iwl_tt_initialize(priv);
3098 return 0;
3099
3100 out_remove_sysfs:
3101 destroy_workqueue(priv->workqueue);
3102 priv->workqueue = NULL;
3103 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
3104 out_free_irq:
3105 free_irq(priv->pci_dev->irq, priv);
3106 iwl_free_isr_ict(priv);
3107 out_disable_msi:
3108 pci_disable_msi(priv->pci_dev);
3109 iwl_uninit_drv(priv);
3110 out_free_eeprom:
3111 iwl_eeprom_free(priv);
3112 out_iounmap:
3113 pci_iounmap(pdev, priv->hw_base);
3114 out_pci_release_regions:
3115 pci_set_drvdata(pdev, NULL);
3116 pci_release_regions(pdev);
3117 out_pci_disable_device:
3118 pci_disable_device(pdev);
3119 out_ieee80211_free_hw:
3120 iwl_free_traffic_mem(priv);
3121 ieee80211_free_hw(priv->hw);
3122 out:
3123 return err;
3124 }
3125
3126 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
3127 {
3128 struct iwl_priv *priv = pci_get_drvdata(pdev);
3129 unsigned long flags;
3130
3131 if (!priv)
3132 return;
3133
3134 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
3135
3136 iwl_dbgfs_unregister(priv);
3137 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
3138
3139 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
3140 * to be called and iwl_down since we are removing the device
3141 * we need to set STATUS_EXIT_PENDING bit.
3142 */
3143 set_bit(STATUS_EXIT_PENDING, &priv->status);
3144 if (priv->mac80211_registered) {
3145 ieee80211_unregister_hw(priv->hw);
3146 priv->mac80211_registered = 0;
3147 } else {
3148 iwl_down(priv);
3149 }
3150
3151 iwl_tt_exit(priv);
3152
3153 /* make sure we flush any pending irq or
3154 * tasklet for the driver
3155 */
3156 spin_lock_irqsave(&priv->lock, flags);
3157 iwl_disable_interrupts(priv);
3158 spin_unlock_irqrestore(&priv->lock, flags);
3159
3160 iwl_synchronize_irq(priv);
3161
3162 iwl_dealloc_ucode_pci(priv);
3163
3164 if (priv->rxq.bd)
3165 iwl_rx_queue_free(priv, &priv->rxq);
3166 iwl_hw_txq_ctx_free(priv);
3167
3168 iwl_clear_stations_table(priv);
3169 iwl_eeprom_free(priv);
3170
3171
3172 /*netif_stop_queue(dev); */
3173 flush_workqueue(priv->workqueue);
3174
3175 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
3176 * priv->workqueue... so we can't take down the workqueue
3177 * until now... */
3178 destroy_workqueue(priv->workqueue);
3179 priv->workqueue = NULL;
3180 iwl_free_traffic_mem(priv);
3181
3182 free_irq(priv->pci_dev->irq, priv);
3183 pci_disable_msi(priv->pci_dev);
3184 pci_iounmap(pdev, priv->hw_base);
3185 pci_release_regions(pdev);
3186 pci_disable_device(pdev);
3187 pci_set_drvdata(pdev, NULL);
3188
3189 iwl_uninit_drv(priv);
3190
3191 iwl_free_isr_ict(priv);
3192
3193 if (priv->ibss_beacon)
3194 dev_kfree_skb(priv->ibss_beacon);
3195
3196 ieee80211_free_hw(priv->hw);
3197 }
3198
3199
3200 /*****************************************************************************
3201 *
3202 * driver and module entry point
3203 *
3204 *****************************************************************************/
3205
3206 /* Hardware specific file defines the PCI IDs table for that hardware module */
3207 static struct pci_device_id iwl_hw_card_ids[] = {
3208 #ifdef CONFIG_IWL4965
3209 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
3210 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
3211 #endif /* CONFIG_IWL4965 */
3212 #ifdef CONFIG_IWL5000
3213 /* 5100 Series WiFi */
3214 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
3215 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
3216 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
3217 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
3218 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
3219 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
3220 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
3221 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
3222 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
3223 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
3224 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
3225 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
3226 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
3227 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
3228 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
3229 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
3230 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
3231 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
3232 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
3233 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
3234 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
3235 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
3236 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
3237 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
3238
3239 /* 5300 Series WiFi */
3240 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
3241 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
3242 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
3243 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
3244 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
3245 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
3246 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
3247 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
3248 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
3249 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
3250 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
3251 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
3252
3253 /* 5350 Series WiFi/WiMax */
3254 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
3255 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
3256 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
3257
3258 /* 5150 Series Wifi/WiMax */
3259 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
3260 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
3261 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
3262 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
3263 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
3264 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
3265
3266 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
3267 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
3268 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
3269 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
3270 /* 6000/6050 Series */
3271 {IWL_PCI_DEVICE(0x008D, PCI_ANY_ID, iwl6000h_2agn_cfg)},
3272 {IWL_PCI_DEVICE(0x008E, PCI_ANY_ID, iwl6000h_2agn_cfg)},
3273 {IWL_PCI_DEVICE(0x422B, PCI_ANY_ID, iwl6000_3agn_cfg)},
3274 {IWL_PCI_DEVICE(0x422C, PCI_ANY_ID, iwl6000i_2agn_cfg)},
3275 {IWL_PCI_DEVICE(0x4238, PCI_ANY_ID, iwl6000_3agn_cfg)},
3276 {IWL_PCI_DEVICE(0x4239, PCI_ANY_ID, iwl6000i_2agn_cfg)},
3277 {IWL_PCI_DEVICE(0x0086, PCI_ANY_ID, iwl6050_3agn_cfg)},
3278 {IWL_PCI_DEVICE(0x0087, PCI_ANY_ID, iwl6050_2agn_cfg)},
3279 {IWL_PCI_DEVICE(0x0088, PCI_ANY_ID, iwl6050_3agn_cfg)},
3280 {IWL_PCI_DEVICE(0x0089, PCI_ANY_ID, iwl6050_2agn_cfg)},
3281 /* 1000 Series WiFi */
3282 {IWL_PCI_DEVICE(0x0083, PCI_ANY_ID, iwl1000_bgn_cfg)},
3283 {IWL_PCI_DEVICE(0x0084, PCI_ANY_ID, iwl1000_bgn_cfg)},
3284 #endif /* CONFIG_IWL5000 */
3285
3286 {0}
3287 };
3288 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
3289
3290 static struct pci_driver iwl_driver = {
3291 .name = DRV_NAME,
3292 .id_table = iwl_hw_card_ids,
3293 .probe = iwl_pci_probe,
3294 .remove = __devexit_p(iwl_pci_remove),
3295 #ifdef CONFIG_PM
3296 .suspend = iwl_pci_suspend,
3297 .resume = iwl_pci_resume,
3298 #endif
3299 };
3300
3301 static int __init iwl_init(void)
3302 {
3303
3304 int ret;
3305 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
3306 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
3307
3308 ret = iwlagn_rate_control_register();
3309 if (ret) {
3310 printk(KERN_ERR DRV_NAME
3311 "Unable to register rate control algorithm: %d\n", ret);
3312 return ret;
3313 }
3314
3315 ret = pci_register_driver(&iwl_driver);
3316 if (ret) {
3317 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
3318 goto error_register;
3319 }
3320
3321 return ret;
3322
3323 error_register:
3324 iwlagn_rate_control_unregister();
3325 return ret;
3326 }
3327
3328 static void __exit iwl_exit(void)
3329 {
3330 pci_unregister_driver(&iwl_driver);
3331 iwlagn_rate_control_unregister();
3332 }
3333
3334 module_exit(iwl_exit);
3335 module_init(iwl_init);
3336
3337 #ifdef CONFIG_IWLWIFI_DEBUG
3338 module_param_named(debug50, iwl_debug_level, uint, 0444);
3339 MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
3340 module_param_named(debug, iwl_debug_level, uint, 0644);
3341 MODULE_PARM_DESC(debug, "debug output mask");
3342 #endif
3343
Linux ARM platform port for MOXA ART SoC