?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
code style scripts/checkpatch.pl (linux-3.9-rc1) formatting
[linux-2.6.32.60-moxart.git] / include / linux / pci.h
blobe07d194d0aec34cd73ed54eb092fe25f9dbc13ce
1 /*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17 #ifndef LINUX_PCI_H
18 #define LINUX_PCI_H
19
20 #include <linux/pci_regs.h> /* The pci register defines */
21
22 /*
23 * The PCI interface treats multi-function devices as independent
24 * devices. The slot/function address of each device is encoded
25 * in a single byte as follows:
26 *
27 * 7:3 = slot
28 * 2:0 = function
29 */
30 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
31 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
32 #define PCI_FUNC(devfn) ((devfn) & 0x07)
33
34 /* Ioctls for /proc/bus/pci/X/Y nodes. */
35 #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
36 #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
37 #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
38 #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
39 #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
40
41 #ifdef __KERNEL__
42
43 #include <linux/mod_devicetable.h>
44
45 #include <linux/types.h>
46 #include <linux/init.h>
47 #include <linux/ioport.h>
48 #include <linux/list.h>
49 #include <linux/compiler.h>
50 #include <linux/errno.h>
51 #include <linux/kobject.h>
52 #include <asm/atomic.h>
53 #include <linux/device.h>
54 #include <linux/io.h>
55 #include <linux/irqreturn.h>
56
57 /* Include the ID list */
58 #include <linux/pci_ids.h>
59
60 /* pci_slot represents a physical slot */
61 struct pci_slot {
62 struct pci_bus *bus; /* The bus this slot is on */
63 struct list_head list; /* node in list of slots on this bus */
64 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
65 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
66 struct kobject kobj;
67 };
68
69 static inline const char *pci_slot_name(const struct pci_slot *slot)
70 {
71 return kobject_name(&slot->kobj);
72 }
73
74 /* File state for mmap()s on /proc/bus/pci/X/Y */
75 enum pci_mmap_state {
76 pci_mmap_io,
77 pci_mmap_mem
78 };
79
80 /* This defines the direction arg to the DMA mapping routines. */
81 #define PCI_DMA_BIDIRECTIONAL 0
82 #define PCI_DMA_TODEVICE 1
83 #define PCI_DMA_FROMDEVICE 2
84 #define PCI_DMA_NONE 3
85
86 /*
87 * For PCI devices, the region numbers are assigned this way:
88 */
89 enum {
90 /* #0-5: standard PCI resources */
91 PCI_STD_RESOURCES,
92 PCI_STD_RESOURCE_END = 5,
93
94 /* #6: expansion ROM resource */
95 PCI_ROM_RESOURCE,
96
97 /* device specific resources */
98 #ifdef CONFIG_PCI_IOV
99 PCI_IOV_RESOURCES,
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
101 #endif
102
103 /* resources assigned to buses behind the bridge */
104 #define PCI_BRIDGE_RESOURCE_NUM 4
105
106 PCI_BRIDGE_RESOURCES,
107 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
108 PCI_BRIDGE_RESOURCE_NUM - 1,
109
110 /* total resources associated with a PCI device */
111 PCI_NUM_RESOURCES,
112
113 /* preserve this for compatibility */
114 DEVICE_COUNT_RESOURCE
115 };
116
117 typedef int __bitwise pci_power_t;
118
119 #define PCI_D0 ((pci_power_t __force) 0)
120 #define PCI_D1 ((pci_power_t __force) 1)
121 #define PCI_D2 ((pci_power_t __force) 2)
122 #define PCI_D3hot ((pci_power_t __force) 3)
123 #define PCI_D3cold ((pci_power_t __force) 4)
124 #define PCI_UNKNOWN ((pci_power_t __force) 5)
125 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
126
127 /* Remember to update this when the list above changes! */
128 extern const char *pci_power_names[];
129
130 static inline const char *pci_power_name(pci_power_t state)
131 {
132 return pci_power_names[1 + (int) state];
133 }
134
135 #define PCI_PM_D2_DELAY 200
136 #define PCI_PM_D3_WAIT 10
137 #define PCI_PM_BUS_WAIT 50
138
139 /** The pci_channel state describes connectivity between the CPU and
140 * the pci device. If some PCI bus between here and the pci device
141 * has crashed or locked up, this info is reflected here.
142 */
143 typedef unsigned int __bitwise pci_channel_state_t;
144
145 enum pci_channel_state {
146 /* I/O channel is in normal state */
147 pci_channel_io_normal = (__force pci_channel_state_t) 1,
148
149 /* I/O to channel is blocked */
150 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
151
152 /* PCI card is dead */
153 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
154 };
155
156 typedef unsigned int __bitwise pcie_reset_state_t;
157
158 enum pcie_reset_state {
159 /* Reset is NOT asserted (Use to deassert reset) */
160 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
161
162 /* Use #PERST to reset PCI-E device */
163 pcie_warm_reset = (__force pcie_reset_state_t) 2,
164
165 /* Use PCI-E Hot Reset to reset device */
166 pcie_hot_reset = (__force pcie_reset_state_t) 3
167 };
168
169 typedef unsigned short __bitwise pci_dev_flags_t;
170 enum pci_dev_flags {
171 /* INTX_DISABLE in PCI_COMMAND register disables MSI
172 * generation too.
173 */
174 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
175 /* Device configuration is irrevocably lost if disabled into D3 */
176 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
177 };
178
179 enum pci_irq_reroute_variant {
180 INTEL_IRQ_REROUTE_VARIANT = 1,
181 MAX_IRQ_REROUTE_VARIANTS = 3
182 };
183
184 typedef unsigned short __bitwise pci_bus_flags_t;
185 enum pci_bus_flags {
186 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
187 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
188 };
189
190 struct pci_cap_saved_state {
191 struct hlist_node next;
192 char cap_nr;
193 u32 data[0];
194 };
195
196 struct pcie_link_state;
197 struct pci_vpd;
198 struct pci_sriov;
199 struct pci_ats;
200
201 /*
202 * The pci_dev structure is used to describe PCI devices.
203 */
204 struct pci_dev {
205 struct list_head bus_list; /* node in per-bus list */
206 struct pci_bus *bus; /* bus this device is on */
207 struct pci_bus *subordinate; /* bus this device bridges to */
208
209 void *sysdata; /* hook for sys-specific extension */
210 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
211 struct pci_slot *slot; /* Physical slot this device is in */
212
213 unsigned int devfn; /* encoded device & function index */
214 unsigned short vendor;
215 unsigned short device;
216 unsigned short subsystem_vendor;
217 unsigned short subsystem_device;
218 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
219 u8 revision; /* PCI revision, low byte of class word */
220 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
221 u8 pcie_type; /* PCI-E device/port type */
222 u8 rom_base_reg; /* which config register controls the ROM */
223 u8 pin; /* which interrupt pin this device uses */
224
225 struct pci_driver *driver; /* which driver has allocated this device */
226 u64 dma_mask; /* Mask of the bits of bus address this
227 device implements. Normally this is
228 0xffffffff. You only need to change
229 this if your device has broken DMA
230 or supports 64-bit transfers. */
231
232 struct device_dma_parameters dma_parms;
233
234 pci_power_t current_state; /* Current operating state. In ACPI-speak,
235 this is D0-D3, D0 being fully functional,
236 and D3 being off. */
237 int pm_cap; /* PM capability offset in the
238 configuration space */
239 unsigned int pme_support:5; /* Bitmask of states from which PME#
240 can be generated */
241 unsigned int d1_support:1; /* Low power state D1 is supported */
242 unsigned int d2_support:1; /* Low power state D2 is supported */
243 unsigned int no_d1d2:1; /* Only allow D0 and D3 */
244 unsigned int wakeup_prepared:1;
245
246 #ifdef CONFIG_PCIEASPM
247 struct pcie_link_state *link_state; /* ASPM link state. */
248 #endif
249
250 pci_channel_state_t error_state; /* current connectivity state */
251 struct device dev; /* Generic device interface */
252
253 int cfg_size; /* Size of configuration space */
254
255 /*
256 * Instead of touching interrupt line and base address registers
257 * directly, use the values stored here. They might be different!
258 */
259 unsigned int irq;
260 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
261
262 /* These fields are used by common fixups */
263 unsigned int transparent:1; /* Transparent PCI bridge */
264 unsigned int multifunction:1;/* Part of multi-function device */
265 /* keep track of device state */
266 unsigned int is_added:1;
267 unsigned int is_busmaster:1; /* device is busmaster */
268 unsigned int no_msi:1; /* device may not use msi */
269 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
270 unsigned int broken_parity_status:1; /* Device generates false positive parity */
271 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
272 unsigned int msi_enabled:1;
273 unsigned int msix_enabled:1;
274 unsigned int ari_enabled:1; /* ARI forwarding */
275 unsigned int is_managed:1;
276 unsigned int is_pcie:1;
277 unsigned int needs_freset:1; /* Dev requires fundamental reset */
278 unsigned int state_saved:1;
279 unsigned int is_physfn:1;
280 unsigned int is_virtfn:1;
281 unsigned int reset_fn:1;
282 unsigned int is_hotplug_bridge:1;
283 pci_dev_flags_t dev_flags;
284 atomic_t enable_cnt; /* pci_enable_device has been called */
285
286 u32 saved_config_space[16]; /* config space saved at suspend time */
287 struct hlist_head saved_cap_space;
288 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
289 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
290 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
291 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
292 #ifdef CONFIG_PCI_MSI
293 struct list_head msi_list;
294 #endif
295 struct pci_vpd *vpd;
296 #ifdef CONFIG_PCI_IOV
297 union {
298 struct pci_sriov *sriov; /* SR-IOV capability related */
299 struct pci_dev *physfn; /* the PF this VF is associated with */
300 };
301 struct pci_ats *ats; /* Address Translation Service */
302 #endif
303 };
304
305 extern struct pci_dev *alloc_pci_dev(void);
306
307 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
308 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
309 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
310
311 static inline int pci_channel_offline(struct pci_dev *pdev)
312 {
313 return (pdev->error_state != pci_channel_io_normal);
314 }
315
316 static inline struct pci_cap_saved_state *pci_find_saved_cap(
317 struct pci_dev *pci_dev, char cap)
318 {
319 struct pci_cap_saved_state *tmp;
320 struct hlist_node *pos;
321
322 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
323 if (tmp->cap_nr == cap)
324 return tmp;
325 }
326 return NULL;
327 }
328
329 static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
330 struct pci_cap_saved_state *new_cap)
331 {
332 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
333 }
334
335 #ifndef PCI_BUS_NUM_RESOURCES
336 #define PCI_BUS_NUM_RESOURCES 16
337 #endif
338
339 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
340
341 struct pci_bus {
342 struct list_head node; /* node in list of buses */
343 struct pci_bus *parent; /* parent bus this bridge is on */
344 struct list_head children; /* list of child buses */
345 struct list_head devices; /* list of devices on this bus */
346 struct pci_dev *self; /* bridge device as seen by parent */
347 struct list_head slots; /* list of slots on this bus */
348 struct resource *resource[PCI_BUS_NUM_RESOURCES];
349 /* address space routed to this bus */
350
351 struct pci_ops *ops; /* configuration access functions */
352 void *sysdata; /* hook for sys-specific extension */
353 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
354
355 unsigned char number; /* bus number */
356 unsigned char primary; /* number of primary bridge */
357 unsigned char secondary; /* number of secondary bridge */
358 unsigned char subordinate; /* max number of subordinate buses */
359
360 char name[48];
361
362 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
363 pci_bus_flags_t bus_flags; /* Inherited by child busses */
364 struct device *bridge;
365 struct device dev;
366 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
367 struct bin_attribute *legacy_mem; /* legacy mem */
368 unsigned int is_added:1;
369 };
370
371 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
372 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
373
374 /*
375 * Returns true if the pci bus is root (behind host-pci bridge),
376 * false otherwise
377 */
378 static inline bool pci_is_root_bus(struct pci_bus *pbus)
379 {
380 return !(pbus->parent);
381 }
382
383 #ifdef CONFIG_PCI_MSI
384 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
385 {
386 return pci_dev->msi_enabled || pci_dev->msix_enabled;
387 }
388 #else
389 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
390 #endif
391
392 /*
393 * Error values that may be returned by PCI functions.
394 */
395 #define PCIBIOS_SUCCESSFUL 0x00
396 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
397 #define PCIBIOS_BAD_VENDOR_ID 0x83
398 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
399 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
400 #define PCIBIOS_SET_FAILED 0x88
401 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
402
403 /* Low-level architecture-dependent routines */
404
405 struct pci_ops {
406 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
407 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
408 };
409
410 /*
411 * ACPI needs to be able to access PCI config space before we've done a
412 * PCI bus scan and created pci_bus structures.
413 */
414 extern int raw_pci_read(unsigned int domain, unsigned int bus,
415 unsigned int devfn, int reg, int len, u32 *val);
416 extern int raw_pci_write(unsigned int domain, unsigned int bus,
417 unsigned int devfn, int reg, int len, u32 val);
418
419 struct pci_bus_region {
420 resource_size_t start;
421 resource_size_t end;
422 };
423
424 struct pci_dynids {
425 spinlock_t lock; /* protects list, index */
426 struct list_head list; /* for IDs added at runtime */
427 };
428
429 /* ---------------------------------------------------------------- */
430 /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
431 * a set of callbacks in struct pci_error_handlers, then that device driver
432 * will be notified of PCI bus errors, and will be driven to recovery
433 * when an error occurs.
434 */
435
436 typedef unsigned int __bitwise pci_ers_result_t;
437
438 enum pci_ers_result {
439 /* no result/none/not supported in device driver */
440 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
441
442 /* Device driver can recover without slot reset */
443 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
444
445 /* Device driver wants slot to be reset. */
446 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
447
448 /* Device has completely failed, is unrecoverable */
449 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
450
451 /* Device driver is fully recovered and operational */
452 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
453 };
454
455 /* PCI bus error event callbacks */
456 struct pci_error_handlers {
457 /* PCI bus error detected on this device */
458 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
459 enum pci_channel_state error);
460
461 /* MMIO has been re-enabled, but not DMA */
462 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
463
464 /* PCI Express link has been reset */
465 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
466
467 /* PCI slot has been reset */
468 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
469
470 /* Device driver may resume normal operations */
471 void (*resume)(struct pci_dev *dev);
472 };
473
474 /* ---------------------------------------------------------------- */
475
476 struct module;
477 struct pci_driver {
478 struct list_head node;
479 char *name;
480 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
481 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
482 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
483 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
484 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
485 int (*resume_early) (struct pci_dev *dev);
486 int (*resume) (struct pci_dev *dev); /* Device woken up */
487 void (*shutdown) (struct pci_dev *dev);
488 struct pci_error_handlers *err_handler;
489 struct device_driver driver;
490 struct pci_dynids dynids;
491 };
492
493 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
494
495 /**
496 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
497 * @_table: device table name
498 *
499 * This macro is used to create a struct pci_device_id array (a device table)
500 * in a generic manner.
501 */
502 #define DEFINE_PCI_DEVICE_TABLE(_table) \
503 const struct pci_device_id _table[] __devinitconst
504
505 /**
506 * PCI_DEVICE - macro used to describe a specific pci device
507 * @vend: the 16 bit PCI Vendor ID
508 * @dev: the 16 bit PCI Device ID
509 *
510 * This macro is used to create a struct pci_device_id that matches a
511 * specific device. The subvendor and subdevice fields will be set to
512 * PCI_ANY_ID.
513 */
514 #define PCI_DEVICE(vend,dev) \
515 .vendor = (vend), .device = (dev), \
516 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
517
518 /**
519 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
520 * @dev_class: the class, subclass, prog-if triple for this device
521 * @dev_class_mask: the class mask for this device
522 *
523 * This macro is used to create a struct pci_device_id that matches a
524 * specific PCI class. The vendor, device, subvendor, and subdevice
525 * fields will be set to PCI_ANY_ID.
526 */
527 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
528 .class = (dev_class), .class_mask = (dev_class_mask), \
529 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
530 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
531
532 /**
533 * PCI_VDEVICE - macro used to describe a specific pci device in short form
534 * @vendor: the vendor name
535 * @device: the 16 bit PCI Device ID
536 *
537 * This macro is used to create a struct pci_device_id that matches a
538 * specific PCI device. The subvendor, and subdevice fields will be set
539 * to PCI_ANY_ID. The macro allows the next field to follow as the device
540 * private data.
541 */
542
543 #define PCI_VDEVICE(vendor, device) \
544 PCI_VENDOR_ID_##vendor, (device), \
545 PCI_ANY_ID, PCI_ANY_ID, 0, 0
546
547 /* these external functions are only available when PCI support is enabled */
548 #ifdef CONFIG_PCI
549
550 extern struct bus_type pci_bus_type;
551
552 /* Do NOT directly access these two variables, unless you are arch specific pci
553 * code, or pci core code. */
554 extern struct list_head pci_root_buses; /* list of all known PCI buses */
555 /* Some device drivers need know if pci is initiated */
556 extern int no_pci_devices(void);
557
558 void pcibios_fixup_bus(struct pci_bus *);
559 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
560 char *pcibios_setup(char *str);
561
562 /* Used only when drivers/pci/setup.c is used */
563 void pcibios_align_resource(void *, struct resource *, resource_size_t,
564 resource_size_t);
565 void pcibios_update_irq(struct pci_dev *, int irq);
566
567 /* Weak but can be overriden by arch */
568 void pci_fixup_cardbus(struct pci_bus *);
569
570 /* Generic PCI functions used internally */
571
572 extern struct pci_bus *pci_find_bus(int domain, int busnr);
573 void pci_bus_add_devices(const struct pci_bus *bus);
574 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
575 struct pci_ops *ops, void *sysdata);
576 static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops,
577 void *sysdata)
578 {
579 struct pci_bus *root_bus;
580 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
581 if (root_bus)
582 pci_bus_add_devices(root_bus);
583 return root_bus;
584 }
585 struct pci_bus *pci_create_bus(struct device *parent, int bus,
586 struct pci_ops *ops, void *sysdata);
587 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
588 int busnr);
589 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
590 const char *name,
591 struct hotplug_slot *hotplug);
592 void pci_destroy_slot(struct pci_slot *slot);
593 void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
594 int pci_scan_slot(struct pci_bus *bus, int devfn);
595 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
596 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
597 unsigned int pci_scan_child_bus(struct pci_bus *bus);
598 int __must_check pci_bus_add_device(struct pci_dev *dev);
599 void pci_read_bridge_bases(struct pci_bus *child);
600 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
601 struct resource *res);
602 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin);
603 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
604 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
605 extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
606 extern void pci_dev_put(struct pci_dev *dev);
607 extern void pci_remove_bus(struct pci_bus *b);
608 extern void pci_remove_bus_device(struct pci_dev *dev);
609 extern void pci_stop_bus_device(struct pci_dev *dev);
610 void pci_setup_cardbus(struct pci_bus *bus);
611 extern void pci_sort_breadthfirst(void);
612
613 /* Generic PCI functions exported to card drivers */
614
615 #ifdef CONFIG_PCI_LEGACY
616 struct pci_dev __deprecated *pci_find_device(unsigned int vendor,
617 unsigned int device,
618 struct pci_dev *from);
619 #endif /* CONFIG_PCI_LEGACY */
620
621 enum pci_lost_interrupt_reason {
622 PCI_LOST_IRQ_NO_INFORMATION = 0,
623 PCI_LOST_IRQ_DISABLE_MSI,
624 PCI_LOST_IRQ_DISABLE_MSIX,
625 PCI_LOST_IRQ_DISABLE_ACPI,
626 };
627 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
628 int pci_find_capability(struct pci_dev *dev, int cap);
629 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
630 int pci_find_ext_capability(struct pci_dev *dev, int cap);
631 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
632 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
633 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
634
635 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
636 struct pci_dev *from);
637 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
638 unsigned int ss_vendor, unsigned int ss_device,
639 struct pci_dev *from);
640 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
641 struct pci_dev *pci_get_bus_and_slot(unsigned int bus, unsigned int devfn);
642 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
643 int pci_dev_present(const struct pci_device_id *ids);
644
645 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
646 int where, u8 *val);
647 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
648 int where, u16 *val);
649 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
650 int where, u32 *val);
651 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
652 int where, u8 val);
653 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
654 int where, u16 val);
655 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
656 int where, u32 val);
657 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
658
659 static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
660 {
661 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
662 }
663 static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
664 {
665 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
666 }
667 static inline int pci_read_config_dword(struct pci_dev *dev, int where,
668 u32 *val)
669 {
670 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
671 }
672 static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
673 {
674 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
675 }
676 static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
677 {
678 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
679 }
680 static inline int pci_write_config_dword(struct pci_dev *dev, int where,
681 u32 val)
682 {
683 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
684 }
685
686 int __must_check pci_enable_device(struct pci_dev *dev);
687 int __must_check pci_enable_device_io(struct pci_dev *dev);
688 int __must_check pci_enable_device_mem(struct pci_dev *dev);
689 int __must_check pci_reenable_device(struct pci_dev *);
690 int __must_check pcim_enable_device(struct pci_dev *pdev);
691 void pcim_pin_device(struct pci_dev *pdev);
692
693 static inline int pci_is_enabled(struct pci_dev *pdev)
694 {
695 return (atomic_read(&pdev->enable_cnt) > 0);
696 }
697
698 static inline int pci_is_managed(struct pci_dev *pdev)
699 {
700 return pdev->is_managed;
701 }
702
703 void pci_disable_device(struct pci_dev *dev);
704 void pci_set_master(struct pci_dev *dev);
705 void pci_clear_master(struct pci_dev *dev);
706 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
707 #define HAVE_PCI_SET_MWI
708 int __must_check pci_set_mwi(struct pci_dev *dev);
709 int pci_try_set_mwi(struct pci_dev *dev);
710 void pci_clear_mwi(struct pci_dev *dev);
711 void pci_intx(struct pci_dev *dev, int enable);
712 void pci_msi_off(struct pci_dev *dev);
713 int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
714 int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask);
715 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
716 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
717 int pcix_get_max_mmrbc(struct pci_dev *dev);
718 int pcix_get_mmrbc(struct pci_dev *dev);
719 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
720 int pcie_get_readrq(struct pci_dev *dev);
721 int pcie_set_readrq(struct pci_dev *dev, int rq);
722 int __pci_reset_function(struct pci_dev *dev);
723 int pci_reset_function(struct pci_dev *dev);
724 void pci_update_resource(struct pci_dev *dev, int resno);
725 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
726 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
727
728 /* ROM control related routines */
729 int pci_enable_rom(struct pci_dev *pdev);
730 void pci_disable_rom(struct pci_dev *pdev);
731 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
732 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
733 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
734
735 /* Power management related routines */
736 int pci_save_state(struct pci_dev *dev);
737 int pci_restore_state(struct pci_dev *dev);
738 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
739 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
740 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
741 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
742 void pci_pme_active(struct pci_dev *dev, bool enable);
743 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
744 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
745 pci_power_t pci_target_state(struct pci_dev *dev);
746 int pci_prepare_to_sleep(struct pci_dev *dev);
747 int pci_back_from_sleep(struct pci_dev *dev);
748
749 /* Functions for PCI Hotplug drivers to use */
750 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
751 #ifdef CONFIG_HOTPLUG
752 unsigned int pci_rescan_bus(struct pci_bus *bus);
753 #endif
754
755 /* Vital product data routines */
756 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
757 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
758 int pci_vpd_truncate(struct pci_dev *dev, size_t size);
759
760 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
761 void pci_bus_assign_resources(const struct pci_bus *bus);
762 void pci_bus_size_bridges(struct pci_bus *bus);
763 int pci_claim_resource(struct pci_dev *, int);
764 void pci_assign_unassigned_resources(void);
765 void pdev_enable_device(struct pci_dev *);
766 void pdev_sort_resources(struct pci_dev *, struct resource_list *);
767 int pci_enable_resources(struct pci_dev *, int mask);
768 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
769 int (*)(struct pci_dev *, u8, u8));
770 #define HAVE_PCI_REQ_REGIONS 2
771 int __must_check pci_request_regions(struct pci_dev *, const char *);
772 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
773 void pci_release_regions(struct pci_dev *);
774 int __must_check pci_request_region(struct pci_dev *, int, const char *);
775 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
776 void pci_release_region(struct pci_dev *, int);
777 int pci_request_selected_regions(struct pci_dev *, int, const char *);
778 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
779 void pci_release_selected_regions(struct pci_dev *, int);
780
781 /* drivers/pci/bus.c */
782 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
783 struct resource *res, resource_size_t size,
784 resource_size_t align, resource_size_t min,
785 unsigned int type_mask,
786 void (*alignf)(void *, struct resource *,
787 resource_size_t, resource_size_t),
788 void *alignf_data);
789 void pci_enable_bridges(struct pci_bus *bus);
790
791 /* Proper probing supporting hot-pluggable devices */
792 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
793 const char *mod_name);
794
795 /*
796 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
797 */
798 #define pci_register_driver(driver) \
799 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
800
801 void pci_unregister_driver(struct pci_driver *dev);
802 void pci_remove_behind_bridge(struct pci_dev *dev);
803 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
804 int pci_add_dynid(struct pci_driver *drv,
805 unsigned int vendor, unsigned int device,
806 unsigned int subvendor, unsigned int subdevice,
807 unsigned int class, unsigned int class_mask,
808 unsigned long driver_data);
809 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
810 struct pci_dev *dev);
811 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
812 int pass);
813
814 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
815 void *userdata);
816 int pci_cfg_space_size_ext(struct pci_dev *dev);
817 int pci_cfg_space_size(struct pci_dev *dev);
818 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
819
820 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
821 unsigned int command_bits, bool change_bridge);
822 /* kmem_cache style wrapper around pci_alloc_consistent() */
823
824 #include <linux/dmapool.h>
825
826 #define pci_pool dma_pool
827 #define pci_pool_create(name, pdev, size, align, allocation) \
828 dma_pool_create(name, &pdev->dev, size, align, allocation)
829 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
830 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
831 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
832
833 enum pci_dma_burst_strategy {
834 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
835 strategy_parameter is N/A */
836 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
837 byte boundaries */
838 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
839 strategy_parameter byte boundaries */
840 };
841
842 struct msix_entry {
843 u32 vector; /* kernel uses to write allocated vector */
844 u16 entry; /* driver uses to specify entry, OS writes */
845 };
846
847
848 #ifndef CONFIG_PCI_MSI
849 static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
850 {
851 return -1;
852 }
853
854 static inline void pci_msi_shutdown(struct pci_dev *dev)
855 { }
856 static inline void pci_disable_msi(struct pci_dev *dev)
857 { }
858
859 static inline int pci_msix_table_size(struct pci_dev *dev)
860 {
861 return 0;
862 }
863 static inline int pci_enable_msix(struct pci_dev *dev,
864 struct msix_entry *entries, int nvec)
865 {
866 return -1;
867 }
868
869 static inline void pci_msix_shutdown(struct pci_dev *dev)
870 { }
871 static inline void pci_disable_msix(struct pci_dev *dev)
872 { }
873
874 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
875 { }
876
877 static inline void pci_restore_msi_state(struct pci_dev *dev)
878 { }
879 static inline int pci_msi_enabled(void)
880 {
881 return 0;
882 }
883 #else
884 extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
885 extern void pci_msi_shutdown(struct pci_dev *dev);
886 extern void pci_disable_msi(struct pci_dev *dev);
887 extern int pci_msix_table_size(struct pci_dev *dev);
888 extern int pci_enable_msix(struct pci_dev *dev,
889 struct msix_entry *entries, int nvec);
890 extern void pci_msix_shutdown(struct pci_dev *dev);
891 extern void pci_disable_msix(struct pci_dev *dev);
892 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
893 extern void pci_restore_msi_state(struct pci_dev *dev);
894 extern int pci_msi_enabled(void);
895 #endif
896
897 #ifndef CONFIG_PCIEASPM
898 static inline int pcie_aspm_enabled(void)
899 {
900 return 0;
901 }
902 #else
903 extern int pcie_aspm_enabled(void);
904 #endif
905
906 #ifndef CONFIG_PCIE_ECRC
907 static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
908 {
909 return;
910 }
911 static inline void pcie_ecrc_get_policy(char *str) {};
912 #else
913 extern void pcie_set_ecrc_checking(struct pci_dev *dev);
914 extern void pcie_ecrc_get_policy(char *str);
915 #endif
916
917 #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
918
919 #ifdef CONFIG_HT_IRQ
920 /* The functions a driver should call */
921 int ht_create_irq(struct pci_dev *dev, int idx);
922 void ht_destroy_irq(unsigned int irq);
923 #endif /* CONFIG_HT_IRQ */
924
925 extern void pci_block_user_cfg_access(struct pci_dev *dev);
926 extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
927
928 /*
929 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
930 * a PCI domain is defined to be a set of PCI busses which share
931 * configuration space.
932 */
933 #ifdef CONFIG_PCI_DOMAINS
934 extern int pci_domains_supported;
935 #else
936 enum { pci_domains_supported = 0 };
937 static inline int pci_domain_nr(struct pci_bus *bus)
938 {
939 return 0;
940 }
941
942 static inline int pci_proc_domain(struct pci_bus *bus)
943 {
944 return 0;
945 }
946 #endif /* CONFIG_PCI_DOMAINS */
947
948 /* some architectures require additional setup to direct VGA traffic */
949 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
950 unsigned int command_bits, bool change_bridge);
951 extern void pci_register_set_vga_state(arch_set_vga_state_t func);
952
953 #else /* CONFIG_PCI is not enabled */
954
955 /*
956 * If the system does not have PCI, clearly these return errors. Define
957 * these as simple inline functions to avoid hair in drivers.
958 */
959
960 #define _PCI_NOP(o, s, t) \
961 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
962 int where, t val) \
963 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
964
965 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
966 _PCI_NOP(o, word, u16 x) \
967 _PCI_NOP(o, dword, u32 x)
968 _PCI_NOP_ALL(read, *)
969 _PCI_NOP_ALL(write,)
970
971 static inline struct pci_dev *pci_find_device(unsigned int vendor,
972 unsigned int device,
973 struct pci_dev *from)
974 {
975 return NULL;
976 }
977
978 static inline struct pci_dev *pci_get_device(unsigned int vendor,
979 unsigned int device,
980 struct pci_dev *from)
981 {
982 return NULL;
983 }
984
985 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
986 unsigned int device,
987 unsigned int ss_vendor,
988 unsigned int ss_device,
989 struct pci_dev *from)
990 {
991 return NULL;
992 }
993
994 static inline struct pci_dev *pci_get_class(unsigned int class,
995 struct pci_dev *from)
996 {
997 return NULL;
998 }
999
1000 #define pci_dev_present(ids) (0)
1001 #define no_pci_devices() (1)
1002 #define pci_dev_put(dev) do { } while (0)
1003
1004 static inline void pci_set_master(struct pci_dev *dev)
1005 { }
1006
1007 static inline int pci_enable_device(struct pci_dev *dev)
1008 {
1009 return -EIO;
1010 }
1011
1012 static inline void pci_disable_device(struct pci_dev *dev)
1013 { }
1014
1015 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1016 {
1017 return -EIO;
1018 }
1019
1020 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1021 {
1022 return -EIO;
1023 }
1024
1025 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1026 unsigned int size)
1027 {
1028 return -EIO;
1029 }
1030
1031 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1032 unsigned long mask)
1033 {
1034 return -EIO;
1035 }
1036
1037 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1038 {
1039 return -EBUSY;
1040 }
1041
1042 static inline int __pci_register_driver(struct pci_driver *drv,
1043 struct module *owner)
1044 {
1045 return 0;
1046 }
1047
1048 static inline int pci_register_driver(struct pci_driver *drv)
1049 {
1050 return 0;
1051 }
1052
1053 static inline void pci_unregister_driver(struct pci_driver *drv)
1054 { }
1055
1056 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1057 {
1058 return 0;
1059 }
1060
1061 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1062 int cap)
1063 {
1064 return 0;
1065 }
1066
1067 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1068 {
1069 return 0;
1070 }
1071
1072 /* Power management related routines */
1073 static inline int pci_save_state(struct pci_dev *dev)
1074 {
1075 return 0;
1076 }
1077
1078 static inline int pci_restore_state(struct pci_dev *dev)
1079 {
1080 return 0;
1081 }
1082
1083 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1084 {
1085 return 0;
1086 }
1087
1088 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1089 pm_message_t state)
1090 {
1091 return PCI_D0;
1092 }
1093
1094 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1095 int enable)
1096 {
1097 return 0;
1098 }
1099
1100 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1101 {
1102 return -EIO;
1103 }
1104
1105 static inline void pci_release_regions(struct pci_dev *dev)
1106 { }
1107
1108 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1109
1110 static inline void pci_block_user_cfg_access(struct pci_dev *dev)
1111 { }
1112
1113 static inline void pci_unblock_user_cfg_access(struct pci_dev *dev)
1114 { }
1115
1116 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1117 { return NULL; }
1118
1119 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1120 unsigned int devfn)
1121 { return NULL; }
1122
1123 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1124 unsigned int devfn)
1125 { return NULL; }
1126
1127 #endif /* CONFIG_PCI */
1128
1129 /* Include architecture-dependent settings and functions */
1130
1131 #include <asm/pci.h>
1132
1133 #ifndef PCIBIOS_MAX_MEM_32
1134 #define PCIBIOS_MAX_MEM_32 (-1)
1135 #endif
1136
1137 /* these helpers provide future and backwards compatibility
1138 * for accessing popular PCI BAR info */
1139 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1140 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1141 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1142 #define pci_resource_len(dev,bar) \
1143 ((pci_resource_start((dev), (bar)) == 0 && \
1144 pci_resource_end((dev), (bar)) == \
1145 pci_resource_start((dev), (bar))) ? 0 : \
1146 \
1147 (pci_resource_end((dev), (bar)) - \
1148 pci_resource_start((dev), (bar)) + 1))
1149
1150 /* Similar to the helpers above, these manipulate per-pci_dev
1151 * driver-specific data. They are really just a wrapper around
1152 * the generic device structure functions of these calls.
1153 */
1154 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1155 {
1156 return dev_get_drvdata(&pdev->dev);
1157 }
1158
1159 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1160 {
1161 dev_set_drvdata(&pdev->dev, data);
1162 }
1163
1164 /* If you want to know what to call your pci_dev, ask this function.
1165 * Again, it's a wrapper around the generic device.
1166 */
1167 static inline const char *pci_name(const struct pci_dev *pdev)
1168 {
1169 return dev_name(&pdev->dev);
1170 }
1171
1172
1173 /* Some archs don't want to expose struct resource to userland as-is
1174 * in sysfs and /proc
1175 */
1176 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1177 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1178 const struct resource *rsrc, resource_size_t *start,
1179 resource_size_t *end)
1180 {
1181 *start = rsrc->start;
1182 *end = rsrc->end;
1183 }
1184 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1185
1186
1187 /*
1188 * The world is not perfect and supplies us with broken PCI devices.
1189 * For at least a part of these bugs we need a work-around, so both
1190 * generic (drivers/pci/quirks.c) and per-architecture code can define
1191 * fixup hooks to be called for particular buggy devices.
1192 */
1193
1194 struct pci_fixup {
1195 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
1196 void (*hook)(struct pci_dev *dev);
1197 };
1198
1199 enum pci_fixup_pass {
1200 pci_fixup_early, /* Before probing BARs */
1201 pci_fixup_header, /* After reading configuration header */
1202 pci_fixup_final, /* Final phase of device fixups */
1203 pci_fixup_enable, /* pci_enable_device() time */
1204 pci_fixup_resume, /* pci_device_resume() */
1205 pci_fixup_suspend, /* pci_device_suspend */
1206 pci_fixup_resume_early, /* pci_device_resume_early() */
1207 };
1208
1209 /* Anonymous variables would be nice... */
1210 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
1211 static const struct pci_fixup __pci_fixup_##name __used \
1212 __attribute__((__section__(#section))) = { vendor, device, hook };
1213 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1214 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1215 vendor##device##hook, vendor, device, hook)
1216 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1217 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1218 vendor##device##hook, vendor, device, hook)
1219 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1220 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1221 vendor##device##hook, vendor, device, hook)
1222 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1223 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1224 vendor##device##hook, vendor, device, hook)
1225 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1226 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1227 resume##vendor##device##hook, vendor, device, hook)
1228 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1229 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1230 resume_early##vendor##device##hook, vendor, device, hook)
1231 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1232 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1233 suspend##vendor##device##hook, vendor, device, hook)
1234
1235
1236 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1237
1238 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1239 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1240 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1241 int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name);
1242 int pcim_iomap_regions_request_all(struct pci_dev *pdev, u16 mask,
1243 const char *name);
1244 void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask);
1245
1246 extern int pci_pci_problems;
1247 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1248 #define PCIPCI_TRITON 2
1249 #define PCIPCI_NATOMA 4
1250 #define PCIPCI_VIAETBF 8
1251 #define PCIPCI_VSFX 16
1252 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1253 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1254
1255 extern unsigned long pci_cardbus_io_size;
1256 extern unsigned long pci_cardbus_mem_size;
1257
1258 extern unsigned long pci_hotplug_io_size;
1259 extern unsigned long pci_hotplug_mem_size;
1260
1261 int pcibios_add_platform_entries(struct pci_dev *dev);
1262 void pcibios_disable_device(struct pci_dev *dev);
1263 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1264 enum pcie_reset_state state);
1265
1266 #ifdef CONFIG_PCI_MMCONFIG
1267 extern void __init pci_mmcfg_early_init(void);
1268 extern void __init pci_mmcfg_late_init(void);
1269 #else
1270 static inline void pci_mmcfg_early_init(void) { }
1271 static inline void pci_mmcfg_late_init(void) { }
1272 #endif
1273
1274 int pci_ext_cfg_avail(struct pci_dev *dev);
1275
1276 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1277
1278 #ifdef CONFIG_PCI_IOV
1279 extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1280 extern void pci_disable_sriov(struct pci_dev *dev);
1281 extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
1282 #else
1283 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1284 {
1285 return -ENODEV;
1286 }
1287 static inline void pci_disable_sriov(struct pci_dev *dev)
1288 {
1289 }
1290 static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1291 {
1292 return IRQ_NONE;
1293 }
1294 #endif
1295
1296 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1297 extern void pci_hp_create_module_link(struct pci_slot *pci_slot);
1298 extern void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1299 #endif
1300
1301 #endif /* __KERNEL__ */
1302 #endif /* LINUX_PCI_H */
Linux ARM platform port for MOXA ART SoC