arch/arm/mach-omap/fpga.c

   1 /*
   2  * linux/arch/arm/mach-omap/fpga.c
   3  *
   4  * Interrupt handler for OMAP-1510 Innovator FPGA
   5  *
   6  * Copyright (C) 2001 RidgeRun, Inc.
   7  * Author: Greg Lonnon <glonnon@ridgerun.com>
   8  *
   9  * Copyright (C) 2002 MontaVista Software, Inc.
  10  *
  11  * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
  12  * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License version 2 as
  16  * published by the Free Software Foundation.
  17  */
  18
  19 #include <linux/config.h>
  20 #include <linux/types.h>
  21 #include <linux/init.h>
  22 #include <linux/kernel.h>
  23 #include <linux/device.h>
  24 #include <linux/errno.h>
  25
  26 #include <asm/hardware.h>
  27 #include <asm/io.h>
  28 #include <asm/irq.h>
  29 #include <asm/mach/irq.h>
  30
  31 #include <asm/arch/fpga.h>
  32 #include <asm/arch/gpio.h>
  33
  34 static void fpga_mask_irq(unsigned int irq)
  35 {
  36         irq -= OMAP1510_IH_FPGA_BASE;
  37
  38         if (irq < 8)
  39                 __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO)
  40                               & ~(1 << irq)), OMAP1510_FPGA_IMR_LO);
  41         else if (irq < 16)
  42                 __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_HI)
  43                               & ~(1 << (irq - 8))), OMAP1510_FPGA_IMR_HI);
  44         else
  45                 __raw_writeb((__raw_readb(INNOVATOR_FPGA_IMR2)
  46                               & ~(1 << (irq - 16))), INNOVATOR_FPGA_IMR2);
  47 }
  48
  49
  50 static inline u32 get_fpga_unmasked_irqs(void)
  51 {
  52         return
  53                 ((__raw_readb(OMAP1510_FPGA_ISR_LO) &
  54                   __raw_readb(OMAP1510_FPGA_IMR_LO))) |
  55                 ((__raw_readb(OMAP1510_FPGA_ISR_HI) &
  56                   __raw_readb(OMAP1510_FPGA_IMR_HI)) << 8) |
  57                 ((__raw_readb(INNOVATOR_FPGA_ISR2) &
  58                   __raw_readb(INNOVATOR_FPGA_IMR2)) << 16);
  59 }
  60
  61
  62 static void fpga_ack_irq(unsigned int irq)
  63 {
  64         /* Don't need to explicitly ACK FPGA interrupts */
  65 }
  66
  67 static void fpga_unmask_irq(unsigned int irq)
  68 {
  69         irq -= OMAP1510_IH_FPGA_BASE;
  70
  71         if (irq < 8)
  72                 __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO) | (1 << irq)),
  73                      OMAP1510_FPGA_IMR_LO);
  74         else if (irq < 16)
  75                 __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_HI)
  76                               | (1 << (irq - 8))), OMAP1510_FPGA_IMR_HI);
  77         else
  78                 __raw_writeb((__raw_readb(INNOVATOR_FPGA_IMR2)
  79                               | (1 << (irq - 16))), INNOVATOR_FPGA_IMR2);
  80 }
  81
  82 static void fpga_mask_ack_irq(unsigned int irq)
  83 {
  84         fpga_mask_irq(irq);
  85         fpga_ack_irq(irq);
  86 }
  87
  88 void innovator_fpga_IRQ_demux(unsigned int irq, struct irqdesc *desc,
  89                               struct pt_regs *regs)
  90 {
  91         struct irqdesc *d;
  92         u32 stat;
  93         int fpga_irq;
  94
  95         /*
  96          * Acknowledge the parent IRQ.
  97          */
  98         desc->chip->ack(irq);
  99
 100         for (;;) {
 101                 stat = get_fpga_unmasked_irqs();
 102
 103                 if (!stat) {
 104                         break;
 105                 }
 106
 107                 for (fpga_irq = OMAP1510_IH_FPGA_BASE;
 108                         (fpga_irq < (OMAP1510_IH_FPGA_BASE + NR_FPGA_IRQS)) && stat;
 109                         fpga_irq++, stat >>= 1) {
 110                         if (stat & 1) {
 111                                 d = irq_desc + fpga_irq;
 112                                 d->handle(fpga_irq, d, regs);
 113                                 desc->chip->unmask(irq);
 114                         }
 115                 }
 116         }
 117 }
 118
 119 static struct irqchip omap_fpga_irq_ack = {
 120         .ack            = fpga_mask_ack_irq,
 121         .mask           = fpga_mask_irq,
 122         .unmask         = fpga_unmask_irq,
 123 };
 124
 125
 126 static struct irqchip omap_fpga_irq = {
 127         .ack            = fpga_ack_irq,
 128         .mask           = fpga_mask_irq,
 129         .unmask         = fpga_unmask_irq,
 130 };
 131
 132 /*
 133  * All of the FPGA interrupt request inputs except for the touchscreen are
 134  * edge-sensitive; the touchscreen is level-sensitive.  The edge-sensitive
 135  * interrupts are acknowledged as a side-effect of reading the interrupt
 136  * status register from the FPGA.  The edge-sensitive interrupt inputs
 137  * cause a problem with level interrupt requests, such as Ethernet.  The
 138  * problem occurs when a level interrupt request is asserted while its
 139  * interrupt input is masked in the FPGA, which results in a missed
 140  * interrupt.
 141  *
 142  * In an attempt to workaround the problem with missed interrupts, the
 143  * mask_ack routine for all of the FPGA interrupts has been changed from
 144  * fpga_mask_ack_irq() to fpga_ack_irq() so that the specific FPGA interrupt
 145  * being serviced is left unmasked.  We can do this because the FPGA cascade
 146  * interrupt is installed with the SA_INTERRUPT flag, which leaves all
 147  * interrupts masked at the CPU while an FPGA interrupt handler executes.
 148  *
 149  * Limited testing indicates that this workaround appears to be effective
 150  * for the smc9194 Ethernet driver used on the Innovator.  It should work
 151  * on other FPGA interrupts as well, but any drivers that explicitly mask
 152  * interrupts at the interrupt controller via disable_irq/enable_irq
 153  * could pose a problem.
 154  */
 155 void omap1510_fpga_init_irq(void)
 156 {
 157         int i;
 158
 159         __raw_writeb(0, OMAP1510_FPGA_IMR_LO);
 160         __raw_writeb(0, OMAP1510_FPGA_IMR_HI);
 161         __raw_writeb(0, INNOVATOR_FPGA_IMR2);
 162
 163         for (i = OMAP1510_IH_FPGA_BASE; i < (OMAP1510_IH_FPGA_BASE + NR_FPGA_IRQS); i++) {
 164
 165                 if (i == OMAP1510_INT_FPGA_TS) {
 166                         /*
 167                          * The touchscreen interrupt is level-sensitive, so
 168                          * we'll use the regular mask_ack routine for it.
 169                          */
 170                         set_irq_chip(i, &omap_fpga_irq_ack);
 171                 }
 172                 else {
 173                         /*
 174                          * All FPGA interrupts except the touchscreen are
 175                          * edge-sensitive, so we won't mask them.
 176                          */
 177                         set_irq_chip(i, &omap_fpga_irq);
 178                 }
 179
 180                 set_irq_handler(i, do_level_IRQ);
 181                 set_irq_flags(i, IRQF_VALID);
 182         }
 183
 184         /*
 185          * The FPGA interrupt line is connected to GPIO13. Claim this pin for
 186          * the ARM.
 187          *
 188          * NOTE: For general GPIO/MPUIO access and interrupts, please see
 189          * gpio.[ch]
 190          */
 191         omap_request_gpio(13);
 192         omap_set_gpio_direction(13, 1);
 193         omap_set_gpio_edge_ctrl(13, OMAP_GPIO_RISING_EDGE);
 194         set_irq_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux);
 195 }
 196
 197 EXPORT_SYMBOL(omap1510_fpga_init_irq);