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[linux-2.6.9-moxart.git] / arch / arm / mach-s3c2410 / gpio.c
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1 /* linux/arch/arm/mach-s3c2410/gpio.c
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2410 GPIO support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 * Changelog
23 * 13-Sep-2004 BJD Implemented change of MISCCR
24 * 14-Sep-2004 BJD Added getpin call
25 * 14-Sep-2004 BJD Fixed bug in setpin() call
26 * 30-Sep-2004 BJD Fixed cfgpin() mask bug
27 * 01-Oct-2004 BJD Added getcfg() to get pin configuration
28 * 01-Oct-2004 BJD Fixed mask bug in pullup() call
29 * 01-Oct-2004 BJD Added getirq() to turn pin into irqno
30 * 04-Oct-2004 BJD Added irq filter controls for GPIO
34 #include <linux/init.h>
35 #include <linux/module.h>
36 #include <linux/interrupt.h>
37 #include <linux/ioport.h>
39 #include <asm/hardware.h>
40 #include <asm/irq.h>
41 #include <asm/io.h>
43 #include <asm/arch/regs-gpio.h>
45 void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function)
47 unsigned long base = S3C2410_GPIO_BASE(pin);
48 unsigned long mask;
49 unsigned long con;
50 unsigned long flags;
52 if (pin < S3C2410_GPIO_BANKB) {
53 mask = 1 << S3C2410_GPIO_OFFSET(pin);
54 } else {
55 mask = 3 << S3C2410_GPIO_OFFSET(pin)*2;
58 local_irq_save(flags);
60 con = __raw_readl(base + 0x00);
61 con &= ~mask;
62 con |= function;
64 __raw_writel(con, base + 0x00);
66 local_irq_restore(flags);
69 unsigned int s3c2410_gpio_getcfg(unsigned int pin)
71 unsigned long base = S3C2410_GPIO_BASE(pin);
72 unsigned long mask;
74 if (pin < S3C2410_GPIO_BANKB) {
75 mask = 1 << S3C2410_GPIO_OFFSET(pin);
76 } else {
77 mask = 3 << S3C2410_GPIO_OFFSET(pin)*2;
80 return __raw_readl(base) & mask;
83 void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
85 unsigned long base = S3C2410_GPIO_BASE(pin);
86 unsigned long offs = S3C2410_GPIO_OFFSET(pin);
87 unsigned long flags;
88 unsigned long up;
90 if (pin < S3C2410_GPIO_BANKB)
91 return;
93 local_irq_save(flags);
95 up = __raw_readl(base + 0x08);
96 up &= ~(1L << offs);
97 up |= to << offs;
98 __raw_writel(up, base + 0x08);
100 local_irq_restore(flags);
103 void s3c2410_gpio_setpin(unsigned int pin, unsigned int to)
105 unsigned long base = S3C2410_GPIO_BASE(pin);
106 unsigned long offs = S3C2410_GPIO_OFFSET(pin);
107 unsigned long flags;
108 unsigned long dat;
110 local_irq_save(flags);
112 dat = __raw_readl(base + 0x04);
113 dat &= ~(1 << offs);
114 dat |= to << offs;
115 __raw_writel(dat, base + 0x04);
117 local_irq_restore(flags);
120 unsigned int s3c2410_gpio_getpin(unsigned int pin)
122 unsigned long base = S3C2410_GPIO_BASE(pin);
123 unsigned long offs = S3C2410_GPIO_OFFSET(pin);
125 return __raw_readl(base + 0x04) & (1<< offs);
128 unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
130 unsigned long flags;
131 unsigned long misccr;
133 local_irq_save(flags);
134 misccr = __raw_readl(S3C2410_MISCCR);
135 misccr &= ~clear;
136 misccr ^= change;
137 __raw_writel(misccr, S3C2410_MISCCR);
138 local_irq_restore(flags);
140 return misccr;
143 int s3c2410_gpio_getirq(unsigned int pin)
145 if (pin < S3C2410_GPF0 || pin > S3C2410_GPG15_EINT23)
146 return -1; /* not valid interrupts */
148 if (pin < S3C2410_GPG0 && pin > S3C2410_GPF7)
149 return -1; /* not valid pin */
151 if (pin < S3C2410_GPF4)
152 return (pin - S3C2410_GPF0) + IRQ_EINT0;
154 if (pin < S3C2410_GPG0)
155 return (pin - S3C2410_GPF4) + IRQ_EINT4;
157 return (pin - S3C2410_GPG0) + IRQ_EINT8;
160 int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
161 unsigned int config)
163 unsigned long reg = S3C2410_EINFLT0;
164 unsigned long flags;
165 unsigned long val;
167 if (pin < S3C2410_GPG8 || pin > S3C2410_GPG15)
168 return -1;
170 config &= 0xff;
172 pin -= S3C2410_GPG8_EINT16;
173 reg += pin & ~3;
175 local_irq_save(flags);
177 /* update filter width and clock source */
179 val = __raw_readl(reg);
180 val &= ~(0xff << ((pin & 3) * 8));
181 val |= config << ((pin & 3) * 8);
182 __raw_writel(val, reg);
184 /* update filter enable */
186 val = __raw_readl(S3C2410_EXTINT2);
187 val &= ~(1 << ((pin * 4) + 3));
188 val |= on << ((pin * 4) + 3);
189 __raw_writel(val, S3C2410_EXTINT2);
191 local_irq_restore(flags);
193 return 0;