arch/ppc64/oprofile/op_impl.h

   1 /*
   2  * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
   3  *
   4  * Based on alpha version.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #ifndef OP_IMPL_H
  13 #define OP_IMPL_H 1
  14
  15 #define OP_MAX_COUNTER 8
  16
  17 #define MSR_PMM         (1UL << (63 - 61))
  18
  19 /* freeze counters. set to 1 on a perfmon exception */
  20 #define MMCR0_FC        (1UL << (31 - 0))
  21
  22 /* freeze in supervisor state */
  23 #define MMCR0_KERNEL_DISABLE (1UL << (31 - 1))
  24
  25 /* freeze in problem state */
  26 #define MMCR0_PROBLEM_DISABLE (1UL << (31 - 2))
  27
  28 /* freeze counters while MSR mark = 1 */
  29 #define MMCR0_FCM1      (1UL << (31 - 3))
  30
  31 /* performance monitor exception enable */
  32 #define MMCR0_PMXE      (1UL << (31 - 5))
  33
  34 /* freeze counters on enabled condition or event */
  35 #define MMCR0_FCECE     (1UL << (31 - 6))
  36
  37 /* PMC1 count enable*/
  38 #define MMCR0_PMC1INTCONTROL    (1UL << (31 - 16))
  39
  40 /* PMCn count enable*/
  41 #define MMCR0_PMCNINTCONTROL    (1UL << (31 - 17))
  42
  43 /* performance monitor alert has occurred, set to 0 after handling exception */
  44 #define MMCR0_PMAO      (1UL << (31 - 24))
  45
  46 /* state of MSR HV when SIAR set */
  47 #define MMCRA_SIHV      (1UL << (63 - 35))
  48
  49 /* state of MSR PR when SIAR set */
  50 #define MMCRA_SIPR      (1UL << (63 - 36))
  51
  52 /* enable sampling */
  53 #define MMCRA_SAMPLE_ENABLE     (1UL << (63 - 63))
  54
  55 /* Per-counter configuration as set via oprofilefs.  */
  56 struct op_counter_config {
  57         unsigned long valid;
  58         unsigned long enabled;
  59         unsigned long event;
  60         unsigned long count;
  61         unsigned long kernel;
  62         /* We dont support per counter user/kernel selection */
  63         unsigned long user;
  64         unsigned long unit_mask;
  65 };
  66
  67 /* System-wide configuration as set via oprofilefs.  */
  68 struct op_system_config {
  69         unsigned long mmcr0;
  70         unsigned long mmcr1;
  71         unsigned long mmcra;
  72         unsigned long enable_kernel;
  73         unsigned long enable_user;
  74 };
  75
  76 /* Per-arch configuration */
  77 struct op_ppc64_model {
  78         void (*reg_setup) (struct op_counter_config *,
  79                            struct op_system_config *,
  80                            int num_counters);
  81         void (*cpu_setup) (void *);
  82         void (*start) (struct op_counter_config *);
  83         void (*stop) (void);
  84         void (*handle_interrupt) (struct pt_regs *,
  85                                   struct op_counter_config *);
  86         int num_counters;
  87 };
  88
  89 static inline unsigned int ctr_read(unsigned int i)
  90 {
  91         switch(i) {
  92         case 0:
  93                 return mfspr(SPRN_PMC1);
  94         case 1:
  95                 return mfspr(SPRN_PMC2);
  96         case 2:
  97                 return mfspr(SPRN_PMC3);
  98         case 3:
  99                 return mfspr(SPRN_PMC4);
 100         case 4:
 101                 return mfspr(SPRN_PMC5);
 102         case 5:
 103                 return mfspr(SPRN_PMC6);
 104         case 6:
 105                 return mfspr(SPRN_PMC7);
 106         case 7:
 107                 return mfspr(SPRN_PMC8);
 108         default:
 109                 return 0;
 110         }
 111 }
 112
 113 static inline void ctr_write(unsigned int i, unsigned int val)
 114 {
 115         switch(i) {
 116         case 0:
 117                 mtspr(SPRN_PMC1, val);
 118                 break;
 119         case 1:
 120                 mtspr(SPRN_PMC2, val);
 121                 break;
 122         case 2:
 123                 mtspr(SPRN_PMC3, val);
 124                 break;
 125         case 3:
 126                 mtspr(SPRN_PMC4, val);
 127                 break;
 128         case 4:
 129                 mtspr(SPRN_PMC5, val);
 130                 break;
 131         case 5:
 132                 mtspr(SPRN_PMC6, val);
 133                 break;
 134         case 6:
 135                 mtspr(SPRN_PMC7, val);
 136                 break;
 137         case 7:
 138                 mtspr(SPRN_PMC8, val);
 139                 break;
 140         default:
 141                 break;
 142         }
 143 }
 144
 145 #endif