drivers/fc4/soc.h

   1 /* soc.h: Definitions for Sparc SUNW,soc Fibre Channel Sbus driver.
   2  *
   3  * Copyright (C) 1996,1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   4  */
   5
   6 #ifndef __SOC_H
   7 #define __SOC_H
   8
   9 #include "fc.h"
  10 #include "fcp.h"
  11 #include "fcp_impl.h"
  12
  13 /* Hardware register offsets and constants first {{{ */
  14 #define CFG     0x00UL          /* Config Register */
  15 #define SAE     0x04UL          /* Slave Access Error Register */
  16 #define CMD     0x08UL          /* Command and Status Register */
  17 #define IMASK   0x0cUL          /* Interrupt Mask Register */
  18
  19 /* Config Register */
  20 #define SOC_CFG_EXT_RAM_BANK_MASK       0x07000000
  21 #define SOC_CFG_EEPROM_BANK_MASK        0x00030000
  22 #define SOC_CFG_BURST64_MASK            0x00000700
  23 #define SOC_CFG_SBUS_PARITY_TEST        0x00000020
  24 #define SOC_CFG_SBUS_PARITY_CHECK       0x00000010
  25 #define SOC_CFG_SBUS_ENHANCED           0x00000008
  26 #define SOC_CFG_BURST_MASK              0x00000007
  27 /* Bursts */
  28 #define SOC_CFG_BURST_4                 0x00000000
  29 #define SOC_CFG_BURST_16                0x00000004
  30 #define SOC_CFG_BURST_32                0x00000005
  31 #define SOC_CFG_BURST_64                0x00000006
  32
  33 /* Slave Access Error Register */
  34 #define SOC_SAE_ALIGNMENT               0x00000004
  35 #define SOC_SAE_UNSUPPORTED             0x00000002
  36 #define SOC_SAE_PARITY                  0x00000001
  37
  38 /* Command & Status Register */
  39 #define SOC_CMD_RSP_QALL                0x000f0000
  40 #define SOC_CMD_RSP_Q0                  0x00010000
  41 #define SOC_CMD_RSP_Q1                  0x00020000
  42 #define SOC_CMD_RSP_Q2                  0x00040000
  43 #define SOC_CMD_RSP_Q3                  0x00080000
  44 #define SOC_CMD_REQ_QALL                0x00000f00
  45 #define SOC_CMD_REQ_Q0                  0x00000100
  46 #define SOC_CMD_REQ_Q1                  0x00000200
  47 #define SOC_CMD_REQ_Q2                  0x00000400
  48 #define SOC_CMD_REQ_Q3                  0x00000800
  49 #define SOC_CMD_SAE                     0x00000080
  50 #define SOC_CMD_INTR_PENDING            0x00000008
  51 #define SOC_CMD_NON_QUEUED              0x00000004
  52 #define SOC_CMD_IDLE                    0x00000002
  53 #define SOC_CMD_SOFT_RESET              0x00000001
  54
  55 /* Interrupt Mask Register */
  56 #define SOC_IMASK_RSP_QALL              0x000f0000
  57 #define SOC_IMASK_RSP_Q0                0x00010000
  58 #define SOC_IMASK_RSP_Q1                0x00020000
  59 #define SOC_IMASK_RSP_Q2                0x00040000
  60 #define SOC_IMASK_RSP_Q3                0x00080000
  61 #define SOC_IMASK_REQ_QALL              0x00000f00
  62 #define SOC_IMASK_REQ_Q0                0x00000100
  63 #define SOC_IMASK_REQ_Q1                0x00000200
  64 #define SOC_IMASK_REQ_Q2                0x00000400
  65 #define SOC_IMASK_REQ_Q3                0x00000800
  66 #define SOC_IMASK_SAE                   0x00000080
  67 #define SOC_IMASK_NON_QUEUED            0x00000004
  68
  69 #define SOC_INTR(s, cmd) \
  70         (((cmd & SOC_CMD_RSP_QALL) | ((~cmd) & SOC_CMD_REQ_QALL)) \
  71          & s->imask)
  72
  73 #define SOC_SETIMASK(s, i) \
  74 do {    (s)->imask = (i); \
  75         sbus_writel((i), (s)->regs + IMASK); \
  76 } while(0)
  77
  78 /* XRAM
  79  *
  80  * This is a 64KB register area. It accepts only halfword access.
  81  * That's why here are the following inline functions...
  82  */
  83
  84 typedef void __iomem *xram_p;
  85
  86 /* Get 32bit number from XRAM */
  87 static inline u32 xram_get_32(xram_p x)
  88 {
  89         return ((sbus_readw(x + 0x00UL) << 16) |
  90                 (sbus_readw(x + 0x02UL)));
  91 }
  92
  93 /* Like the above, but when we don't care about the high 16 bits */
  94 static inline u32 xram_get_32low(xram_p x)
  95 {
  96         return (u32) sbus_readw(x + 0x02UL);
  97 }
  98
  99 static inline u16 xram_get_16(xram_p x)
 100 {
 101         return sbus_readw(x);
 102 }
 103
 104 static inline u8 xram_get_8(xram_p x)
 105 {
 106         if ((unsigned long)x & 0x1UL) {
 107                 x = x - 1;
 108                 return (u8) sbus_readw(x);
 109         } else {
 110                 return (u8) (sbus_readw(x) >> 8);
 111         }
 112 }
 113
 114 static inline void xram_copy_from(void *p, xram_p x, int len)
 115 {
 116         for (len >>= 2; len > 0; len--, x += sizeof(u32)) {
 117                 u32 val, *p32 = p;
 118
 119                 val = ((sbus_readw(x + 0x00UL) << 16) |
 120                        (sbus_readw(x + 0x02UL)));
 121                 *p32++ = val;
 122                 p = p32;
 123         }
 124 }
 125
 126 static inline void xram_copy_to(xram_p x, void *p, int len)
 127 {
 128         for (len >>= 2; len > 0; len--, x += sizeof(u32)) {
 129                 u32 tmp, *p32 = p;
 130
 131                 tmp = *p32++;
 132                 p = p32;
 133                 sbus_writew(tmp >> 16, x + 0x00UL);
 134                 sbus_writew(tmp, x + 0x02UL);
 135         }
 136 }
 137
 138 static inline void xram_bzero(xram_p x, int len)
 139 {
 140         for (len >>= 1; len > 0; len--, x += sizeof(u16))
 141                 sbus_writew(0, x);
 142 }
 143
 144 /* Circular Queue */
 145
 146 #define SOC_CQ_REQ_OFFSET       (0x100 * sizeof(u16))
 147 #define SOC_CQ_RSP_OFFSET       (0x110 * sizeof(u16))
 148
 149 typedef struct {
 150         u32                     address;
 151         u8                      in;
 152         u8                      out;
 153         u8                      last;
 154         u8                      seqno;
 155 } soc_hw_cq;
 156
 157 #define SOC_PORT_A      0x0000  /* From/To Port A */
 158 #define SOC_PORT_B      0x0001  /* From/To Port A */
 159 #define SOC_FC_HDR      0x0002  /* Contains FC Header */
 160 #define SOC_NORSP       0x0004  /* Don't generate response nor interrupt */
 161 #define SOC_NOINT       0x0008  /* Generate response but not interrupt */
 162 #define SOC_XFERRDY     0x0010  /* Generate XFERRDY */
 163 #define SOC_IGNOREPARAM 0x0020  /* Ignore PARAM field in the FC header */
 164 #define SOC_COMPLETE    0x0040  /* Command completed */
 165 #define SOC_UNSOLICITED 0x0080  /* For request this is the packet to establish unsolicited pools, */
 166                                 /* for rsp this is unsolicited packet */
 167 #define SOC_STATUS      0x0100  /* State change (on/off line) */
 168
 169 typedef struct {
 170         u32                     token;
 171         u16                     flags;
 172         u8                      class;
 173         u8                      segcnt;
 174         u32                     bytecnt;
 175 } soc_hdr;
 176
 177 typedef struct {
 178         u32                     base;
 179         u32                     count;
 180 } soc_data;
 181
 182 #define SOC_CQTYPE_OUTBOUND     0x01
 183 #define SOC_CQTYPE_INBOUND      0x02
 184 #define SOC_CQTYPE_SIMPLE       0x03
 185 #define SOC_CQTYPE_IO_WRITE     0x04
 186 #define SOC_CQTYPE_IO_READ      0x05
 187 #define SOC_CQTYPE_UNSOLICITED  0x06
 188 #define SOC_CQTYPE_DIAG         0x07
 189 #define SOC_CQTYPE_OFFLINE      0x08
 190 #define SOC_CQTYPE_RESPONSE     0x10
 191 #define SOC_CQTYPE_INLINE       0x20
 192
 193 #define SOC_CQFLAGS_CONT        0x01
 194 #define SOC_CQFLAGS_FULL        0x02
 195 #define SOC_CQFLAGS_BADHDR      0x04
 196 #define SOC_CQFLAGS_BADPKT      0x08
 197
 198 typedef struct {
 199         soc_hdr                 shdr;
 200         soc_data                data[3];
 201         fc_hdr                  fchdr;
 202         u8                      count;
 203         u8                      type;
 204         u8                      flags;
 205         u8                      seqno;
 206 } soc_req;
 207
 208 #define SOC_OK                  0
 209 #define SOC_P_RJT               2
 210 #define SOC_F_RJT               3
 211 #define SOC_P_BSY               4
 212 #define SOC_F_BSY               5
 213 #define SOC_ONLINE              0x10
 214 #define SOC_OFFLINE             0x11
 215 #define SOC_TIMEOUT             0x12
 216 #define SOC_OVERRUN             0x13
 217 #define SOC_UNKOWN_CQ_TYPE      0x20
 218 #define SOC_BAD_SEG_CNT         0x21
 219 #define SOC_MAX_XCHG_EXCEEDED   0x22
 220 #define SOC_BAD_XID             0x23
 221 #define SOC_XCHG_BUSY           0x24
 222 #define SOC_BAD_POOL_ID         0x25
 223 #define SOC_INSUFFICIENT_CQES   0x26
 224 #define SOC_ALLOC_FAIL          0x27
 225 #define SOC_BAD_SID             0x28
 226 #define SOC_NO_SEG_INIT         0x29
 227
 228 typedef struct {
 229         soc_hdr                 shdr;
 230         u32                     status;
 231         soc_data                data;
 232         u8                      xxx1[12];
 233         fc_hdr                  fchdr;
 234         u8                      count;
 235         u8                      type;
 236         u8                      flags;
 237         u8                      seqno;
 238 } soc_rsp;
 239
 240 /* }}} */
 241
 242 /* Now our software structures and constants we use to drive the beast {{{ */
 243
 244 #define SOC_CQ_REQ0_SIZE        4
 245 #define SOC_CQ_REQ1_SIZE        64
 246 #define SOC_CQ_RSP0_SIZE        8
 247 #define SOC_CQ_RSP1_SIZE        4
 248
 249 #define SOC_SOLICITED_RSP_Q     0
 250 #define SOC_UNSOLICITED_RSP_Q   1
 251
 252 struct soc;
 253
 254 typedef struct {
 255         /* This must come first */
 256         fc_channel              fc;
 257         struct soc              *s;
 258         u16                     flags;
 259         u16                     mask;
 260 } soc_port;
 261
 262 typedef struct {
 263         soc_hw_cq               *hw_cq; /* Related XRAM cq */
 264         soc_req                 *pool;
 265         u8                      in;
 266         u8                      out;
 267         u8                      last;
 268         u8                      seqno;
 269 } soc_cq;
 270
 271 struct soc {
 272         spinlock_t              lock;
 273         soc_port                port[2]; /* Every SOC has one or two FC ports */
 274         soc_cq                  req[2]; /* Request CQs */
 275         soc_cq                  rsp[2]; /* Response CQs */
 276         int                     soc_no;
 277         void __iomem            *regs;
 278         xram_p                  xram;
 279         fc_wwn                  wwn;
 280         u32                     imask;  /* Our copy of regs->imask */
 281         u32                     cfg;    /* Our copy of regs->cfg */
 282         char                    serv_params[80];
 283         struct soc              *next;
 284         int                     curr_port; /* Which port will have priority to fcp_queue_empty */
 285
 286         soc_req                 *req_cpu;
 287         u32                     req_dvma;
 288 };
 289
 290 /* }}} */
 291
 292 #endif /* !(__SOC_H) */