drivers/mmc.old/mmci.c

   1 /*
   2  *  linux/drivers/mmc/mmci.c - ARM PrimeCell MMCI PL180/1 driver
   3  *
   4  *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/config.h>
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/init.h>
  14 #include <linux/ioport.h>
  15 #include <linux/device.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/delay.h>
  18 #include <linux/err.h>
  19 #include <linux/highmem.h>
  20 #include <linux/mmc/host.h>
  21 #include <linux/mmc/protocol.h>
  22
  23 #include <asm/div64.h>
  24 #include <asm/io.h>
  25 #include <asm/irq.h>
  26 #include <asm/scatterlist.h>
  27 #include <asm/hardware/amba.h>
  28 #include <asm/hardware/clock.h>
  29 #include <asm/mach/mmc.h>
  30
  31 #include "mmci.h"
  32
  33 #define DRIVER_NAME "mmci-pl18x"
  34
  35 #ifdef CONFIG_MMC_DEBUG
  36 #define DBG(host,fmt,args...)   \
  37         pr_debug("%s: %s: " fmt, mmc_hostname(host->mmc), __func__ , args)
  38 #else
  39 #define DBG(host,fmt,args...)   do { } while (0)
  40 #endif
  41
  42 static unsigned int fmax = 515633;
  43
  44 static void
  45 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
  46 {
  47         writel(0, host->base + MMCICOMMAND);
  48
  49         host->mrq = NULL;
  50         host->cmd = NULL;
  51
  52         if (mrq->data)
  53                 mrq->data->bytes_xfered = host->data_xfered;
  54
  55         /*
  56          * Need to drop the host lock here; mmc_request_done may call
  57          * back into the driver...
  58          */
  59         spin_unlock(&host->lock);
  60         mmc_request_done(host->mmc, mrq);
  61         spin_lock(&host->lock);
  62 }
  63
  64 static void mmci_stop_data(struct mmci_host *host)
  65 {
  66         writel(0, host->base + MMCIDATACTRL);
  67         writel(0, host->base + MMCIMASK1);
  68         host->data = NULL;
  69 }
  70
  71 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
  72 {
  73         unsigned int datactrl, timeout, irqmask;
  74         unsigned long long clks;
  75         void __iomem *base;
  76
  77         DBG(host, "blksz %04x blks %04x flags %08x\n",
  78             1 << data->blksz_bits, data->blocks, data->flags);
  79
  80         host->data = data;
  81         host->size = data->blocks << data->blksz_bits;
  82         host->data_xfered = 0;
  83
  84         mmci_init_sg(host, data);
  85
  86         clks = (unsigned long long)data->timeout_ns * host->cclk;
  87         do_div(clks, 1000000000UL);
  88
  89         timeout = data->timeout_clks + (unsigned int)clks;
  90
  91         base = host->base;
  92         writel(timeout, base + MMCIDATATIMER);
  93         writel(host->size, base + MMCIDATALENGTH);
  94
  95         datactrl = MCI_DPSM_ENABLE | data->blksz_bits << 4;
  96         if (data->flags & MMC_DATA_READ) {
  97                 datactrl |= MCI_DPSM_DIRECTION;
  98                 irqmask = MCI_RXFIFOHALFFULLMASK;
  99         } else {
 100                 /*
 101                  * We don't actually need to include "FIFO empty" here
 102                  * since its implicit in "FIFO half empty".
 103                  */
 104                 irqmask = MCI_TXFIFOHALFEMPTYMASK;
 105         }
 106
 107         writel(datactrl, base + MMCIDATACTRL);
 108         writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
 109         writel(irqmask, base + MMCIMASK1);
 110 }
 111
 112 static void
 113 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
 114 {
 115         void __iomem *base = host->base;
 116
 117         DBG(host, "op %02x arg %08x flags %08x\n",
 118             cmd->opcode, cmd->arg, cmd->flags);
 119
 120         if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
 121                 writel(0, base + MMCICOMMAND);
 122                 udelay(1);
 123         }
 124
 125         c |= cmd->opcode | MCI_CPSM_ENABLE;
 126         switch (cmd->flags & MMC_RSP_MASK) {
 127         case MMC_RSP_NONE:
 128         default:
 129                 break;
 130         case MMC_RSP_LONG:
 131                 c |= MCI_CPSM_LONGRSP;
 132         case MMC_RSP_SHORT:
 133                 c |= MCI_CPSM_RESPONSE;
 134                 break;
 135         }
 136         if (/*interrupt*/0)
 137                 c |= MCI_CPSM_INTERRUPT;
 138
 139         host->cmd = cmd;
 140
 141         writel(cmd->arg, base + MMCIARGUMENT);
 142         writel(c, base + MMCICOMMAND);
 143 }
 144
 145 static void
 146 mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
 147               unsigned int status)
 148 {
 149         if (status & MCI_DATABLOCKEND) {
 150                 host->data_xfered += 1 << data->blksz_bits;
 151         }
 152         if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
 153                 if (status & MCI_DATACRCFAIL)
 154                         data->error = MMC_ERR_BADCRC;
 155                 else if (status & MCI_DATATIMEOUT)
 156                         data->error = MMC_ERR_TIMEOUT;
 157                 else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN))
 158                         data->error = MMC_ERR_FIFO;
 159                 status |= MCI_DATAEND;
 160         }
 161         if (status & MCI_DATAEND) {
 162                 mmci_stop_data(host);
 163
 164                 if (!data->stop) {
 165                         mmci_request_end(host, data->mrq);
 166                 } else {
 167                         mmci_start_command(host, data->stop, 0);
 168                 }
 169         }
 170 }
 171
 172 static void
 173 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
 174              unsigned int status)
 175 {
 176         void __iomem *base = host->base;
 177
 178         host->cmd = NULL;
 179
 180         cmd->resp[0] = readl(base + MMCIRESPONSE0);
 181         cmd->resp[1] = readl(base + MMCIRESPONSE1);
 182         cmd->resp[2] = readl(base + MMCIRESPONSE2);
 183         cmd->resp[3] = readl(base + MMCIRESPONSE3);
 184
 185         if (status & MCI_CMDTIMEOUT) {
 186                 cmd->error = MMC_ERR_TIMEOUT;
 187         } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
 188                 cmd->error = MMC_ERR_BADCRC;
 189         }
 190
 191         if (!cmd->data || cmd->error != MMC_ERR_NONE) {
 192                 mmci_request_end(host, cmd->mrq);
 193         } else if (!(cmd->data->flags & MMC_DATA_READ)) {
 194                 mmci_start_data(host, cmd->data);
 195         }
 196 }
 197
 198 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
 199 {
 200         void __iomem *base = host->base;
 201         char *ptr = buffer;
 202         u32 status;
 203
 204         do {
 205                 int count = host->size - (readl(base + MMCIFIFOCNT) << 2);
 206
 207                 if (count > remain)
 208                         count = remain;
 209
 210                 if (count <= 0)
 211                         break;
 212
 213                 readsl(base + MMCIFIFO, ptr, count >> 2);
 214
 215                 ptr += count;
 216                 remain -= count;
 217
 218                 if (remain == 0)
 219                         break;
 220
 221                 status = readl(base + MMCISTATUS);
 222         } while (status & MCI_RXDATAAVLBL);
 223
 224         return ptr - buffer;
 225 }
 226
 227 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
 228 {
 229         void __iomem *base = host->base;
 230         char *ptr = buffer;
 231
 232         do {
 233                 unsigned int count, maxcnt;
 234
 235                 maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE : MCI_FIFOHALFSIZE;
 236                 count = min(remain, maxcnt);
 237
 238                 writesl(base + MMCIFIFO, ptr, count >> 2);
 239
 240                 ptr += count;
 241                 remain -= count;
 242
 243                 if (remain == 0)
 244                         break;
 245
 246                 status = readl(base + MMCISTATUS);
 247         } while (status & MCI_TXFIFOHALFEMPTY);
 248
 249         return ptr - buffer;
 250 }
 251
 252 /*
 253  * PIO data transfer IRQ handler.
 254  */
 255 static irqreturn_t mmci_pio_irq(int irq, void *dev_id, struct pt_regs *regs)
 256 {
 257         struct mmci_host *host = dev_id;
 258         void __iomem *base = host->base;
 259         u32 status;
 260
 261         status = readl(base + MMCISTATUS);
 262
 263         DBG(host, "irq1 %08x\n", status);
 264
 265         do {
 266                 unsigned long flags;
 267                 unsigned int remain, len;
 268                 char *buffer;
 269
 270                 /*
 271                  * For write, we only need to test the half-empty flag
 272                  * here - if the FIFO is completely empty, then by
 273                  * definition it is more than half empty.
 274                  *
 275                  * For read, check for data available.
 276                  */
 277                 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
 278                         break;
 279
 280                 /*
 281                  * Map the current scatter buffer.
 282                  */
 283                 buffer = mmci_kmap_atomic(host, &flags) + host->sg_off;
 284                 remain = host->sg_ptr->length - host->sg_off;
 285
 286                 len = 0;
 287                 if (status & MCI_RXACTIVE)
 288                         len = mmci_pio_read(host, buffer, remain);
 289                 if (status & MCI_TXACTIVE)
 290                         len = mmci_pio_write(host, buffer, remain, status);
 291
 292                 /*
 293                  * Unmap the buffer.
 294                  */
 295                 mmci_kunmap_atomic(host, &flags);
 296
 297                 host->sg_off += len;
 298                 host->size -= len;
 299                 remain -= len;
 300
 301                 if (remain)
 302                         break;
 303
 304                 if (!mmci_next_sg(host))
 305                         break;
 306
 307                 status = readl(base + MMCISTATUS);
 308         } while (1);
 309
 310         /*
 311          * If we're nearing the end of the read, switch to
 312          * "any data available" mode.
 313          */
 314         if (status & MCI_RXACTIVE && host->size < MCI_FIFOSIZE)
 315                 writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1);
 316
 317         /*
 318          * If we run out of data, disable the data IRQs; this
 319          * prevents a race where the FIFO becomes empty before
 320          * the chip itself has disabled the data path, and
 321          * stops us racing with our data end IRQ.
 322          */
 323         if (host->size == 0) {
 324                 writel(0, base + MMCIMASK1);
 325                 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
 326         }
 327
 328         return IRQ_HANDLED;
 329 }
 330
 331 /*
 332  * Handle completion of command and data transfers.
 333  */
 334 static irqreturn_t mmci_irq(int irq, void *dev_id, struct pt_regs *regs)
 335 {
 336         struct mmci_host *host = dev_id;
 337         u32 status;
 338         int ret = 0;
 339
 340         spin_lock(&host->lock);
 341
 342         do {
 343                 struct mmc_command *cmd;
 344                 struct mmc_data *data;
 345
 346                 status = readl(host->base + MMCISTATUS);
 347                 status &= readl(host->base + MMCIMASK0);
 348                 writel(status, host->base + MMCICLEAR);
 349
 350                 DBG(host, "irq0 %08x\n", status);
 351
 352                 data = host->data;
 353                 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|
 354                               MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data)
 355                         mmci_data_irq(host, data, status);
 356
 357                 cmd = host->cmd;
 358                 if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
 359                         mmci_cmd_irq(host, cmd, status);
 360
 361                 ret = 1;
 362         } while (status);
 363
 364         spin_unlock(&host->lock);
 365
 366         return IRQ_RETVAL(ret);
 367 }
 368
 369 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
 370 {
 371         struct mmci_host *host = mmc_priv(mmc);
 372
 373         WARN_ON(host->mrq != NULL);
 374
 375         spin_lock_irq(&host->lock);
 376
 377         host->mrq = mrq;
 378
 379         if (mrq->data && mrq->data->flags & MMC_DATA_READ)
 380                 mmci_start_data(host, mrq->data);
 381
 382         mmci_start_command(host, mrq->cmd, 0);
 383
 384         spin_unlock_irq(&host->lock);
 385 }
 386
 387 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 388 {
 389         struct mmci_host *host = mmc_priv(mmc);
 390         u32 clk = 0, pwr = 0;
 391
 392         DBG(host, "clock %uHz busmode %u powermode %u Vdd %u\n",
 393             ios->clock, ios->bus_mode, ios->power_mode, ios->vdd);
 394
 395         if (ios->clock) {
 396                 if (ios->clock >= host->mclk) {
 397                         clk = MCI_CLK_BYPASS;
 398                         host->cclk = host->mclk;
 399                 } else {
 400                         clk = host->mclk / (2 * ios->clock) - 1;
 401                         if (clk > 256)
 402                                 clk = 255;
 403                         host->cclk = host->mclk / (2 * (clk + 1));
 404                 }
 405                 clk |= MCI_CLK_ENABLE;
 406         }
 407
 408         if (host->plat->translate_vdd)
 409                 pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd);
 410
 411         switch (ios->power_mode) {
 412         case MMC_POWER_OFF:
 413                 break;
 414         case MMC_POWER_UP:
 415                 pwr |= MCI_PWR_UP;
 416                 break;
 417         case MMC_POWER_ON:
 418                 pwr |= MCI_PWR_ON;
 419                 break;
 420         }
 421
 422         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 423                 pwr |= MCI_ROD;
 424
 425         writel(clk, host->base + MMCICLOCK);
 426
 427         if (host->pwr != pwr) {
 428                 host->pwr = pwr;
 429                 writel(pwr, host->base + MMCIPOWER);
 430         }
 431 }
 432
 433 static struct mmc_host_ops mmci_ops = {
 434         .request        = mmci_request,
 435         .set_ios        = mmci_set_ios,
 436 };
 437
 438 static void mmci_check_status(unsigned long data)
 439 {
 440         struct mmci_host *host = (struct mmci_host *)data;
 441         unsigned int status;
 442
 443         status = host->plat->status(mmc_dev(host->mmc));
 444         if (status ^ host->oldstat)
 445                 mmc_detect_change(host->mmc, 0);
 446
 447         host->oldstat = status;
 448         mod_timer(&host->timer, jiffies + HZ);
 449 }
 450
 451 static int mmci_probe(struct amba_device *dev, void *id)
 452 {
 453         struct mmc_platform_data *plat = dev->dev.platform_data;
 454         struct mmci_host *host;
 455         struct mmc_host *mmc;
 456         int ret;
 457
 458         /* must have platform data */
 459         if (!plat) {
 460                 ret = -EINVAL;
 461                 goto out;
 462         }
 463
 464         ret = amba_request_regions(dev, DRIVER_NAME);
 465         if (ret)
 466                 goto out;
 467
 468         mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
 469         if (!mmc) {
 470                 ret = -ENOMEM;
 471                 goto rel_regions;
 472         }
 473
 474         host = mmc_priv(mmc);
 475         host->clk = clk_get(&dev->dev, "MCLK");
 476         if (IS_ERR(host->clk)) {
 477                 ret = PTR_ERR(host->clk);
 478                 host->clk = NULL;
 479                 goto host_free;
 480         }
 481
 482         ret = clk_use(host->clk);
 483         if (ret)
 484                 goto clk_free;
 485
 486         ret = clk_enable(host->clk);
 487         if (ret)
 488                 goto clk_unuse;
 489
 490         host->plat = plat;
 491         host->mclk = clk_get_rate(host->clk);
 492         host->mmc = mmc;
 493         host->base = ioremap(dev->res.start, SZ_4K);
 494         if (!host->base) {
 495                 ret = -ENOMEM;
 496                 goto clk_disable;
 497         }
 498
 499         mmc->ops = &mmci_ops;
 500         mmc->f_min = (host->mclk + 511) / 512;
 501         mmc->f_max = min(host->mclk, fmax);
 502         mmc->ocr_avail = plat->ocr_mask;
 503
 504         /*
 505          * We can do SGIO
 506          */
 507         mmc->max_hw_segs = 16;
 508         mmc->max_phys_segs = NR_SG;
 509
 510         /*
 511          * Since we only have a 16-bit data length register, we must
 512          * ensure that we don't exceed 2^16-1 bytes in a single request.
 513          * Choose 64 (512-byte) sectors as the limit.
 514          */
 515         mmc->max_sectors = 64;
 516
 517         /*
 518          * Set the maximum segment size.  Since we aren't doing DMA
 519          * (yet) we are only limited by the data length register.
 520          */
 521         mmc->max_seg_size = mmc->max_sectors << 9;
 522
 523         spin_lock_init(&host->lock);
 524
 525         writel(0, host->base + MMCIMASK0);
 526         writel(0, host->base + MMCIMASK1);
 527         writel(0xfff, host->base + MMCICLEAR);
 528
 529         ret = request_irq(dev->irq[0], mmci_irq, SA_SHIRQ, DRIVER_NAME " (cmd)", host);
 530         if (ret)
 531                 goto unmap;
 532
 533         ret = request_irq(dev->irq[1], mmci_pio_irq, SA_SHIRQ, DRIVER_NAME " (pio)", host);
 534         if (ret)
 535                 goto irq0_free;
 536
 537         writel(MCI_IRQENABLE, host->base + MMCIMASK0);
 538
 539         amba_set_drvdata(dev, mmc);
 540
 541         mmc_add_host(mmc);
 542
 543         printk(KERN_INFO "%s: MMCI rev %x cfg %02x at 0x%08lx irq %d,%d\n",
 544                 mmc_hostname(mmc), amba_rev(dev), amba_config(dev),
 545                 dev->res.start, dev->irq[0], dev->irq[1]);
 546
 547         init_timer(&host->timer);
 548         host->timer.data = (unsigned long)host;
 549         host->timer.function = mmci_check_status;
 550         host->timer.expires = jiffies + HZ;
 551         add_timer(&host->timer);
 552
 553         return 0;
 554
 555  irq0_free:
 556         free_irq(dev->irq[0], host);
 557  unmap:
 558         iounmap(host->base);
 559  clk_disable:
 560         clk_disable(host->clk);
 561  clk_unuse:
 562         clk_unuse(host->clk);
 563  clk_free:
 564         clk_put(host->clk);
 565  host_free:
 566         mmc_free_host(mmc);
 567  rel_regions:
 568         amba_release_regions(dev);
 569  out:
 570         return ret;
 571 }
 572
 573 static int mmci_remove(struct amba_device *dev)
 574 {
 575         struct mmc_host *mmc = amba_get_drvdata(dev);
 576
 577         amba_set_drvdata(dev, NULL);
 578
 579         if (mmc) {
 580                 struct mmci_host *host = mmc_priv(mmc);
 581
 582                 del_timer_sync(&host->timer);
 583
 584                 mmc_remove_host(mmc);
 585
 586                 writel(0, host->base + MMCIMASK0);
 587                 writel(0, host->base + MMCIMASK1);
 588
 589                 writel(0, host->base + MMCICOMMAND);
 590                 writel(0, host->base + MMCIDATACTRL);
 591
 592                 free_irq(dev->irq[0], host);
 593                 free_irq(dev->irq[1], host);
 594
 595                 iounmap(host->base);
 596                 clk_disable(host->clk);
 597                 clk_unuse(host->clk);
 598                 clk_put(host->clk);
 599
 600                 mmc_free_host(mmc);
 601
 602                 amba_release_regions(dev);
 603         }
 604
 605         return 0;
 606 }
 607
 608 #ifdef CONFIG_PM
 609 static int mmci_suspend(struct amba_device *dev, pm_message_t state)
 610 {
 611         struct mmc_host *mmc = amba_get_drvdata(dev);
 612         int ret = 0;
 613
 614         if (mmc) {
 615                 struct mmci_host *host = mmc_priv(mmc);
 616
 617                 ret = mmc_suspend_host(mmc, state);
 618                 if (ret == 0)
 619                         writel(0, host->base + MMCIMASK0);
 620         }
 621
 622         return ret;
 623 }
 624
 625 static int mmci_resume(struct amba_device *dev)
 626 {
 627         struct mmc_host *mmc = amba_get_drvdata(dev);
 628         int ret = 0;
 629
 630         if (mmc) {
 631                 struct mmci_host *host = mmc_priv(mmc);
 632
 633                 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
 634
 635                 ret = mmc_resume_host(mmc);
 636         }
 637
 638         return ret;
 639 }
 640 #else
 641 #define mmci_suspend    NULL
 642 #define mmci_resume     NULL
 643 #endif
 644
 645 static struct amba_id mmci_ids[] = {
 646         {
 647                 .id     = 0x00041180,
 648                 .mask   = 0x000fffff,
 649         },
 650         {
 651                 .id     = 0x00041181,
 652                 .mask   = 0x000fffff,
 653         },
 654         { 0, 0 },
 655 };
 656
 657 static struct amba_driver mmci_driver = {
 658         .drv            = {
 659                 .name   = DRIVER_NAME,
 660         },
 661         .probe          = mmci_probe,
 662         .remove         = mmci_remove,
 663         .suspend        = mmci_suspend,
 664         .resume         = mmci_resume,
 665         .id_table       = mmci_ids,
 666 };
 667
 668 static int __init mmci_init(void)
 669 {
 670         return amba_driver_register(&mmci_driver);
 671 }
 672
 673 static void __exit mmci_exit(void)
 674 {
 675         amba_driver_unregister(&mmci_driver);
 676 }
 677
 678 module_init(mmci_init);
 679 module_exit(mmci_exit);
 680 module_param(fmax, uint, 0444);
 681
 682 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
 683 MODULE_LICENSE("GPL");