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MOXA linux-2.6.x / linux-2.6.9-uc0 from sdlinux-moxaart.tgz
[linux-2.6.9-moxart.git] / drivers / net / 8139cp.c
blobdd50db08343874c16f30cf517e0248b1fc0f8dd2
1 /* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
2 /*
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
4
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
11
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
18
19 See the file COPYING in this distribution for more information.
20
21 Contributors:
22
23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
26
27 TODO:
28 * Test Tx checksumming thoroughly
29 * Implement dev->tx_timeout
30
31 Low priority TODO:
32 * Complete reset on PciErr
33 * Consider Rx interrupt mitigation using TimerIntr
34 * Investigate using skb->priority with h/w VLAN priority
35 * Investigate using High Priority Tx Queue with skb->priority
36 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
37 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
38 * Implement Tx software interrupt mitigation via
39 Tx descriptor bit
40 * The real minimum of CP_MIN_MTU is 4 bytes. However,
41 for this to be supported, one must(?) turn on packet padding.
42 * Support external MII transceivers (patch available)
43
44 NOTES:
45 * TX checksumming is considered experimental. It is off by
46 default, use ethtool to turn it on.
47
48 */
49
50 #define DRV_NAME "8139cp"
51 #define DRV_VERSION "1.2"
52 #define DRV_RELDATE "Mar 22, 2004"
53
54
55 #include <linux/config.h>
56 #include <linux/module.h>
57 #include <linux/kernel.h>
58 #include <linux/compiler.h>
59 #include <linux/netdevice.h>
60 #include <linux/etherdevice.h>
61 #include <linux/init.h>
62 #include <linux/pci.h>
63 #include <linux/delay.h>
64 #include <linux/ethtool.h>
65 #include <linux/mii.h>
66 #include <linux/if_vlan.h>
67 #include <linux/crc32.h>
68 #include <linux/in.h>
69 #include <linux/ip.h>
70 #include <linux/tcp.h>
71 #include <linux/udp.h>
72 #include <linux/cache.h>
73 #include <asm/io.h>
74 #include <asm/uaccess.h>
75
76 /* VLAN tagging feature enable/disable */
77 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
78 #define CP_VLAN_TAG_USED 1
79 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
80 do { (tx_desc)->opts2 = (vlan_tag_value); } while (0)
81 #else
82 #define CP_VLAN_TAG_USED 0
83 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
84 do { (tx_desc)->opts2 = 0; } while (0)
85 #endif
86
87 /* These identify the driver base version and may not be removed. */
88 static char version[] =
89 KERN_INFO DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
90
91 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
92 MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
93 MODULE_LICENSE("GPL");
94
95 static int debug = -1;
96 MODULE_PARM (debug, "i");
97 MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
98
99 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
100 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
101 static int multicast_filter_limit = 32;
102 MODULE_PARM (multicast_filter_limit, "i");
103 MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
104
105 #define PFX DRV_NAME ": "
106
107 #ifndef TRUE
108 #define FALSE 0
109 #define TRUE (!FALSE)
110 #endif
111
112 #define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
113 NETIF_MSG_PROBE | \
114 NETIF_MSG_LINK)
115 #define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
116 #define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
117 #define CP_REGS_SIZE (0xff + 1)
118 #define CP_REGS_VER 1 /* version 1 */
119 #define CP_RX_RING_SIZE 64
120 #define CP_TX_RING_SIZE 64
121 #define CP_RING_BYTES \
122 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
123 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
124 CP_STATS_SIZE)
125 #define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
126 #define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
127 #define TX_BUFFS_AVAIL(CP) \
128 (((CP)->tx_tail <= (CP)->tx_head) ? \
129 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
130 (CP)->tx_tail - (CP)->tx_head - 1)
131
132 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
133 #define RX_OFFSET 2
134 #define CP_INTERNAL_PHY 32
135
136 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
137 #define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
138 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
139 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
140 #define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
141
142 /* Time in jiffies before concluding the transmitter is hung. */
143 #define TX_TIMEOUT (6*HZ)
144
145 /* hardware minimum and maximum for a single frame's data payload */
146 #define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
147 #define CP_MAX_MTU 4096
148
149 enum {
150 /* NIC register offsets */
151 MAC0 = 0x00, /* Ethernet hardware address. */
152 MAR0 = 0x08, /* Multicast filter. */
153 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
154 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
155 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
156 Cmd = 0x37, /* Command register */
157 IntrMask = 0x3C, /* Interrupt mask */
158 IntrStatus = 0x3E, /* Interrupt status */
159 TxConfig = 0x40, /* Tx configuration */
160 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
161 RxConfig = 0x44, /* Rx configuration */
162 RxMissed = 0x4C, /* 24 bits valid, write clears */
163 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
164 Config1 = 0x52, /* Config1 */
165 Config3 = 0x59, /* Config3 */
166 Config4 = 0x5A, /* Config4 */
167 MultiIntr = 0x5C, /* Multiple interrupt select */
168 BasicModeCtrl = 0x62, /* MII BMCR */
169 BasicModeStatus = 0x64, /* MII BMSR */
170 NWayAdvert = 0x66, /* MII ADVERTISE */
171 NWayLPAR = 0x68, /* MII LPA */
172 NWayExpansion = 0x6A, /* MII Expansion */
173 Config5 = 0xD8, /* Config5 */
174 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
175 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
176 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
177 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
178 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
179 TxThresh = 0xEC, /* Early Tx threshold */
180 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
181 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
182
183 /* Tx and Rx status descriptors */
184 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
185 RingEnd = (1 << 30), /* End of descriptor ring */
186 FirstFrag = (1 << 29), /* First segment of a packet */
187 LastFrag = (1 << 28), /* Final segment of a packet */
188 TxError = (1 << 23), /* Tx error summary */
189 RxError = (1 << 20), /* Rx error summary */
190 IPCS = (1 << 18), /* Calculate IP checksum */
191 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
192 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
193 TxVlanTag = (1 << 17), /* Add VLAN tag */
194 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
195 IPFail = (1 << 15), /* IP checksum failed */
196 UDPFail = (1 << 14), /* UDP/IP checksum failed */
197 TCPFail = (1 << 13), /* TCP/IP checksum failed */
198 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
199 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
200 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
201 RxProtoTCP = 1,
202 RxProtoUDP = 2,
203 RxProtoIP = 3,
204 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
205 TxOWC = (1 << 22), /* Tx Out-of-window collision */
206 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
207 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
208 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
209 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
210 RxErrFrame = (1 << 27), /* Rx frame alignment error */
211 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
212 RxErrCRC = (1 << 18), /* Rx CRC error */
213 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
214 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
215 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
216
217 /* StatsAddr register */
218 DumpStats = (1 << 3), /* Begin stats dump */
219
220 /* RxConfig register */
221 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
222 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
223 AcceptErr = 0x20, /* Accept packets with CRC errors */
224 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
225 AcceptBroadcast = 0x08, /* Accept broadcast packets */
226 AcceptMulticast = 0x04, /* Accept multicast packets */
227 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
228 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
229
230 /* IntrMask / IntrStatus registers */
231 PciErr = (1 << 15), /* System error on the PCI bus */
232 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
233 LenChg = (1 << 13), /* Cable length change */
234 SWInt = (1 << 8), /* Software-requested interrupt */
235 TxEmpty = (1 << 7), /* No Tx descriptors available */
236 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
237 LinkChg = (1 << 5), /* Packet underrun, or link change */
238 RxEmpty = (1 << 4), /* No Rx descriptors available */
239 TxErr = (1 << 3), /* Tx error */
240 TxOK = (1 << 2), /* Tx packet sent */
241 RxErr = (1 << 1), /* Rx error */
242 RxOK = (1 << 0), /* Rx packet received */
243 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
244 but hardware likes to raise it */
245
246 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
247 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
248 RxErr | RxOK | IntrResvd,
249
250 /* C mode command register */
251 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
252 RxOn = (1 << 3), /* Rx mode enable */
253 TxOn = (1 << 2), /* Tx mode enable */
254
255 /* C+ mode command register */
256 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
257 RxChkSum = (1 << 5), /* Rx checksum offload enable */
258 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
259 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
260 CpRxOn = (1 << 1), /* Rx mode enable */
261 CpTxOn = (1 << 0), /* Tx mode enable */
262
263 /* Cfg9436 EEPROM control register */
264 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
265 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
266
267 /* TxConfig register */
268 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
269 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
270
271 /* Early Tx Threshold register */
272 TxThreshMask = 0x3f, /* Mask bits 5-0 */
273 TxThreshMax = 2048, /* Max early Tx threshold */
274
275 /* Config1 register */
276 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
277 LWACT = (1 << 4), /* LWAKE active mode */
278 PMEnable = (1 << 0), /* Enable various PM features of chip */
279
280 /* Config3 register */
281 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
282 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
283 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
284
285 /* Config4 register */
286 LWPTN = (1 << 1), /* LWAKE Pattern */
287 LWPME = (1 << 4), /* LANWAKE vs PMEB */
288
289 /* Config5 register */
290 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
291 MWF = (1 << 5), /* Accept Multicast wakeup frame */
292 UWF = (1 << 4), /* Accept Unicast wakeup frame */
293 LANWake = (1 << 1), /* Enable LANWake signal */
294 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
295
296 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
297 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
298 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
299 };
300
301 static const unsigned int cp_rx_config =
302 (RX_FIFO_THRESH << RxCfgFIFOShift) |
303 (RX_DMA_BURST << RxCfgDMAShift);
304
305 struct cp_desc {
306 u32 opts1;
307 u32 opts2;
308 u64 addr;
309 };
310
311 struct ring_info {
312 struct sk_buff *skb;
313 dma_addr_t mapping;
314 unsigned frag;
315 };
316
317 struct cp_dma_stats {
318 u64 tx_ok;
319 u64 rx_ok;
320 u64 tx_err;
321 u32 rx_err;
322 u16 rx_fifo;
323 u16 frame_align;
324 u32 tx_ok_1col;
325 u32 tx_ok_mcol;
326 u64 rx_ok_phys;
327 u64 rx_ok_bcast;
328 u32 rx_ok_mcast;
329 u16 tx_abort;
330 u16 tx_underrun;
331 } __attribute__((packed));
332
333 struct cp_extra_stats {
334 unsigned long rx_frags;
335 };
336
337 struct cp_private {
338 void *regs;
339 struct net_device *dev;
340 spinlock_t lock;
341 u32 msg_enable;
342
343 struct pci_dev *pdev;
344 u32 rx_config;
345 u16 cpcmd;
346
347 struct net_device_stats net_stats;
348 struct cp_extra_stats cp_stats;
349 struct cp_dma_stats *nic_stats;
350 dma_addr_t nic_stats_dma;
351
352 unsigned rx_tail ____cacheline_aligned;
353 struct cp_desc *rx_ring;
354 struct ring_info rx_skb[CP_RX_RING_SIZE];
355 unsigned rx_buf_sz;
356
357 unsigned tx_head ____cacheline_aligned;
358 unsigned tx_tail;
359
360 struct cp_desc *tx_ring;
361 struct ring_info tx_skb[CP_TX_RING_SIZE];
362 dma_addr_t ring_dma;
363
364 #if CP_VLAN_TAG_USED
365 struct vlan_group *vlgrp;
366 #endif
367
368 unsigned int wol_enabled : 1; /* Is Wake-on-LAN enabled? */
369 u32 power_state[16];
370
371 struct mii_if_info mii_if;
372 };
373
374 #define cpr8(reg) readb(cp->regs + (reg))
375 #define cpr16(reg) readw(cp->regs + (reg))
376 #define cpr32(reg) readl(cp->regs + (reg))
377 #define cpw8(reg,val) writeb((val), cp->regs + (reg))
378 #define cpw16(reg,val) writew((val), cp->regs + (reg))
379 #define cpw32(reg,val) writel((val), cp->regs + (reg))
380 #define cpw8_f(reg,val) do { \
381 writeb((val), cp->regs + (reg)); \
382 readb(cp->regs + (reg)); \
383 } while (0)
384 #define cpw16_f(reg,val) do { \
385 writew((val), cp->regs + (reg)); \
386 readw(cp->regs + (reg)); \
387 } while (0)
388 #define cpw32_f(reg,val) do { \
389 writel((val), cp->regs + (reg)); \
390 readl(cp->regs + (reg)); \
391 } while (0)
392
393
394 static void __cp_set_rx_mode (struct net_device *dev);
395 static void cp_tx (struct cp_private *cp);
396 static void cp_clean_rings (struct cp_private *cp);
397
398 static struct pci_device_id cp_pci_tbl[] = {
399 { PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139,
400 PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
401 #ifdef CONFIG_SH_SECUREEDGE5410
402 /* Bogus 8139 silicon reports 8129 without external PROM :-( */
403 { PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8129,
404 PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
405 #endif
406 { },
407 };
408 MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
409
410 static struct {
411 const char str[ETH_GSTRING_LEN];
412 } ethtool_stats_keys[] = {
413 { "tx_ok" },
414 { "rx_ok" },
415 { "tx_err" },
416 { "rx_err" },
417 { "rx_fifo" },
418 { "frame_align" },
419 { "tx_ok_1col" },
420 { "tx_ok_mcol" },
421 { "rx_ok_phys" },
422 { "rx_ok_bcast" },
423 { "rx_ok_mcast" },
424 { "tx_abort" },
425 { "tx_underrun" },
426 { "rx_frags" },
427 };
428
429
430 #if CP_VLAN_TAG_USED
431 static void cp_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
432 {
433 struct cp_private *cp = netdev_priv(dev);
434 unsigned long flags;
435
436 spin_lock_irqsave(&cp->lock, flags);
437 cp->vlgrp = grp;
438 cp->cpcmd |= RxVlanOn;
439 cpw16(CpCmd, cp->cpcmd);
440 spin_unlock_irqrestore(&cp->lock, flags);
441 }
442
443 static void cp_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
444 {
445 struct cp_private *cp = netdev_priv(dev);
446 unsigned long flags;
447
448 spin_lock_irqsave(&cp->lock, flags);
449 cp->cpcmd &= ~RxVlanOn;
450 cpw16(CpCmd, cp->cpcmd);
451 if (cp->vlgrp)
452 cp->vlgrp->vlan_devices[vid] = NULL;
453 spin_unlock_irqrestore(&cp->lock, flags);
454 }
455 #endif /* CP_VLAN_TAG_USED */
456
457 static inline void cp_set_rxbufsize (struct cp_private *cp)
458 {
459 unsigned int mtu = cp->dev->mtu;
460
461 if (mtu > ETH_DATA_LEN)
462 /* MTU + ethernet header + FCS + optional VLAN tag */
463 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
464 else
465 cp->rx_buf_sz = PKT_BUF_SZ;
466 }
467
468 static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
469 struct cp_desc *desc)
470 {
471 skb->protocol = eth_type_trans (skb, cp->dev);
472
473 cp->net_stats.rx_packets++;
474 cp->net_stats.rx_bytes += skb->len;
475 cp->dev->last_rx = jiffies;
476
477 #if CP_VLAN_TAG_USED
478 if (cp->vlgrp && (desc->opts2 & RxVlanTagged)) {
479 vlan_hwaccel_receive_skb(skb, cp->vlgrp,
480 be16_to_cpu(desc->opts2 & 0xffff));
481 } else
482 #endif
483 netif_receive_skb(skb);
484 }
485
486 static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
487 u32 status, u32 len)
488 {
489 if (netif_msg_rx_err (cp))
490 printk (KERN_DEBUG
491 "%s: rx err, slot %d status 0x%x len %d\n",
492 cp->dev->name, rx_tail, status, len);
493 cp->net_stats.rx_errors++;
494 if (status & RxErrFrame)
495 cp->net_stats.rx_frame_errors++;
496 if (status & RxErrCRC)
497 cp->net_stats.rx_crc_errors++;
498 if ((status & RxErrRunt) || (status & RxErrLong))
499 cp->net_stats.rx_length_errors++;
500 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
501 cp->net_stats.rx_length_errors++;
502 if (status & RxErrFIFO)
503 cp->net_stats.rx_fifo_errors++;
504 }
505
506 static inline unsigned int cp_rx_csum_ok (u32 status)
507 {
508 unsigned int protocol = (status >> 16) & 0x3;
509
510 if (likely((protocol == RxProtoTCP) && (!(status & TCPFail))))
511 return 1;
512 else if ((protocol == RxProtoUDP) && (!(status & UDPFail)))
513 return 1;
514 else if ((protocol == RxProtoIP) && (!(status & IPFail)))
515 return 1;
516 return 0;
517 }
518
519 static int cp_rx_poll (struct net_device *dev, int *budget)
520 {
521 struct cp_private *cp = netdev_priv(dev);
522 unsigned rx_tail = cp->rx_tail;
523 unsigned rx_work = dev->quota;
524 unsigned rx;
525
526 rx_status_loop:
527 rx = 0;
528 cpw16(IntrStatus, cp_rx_intr_mask);
529
530 while (1) {
531 u32 status, len;
532 dma_addr_t mapping;
533 struct sk_buff *skb, *new_skb;
534 struct cp_desc *desc;
535 unsigned buflen;
536
537 skb = cp->rx_skb[rx_tail].skb;
538 if (!skb)
539 BUG();
540
541 desc = &cp->rx_ring[rx_tail];
542 status = le32_to_cpu(desc->opts1);
543 if (status & DescOwn)
544 break;
545
546 len = (status & 0x1fff) - 4;
547 mapping = cp->rx_skb[rx_tail].mapping;
548
549 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
550 /* we don't support incoming fragmented frames.
551 * instead, we attempt to ensure that the
552 * pre-allocated RX skbs are properly sized such
553 * that RX fragments are never encountered
554 */
555 cp_rx_err_acct(cp, rx_tail, status, len);
556 cp->net_stats.rx_dropped++;
557 cp->cp_stats.rx_frags++;
558 goto rx_next;
559 }
560
561 if (status & (RxError | RxErrFIFO)) {
562 cp_rx_err_acct(cp, rx_tail, status, len);
563 goto rx_next;
564 }
565
566 if (netif_msg_rx_status(cp))
567 printk(KERN_DEBUG "%s: rx slot %d status 0x%x len %d\n",
568 cp->dev->name, rx_tail, status, len);
569
570 buflen = cp->rx_buf_sz + RX_OFFSET;
571 new_skb = dev_alloc_skb (buflen);
572 if (!new_skb) {
573 cp->net_stats.rx_dropped++;
574 goto rx_next;
575 }
576
577 skb_reserve(new_skb, RX_OFFSET);
578 new_skb->dev = cp->dev;
579
580 pci_unmap_single(cp->pdev, mapping,
581 buflen, PCI_DMA_FROMDEVICE);
582
583 /* Handle checksum offloading for incoming packets. */
584 if (cp_rx_csum_ok(status))
585 skb->ip_summed = CHECKSUM_UNNECESSARY;
586 else
587 skb->ip_summed = CHECKSUM_NONE;
588
589 skb_put(skb, len);
590
591 mapping =
592 cp->rx_skb[rx_tail].mapping =
593 pci_map_single(cp->pdev, new_skb->tail,
594 buflen, PCI_DMA_FROMDEVICE);
595 cp->rx_skb[rx_tail].skb = new_skb;
596
597 cp_rx_skb(cp, skb, desc);
598 rx++;
599
600 rx_next:
601 cp->rx_ring[rx_tail].opts2 = 0;
602 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
603 if (rx_tail == (CP_RX_RING_SIZE - 1))
604 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
605 cp->rx_buf_sz);
606 else
607 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
608 rx_tail = NEXT_RX(rx_tail);
609
610 if (!rx_work--)
611 break;
612 }
613
614 cp->rx_tail = rx_tail;
615
616 dev->quota -= rx;
617 *budget -= rx;
618
619 /* if we did not reach work limit, then we're done with
620 * this round of polling
621 */
622 if (rx_work) {
623 if (cpr16(IntrStatus) & cp_rx_intr_mask)
624 goto rx_status_loop;
625
626 local_irq_disable();
627 cpw16_f(IntrMask, cp_intr_mask);
628 __netif_rx_complete(dev);
629 local_irq_enable();
630
631 return 0; /* done */
632 }
633
634 return 1; /* not done */
635 }
636
637 static irqreturn_t
638 cp_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
639 {
640 struct net_device *dev = dev_instance;
641 struct cp_private *cp;
642 u16 status;
643
644 if (unlikely(dev == NULL))
645 return IRQ_NONE;
646 cp = netdev_priv(dev);
647
648 status = cpr16(IntrStatus);
649 if (!status || (status == 0xFFFF))
650 return IRQ_NONE;
651
652 if (netif_msg_intr(cp))
653 printk(KERN_DEBUG "%s: intr, status %04x cmd %02x cpcmd %04x\n",
654 dev->name, status, cpr8(Cmd), cpr16(CpCmd));
655
656 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
657
658 spin_lock(&cp->lock);
659
660 /* close possible race's with dev_close */
661 if (unlikely(!netif_running(dev))) {
662 cpw16(IntrMask, 0);
663 spin_unlock(&cp->lock);
664 return IRQ_HANDLED;
665 }
666
667 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
668 if (netif_rx_schedule_prep(dev)) {
669 cpw16_f(IntrMask, cp_norx_intr_mask);
670 __netif_rx_schedule(dev);
671 }
672
673 if (status & (TxOK | TxErr | TxEmpty | SWInt))
674 cp_tx(cp);
675 if (status & LinkChg)
676 mii_check_media(&cp->mii_if, netif_msg_link(cp), FALSE);
677
678 spin_unlock(&cp->lock);
679
680 if (status & PciErr) {
681 u16 pci_status;
682
683 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
684 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
685 printk(KERN_ERR "%s: PCI bus error, status=%04x, PCI status=%04x\n",
686 dev->name, status, pci_status);
687
688 /* TODO: reset hardware */
689 }
690
691 return IRQ_HANDLED;
692 }
693
694 static void cp_tx (struct cp_private *cp)
695 {
696 unsigned tx_head = cp->tx_head;
697 unsigned tx_tail = cp->tx_tail;
698
699 while (tx_tail != tx_head) {
700 struct sk_buff *skb;
701 u32 status;
702
703 rmb();
704 status = le32_to_cpu(cp->tx_ring[tx_tail].opts1);
705 if (status & DescOwn)
706 break;
707
708 skb = cp->tx_skb[tx_tail].skb;
709 if (!skb)
710 BUG();
711
712 pci_unmap_single(cp->pdev, cp->tx_skb[tx_tail].mapping,
713 skb->len, PCI_DMA_TODEVICE);
714
715 if (status & LastFrag) {
716 if (status & (TxError | TxFIFOUnder)) {
717 if (netif_msg_tx_err(cp))
718 printk(KERN_DEBUG "%s: tx err, status 0x%x\n",
719 cp->dev->name, status);
720 cp->net_stats.tx_errors++;
721 if (status & TxOWC)
722 cp->net_stats.tx_window_errors++;
723 if (status & TxMaxCol)
724 cp->net_stats.tx_aborted_errors++;
725 if (status & TxLinkFail)
726 cp->net_stats.tx_carrier_errors++;
727 if (status & TxFIFOUnder)
728 cp->net_stats.tx_fifo_errors++;
729 } else {
730 cp->net_stats.collisions +=
731 ((status >> TxColCntShift) & TxColCntMask);
732 cp->net_stats.tx_packets++;
733 cp->net_stats.tx_bytes += skb->len;
734 if (netif_msg_tx_done(cp))
735 printk(KERN_DEBUG "%s: tx done, slot %d\n", cp->dev->name, tx_tail);
736 }
737 dev_kfree_skb_irq(skb);
738 }
739
740 cp->tx_skb[tx_tail].skb = NULL;
741
742 tx_tail = NEXT_TX(tx_tail);
743 }
744
745 cp->tx_tail = tx_tail;
746
747 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
748 netif_wake_queue(cp->dev);
749 }
750
751 static int cp_start_xmit (struct sk_buff *skb, struct net_device *dev)
752 {
753 struct cp_private *cp = netdev_priv(dev);
754 unsigned entry;
755 u32 eor;
756 #if CP_VLAN_TAG_USED
757 u32 vlan_tag = 0;
758 #endif
759
760 spin_lock_irq(&cp->lock);
761
762 /* This is a hard error, log it. */
763 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
764 netif_stop_queue(dev);
765 spin_unlock_irq(&cp->lock);
766 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
767 dev->name);
768 return 1;
769 }
770
771 #if CP_VLAN_TAG_USED
772 if (cp->vlgrp && vlan_tx_tag_present(skb))
773 vlan_tag = TxVlanTag | cpu_to_be16(vlan_tx_tag_get(skb));
774 #endif
775
776 entry = cp->tx_head;
777 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
778 if (skb_shinfo(skb)->nr_frags == 0) {
779 struct cp_desc *txd = &cp->tx_ring[entry];
780 u32 len;
781 dma_addr_t mapping;
782
783 len = skb->len;
784 mapping = pci_map_single(cp->pdev, skb->data, len, PCI_DMA_TODEVICE);
785 CP_VLAN_TX_TAG(txd, vlan_tag);
786 txd->addr = cpu_to_le64(mapping);
787 wmb();
788
789 if (skb->ip_summed == CHECKSUM_HW) {
790 const struct iphdr *ip = skb->nh.iph;
791 if (ip->protocol == IPPROTO_TCP)
792 txd->opts1 = cpu_to_le32(eor | len | DescOwn |
793 FirstFrag | LastFrag |
794 IPCS | TCPCS);
795 else if (ip->protocol == IPPROTO_UDP)
796 txd->opts1 = cpu_to_le32(eor | len | DescOwn |
797 FirstFrag | LastFrag |
798 IPCS | UDPCS);
799 else
800 BUG();
801 } else
802 txd->opts1 = cpu_to_le32(eor | len | DescOwn |
803 FirstFrag | LastFrag);
804 wmb();
805
806 cp->tx_skb[entry].skb = skb;
807 cp->tx_skb[entry].mapping = mapping;
808 cp->tx_skb[entry].frag = 0;
809 entry = NEXT_TX(entry);
810 } else {
811 struct cp_desc *txd;
812 u32 first_len, first_eor;
813 dma_addr_t first_mapping;
814 int frag, first_entry = entry;
815 const struct iphdr *ip = skb->nh.iph;
816
817 /* We must give this initial chunk to the device last.
818 * Otherwise we could race with the device.
819 */
820 first_eor = eor;
821 first_len = skb_headlen(skb);
822 first_mapping = pci_map_single(cp->pdev, skb->data,
823 first_len, PCI_DMA_TODEVICE);
824 cp->tx_skb[entry].skb = skb;
825 cp->tx_skb[entry].mapping = first_mapping;
826 cp->tx_skb[entry].frag = 1;
827 entry = NEXT_TX(entry);
828
829 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
830 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
831 u32 len;
832 u32 ctrl;
833 dma_addr_t mapping;
834
835 len = this_frag->size;
836 mapping = pci_map_single(cp->pdev,
837 ((void *) page_address(this_frag->page) +
838 this_frag->page_offset),
839 len, PCI_DMA_TODEVICE);
840 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
841
842 if (skb->ip_summed == CHECKSUM_HW) {
843 ctrl = eor | len | DescOwn | IPCS;
844 if (ip->protocol == IPPROTO_TCP)
845 ctrl |= TCPCS;
846 else if (ip->protocol == IPPROTO_UDP)
847 ctrl |= UDPCS;
848 else
849 BUG();
850 } else
851 ctrl = eor | len | DescOwn;
852
853 if (frag == skb_shinfo(skb)->nr_frags - 1)
854 ctrl |= LastFrag;
855
856 txd = &cp->tx_ring[entry];
857 CP_VLAN_TX_TAG(txd, vlan_tag);
858 txd->addr = cpu_to_le64(mapping);
859 wmb();
860
861 txd->opts1 = cpu_to_le32(ctrl);
862 wmb();
863
864 cp->tx_skb[entry].skb = skb;
865 cp->tx_skb[entry].mapping = mapping;
866 cp->tx_skb[entry].frag = frag + 2;
867 entry = NEXT_TX(entry);
868 }
869
870 txd = &cp->tx_ring[first_entry];
871 CP_VLAN_TX_TAG(txd, vlan_tag);
872 txd->addr = cpu_to_le64(first_mapping);
873 wmb();
874
875 if (skb->ip_summed == CHECKSUM_HW) {
876 if (ip->protocol == IPPROTO_TCP)
877 txd->opts1 = cpu_to_le32(first_eor | first_len |
878 FirstFrag | DescOwn |
879 IPCS | TCPCS);
880 else if (ip->protocol == IPPROTO_UDP)
881 txd->opts1 = cpu_to_le32(first_eor | first_len |
882 FirstFrag | DescOwn |
883 IPCS | UDPCS);
884 else
885 BUG();
886 } else
887 txd->opts1 = cpu_to_le32(first_eor | first_len |
888 FirstFrag | DescOwn);
889 wmb();
890 }
891 cp->tx_head = entry;
892 if (netif_msg_tx_queued(cp))
893 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
894 dev->name, entry, skb->len);
895 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
896 netif_stop_queue(dev);
897
898 spin_unlock_irq(&cp->lock);
899
900 cpw8(TxPoll, NormalTxPoll);
901 dev->trans_start = jiffies;
902
903 return 0;
904 }
905
906 /* Set or clear the multicast filter for this adaptor.
907 This routine is not state sensitive and need not be SMP locked. */
908
909 static void __cp_set_rx_mode (struct net_device *dev)
910 {
911 struct cp_private *cp = netdev_priv(dev);
912 u32 mc_filter[2]; /* Multicast hash filter */
913 int i, rx_mode;
914 u32 tmp;
915
916 /* Note: do not reorder, GCC is clever about common statements. */
917 if (dev->flags & IFF_PROMISC) {
918 /* Unconditionally log net taps. */
919 printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n",
920 dev->name);
921 rx_mode =
922 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
923 AcceptAllPhys;
924 mc_filter[1] = mc_filter[0] = 0xffffffff;
925 } else if ((dev->mc_count > multicast_filter_limit)
926 || (dev->flags & IFF_ALLMULTI)) {
927 /* Too many to filter perfectly -- accept all multicasts. */
928 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
929 mc_filter[1] = mc_filter[0] = 0xffffffff;
930 } else {
931 struct dev_mc_list *mclist;
932 rx_mode = AcceptBroadcast | AcceptMyPhys;
933 mc_filter[1] = mc_filter[0] = 0;
934 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
935 i++, mclist = mclist->next) {
936 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
937
938 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
939 rx_mode |= AcceptMulticast;
940 }
941 }
942
943 /* We can safely update without stopping the chip. */
944 tmp = cp_rx_config | rx_mode;
945 if (cp->rx_config != tmp) {
946 cpw32_f (RxConfig, tmp);
947 cp->rx_config = tmp;
948 }
949 cpw32_f (MAR0 + 0, mc_filter[0]);
950 cpw32_f (MAR0 + 4, mc_filter[1]);
951 }
952
953 static void cp_set_rx_mode (struct net_device *dev)
954 {
955 unsigned long flags;
956 struct cp_private *cp = netdev_priv(dev);
957
958 spin_lock_irqsave (&cp->lock, flags);
959 __cp_set_rx_mode(dev);
960 spin_unlock_irqrestore (&cp->lock, flags);
961 }
962
963 static void __cp_get_stats(struct cp_private *cp)
964 {
965 /* only lower 24 bits valid; write any value to clear */
966 cp->net_stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
967 cpw32 (RxMissed, 0);
968 }
969
970 static struct net_device_stats *cp_get_stats(struct net_device *dev)
971 {
972 struct cp_private *cp = netdev_priv(dev);
973 unsigned long flags;
974
975 /* The chip only need report frame silently dropped. */
976 spin_lock_irqsave(&cp->lock, flags);
977 if (netif_running(dev) && netif_device_present(dev))
978 __cp_get_stats(cp);
979 spin_unlock_irqrestore(&cp->lock, flags);
980
981 return &cp->net_stats;
982 }
983
984 static void cp_stop_hw (struct cp_private *cp)
985 {
986 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
987 cpw16_f(IntrMask, 0);
988 cpw8(Cmd, 0);
989 cpw16_f(CpCmd, 0);
990 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
991
992 cp->rx_tail = 0;
993 cp->tx_head = cp->tx_tail = 0;
994 }
995
996 static void cp_reset_hw (struct cp_private *cp)
997 {
998 unsigned work = 1000;
999
1000 cpw8(Cmd, CmdReset);
1001
1002 while (work--) {
1003 if (!(cpr8(Cmd) & CmdReset))
1004 return;
1005
1006 set_current_state(TASK_UNINTERRUPTIBLE);
1007 schedule_timeout(10);
1008 }
1009
1010 printk(KERN_ERR "%s: hardware reset timeout\n", cp->dev->name);
1011 }
1012
1013 static inline void cp_start_hw (struct cp_private *cp)
1014 {
1015 cpw16(CpCmd, cp->cpcmd);
1016 cpw8(Cmd, RxOn | TxOn);
1017 }
1018
1019 static void cp_init_hw (struct cp_private *cp)
1020 {
1021 struct net_device *dev = cp->dev;
1022 dma_addr_t ring_dma;
1023
1024 cp_reset_hw(cp);
1025
1026 cpw8_f (Cfg9346, Cfg9346_Unlock);
1027
1028 /* Restore our idea of the MAC address. */
1029 cpw32_f (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1030 cpw32_f (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1031
1032 cp_start_hw(cp);
1033 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1034
1035 __cp_set_rx_mode(dev);
1036 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1037
1038 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1039 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1040 cpw8(Config3, PARMEnable);
1041 cp->wol_enabled = 0;
1042
1043 cpw8(Config5, cpr8(Config5) & PMEStatus);
1044
1045 cpw32_f(HiTxRingAddr, 0);
1046 cpw32_f(HiTxRingAddr + 4, 0);
1047
1048 ring_dma = cp->ring_dma;
1049 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1050 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1051
1052 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1053 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1054 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1055
1056 cpw16(MultiIntr, 0);
1057
1058 cpw16_f(IntrMask, cp_intr_mask);
1059
1060 cpw8_f(Cfg9346, Cfg9346_Lock);
1061 }
1062
1063 static int cp_refill_rx (struct cp_private *cp)
1064 {
1065 unsigned i;
1066
1067 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1068 struct sk_buff *skb;
1069
1070 skb = dev_alloc_skb(cp->rx_buf_sz + RX_OFFSET);
1071 if (!skb)
1072 goto err_out;
1073
1074 skb->dev = cp->dev;
1075 skb_reserve(skb, RX_OFFSET);
1076
1077 cp->rx_skb[i].mapping = pci_map_single(cp->pdev,
1078 skb->tail, cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1079 cp->rx_skb[i].skb = skb;
1080 cp->rx_skb[i].frag = 0;
1081
1082 cp->rx_ring[i].opts2 = 0;
1083 cp->rx_ring[i].addr = cpu_to_le64(cp->rx_skb[i].mapping);
1084 if (i == (CP_RX_RING_SIZE - 1))
1085 cp->rx_ring[i].opts1 =
1086 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1087 else
1088 cp->rx_ring[i].opts1 =
1089 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1090 }
1091
1092 return 0;
1093
1094 err_out:
1095 cp_clean_rings(cp);
1096 return -ENOMEM;
1097 }
1098
1099 static int cp_init_rings (struct cp_private *cp)
1100 {
1101 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1102 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1103
1104 cp->rx_tail = 0;
1105 cp->tx_head = cp->tx_tail = 0;
1106
1107 return cp_refill_rx (cp);
1108 }
1109
1110 static int cp_alloc_rings (struct cp_private *cp)
1111 {
1112 void *mem;
1113
1114 mem = pci_alloc_consistent(cp->pdev, CP_RING_BYTES, &cp->ring_dma);
1115 if (!mem)
1116 return -ENOMEM;
1117
1118 cp->rx_ring = mem;
1119 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1120
1121 mem += (CP_RING_BYTES - CP_STATS_SIZE);
1122 cp->nic_stats = mem;
1123 cp->nic_stats_dma = cp->ring_dma + (CP_RING_BYTES - CP_STATS_SIZE);
1124
1125 return cp_init_rings(cp);
1126 }
1127
1128 static void cp_clean_rings (struct cp_private *cp)
1129 {
1130 unsigned i;
1131
1132 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1133 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1134
1135 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1136 if (cp->rx_skb[i].skb) {
1137 pci_unmap_single(cp->pdev, cp->rx_skb[i].mapping,
1138 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1139 dev_kfree_skb(cp->rx_skb[i].skb);
1140 }
1141 }
1142
1143 for (i = 0; i < CP_TX_RING_SIZE; i++) {
1144 if (cp->tx_skb[i].skb) {
1145 struct sk_buff *skb = cp->tx_skb[i].skb;
1146 pci_unmap_single(cp->pdev, cp->tx_skb[i].mapping,
1147 skb->len, PCI_DMA_TODEVICE);
1148 dev_kfree_skb(skb);
1149 cp->net_stats.tx_dropped++;
1150 }
1151 }
1152
1153 memset(&cp->rx_skb, 0, sizeof(struct ring_info) * CP_RX_RING_SIZE);
1154 memset(&cp->tx_skb, 0, sizeof(struct ring_info) * CP_TX_RING_SIZE);
1155 }
1156
1157 static void cp_free_rings (struct cp_private *cp)
1158 {
1159 cp_clean_rings(cp);
1160 pci_free_consistent(cp->pdev, CP_RING_BYTES, cp->rx_ring, cp->ring_dma);
1161 cp->rx_ring = NULL;
1162 cp->tx_ring = NULL;
1163 cp->nic_stats = NULL;
1164 }
1165
1166 static int cp_open (struct net_device *dev)
1167 {
1168 struct cp_private *cp = netdev_priv(dev);
1169 int rc;
1170
1171 if (netif_msg_ifup(cp))
1172 printk(KERN_DEBUG "%s: enabling interface\n", dev->name);
1173
1174 rc = cp_alloc_rings(cp);
1175 if (rc)
1176 return rc;
1177
1178 cp_init_hw(cp);
1179
1180 rc = request_irq(dev->irq, cp_interrupt, SA_SHIRQ, dev->name, dev);
1181 if (rc)
1182 goto err_out_hw;
1183
1184 netif_carrier_off(dev);
1185 mii_check_media(&cp->mii_if, netif_msg_link(cp), TRUE);
1186 netif_start_queue(dev);
1187
1188 return 0;
1189
1190 err_out_hw:
1191 cp_stop_hw(cp);
1192 cp_free_rings(cp);
1193 return rc;
1194 }
1195
1196 static int cp_close (struct net_device *dev)
1197 {
1198 struct cp_private *cp = netdev_priv(dev);
1199 unsigned long flags;
1200
1201 if (netif_msg_ifdown(cp))
1202 printk(KERN_DEBUG "%s: disabling interface\n", dev->name);
1203
1204 spin_lock_irqsave(&cp->lock, flags);
1205
1206 netif_stop_queue(dev);
1207 netif_carrier_off(dev);
1208
1209 cp_stop_hw(cp);
1210
1211 spin_unlock_irqrestore(&cp->lock, flags);
1212
1213 synchronize_irq(dev->irq);
1214 free_irq(dev->irq, dev);
1215
1216 cp_free_rings(cp);
1217 return 0;
1218 }
1219
1220 #ifdef BROKEN
1221 static int cp_change_mtu(struct net_device *dev, int new_mtu)
1222 {
1223 struct cp_private *cp = netdev_priv(dev);
1224 int rc;
1225 unsigned long flags;
1226
1227 /* check for invalid MTU, according to hardware limits */
1228 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1229 return -EINVAL;
1230
1231 /* if network interface not up, no need for complexity */
1232 if (!netif_running(dev)) {
1233 dev->mtu = new_mtu;
1234 cp_set_rxbufsize(cp); /* set new rx buf size */
1235 return 0;
1236 }
1237
1238 spin_lock_irqsave(&cp->lock, flags);
1239
1240 cp_stop_hw(cp); /* stop h/w and free rings */
1241 cp_clean_rings(cp);
1242
1243 dev->mtu = new_mtu;
1244 cp_set_rxbufsize(cp); /* set new rx buf size */
1245
1246 rc = cp_init_rings(cp); /* realloc and restart h/w */
1247 cp_start_hw(cp);
1248
1249 spin_unlock_irqrestore(&cp->lock, flags);
1250
1251 return rc;
1252 }
1253 #endif /* BROKEN */
1254
1255 static char mii_2_8139_map[8] = {
1256 BasicModeCtrl,
1257 BasicModeStatus,
1258 0,
1259 0,
1260 NWayAdvert,
1261 NWayLPAR,
1262 NWayExpansion,
1263 0
1264 };
1265
1266 static int mdio_read(struct net_device *dev, int phy_id, int location)
1267 {
1268 struct cp_private *cp = netdev_priv(dev);
1269
1270 return location < 8 && mii_2_8139_map[location] ?
1271 readw(cp->regs + mii_2_8139_map[location]) : 0;
1272 }
1273
1274
1275 static void mdio_write(struct net_device *dev, int phy_id, int location,
1276 int value)
1277 {
1278 struct cp_private *cp = netdev_priv(dev);
1279
1280 if (location == 0) {
1281 cpw8(Cfg9346, Cfg9346_Unlock);
1282 cpw16(BasicModeCtrl, value);
1283 cpw8(Cfg9346, Cfg9346_Lock);
1284 } else if (location < 8 && mii_2_8139_map[location])
1285 cpw16(mii_2_8139_map[location], value);
1286 }
1287
1288 /* Set the ethtool Wake-on-LAN settings */
1289 static int netdev_set_wol (struct cp_private *cp,
1290 const struct ethtool_wolinfo *wol)
1291 {
1292 u8 options;
1293
1294 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1295 /* If WOL is being disabled, no need for complexity */
1296 if (wol->wolopts) {
1297 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1298 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1299 }
1300
1301 cpw8 (Cfg9346, Cfg9346_Unlock);
1302 cpw8 (Config3, options);
1303 cpw8 (Cfg9346, Cfg9346_Lock);
1304
1305 options = 0; /* Paranoia setting */
1306 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1307 /* If WOL is being disabled, no need for complexity */
1308 if (wol->wolopts) {
1309 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1310 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1311 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1312 }
1313
1314 cpw8 (Config5, options);
1315
1316 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1317
1318 return 0;
1319 }
1320
1321 /* Get the ethtool Wake-on-LAN settings */
1322 static void netdev_get_wol (struct cp_private *cp,
1323 struct ethtool_wolinfo *wol)
1324 {
1325 u8 options;
1326
1327 wol->wolopts = 0; /* Start from scratch */
1328 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1329 WAKE_MCAST | WAKE_UCAST;
1330 /* We don't need to go on if WOL is disabled */
1331 if (!cp->wol_enabled) return;
1332
1333 options = cpr8 (Config3);
1334 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1335 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1336
1337 options = 0; /* Paranoia setting */
1338 options = cpr8 (Config5);
1339 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1340 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1341 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1342 }
1343
1344 static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1345 {
1346 struct cp_private *cp = netdev_priv(dev);
1347
1348 strcpy (info->driver, DRV_NAME);
1349 strcpy (info->version, DRV_VERSION);
1350 strcpy (info->bus_info, pci_name(cp->pdev));
1351 }
1352
1353 static int cp_get_regs_len(struct net_device *dev)
1354 {
1355 return CP_REGS_SIZE;
1356 }
1357
1358 static int cp_get_stats_count (struct net_device *dev)
1359 {
1360 return CP_NUM_STATS;
1361 }
1362
1363 static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1364 {
1365 struct cp_private *cp = netdev_priv(dev);
1366 int rc;
1367 unsigned long flags;
1368
1369 spin_lock_irqsave(&cp->lock, flags);
1370 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1371 spin_unlock_irqrestore(&cp->lock, flags);
1372
1373 return rc;
1374 }
1375
1376 static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1377 {
1378 struct cp_private *cp = netdev_priv(dev);
1379 int rc;
1380 unsigned long flags;
1381
1382 spin_lock_irqsave(&cp->lock, flags);
1383 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1384 spin_unlock_irqrestore(&cp->lock, flags);
1385
1386 return rc;
1387 }
1388
1389 static int cp_nway_reset(struct net_device *dev)
1390 {
1391 struct cp_private *cp = netdev_priv(dev);
1392 return mii_nway_restart(&cp->mii_if);
1393 }
1394
1395 static u32 cp_get_msglevel(struct net_device *dev)
1396 {
1397 struct cp_private *cp = netdev_priv(dev);
1398 return cp->msg_enable;
1399 }
1400
1401 static void cp_set_msglevel(struct net_device *dev, u32 value)
1402 {
1403 struct cp_private *cp = netdev_priv(dev);
1404 cp->msg_enable = value;
1405 }
1406
1407 static u32 cp_get_rx_csum(struct net_device *dev)
1408 {
1409 struct cp_private *cp = netdev_priv(dev);
1410 return (cpr16(CpCmd) & RxChkSum) ? 1 : 0;
1411 }
1412
1413 static int cp_set_rx_csum(struct net_device *dev, u32 data)
1414 {
1415 struct cp_private *cp = netdev_priv(dev);
1416 u16 cmd = cp->cpcmd, newcmd;
1417
1418 newcmd = cmd;
1419
1420 if (data)
1421 newcmd |= RxChkSum;
1422 else
1423 newcmd &= ~RxChkSum;
1424
1425 if (newcmd != cmd) {
1426 unsigned long flags;
1427
1428 spin_lock_irqsave(&cp->lock, flags);
1429 cp->cpcmd = newcmd;
1430 cpw16_f(CpCmd, newcmd);
1431 spin_unlock_irqrestore(&cp->lock, flags);
1432 }
1433
1434 return 0;
1435 }
1436
1437 static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1438 void *p)
1439 {
1440 struct cp_private *cp = netdev_priv(dev);
1441 unsigned long flags;
1442
1443 if (regs->len < CP_REGS_SIZE)
1444 return /* -EINVAL */;
1445
1446 regs->version = CP_REGS_VER;
1447
1448 spin_lock_irqsave(&cp->lock, flags);
1449 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1450 spin_unlock_irqrestore(&cp->lock, flags);
1451 }
1452
1453 static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1454 {
1455 struct cp_private *cp = netdev_priv(dev);
1456 unsigned long flags;
1457
1458 spin_lock_irqsave (&cp->lock, flags);
1459 netdev_get_wol (cp, wol);
1460 spin_unlock_irqrestore (&cp->lock, flags);
1461 }
1462
1463 static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1464 {
1465 struct cp_private *cp = netdev_priv(dev);
1466 unsigned long flags;
1467 int rc;
1468
1469 spin_lock_irqsave (&cp->lock, flags);
1470 rc = netdev_set_wol (cp, wol);
1471 spin_unlock_irqrestore (&cp->lock, flags);
1472
1473 return rc;
1474 }
1475
1476 static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1477 {
1478 switch (stringset) {
1479 case ETH_SS_STATS:
1480 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
1481 break;
1482 default:
1483 BUG();
1484 break;
1485 }
1486 }
1487
1488 static void cp_get_ethtool_stats (struct net_device *dev,
1489 struct ethtool_stats *estats, u64 *tmp_stats)
1490 {
1491 struct cp_private *cp = netdev_priv(dev);
1492 unsigned int work = 100;
1493 int i;
1494
1495 /* begin NIC statistics dump */
1496 cpw32(StatsAddr + 4, (cp->nic_stats_dma >> 16) >> 16);
1497 cpw32(StatsAddr, (cp->nic_stats_dma & 0xffffffff) | DumpStats);
1498 cpr32(StatsAddr);
1499
1500 while (work-- > 0) {
1501 if ((cpr32(StatsAddr) & DumpStats) == 0)
1502 break;
1503 cpu_relax();
1504 }
1505
1506 if (cpr32(StatsAddr) & DumpStats)
1507 return /* -EIO */;
1508
1509 i = 0;
1510 tmp_stats[i++] = le64_to_cpu(cp->nic_stats->tx_ok);
1511 tmp_stats[i++] = le64_to_cpu(cp->nic_stats->rx_ok);
1512 tmp_stats[i++] = le64_to_cpu(cp->nic_stats->tx_err);
1513 tmp_stats[i++] = le32_to_cpu(cp->nic_stats->rx_err);
1514 tmp_stats[i++] = le16_to_cpu(cp->nic_stats->rx_fifo);
1515 tmp_stats[i++] = le16_to_cpu(cp->nic_stats->frame_align);
1516 tmp_stats[i++] = le32_to_cpu(cp->nic_stats->tx_ok_1col);
1517 tmp_stats[i++] = le32_to_cpu(cp->nic_stats->tx_ok_mcol);
1518 tmp_stats[i++] = le64_to_cpu(cp->nic_stats->rx_ok_phys);
1519 tmp_stats[i++] = le64_to_cpu(cp->nic_stats->rx_ok_bcast);
1520 tmp_stats[i++] = le32_to_cpu(cp->nic_stats->rx_ok_mcast);
1521 tmp_stats[i++] = le16_to_cpu(cp->nic_stats->tx_abort);
1522 tmp_stats[i++] = le16_to_cpu(cp->nic_stats->tx_underrun);
1523 tmp_stats[i++] = cp->cp_stats.rx_frags;
1524 if (i != CP_NUM_STATS)
1525 BUG();
1526 }
1527
1528 static struct ethtool_ops cp_ethtool_ops = {
1529 .get_drvinfo = cp_get_drvinfo,
1530 .get_regs_len = cp_get_regs_len,
1531 .get_stats_count = cp_get_stats_count,
1532 .get_settings = cp_get_settings,
1533 .set_settings = cp_set_settings,
1534 .nway_reset = cp_nway_reset,
1535 .get_link = ethtool_op_get_link,
1536 .get_msglevel = cp_get_msglevel,
1537 .set_msglevel = cp_set_msglevel,
1538 .get_rx_csum = cp_get_rx_csum,
1539 .set_rx_csum = cp_set_rx_csum,
1540 .get_tx_csum = ethtool_op_get_tx_csum,
1541 .set_tx_csum = ethtool_op_set_tx_csum, /* local! */
1542 .get_sg = ethtool_op_get_sg,
1543 .set_sg = ethtool_op_set_sg,
1544 .get_regs = cp_get_regs,
1545 .get_wol = cp_get_wol,
1546 .set_wol = cp_set_wol,
1547 .get_strings = cp_get_strings,
1548 .get_ethtool_stats = cp_get_ethtool_stats,
1549 };
1550
1551 static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1552 {
1553 struct cp_private *cp = netdev_priv(dev);
1554 int rc;
1555 unsigned long flags;
1556
1557 if (!netif_running(dev))
1558 return -EINVAL;
1559
1560 spin_lock_irqsave(&cp->lock, flags);
1561 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1562 spin_unlock_irqrestore(&cp->lock, flags);
1563 return rc;
1564 }
1565
1566 /* Serial EEPROM section. */
1567
1568 /* EEPROM_Ctrl bits. */
1569 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1570 #define EE_CS 0x08 /* EEPROM chip select. */
1571 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1572 #define EE_WRITE_0 0x00
1573 #define EE_WRITE_1 0x02
1574 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1575 #define EE_ENB (0x80 | EE_CS)
1576
1577 /* Delay between EEPROM clock transitions.
1578 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1579 */
1580
1581 #define eeprom_delay() readl(ee_addr)
1582
1583 /* The EEPROM commands include the alway-set leading bit. */
1584 #define EE_WRITE_CMD (5)
1585 #define EE_READ_CMD (6)
1586 #define EE_ERASE_CMD (7)
1587
1588 static int read_eeprom (void *ioaddr, int location, int addr_len)
1589 {
1590 int i;
1591 unsigned retval = 0;
1592 void *ee_addr = ioaddr + Cfg9346;
1593 int read_cmd = location | (EE_READ_CMD << addr_len);
1594
1595 writeb (EE_ENB & ~EE_CS, ee_addr);
1596 writeb (EE_ENB, ee_addr);
1597 eeprom_delay ();
1598
1599 /* Shift the read command bits out. */
1600 for (i = 4 + addr_len; i >= 0; i--) {
1601 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1602 writeb (EE_ENB | dataval, ee_addr);
1603 eeprom_delay ();
1604 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1605 eeprom_delay ();
1606 }
1607 writeb (EE_ENB, ee_addr);
1608 eeprom_delay ();
1609
1610 for (i = 16; i > 0; i--) {
1611 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1612 eeprom_delay ();
1613 retval =
1614 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1615 0);
1616 writeb (EE_ENB, ee_addr);
1617 eeprom_delay ();
1618 }
1619
1620 /* Terminate the EEPROM access. */
1621 writeb (~EE_CS, ee_addr);
1622 eeprom_delay ();
1623
1624 return retval;
1625 }
1626
1627 /* Put the board into D3cold state and wait for WakeUp signal */
1628 static void cp_set_d3_state (struct cp_private *cp)
1629 {
1630 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1631 pci_set_power_state (cp->pdev, 3);
1632 }
1633
1634 static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1635 {
1636 struct net_device *dev;
1637 struct cp_private *cp;
1638 int rc;
1639 void *regs;
1640 long pciaddr;
1641 unsigned int addr_len, i, pci_using_dac;
1642 u8 pci_rev;
1643
1644 #ifndef MODULE
1645 static int version_printed;
1646 if (version_printed++ == 0)
1647 printk("%s", version);
1648 #endif
1649
1650 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
1651
1652 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
1653 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev < 0x20) {
1654 printk(KERN_ERR PFX "pci dev %s (id %04x:%04x rev %02x) is not an 8139C+ compatible chip\n",
1655 pci_name(pdev), pdev->vendor, pdev->device, pci_rev);
1656 printk(KERN_ERR PFX "Try the \"8139too\" driver instead.\n");
1657 return -ENODEV;
1658 }
1659
1660 dev = alloc_etherdev(sizeof(struct cp_private));
1661 if (!dev)
1662 return -ENOMEM;
1663 SET_MODULE_OWNER(dev);
1664 SET_NETDEV_DEV(dev, &pdev->dev);
1665
1666 cp = netdev_priv(dev);
1667 cp->pdev = pdev;
1668 cp->dev = dev;
1669 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1670 spin_lock_init (&cp->lock);
1671 cp->mii_if.dev = dev;
1672 cp->mii_if.mdio_read = mdio_read;
1673 cp->mii_if.mdio_write = mdio_write;
1674 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1675 cp->mii_if.phy_id_mask = 0x1f;
1676 cp->mii_if.reg_num_mask = 0x1f;
1677 cp_set_rxbufsize(cp);
1678
1679 rc = pci_enable_device(pdev);
1680 if (rc)
1681 goto err_out_free;
1682
1683 rc = pci_set_mwi(pdev);
1684 if (rc)
1685 goto err_out_disable;
1686
1687 rc = pci_request_regions(pdev, DRV_NAME);
1688 if (rc)
1689 goto err_out_mwi;
1690
1691 pciaddr = pci_resource_start(pdev, 1);
1692 if (!pciaddr) {
1693 rc = -EIO;
1694 printk(KERN_ERR PFX "no MMIO resource for pci dev %s\n",
1695 pci_name(pdev));
1696 goto err_out_res;
1697 }
1698 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1699 rc = -EIO;
1700 printk(KERN_ERR PFX "MMIO resource (%lx) too small on pci dev %s\n",
1701 pci_resource_len(pdev, 1), pci_name(pdev));
1702 goto err_out_res;
1703 }
1704
1705 /* Configure DMA attributes. */
1706 if ((sizeof(dma_addr_t) > 4) &&
1707 !pci_set_consistent_dma_mask(pdev, 0xffffffffffffffffULL) &&
1708 !pci_set_dma_mask(pdev, 0xffffffffffffffffULL)) {
1709 pci_using_dac = 1;
1710 } else {
1711 pci_using_dac = 0;
1712
1713 rc = pci_set_dma_mask(pdev, 0xffffffffULL);
1714 if (rc) {
1715 printk(KERN_ERR PFX "No usable DMA configuration, "
1716 "aborting.\n");
1717 goto err_out_res;
1718 }
1719 rc = pci_set_consistent_dma_mask(pdev, 0xffffffffULL);
1720 if (rc) {
1721 printk(KERN_ERR PFX "No usable consistent DMA configuration, "
1722 "aborting.\n");
1723 goto err_out_res;
1724 }
1725 }
1726
1727 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1728 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1729
1730 regs = ioremap(pciaddr, CP_REGS_SIZE);
1731 if (!regs) {
1732 rc = -EIO;
1733 printk(KERN_ERR PFX "Cannot map PCI MMIO (%lx@%lx) on pci dev %s\n",
1734 pci_resource_len(pdev, 1), pciaddr, pci_name(pdev));
1735 goto err_out_res;
1736 }
1737 dev->base_addr = (unsigned long) regs;
1738 cp->regs = regs;
1739
1740 cp_stop_hw(cp);
1741
1742 #ifdef CONFIG_SH_SECUREEDGE5410
1743 /* Don't rely on the eeprom, get MAC from chip. */
1744 for (i = 0; i < 6; i++)
1745 dev->dev_addr[i] = readb(regs + MAC0 + i);
1746 #else
1747 /* read MAC address from EEPROM */
1748 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1749 for (i = 0; i < 3; i++)
1750 ((u16 *) (dev->dev_addr))[i] =
1751 le16_to_cpu (read_eeprom (regs, i + 7, addr_len));
1752 #endif
1753
1754 dev->open = cp_open;
1755 dev->stop = cp_close;
1756 dev->set_multicast_list = cp_set_rx_mode;
1757 dev->hard_start_xmit = cp_start_xmit;
1758 dev->get_stats = cp_get_stats;
1759 dev->do_ioctl = cp_ioctl;
1760 dev->poll = cp_rx_poll;
1761 dev->weight = 16; /* arbitrary? from NAPI_HOWTO.txt. */
1762 #ifdef BROKEN
1763 dev->change_mtu = cp_change_mtu;
1764 #endif
1765 dev->ethtool_ops = &cp_ethtool_ops;
1766 #if 0
1767 dev->tx_timeout = cp_tx_timeout;
1768 dev->watchdog_timeo = TX_TIMEOUT;
1769 #endif
1770
1771 #if CP_VLAN_TAG_USED
1772 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1773 dev->vlan_rx_register = cp_vlan_rx_register;
1774 dev->vlan_rx_kill_vid = cp_vlan_rx_kill_vid;
1775 #endif
1776
1777 if (pci_using_dac)
1778 dev->features |= NETIF_F_HIGHDMA;
1779
1780 dev->irq = pdev->irq;
1781
1782 rc = register_netdev(dev);
1783 if (rc)
1784 goto err_out_iomap;
1785
1786 printk (KERN_INFO "%s: RTL-8139C+ at 0x%lx, "
1787 "%02x:%02x:%02x:%02x:%02x:%02x, "
1788 "IRQ %d\n",
1789 dev->name,
1790 dev->base_addr,
1791 dev->dev_addr[0], dev->dev_addr[1],
1792 dev->dev_addr[2], dev->dev_addr[3],
1793 dev->dev_addr[4], dev->dev_addr[5],
1794 dev->irq);
1795
1796 pci_set_drvdata(pdev, dev);
1797
1798 /* enable busmastering and memory-write-invalidate */
1799 pci_set_master(pdev);
1800
1801 if (cp->wol_enabled) cp_set_d3_state (cp);
1802
1803 return 0;
1804
1805 err_out_iomap:
1806 iounmap(regs);
1807 err_out_res:
1808 pci_release_regions(pdev);
1809 err_out_mwi:
1810 pci_clear_mwi(pdev);
1811 err_out_disable:
1812 pci_disable_device(pdev);
1813 err_out_free:
1814 free_netdev(dev);
1815 return rc;
1816 }
1817
1818 static void cp_remove_one (struct pci_dev *pdev)
1819 {
1820 struct net_device *dev = pci_get_drvdata(pdev);
1821 struct cp_private *cp = netdev_priv(dev);
1822
1823 if (!dev)
1824 BUG();
1825 unregister_netdev(dev);
1826 iounmap(cp->regs);
1827 if (cp->wol_enabled) pci_set_power_state (pdev, 0);
1828 pci_release_regions(pdev);
1829 pci_clear_mwi(pdev);
1830 pci_disable_device(pdev);
1831 pci_set_drvdata(pdev, NULL);
1832 free_netdev(dev);
1833 }
1834
1835 #ifdef CONFIG_PM
1836 static int cp_suspend (struct pci_dev *pdev, u32 state)
1837 {
1838 struct net_device *dev;
1839 struct cp_private *cp;
1840 unsigned long flags;
1841
1842 dev = pci_get_drvdata (pdev);
1843 cp = netdev_priv(dev);
1844
1845 if (!dev || !netif_running (dev)) return 0;
1846
1847 netif_device_detach (dev);
1848 netif_stop_queue (dev);
1849
1850 spin_lock_irqsave (&cp->lock, flags);
1851
1852 /* Disable Rx and Tx */
1853 cpw16 (IntrMask, 0);
1854 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
1855
1856 spin_unlock_irqrestore (&cp->lock, flags);
1857
1858 if (cp->pdev && cp->wol_enabled) {
1859 pci_save_state (cp->pdev, cp->power_state);
1860 cp_set_d3_state (cp);
1861 }
1862
1863 return 0;
1864 }
1865
1866 static int cp_resume (struct pci_dev *pdev)
1867 {
1868 struct net_device *dev;
1869 struct cp_private *cp;
1870
1871 dev = pci_get_drvdata (pdev);
1872 cp = netdev_priv(dev);
1873
1874 netif_device_attach (dev);
1875
1876 if (cp->pdev && cp->wol_enabled) {
1877 pci_set_power_state (cp->pdev, 0);
1878 pci_restore_state (cp->pdev, cp->power_state);
1879 }
1880
1881 cp_init_hw (cp);
1882 netif_start_queue (dev);
1883
1884 return 0;
1885 }
1886 #endif /* CONFIG_PM */
1887
1888 static struct pci_driver cp_driver = {
1889 .name = DRV_NAME,
1890 .id_table = cp_pci_tbl,
1891 .probe = cp_init_one,
1892 .remove = cp_remove_one,
1893 #ifdef CONFIG_PM
1894 .resume = cp_resume,
1895 .suspend = cp_suspend,
1896 #endif
1897 };
1898
1899 static int __init cp_init (void)
1900 {
1901 #ifdef MODULE
1902 printk("%s", version);
1903 #endif
1904 return pci_module_init (&cp_driver);
1905 }
1906
1907 static void __exit cp_exit (void)
1908 {
1909 pci_unregister_driver (&cp_driver);
1910 }
1911
1912 module_init(cp_init);
1913 module_exit(cp_exit);
MOXA 2.6.9 from sdlinux-moxaart.tgz