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MOXA linux-2.6.x / linux-2.6.9-uc0 from sdlinux-moxaart.tgz
[linux-2.6.9-moxart.git] / drivers / net / pci-skeleton.c
blobf931248987f797ff995f1fd024810b66d2dc6254
1 /*
2
3 drivers/net/pci-skeleton.c
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6
7 Original code came from 8139too.c, which in turns was based
8 originally on Donald Becker's rtl8139.c driver, versions 1.11
9 and older. This driver was originally based on rtl8139.c
10 version 1.07. Header of rtl8139.c version 1.11:
11
12 -----<snip>-----
13
14 Written 1997-2000 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41
42 -----------------------------------------------------------------------------
43
44 Theory of Operation
45
46 I. Board Compatibility
47
48 This device driver is designed for the RealTek RTL8139 series, the RealTek
49 Fast Ethernet controllers for PCI and CardBus. This chip is used on many
50 low-end boards, sometimes with its markings changed.
51
52
53 II. Board-specific settings
54
55 PCI bus devices are configured by the system at boot time, so no jumpers
56 need to be set on the board. The system BIOS will assign the
57 PCI INTA signal to a (preferably otherwise unused) system IRQ line.
58
59 III. Driver operation
60
61 IIIa. Rx Ring buffers
62
63 The receive unit uses a single linear ring buffer rather than the more
64 common (and more efficient) descriptor-based architecture. Incoming frames
65 are sequentially stored into the Rx region, and the host copies them into
66 skbuffs.
67
68 Comment: While it is theoretically possible to process many frames in place,
69 any delay in Rx processing would cause us to drop frames. More importantly,
70 the Linux protocol stack is not designed to operate in this manner.
71
72 IIIb. Tx operation
73
74 The RTL8139 uses a fixed set of four Tx descriptors in register space.
75 In a stunningly bad design choice, Tx frames must be 32 bit aligned. Linux
76 aligns the IP header on word boundaries, and 14 byte ethernet header means
77 that almost all frames will need to be copied to an alignment buffer.
78
79 IVb. References
80
81 http://www.realtek.com.tw/cn/cn.html
82 http://www.scyld.com/expert/NWay.html
83
84 IVc. Errata
85
86 */
87
88 #include <linux/config.h>
89 #include <linux/module.h>
90 #include <linux/kernel.h>
91 #include <linux/pci.h>
92 #include <linux/init.h>
93 #include <linux/ioport.h>
94 #include <linux/netdevice.h>
95 #include <linux/etherdevice.h>
96 #include <linux/delay.h>
97 #include <linux/ethtool.h>
98 #include <linux/mii.h>
99 #include <linux/crc32.h>
100 #include <asm/io.h>
101
102 #define NETDRV_VERSION "1.0.0"
103 #define MODNAME "netdrv"
104 #define NETDRV_DRIVER_LOAD_MSG "MyVendor Fast Ethernet driver " NETDRV_VERSION " loaded"
105 #define PFX MODNAME ": "
106
107 static char version[] __devinitdata =
108 KERN_INFO NETDRV_DRIVER_LOAD_MSG "\n"
109 KERN_INFO " Support available from http://foo.com/bar/baz.html\n";
110
111 /* define to 1 to enable PIO instead of MMIO */
112 #undef USE_IO_OPS
113
114 /* define to 1 to enable copious debugging info */
115 #undef NETDRV_DEBUG
116
117 /* define to 1 to disable lightweight runtime debugging checks */
118 #undef NETDRV_NDEBUG
119
120
121 #ifdef NETDRV_DEBUG
122 /* note: prints function name for you */
123 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
124 #else
125 # define DPRINTK(fmt, args...)
126 #endif
127
128 #ifdef NETDRV_NDEBUG
129 # define assert(expr) do {} while (0)
130 #else
131 # define assert(expr) \
132 if(!(expr)) { \
133 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
134 #expr,__FILE__,__FUNCTION__,__LINE__); \
135 }
136 #endif
137
138
139 /* A few user-configurable values. */
140 /* media options */
141 static int media[] = {-1, -1, -1, -1, -1, -1, -1, -1};
142
143 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
144 static int max_interrupt_work = 20;
145
146 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
147 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
148 static int multicast_filter_limit = 32;
149
150 /* Size of the in-memory receive ring. */
151 #define RX_BUF_LEN_IDX 2 /* 0==8K, 1==16K, 2==32K, 3==64K */
152 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
153 #define RX_BUF_PAD 16
154 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
155 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
156
157 /* Number of Tx descriptor registers. */
158 #define NUM_TX_DESC 4
159
160 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
161 #define MAX_ETH_FRAME_SIZE 1536
162
163 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
164 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
165 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
166
167 /* PCI Tuning Parameters
168 Threshold is bytes transferred to chip before transmission starts. */
169 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
170
171 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
172 #define RX_FIFO_THRESH 6 /* Rx buffer level before first PCI xfer. */
173 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
174 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
175
176
177 /* Operational parameters that usually are not changed. */
178 /* Time in jiffies before concluding the transmitter is hung. */
179 #define TX_TIMEOUT (6*HZ)
180
181
182 enum {
183 HAS_CHIP_XCVR = 0x020000,
184 HAS_LNK_CHNG = 0x040000,
185 };
186
187 #define NETDRV_MIN_IO_SIZE 0x80
188 #define RTL8139B_IO_SIZE 256
189
190 #define NETDRV_CAPS HAS_CHIP_XCVR|HAS_LNK_CHNG
191
192 typedef enum {
193 RTL8139 = 0,
194 NETDRV_CB,
195 SMC1211TX,
196 /*MPX5030,*/
197 DELTA8139,
198 ADDTRON8139,
199 } board_t;
200
201
202 /* indexed by board_t, above */
203 static struct {
204 const char *name;
205 } board_info[] __devinitdata = {
206 { "RealTek RTL8139 Fast Ethernet" },
207 { "RealTek RTL8139B PCI/CardBus" },
208 { "SMC1211TX EZCard 10/100 (RealTek RTL8139)" },
209 /* { MPX5030, "Accton MPX5030 (RealTek RTL8139)" },*/
210 { "Delta Electronics 8139 10/100BaseTX" },
211 { "Addtron Technolgy 8139 10/100BaseTX" },
212 };
213
214
215 static struct pci_device_id netdrv_pci_tbl[] = {
216 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
217 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, NETDRV_CB },
218 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMC1211TX },
219 /* {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MPX5030 },*/
220 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DELTA8139 },
221 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ADDTRON8139 },
222 {0,}
223 };
224 MODULE_DEVICE_TABLE (pci, netdrv_pci_tbl);
225
226
227 /* The rest of these values should never change. */
228
229 /* Symbolic offsets to registers. */
230 enum NETDRV_registers {
231 MAC0 = 0, /* Ethernet hardware address. */
232 MAR0 = 8, /* Multicast filter. */
233 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
234 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
235 RxBuf = 0x30,
236 RxEarlyCnt = 0x34,
237 RxEarlyStatus = 0x36,
238 ChipCmd = 0x37,
239 RxBufPtr = 0x38,
240 RxBufAddr = 0x3A,
241 IntrMask = 0x3C,
242 IntrStatus = 0x3E,
243 TxConfig = 0x40,
244 ChipVersion = 0x43,
245 RxConfig = 0x44,
246 Timer = 0x48, /* A general-purpose counter. */
247 RxMissed = 0x4C, /* 24 bits valid, write clears. */
248 Cfg9346 = 0x50,
249 Config0 = 0x51,
250 Config1 = 0x52,
251 FlashReg = 0x54,
252 MediaStatus = 0x58,
253 Config3 = 0x59,
254 Config4 = 0x5A, /* absent on RTL-8139A */
255 HltClk = 0x5B,
256 MultiIntr = 0x5C,
257 TxSummary = 0x60,
258 BasicModeCtrl = 0x62,
259 BasicModeStatus = 0x64,
260 NWayAdvert = 0x66,
261 NWayLPAR = 0x68,
262 NWayExpansion = 0x6A,
263 /* Undocumented registers, but required for proper operation. */
264 FIFOTMS = 0x70, /* FIFO Control and test. */
265 CSCR = 0x74, /* Chip Status and Configuration Register. */
266 PARA78 = 0x78,
267 PARA7c = 0x7c, /* Magic transceiver parameter register. */
268 Config5 = 0xD8, /* absent on RTL-8139A */
269 };
270
271 enum ClearBitMasks {
272 MultiIntrClear = 0xF000,
273 ChipCmdClear = 0xE2,
274 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
275 };
276
277 enum ChipCmdBits {
278 CmdReset = 0x10,
279 CmdRxEnb = 0x08,
280 CmdTxEnb = 0x04,
281 RxBufEmpty = 0x01,
282 };
283
284 /* Interrupt register bits, using my own meaningful names. */
285 enum IntrStatusBits {
286 PCIErr = 0x8000,
287 PCSTimeout = 0x4000,
288 RxFIFOOver = 0x40,
289 RxUnderrun = 0x20,
290 RxOverflow = 0x10,
291 TxErr = 0x08,
292 TxOK = 0x04,
293 RxErr = 0x02,
294 RxOK = 0x01,
295 };
296 enum TxStatusBits {
297 TxHostOwns = 0x2000,
298 TxUnderrun = 0x4000,
299 TxStatOK = 0x8000,
300 TxOutOfWindow = 0x20000000,
301 TxAborted = 0x40000000,
302 TxCarrierLost = 0x80000000,
303 };
304 enum RxStatusBits {
305 RxMulticast = 0x8000,
306 RxPhysical = 0x4000,
307 RxBroadcast = 0x2000,
308 RxBadSymbol = 0x0020,
309 RxRunt = 0x0010,
310 RxTooLong = 0x0008,
311 RxCRCErr = 0x0004,
312 RxBadAlign = 0x0002,
313 RxStatusOK = 0x0001,
314 };
315
316 /* Bits in RxConfig. */
317 enum rx_mode_bits {
318 AcceptErr = 0x20,
319 AcceptRunt = 0x10,
320 AcceptBroadcast = 0x08,
321 AcceptMulticast = 0x04,
322 AcceptMyPhys = 0x02,
323 AcceptAllPhys = 0x01,
324 };
325
326 /* Bits in TxConfig. */
327 enum tx_config_bits {
328 TxIFG1 = (1 << 25), /* Interframe Gap Time */
329 TxIFG0 = (1 << 24), /* Enabling these bits violates IEEE 802.3 */
330 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
331 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
332 TxClearAbt = (1 << 0), /* Clear abort (WO) */
333 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
334
335 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
336 };
337
338 /* Bits in Config1 */
339 enum Config1Bits {
340 Cfg1_PM_Enable = 0x01,
341 Cfg1_VPD_Enable = 0x02,
342 Cfg1_PIO = 0x04,
343 Cfg1_MMIO = 0x08,
344 Cfg1_LWAKE = 0x10,
345 Cfg1_Driver_Load = 0x20,
346 Cfg1_LED0 = 0x40,
347 Cfg1_LED1 = 0x80,
348 };
349
350 enum RxConfigBits {
351 /* Early Rx threshold, none or X/16 */
352 RxCfgEarlyRxNone = 0,
353 RxCfgEarlyRxShift = 24,
354
355 /* rx fifo threshold */
356 RxCfgFIFOShift = 13,
357 RxCfgFIFONone = (7 << RxCfgFIFOShift),
358
359 /* Max DMA burst */
360 RxCfgDMAShift = 8,
361 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
362
363 /* rx ring buffer length */
364 RxCfgRcv8K = 0,
365 RxCfgRcv16K = (1 << 11),
366 RxCfgRcv32K = (1 << 12),
367 RxCfgRcv64K = (1 << 11) | (1 << 12),
368
369 /* Disable packet wrap at end of Rx buffer */
370 RxNoWrap = (1 << 7),
371 };
372
373
374 /* Twister tuning parameters from RealTek.
375 Completely undocumented, but required to tune bad links. */
376 enum CSCRBits {
377 CSCR_LinkOKBit = 0x0400,
378 CSCR_LinkChangeBit = 0x0800,
379 CSCR_LinkStatusBits = 0x0f000,
380 CSCR_LinkDownOffCmd = 0x003c0,
381 CSCR_LinkDownCmd = 0x0f3c0,
382 };
383
384
385 enum Cfg9346Bits {
386 Cfg9346_Lock = 0x00,
387 Cfg9346_Unlock = 0xC0,
388 };
389
390
391 #define PARA78_default 0x78fa8388
392 #define PARA7c_default 0xcb38de43 /* param[0][3] */
393 #define PARA7c_xxx 0xcb38de43
394 static const unsigned long param[4][4] = {
395 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
396 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
397 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
398 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
399 };
400
401 struct ring_info {
402 struct sk_buff *skb;
403 dma_addr_t mapping;
404 };
405
406
407 typedef enum {
408 CH_8139 = 0,
409 CH_8139_K,
410 CH_8139A,
411 CH_8139B,
412 CH_8130,
413 CH_8139C,
414 } chip_t;
415
416
417 /* directly indexed by chip_t, above */
418 const static struct {
419 const char *name;
420 u8 version; /* from RTL8139C docs */
421 u32 RxConfigMask; /* should clear the bits supported by this chip */
422 } rtl_chip_info[] = {
423 { "RTL-8139",
424 0x40,
425 0xf0fe0040, /* XXX copied from RTL8139A, verify */
426 },
427
428 { "RTL-8139 rev K",
429 0x60,
430 0xf0fe0040,
431 },
432
433 { "RTL-8139A",
434 0x70,
435 0xf0fe0040,
436 },
437
438 { "RTL-8139B",
439 0x78,
440 0xf0fc0040
441 },
442
443 { "RTL-8130",
444 0x7C,
445 0xf0fe0040, /* XXX copied from RTL8139A, verify */
446 },
447
448 { "RTL-8139C",
449 0x74,
450 0xf0fc0040, /* XXX copied from RTL8139B, verify */
451 },
452
453 };
454
455
456 struct netdrv_private {
457 board_t board;
458 void *mmio_addr;
459 int drv_flags;
460 struct pci_dev *pci_dev;
461 struct net_device_stats stats;
462 struct timer_list timer; /* Media selection timer. */
463 unsigned char *rx_ring;
464 unsigned int cur_rx; /* Index into the Rx buffer of next Rx pkt. */
465 unsigned int tx_flag;
466 atomic_t cur_tx;
467 atomic_t dirty_tx;
468 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
469 struct ring_info tx_info[NUM_TX_DESC];
470 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
471 unsigned char *tx_bufs; /* Tx bounce buffer region. */
472 dma_addr_t rx_ring_dma;
473 dma_addr_t tx_bufs_dma;
474 char phys[4]; /* MII device addresses. */
475 char twistie, twist_row, twist_col; /* Twister tune state. */
476 unsigned int full_duplex:1; /* Full-duplex operation requested. */
477 unsigned int duplex_lock:1;
478 unsigned int default_port:4; /* Last dev->if_port value. */
479 unsigned int media2:4; /* Secondary monitored media port. */
480 unsigned int medialock:1; /* Don't sense media type. */
481 unsigned int mediasense:1; /* Media sensing in progress. */
482 spinlock_t lock;
483 chip_t chipset;
484 u32 pci_state[16]; /* Data saved during suspend */
485 };
486
487 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
488 MODULE_DESCRIPTION ("Skeleton for a PCI Fast Ethernet driver");
489 MODULE_LICENSE("GPL");
490 MODULE_PARM (multicast_filter_limit, "i");
491 MODULE_PARM (max_interrupt_work, "i");
492 MODULE_PARM (media, "1-" __MODULE_STRING(8) "i");
493 MODULE_PARM_DESC (multicast_filter_limit, "pci-skeleton maximum number of filtered multicast addresses");
494 MODULE_PARM_DESC (max_interrupt_work, "pci-skeleton maximum events handled per interrupt");
495 MODULE_PARM_DESC (media, "pci-skeleton: Bits 0-3: media type, bit 17: full duplex");
496
497 static int read_eeprom (void *ioaddr, int location, int addr_len);
498 static int netdrv_open (struct net_device *dev);
499 static int mdio_read (struct net_device *dev, int phy_id, int location);
500 static void mdio_write (struct net_device *dev, int phy_id, int location,
501 int val);
502 static void netdrv_timer (unsigned long data);
503 static void netdrv_tx_timeout (struct net_device *dev);
504 static void netdrv_init_ring (struct net_device *dev);
505 static int netdrv_start_xmit (struct sk_buff *skb,
506 struct net_device *dev);
507 static irqreturn_t netdrv_interrupt (int irq, void *dev_instance,
508 struct pt_regs *regs);
509 static int netdrv_close (struct net_device *dev);
510 static int netdrv_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
511 static struct net_device_stats *netdrv_get_stats (struct net_device *dev);
512 static void netdrv_set_rx_mode (struct net_device *dev);
513 static void netdrv_hw_start (struct net_device *dev);
514
515
516 #ifdef USE_IO_OPS
517
518 #define NETDRV_R8(reg) inb (((unsigned long)ioaddr) + (reg))
519 #define NETDRV_R16(reg) inw (((unsigned long)ioaddr) + (reg))
520 #define NETDRV_R32(reg) ((unsigned long) inl (((unsigned long)ioaddr) + (reg)))
521 #define NETDRV_W8(reg, val8) outb ((val8), ((unsigned long)ioaddr) + (reg))
522 #define NETDRV_W16(reg, val16) outw ((val16), ((unsigned long)ioaddr) + (reg))
523 #define NETDRV_W32(reg, val32) outl ((val32), ((unsigned long)ioaddr) + (reg))
524 #define NETDRV_W8_F NETDRV_W8
525 #define NETDRV_W16_F NETDRV_W16
526 #define NETDRV_W32_F NETDRV_W32
527 #undef readb
528 #undef readw
529 #undef readl
530 #undef writeb
531 #undef writew
532 #undef writel
533 #define readb(addr) inb((unsigned long)(addr))
534 #define readw(addr) inw((unsigned long)(addr))
535 #define readl(addr) inl((unsigned long)(addr))
536 #define writeb(val,addr) outb((val),(unsigned long)(addr))
537 #define writew(val,addr) outw((val),(unsigned long)(addr))
538 #define writel(val,addr) outl((val),(unsigned long)(addr))
539
540 #else
541
542 /* write MMIO register, with flush */
543 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
544 #define NETDRV_W8_F(reg, val8) do { writeb ((val8), ioaddr + (reg)); readb (ioaddr + (reg)); } while (0)
545 #define NETDRV_W16_F(reg, val16) do { writew ((val16), ioaddr + (reg)); readw (ioaddr + (reg)); } while (0)
546 #define NETDRV_W32_F(reg, val32) do { writel ((val32), ioaddr + (reg)); readl (ioaddr + (reg)); } while (0)
547
548
549 #if MMIO_FLUSH_AUDIT_COMPLETE
550
551 /* write MMIO register */
552 #define NETDRV_W8(reg, val8) writeb ((val8), ioaddr + (reg))
553 #define NETDRV_W16(reg, val16) writew ((val16), ioaddr + (reg))
554 #define NETDRV_W32(reg, val32) writel ((val32), ioaddr + (reg))
555
556 #else
557
558 /* write MMIO register, then flush */
559 #define NETDRV_W8 NETDRV_W8_F
560 #define NETDRV_W16 NETDRV_W16_F
561 #define NETDRV_W32 NETDRV_W32_F
562
563 #endif /* MMIO_FLUSH_AUDIT_COMPLETE */
564
565 /* read MMIO register */
566 #define NETDRV_R8(reg) readb (ioaddr + (reg))
567 #define NETDRV_R16(reg) readw (ioaddr + (reg))
568 #define NETDRV_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
569
570 #endif /* USE_IO_OPS */
571
572
573 static const u16 netdrv_intr_mask =
574 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
575 TxErr | TxOK | RxErr | RxOK;
576
577 static const unsigned int netdrv_rx_config =
578 RxCfgEarlyRxNone | RxCfgRcv32K | RxNoWrap |
579 (RX_FIFO_THRESH << RxCfgFIFOShift) |
580 (RX_DMA_BURST << RxCfgDMAShift);
581
582
583 static int __devinit netdrv_init_board (struct pci_dev *pdev,
584 struct net_device **dev_out,
585 void **ioaddr_out)
586 {
587 void *ioaddr = NULL;
588 struct net_device *dev;
589 struct netdrv_private *tp;
590 int rc, i;
591 u32 pio_start, pio_end, pio_flags, pio_len;
592 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
593 u32 tmp;
594
595 DPRINTK ("ENTER\n");
596
597 assert (pdev != NULL);
598 assert (ioaddr_out != NULL);
599
600 *ioaddr_out = NULL;
601 *dev_out = NULL;
602
603 /* dev zeroed in alloc_etherdev */
604 dev = alloc_etherdev (sizeof (*tp));
605 if (dev == NULL) {
606 printk (KERN_ERR PFX "unable to alloc new ethernet\n");
607 DPRINTK ("EXIT, returning -ENOMEM\n");
608 return -ENOMEM;
609 }
610 SET_MODULE_OWNER(dev);
611 SET_NETDEV_DEV(dev, &pdev->dev);
612 tp = dev->priv;
613
614 /* enable device (incl. PCI PM wakeup), and bus-mastering */
615 rc = pci_enable_device (pdev);
616 if (rc)
617 goto err_out;
618
619 pio_start = pci_resource_start (pdev, 0);
620 pio_end = pci_resource_end (pdev, 0);
621 pio_flags = pci_resource_flags (pdev, 0);
622 pio_len = pci_resource_len (pdev, 0);
623
624 mmio_start = pci_resource_start (pdev, 1);
625 mmio_end = pci_resource_end (pdev, 1);
626 mmio_flags = pci_resource_flags (pdev, 1);
627 mmio_len = pci_resource_len (pdev, 1);
628
629 /* set this immediately, we need to know before
630 * we talk to the chip directly */
631 DPRINTK("PIO region size == 0x%02X\n", pio_len);
632 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
633
634 /* make sure PCI base addr 0 is PIO */
635 if (!(pio_flags & IORESOURCE_IO)) {
636 printk (KERN_ERR PFX "region #0 not a PIO resource, aborting\n");
637 rc = -ENODEV;
638 goto err_out;
639 }
640
641 /* make sure PCI base addr 1 is MMIO */
642 if (!(mmio_flags & IORESOURCE_MEM)) {
643 printk (KERN_ERR PFX "region #1 not an MMIO resource, aborting\n");
644 rc = -ENODEV;
645 goto err_out;
646 }
647
648 /* check for weird/broken PCI region reporting */
649 if ((pio_len < NETDRV_MIN_IO_SIZE) ||
650 (mmio_len < NETDRV_MIN_IO_SIZE)) {
651 printk (KERN_ERR PFX "Invalid PCI region size(s), aborting\n");
652 rc = -ENODEV;
653 goto err_out;
654 }
655
656 rc = pci_request_regions (pdev, "pci-skeleton");
657 if (rc)
658 goto err_out;
659
660 pci_set_master (pdev);
661
662 #ifdef USE_IO_OPS
663 ioaddr = (void *) pio_start;
664 #else
665 /* ioremap MMIO region */
666 ioaddr = ioremap (mmio_start, mmio_len);
667 if (ioaddr == NULL) {
668 printk (KERN_ERR PFX "cannot remap MMIO, aborting\n");
669 rc = -EIO;
670 goto err_out_free_res;
671 }
672 #endif /* USE_IO_OPS */
673
674 /* Soft reset the chip. */
675 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) | CmdReset);
676
677 /* Check that the chip has finished the reset. */
678 for (i = 1000; i > 0; i--)
679 if ((NETDRV_R8 (ChipCmd) & CmdReset) == 0)
680 break;
681 else
682 udelay (10);
683
684 /* Bring the chip out of low-power mode. */
685 /* <insert device-specific code here> */
686
687 #ifndef USE_IO_OPS
688 /* sanity checks -- ensure PIO and MMIO registers agree */
689 assert (inb (pio_start+Config0) == readb (ioaddr+Config0));
690 assert (inb (pio_start+Config1) == readb (ioaddr+Config1));
691 assert (inb (pio_start+TxConfig) == readb (ioaddr+TxConfig));
692 assert (inb (pio_start+RxConfig) == readb (ioaddr+RxConfig));
693 #endif /* !USE_IO_OPS */
694
695 /* identify chip attached to board */
696 tmp = NETDRV_R8 (ChipVersion);
697 for (i = ARRAY_SIZE (rtl_chip_info) - 1; i >= 0; i--)
698 if (tmp == rtl_chip_info[i].version) {
699 tp->chipset = i;
700 goto match;
701 }
702
703 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
704 printk (KERN_DEBUG PFX "PCI device %s: unknown chip version, assuming RTL-8139\n",
705 pci_name(pdev));
706 printk (KERN_DEBUG PFX "PCI device %s: TxConfig = 0x%lx\n", pci_name(pdev), NETDRV_R32 (TxConfig));
707 tp->chipset = 0;
708
709 match:
710 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
711 tmp,
712 tp->chipset,
713 rtl_chip_info[tp->chipset].name);
714
715 i = register_netdev (dev);
716 if (i)
717 goto err_out_unmap;
718
719 DPRINTK ("EXIT, returning 0\n");
720 *ioaddr_out = ioaddr;
721 *dev_out = dev;
722 return 0;
723
724 err_out_unmap:
725 #ifndef USE_IO_OPS
726 iounmap(ioaddr);
727 err_out_free_res:
728 #endif
729 pci_release_regions (pdev);
730 err_out:
731 free_netdev (dev);
732 DPRINTK ("EXIT, returning %d\n", rc);
733 return rc;
734 }
735
736
737 static int __devinit netdrv_init_one (struct pci_dev *pdev,
738 const struct pci_device_id *ent)
739 {
740 struct net_device *dev = NULL;
741 struct netdrv_private *tp;
742 int i, addr_len, option;
743 void *ioaddr = NULL;
744 static int board_idx = -1;
745
746 /* when built into the kernel, we only print version if device is found */
747 #ifndef MODULE
748 static int printed_version;
749 if (!printed_version++)
750 printk(version);
751 #endif
752
753 DPRINTK ("ENTER\n");
754
755 assert (pdev != NULL);
756 assert (ent != NULL);
757
758 board_idx++;
759
760 i = netdrv_init_board (pdev, &dev, &ioaddr);
761 if (i < 0) {
762 DPRINTK ("EXIT, returning %d\n", i);
763 return i;
764 }
765
766 tp = dev->priv;
767
768 assert (ioaddr != NULL);
769 assert (dev != NULL);
770 assert (tp != NULL);
771
772 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
773 for (i = 0; i < 3; i++)
774 ((u16 *) (dev->dev_addr))[i] =
775 le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
776
777 /* The Rtl8139-specific entries in the device structure. */
778 dev->open = netdrv_open;
779 dev->hard_start_xmit = netdrv_start_xmit;
780 dev->stop = netdrv_close;
781 dev->get_stats = netdrv_get_stats;
782 dev->set_multicast_list = netdrv_set_rx_mode;
783 dev->do_ioctl = netdrv_ioctl;
784 dev->tx_timeout = netdrv_tx_timeout;
785 dev->watchdog_timeo = TX_TIMEOUT;
786
787 dev->irq = pdev->irq;
788 dev->base_addr = (unsigned long) ioaddr;
789
790 /* dev->priv/tp zeroed and aligned in alloc_etherdev */
791 tp = dev->priv;
792
793 /* note: tp->chipset set in netdrv_init_board */
794 tp->drv_flags = PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
795 PCI_COMMAND_MASTER | NETDRV_CAPS;
796 tp->pci_dev = pdev;
797 tp->board = ent->driver_data;
798 tp->mmio_addr = ioaddr;
799 tp->lock = SPIN_LOCK_UNLOCKED;
800
801 pci_set_drvdata(pdev, dev);
802
803 tp->phys[0] = 32;
804
805 printk (KERN_INFO "%s: %s at 0x%lx, "
806 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
807 "IRQ %d\n",
808 dev->name,
809 board_info[ent->driver_data].name,
810 dev->base_addr,
811 dev->dev_addr[0], dev->dev_addr[1],
812 dev->dev_addr[2], dev->dev_addr[3],
813 dev->dev_addr[4], dev->dev_addr[5],
814 dev->irq);
815
816 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
817 dev->name, rtl_chip_info[tp->chipset].name);
818
819 /* Put the chip into low-power mode. */
820 NETDRV_W8_F (Cfg9346, Cfg9346_Unlock);
821
822 /* The lower four bits are the media type. */
823 option = (board_idx > 7) ? 0 : media[board_idx];
824 if (option > 0) {
825 tp->full_duplex = (option & 0x200) ? 1 : 0;
826 tp->default_port = option & 15;
827 if (tp->default_port)
828 tp->medialock = 1;
829 }
830
831 if (tp->full_duplex) {
832 printk (KERN_INFO
833 "%s: Media type forced to Full Duplex.\n",
834 dev->name);
835 mdio_write (dev, tp->phys[0], MII_ADVERTISE, ADVERTISE_FULL);
836 tp->duplex_lock = 1;
837 }
838
839 DPRINTK ("EXIT - returning 0\n");
840 return 0;
841 }
842
843
844 static void __devexit netdrv_remove_one (struct pci_dev *pdev)
845 {
846 struct net_device *dev = pci_get_drvdata (pdev);
847 struct netdrv_private *np;
848
849 DPRINTK ("ENTER\n");
850
851 assert (dev != NULL);
852
853 np = dev->priv;
854 assert (np != NULL);
855
856 unregister_netdev (dev);
857
858 #ifndef USE_IO_OPS
859 iounmap (np->mmio_addr);
860 #endif /* !USE_IO_OPS */
861
862 pci_release_regions (pdev);
863
864 free_netdev (dev);
865
866 pci_set_drvdata (pdev, NULL);
867
868 pci_disable_device (pdev);
869
870 DPRINTK ("EXIT\n");
871 }
872
873
874 /* Serial EEPROM section. */
875
876 /* EEPROM_Ctrl bits. */
877 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
878 #define EE_CS 0x08 /* EEPROM chip select. */
879 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
880 #define EE_WRITE_0 0x00
881 #define EE_WRITE_1 0x02
882 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
883 #define EE_ENB (0x80 | EE_CS)
884
885 /* Delay between EEPROM clock transitions.
886 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
887 */
888
889 #define eeprom_delay() readl(ee_addr)
890
891 /* The EEPROM commands include the alway-set leading bit. */
892 #define EE_WRITE_CMD (5)
893 #define EE_READ_CMD (6)
894 #define EE_ERASE_CMD (7)
895
896 static int __devinit read_eeprom (void *ioaddr, int location, int addr_len)
897 {
898 int i;
899 unsigned retval = 0;
900 void *ee_addr = ioaddr + Cfg9346;
901 int read_cmd = location | (EE_READ_CMD << addr_len);
902
903 DPRINTK ("ENTER\n");
904
905 writeb (EE_ENB & ~EE_CS, ee_addr);
906 writeb (EE_ENB, ee_addr);
907 eeprom_delay ();
908
909 /* Shift the read command bits out. */
910 for (i = 4 + addr_len; i >= 0; i--) {
911 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
912 writeb (EE_ENB | dataval, ee_addr);
913 eeprom_delay ();
914 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
915 eeprom_delay ();
916 }
917 writeb (EE_ENB, ee_addr);
918 eeprom_delay ();
919
920 for (i = 16; i > 0; i--) {
921 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
922 eeprom_delay ();
923 retval =
924 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
925 0);
926 writeb (EE_ENB, ee_addr);
927 eeprom_delay ();
928 }
929
930 /* Terminate the EEPROM access. */
931 writeb (~EE_CS, ee_addr);
932 eeprom_delay ();
933
934 DPRINTK ("EXIT - returning %d\n", retval);
935 return retval;
936 }
937
938 /* MII serial management: mostly bogus for now. */
939 /* Read and write the MII management registers using software-generated
940 serial MDIO protocol.
941 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
942 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
943 "overclocking" issues. */
944 #define MDIO_DIR 0x80
945 #define MDIO_DATA_OUT 0x04
946 #define MDIO_DATA_IN 0x02
947 #define MDIO_CLK 0x01
948 #define MDIO_WRITE0 (MDIO_DIR)
949 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
950
951 #define mdio_delay() readb(mdio_addr)
952
953
954 static char mii_2_8139_map[8] = {
955 BasicModeCtrl,
956 BasicModeStatus,
957 0,
958 0,
959 NWayAdvert,
960 NWayLPAR,
961 NWayExpansion,
962 0
963 };
964
965
966 /* Syncronize the MII management interface by shifting 32 one bits out. */
967 static void mdio_sync (void *mdio_addr)
968 {
969 int i;
970
971 DPRINTK ("ENTER\n");
972
973 for (i = 32; i >= 0; i--) {
974 writeb (MDIO_WRITE1, mdio_addr);
975 mdio_delay ();
976 writeb (MDIO_WRITE1 | MDIO_CLK, mdio_addr);
977 mdio_delay ();
978 }
979
980 DPRINTK ("EXIT\n");
981 }
982
983
984 static int mdio_read (struct net_device *dev, int phy_id, int location)
985 {
986 struct netdrv_private *tp = dev->priv;
987 void *mdio_addr = tp->mmio_addr + Config4;
988 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
989 int retval = 0;
990 int i;
991
992 DPRINTK ("ENTER\n");
993
994 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
995 DPRINTK ("EXIT after directly using 8139 internal regs\n");
996 return location < 8 && mii_2_8139_map[location] ?
997 readw (tp->mmio_addr + mii_2_8139_map[location]) : 0;
998 }
999 mdio_sync (mdio_addr);
1000 /* Shift the read command bits out. */
1001 for (i = 15; i >= 0; i--) {
1002 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1003
1004 writeb (MDIO_DIR | dataval, mdio_addr);
1005 mdio_delay ();
1006 writeb (MDIO_DIR | dataval | MDIO_CLK, mdio_addr);
1007 mdio_delay ();
1008 }
1009
1010 /* Read the two transition, 16 data, and wire-idle bits. */
1011 for (i = 19; i > 0; i--) {
1012 writeb (0, mdio_addr);
1013 mdio_delay ();
1014 retval =
1015 (retval << 1) | ((readb (mdio_addr) & MDIO_DATA_IN) ? 1
1016 : 0);
1017 writeb (MDIO_CLK, mdio_addr);
1018 mdio_delay ();
1019 }
1020
1021 DPRINTK ("EXIT, returning %d\n", (retval >> 1) & 0xffff);
1022 return (retval >> 1) & 0xffff;
1023 }
1024
1025
1026 static void mdio_write (struct net_device *dev, int phy_id, int location,
1027 int value)
1028 {
1029 struct netdrv_private *tp = dev->priv;
1030 void *mdio_addr = tp->mmio_addr + Config4;
1031 int mii_cmd =
1032 (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1033 int i;
1034
1035 DPRINTK ("ENTER\n");
1036
1037 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1038 if (location < 8 && mii_2_8139_map[location]) {
1039 writew (value,
1040 tp->mmio_addr + mii_2_8139_map[location]);
1041 readw (tp->mmio_addr + mii_2_8139_map[location]);
1042 }
1043 DPRINTK ("EXIT after directly using 8139 internal regs\n");
1044 return;
1045 }
1046 mdio_sync (mdio_addr);
1047
1048 /* Shift the command bits out. */
1049 for (i = 31; i >= 0; i--) {
1050 int dataval =
1051 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1052 writeb (dataval, mdio_addr);
1053 mdio_delay ();
1054 writeb (dataval | MDIO_CLK, mdio_addr);
1055 mdio_delay ();
1056 }
1057
1058 /* Clear out extra bits. */
1059 for (i = 2; i > 0; i--) {
1060 writeb (0, mdio_addr);
1061 mdio_delay ();
1062 writeb (MDIO_CLK, mdio_addr);
1063 mdio_delay ();
1064 }
1065
1066 DPRINTK ("EXIT\n");
1067 }
1068
1069
1070 static int netdrv_open (struct net_device *dev)
1071 {
1072 struct netdrv_private *tp = dev->priv;
1073 int retval;
1074 #ifdef NETDRV_DEBUG
1075 void *ioaddr = tp->mmio_addr;
1076 #endif
1077
1078 DPRINTK ("ENTER\n");
1079
1080 retval = request_irq (dev->irq, netdrv_interrupt, SA_SHIRQ, dev->name, dev);
1081 if (retval) {
1082 DPRINTK ("EXIT, returning %d\n", retval);
1083 return retval;
1084 }
1085
1086 tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1087 &tp->tx_bufs_dma);
1088 tp->rx_ring = pci_alloc_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1089 &tp->rx_ring_dma);
1090 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1091 free_irq(dev->irq, dev);
1092
1093 if (tp->tx_bufs)
1094 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1095 tp->tx_bufs, tp->tx_bufs_dma);
1096 if (tp->rx_ring)
1097 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1098 tp->rx_ring, tp->rx_ring_dma);
1099
1100 DPRINTK ("EXIT, returning -ENOMEM\n");
1101 return -ENOMEM;
1102
1103 }
1104
1105 tp->full_duplex = tp->duplex_lock;
1106 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1107
1108 netdrv_init_ring (dev);
1109 netdrv_hw_start (dev);
1110
1111 DPRINTK ("%s: netdrv_open() ioaddr %#lx IRQ %d"
1112 " GP Pins %2.2x %s-duplex.\n",
1113 dev->name, pci_resource_start (tp->pci_dev, 1),
1114 dev->irq, NETDRV_R8 (MediaStatus),
1115 tp->full_duplex ? "full" : "half");
1116
1117 /* Set the timer to switch to check for link beat and perhaps switch
1118 to an alternate media type. */
1119 init_timer (&tp->timer);
1120 tp->timer.expires = jiffies + 3 * HZ;
1121 tp->timer.data = (unsigned long) dev;
1122 tp->timer.function = &netdrv_timer;
1123 add_timer (&tp->timer);
1124
1125 DPRINTK ("EXIT, returning 0\n");
1126 return 0;
1127 }
1128
1129
1130 /* Start the hardware at open or resume. */
1131 static void netdrv_hw_start (struct net_device *dev)
1132 {
1133 struct netdrv_private *tp = dev->priv;
1134 void *ioaddr = tp->mmio_addr;
1135 u32 i;
1136
1137 DPRINTK ("ENTER\n");
1138
1139 /* Soft reset the chip. */
1140 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) | CmdReset);
1141 udelay (100);
1142
1143 /* Check that the chip has finished the reset. */
1144 for (i = 1000; i > 0; i--)
1145 if ((NETDRV_R8 (ChipCmd) & CmdReset) == 0)
1146 break;
1147
1148 /* Restore our idea of the MAC address. */
1149 NETDRV_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1150 NETDRV_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1151
1152 /* Must enable Tx/Rx before setting transfer thresholds! */
1153 NETDRV_W8_F (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) |
1154 CmdRxEnb | CmdTxEnb);
1155
1156 i = netdrv_rx_config |
1157 (NETDRV_R32 (RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1158 NETDRV_W32_F (RxConfig, i);
1159
1160 /* Check this value: the documentation for IFG contradicts ifself. */
1161 NETDRV_W32 (TxConfig, (TX_DMA_BURST << TxDMAShift));
1162
1163 /* unlock Config[01234] and BMCR register writes */
1164 NETDRV_W8_F (Cfg9346, Cfg9346_Unlock);
1165 udelay (10);
1166
1167 tp->cur_rx = 0;
1168
1169 /* Lock Config[01234] and BMCR register writes */
1170 NETDRV_W8_F (Cfg9346, Cfg9346_Lock);
1171 udelay (10);
1172
1173 /* init Rx ring buffer DMA address */
1174 NETDRV_W32_F (RxBuf, tp->rx_ring_dma);
1175
1176 /* init Tx buffer DMA addresses */
1177 for (i = 0; i < NUM_TX_DESC; i++)
1178 NETDRV_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1179
1180 NETDRV_W32_F (RxMissed, 0);
1181
1182 netdrv_set_rx_mode (dev);
1183
1184 /* no early-rx interrupts */
1185 NETDRV_W16 (MultiIntr, NETDRV_R16 (MultiIntr) & MultiIntrClear);
1186
1187 /* make sure RxTx has started */
1188 NETDRV_W8_F (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) |
1189 CmdRxEnb | CmdTxEnb);
1190
1191 /* Enable all known interrupts by setting the interrupt mask. */
1192 NETDRV_W16_F (IntrMask, netdrv_intr_mask);
1193
1194 netif_start_queue (dev);
1195
1196 DPRINTK ("EXIT\n");
1197 }
1198
1199
1200 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1201 static void netdrv_init_ring (struct net_device *dev)
1202 {
1203 struct netdrv_private *tp = dev->priv;
1204 int i;
1205
1206 DPRINTK ("ENTER\n");
1207
1208 tp->cur_rx = 0;
1209 atomic_set (&tp->cur_tx, 0);
1210 atomic_set (&tp->dirty_tx, 0);
1211
1212 for (i = 0; i < NUM_TX_DESC; i++) {
1213 tp->tx_info[i].skb = NULL;
1214 tp->tx_info[i].mapping = 0;
1215 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1216 }
1217
1218 DPRINTK ("EXIT\n");
1219 }
1220
1221
1222 static void netdrv_timer (unsigned long data)
1223 {
1224 struct net_device *dev = (struct net_device *) data;
1225 struct netdrv_private *tp = dev->priv;
1226 void *ioaddr = tp->mmio_addr;
1227 int next_tick = 60 * HZ;
1228 int mii_lpa;
1229
1230 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1231
1232 if (!tp->duplex_lock && mii_lpa != 0xffff) {
1233 int duplex = (mii_lpa & LPA_100FULL)
1234 || (mii_lpa & 0x01C0) == 0x0040;
1235 if (tp->full_duplex != duplex) {
1236 tp->full_duplex = duplex;
1237 printk (KERN_INFO
1238 "%s: Setting %s-duplex based on MII #%d link"
1239 " partner ability of %4.4x.\n", dev->name,
1240 tp->full_duplex ? "full" : "half",
1241 tp->phys[0], mii_lpa);
1242 NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1243 NETDRV_W8 (Config1, tp->full_duplex ? 0x60 : 0x20);
1244 NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1245 }
1246 }
1247
1248 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1249 dev->name, NETDRV_R16 (NWayLPAR));
1250 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x"
1251 " RxStatus %4.4x.\n", dev->name,
1252 NETDRV_R16 (IntrMask),
1253 NETDRV_R16 (IntrStatus),
1254 NETDRV_R32 (RxEarlyStatus));
1255 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1256 dev->name, NETDRV_R8 (Config0),
1257 NETDRV_R8 (Config1));
1258
1259 tp->timer.expires = jiffies + next_tick;
1260 add_timer (&tp->timer);
1261 }
1262
1263
1264 static void netdrv_tx_clear (struct netdrv_private *tp)
1265 {
1266 int i;
1267
1268 atomic_set (&tp->cur_tx, 0);
1269 atomic_set (&tp->dirty_tx, 0);
1270
1271 /* Dump the unsent Tx packets. */
1272 for (i = 0; i < NUM_TX_DESC; i++) {
1273 struct ring_info *rp = &tp->tx_info[i];
1274 if (rp->mapping != 0) {
1275 pci_unmap_single (tp->pci_dev, rp->mapping,
1276 rp->skb->len, PCI_DMA_TODEVICE);
1277 rp->mapping = 0;
1278 }
1279 if (rp->skb) {
1280 dev_kfree_skb (rp->skb);
1281 rp->skb = NULL;
1282 tp->stats.tx_dropped++;
1283 }
1284 }
1285 }
1286
1287
1288 static void netdrv_tx_timeout (struct net_device *dev)
1289 {
1290 struct netdrv_private *tp = dev->priv;
1291 void *ioaddr = tp->mmio_addr;
1292 int i;
1293 u8 tmp8;
1294 unsigned long flags;
1295
1296 DPRINTK ("%s: Transmit timeout, status %2.2x %4.4x "
1297 "media %2.2x.\n", dev->name,
1298 NETDRV_R8 (ChipCmd),
1299 NETDRV_R16 (IntrStatus),
1300 NETDRV_R8 (MediaStatus));
1301
1302 /* disable Tx ASAP, if not already */
1303 tmp8 = NETDRV_R8 (ChipCmd);
1304 if (tmp8 & CmdTxEnb)
1305 NETDRV_W8 (ChipCmd, tmp8 & ~CmdTxEnb);
1306
1307 /* Disable interrupts by clearing the interrupt mask. */
1308 NETDRV_W16 (IntrMask, 0x0000);
1309
1310 /* Emit info to figure out what went wrong. */
1311 printk (KERN_DEBUG "%s: Tx queue start entry %d dirty entry %d.\n",
1312 dev->name, atomic_read (&tp->cur_tx),
1313 atomic_read (&tp->dirty_tx));
1314 for (i = 0; i < NUM_TX_DESC; i++)
1315 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1316 dev->name, i, NETDRV_R32 (TxStatus0 + (i * 4)),
1317 i == atomic_read (&tp->dirty_tx) % NUM_TX_DESC ?
1318 " (queue head)" : "");
1319
1320 /* Stop a shared interrupt from scavenging while we are. */
1321 spin_lock_irqsave (&tp->lock, flags);
1322
1323 netdrv_tx_clear (tp);
1324
1325 spin_unlock_irqrestore (&tp->lock, flags);
1326
1327 /* ...and finally, reset everything */
1328 netdrv_hw_start (dev);
1329
1330 netif_wake_queue (dev);
1331 }
1332
1333
1334
1335 static int netdrv_start_xmit (struct sk_buff *skb, struct net_device *dev)
1336 {
1337 struct netdrv_private *tp = dev->priv;
1338 void *ioaddr = tp->mmio_addr;
1339 int entry;
1340
1341 /* Calculate the next Tx descriptor entry. */
1342 entry = atomic_read (&tp->cur_tx) % NUM_TX_DESC;
1343
1344 assert (tp->tx_info[entry].skb == NULL);
1345 assert (tp->tx_info[entry].mapping == 0);
1346
1347 tp->tx_info[entry].skb = skb;
1348 /* tp->tx_info[entry].mapping = 0; */
1349 memcpy (tp->tx_buf[entry], skb->data, skb->len);
1350
1351 /* Note: the chip doesn't have auto-pad! */
1352 NETDRV_W32 (TxStatus0 + (entry * sizeof(u32)),
1353 tp->tx_flag | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
1354
1355 dev->trans_start = jiffies;
1356 atomic_inc (&tp->cur_tx);
1357 if ((atomic_read (&tp->cur_tx) - atomic_read (&tp->dirty_tx)) >= NUM_TX_DESC)
1358 netif_stop_queue (dev);
1359
1360 DPRINTK ("%s: Queued Tx packet at %p size %u to slot %d.\n",
1361 dev->name, skb->data, skb->len, entry);
1362
1363 return 0;
1364 }
1365
1366
1367 static void netdrv_tx_interrupt (struct net_device *dev,
1368 struct netdrv_private *tp,
1369 void *ioaddr)
1370 {
1371 int cur_tx, dirty_tx, tx_left;
1372
1373 assert (dev != NULL);
1374 assert (tp != NULL);
1375 assert (ioaddr != NULL);
1376
1377 dirty_tx = atomic_read (&tp->dirty_tx);
1378
1379 cur_tx = atomic_read (&tp->cur_tx);
1380 tx_left = cur_tx - dirty_tx;
1381 while (tx_left > 0) {
1382 int entry = dirty_tx % NUM_TX_DESC;
1383 int txstatus;
1384
1385 txstatus = NETDRV_R32 (TxStatus0 + (entry * sizeof (u32)));
1386
1387 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1388 break; /* It still hasn't been Txed */
1389
1390 /* Note: TxCarrierLost is always asserted at 100mbps. */
1391 if (txstatus & (TxOutOfWindow | TxAborted)) {
1392 /* There was an major error, log it. */
1393 DPRINTK ("%s: Transmit error, Tx status %8.8x.\n",
1394 dev->name, txstatus);
1395 tp->stats.tx_errors++;
1396 if (txstatus & TxAborted) {
1397 tp->stats.tx_aborted_errors++;
1398 NETDRV_W32 (TxConfig, TxClearAbt | (TX_DMA_BURST << TxDMAShift));
1399 }
1400 if (txstatus & TxCarrierLost)
1401 tp->stats.tx_carrier_errors++;
1402 if (txstatus & TxOutOfWindow)
1403 tp->stats.tx_window_errors++;
1404 } else {
1405 if (txstatus & TxUnderrun) {
1406 /* Add 64 to the Tx FIFO threshold. */
1407 if (tp->tx_flag < 0x00300000)
1408 tp->tx_flag += 0x00020000;
1409 tp->stats.tx_fifo_errors++;
1410 }
1411 tp->stats.collisions += (txstatus >> 24) & 15;
1412 tp->stats.tx_bytes += txstatus & 0x7ff;
1413 tp->stats.tx_packets++;
1414 }
1415
1416 /* Free the original skb. */
1417 if (tp->tx_info[entry].mapping != 0) {
1418 pci_unmap_single(tp->pci_dev,
1419 tp->tx_info[entry].mapping,
1420 tp->tx_info[entry].skb->len,
1421 PCI_DMA_TODEVICE);
1422 tp->tx_info[entry].mapping = 0;
1423 }
1424 dev_kfree_skb_irq (tp->tx_info[entry].skb);
1425 tp->tx_info[entry].skb = NULL;
1426 dirty_tx++;
1427 if (dirty_tx < 0) { /* handle signed int overflow */
1428 atomic_sub (cur_tx, &tp->cur_tx); /* XXX racy? */
1429 dirty_tx = cur_tx - tx_left + 1;
1430 }
1431 if (netif_queue_stopped (dev))
1432 netif_wake_queue (dev);
1433
1434 cur_tx = atomic_read (&tp->cur_tx);
1435 tx_left = cur_tx - dirty_tx;
1436
1437 }
1438
1439 #ifndef NETDRV_NDEBUG
1440 if (atomic_read (&tp->cur_tx) - dirty_tx > NUM_TX_DESC) {
1441 printk (KERN_ERR
1442 "%s: Out-of-sync dirty pointer, %d vs. %d.\n",
1443 dev->name, dirty_tx, atomic_read (&tp->cur_tx));
1444 dirty_tx += NUM_TX_DESC;
1445 }
1446 #endif /* NETDRV_NDEBUG */
1447
1448 atomic_set (&tp->dirty_tx, dirty_tx);
1449 }
1450
1451
1452 /* TODO: clean this up! Rx reset need not be this intensive */
1453 static void netdrv_rx_err (u32 rx_status, struct net_device *dev,
1454 struct netdrv_private *tp, void *ioaddr)
1455 {
1456 u8 tmp8;
1457 int tmp_work = 1000;
1458
1459 DPRINTK ("%s: Ethernet frame had errors, status %8.8x.\n",
1460 dev->name, rx_status);
1461 if (rx_status & RxTooLong) {
1462 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1463 dev->name, rx_status);
1464 /* A.C.: The chip hangs here. */
1465 }
1466 tp->stats.rx_errors++;
1467 if (rx_status & (RxBadSymbol | RxBadAlign))
1468 tp->stats.rx_frame_errors++;
1469 if (rx_status & (RxRunt | RxTooLong))
1470 tp->stats.rx_length_errors++;
1471 if (rx_status & RxCRCErr)
1472 tp->stats.rx_crc_errors++;
1473 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1474 tp->cur_rx = 0;
1475
1476 /* disable receive */
1477 tmp8 = NETDRV_R8 (ChipCmd) & ChipCmdClear;
1478 NETDRV_W8_F (ChipCmd, tmp8 | CmdTxEnb);
1479
1480 /* A.C.: Reset the multicast list. */
1481 netdrv_set_rx_mode (dev);
1482
1483 /* XXX potentially temporary hack to
1484 * restart hung receiver */
1485 while (--tmp_work > 0) {
1486 tmp8 = NETDRV_R8 (ChipCmd);
1487 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1488 break;
1489 NETDRV_W8_F (ChipCmd,
1490 (tmp8 & ChipCmdClear) | CmdRxEnb | CmdTxEnb);
1491 }
1492
1493 /* G.S.: Re-enable receiver */
1494 /* XXX temporary hack to work around receiver hang */
1495 netdrv_set_rx_mode (dev);
1496
1497 if (tmp_work <= 0)
1498 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1499 }
1500
1501
1502 /* The data sheet doesn't describe the Rx ring at all, so I'm guessing at the
1503 field alignments and semantics. */
1504 static void netdrv_rx_interrupt (struct net_device *dev,
1505 struct netdrv_private *tp, void *ioaddr)
1506 {
1507 unsigned char *rx_ring;
1508 u16 cur_rx;
1509
1510 assert (dev != NULL);
1511 assert (tp != NULL);
1512 assert (ioaddr != NULL);
1513
1514 rx_ring = tp->rx_ring;
1515 cur_rx = tp->cur_rx;
1516
1517 DPRINTK ("%s: In netdrv_rx(), current %4.4x BufAddr %4.4x,"
1518 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
1519 NETDRV_R16 (RxBufAddr),
1520 NETDRV_R16 (RxBufPtr), NETDRV_R8 (ChipCmd));
1521
1522 while ((NETDRV_R8 (ChipCmd) & RxBufEmpty) == 0) {
1523 int ring_offset = cur_rx % RX_BUF_LEN;
1524 u32 rx_status;
1525 unsigned int rx_size;
1526 unsigned int pkt_size;
1527 struct sk_buff *skb;
1528
1529 /* read size+status of next frame from DMA ring buffer */
1530 rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
1531 rx_size = rx_status >> 16;
1532 pkt_size = rx_size - 4;
1533
1534 DPRINTK ("%s: netdrv_rx() status %4.4x, size %4.4x,"
1535 " cur %4.4x.\n", dev->name, rx_status,
1536 rx_size, cur_rx);
1537 #if NETDRV_DEBUG > 2
1538 {
1539 int i;
1540 DPRINTK ("%s: Frame contents ", dev->name);
1541 for (i = 0; i < 70; i++)
1542 printk (" %2.2x",
1543 rx_ring[ring_offset + i]);
1544 printk (".\n");
1545 }
1546 #endif
1547
1548 /* If Rx err or invalid rx_size/rx_status received
1549 * (which happens if we get lost in the ring),
1550 * Rx process gets reset, so we abort any further
1551 * Rx processing.
1552 */
1553 if ((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
1554 (!(rx_status & RxStatusOK))) {
1555 netdrv_rx_err (rx_status, dev, tp, ioaddr);
1556 return;
1557 }
1558
1559 /* Malloc up new buffer, compatible with net-2e. */
1560 /* Omit the four octet CRC from the length. */
1561
1562 /* TODO: consider allocating skb's outside of
1563 * interrupt context, both to speed interrupt processing,
1564 * and also to reduce the chances of having to
1565 * drop packets here under memory pressure.
1566 */
1567
1568 skb = dev_alloc_skb (pkt_size + 2);
1569 if (skb) {
1570 skb->dev = dev;
1571 skb_reserve (skb, 2); /* 16 byte align the IP fields. */
1572
1573 eth_copy_and_sum (skb, &rx_ring[ring_offset + 4], pkt_size, 0);
1574 skb_put (skb, pkt_size);
1575
1576 skb->protocol = eth_type_trans (skb, dev);
1577 netif_rx (skb);
1578 dev->last_rx = jiffies;
1579 tp->stats.rx_bytes += pkt_size;
1580 tp->stats.rx_packets++;
1581 } else {
1582 printk (KERN_WARNING
1583 "%s: Memory squeeze, dropping packet.\n",
1584 dev->name);
1585 tp->stats.rx_dropped++;
1586 }
1587
1588 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
1589 NETDRV_W16_F (RxBufPtr, cur_rx - 16);
1590 }
1591
1592 DPRINTK ("%s: Done netdrv_rx(), current %4.4x BufAddr %4.4x,"
1593 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
1594 NETDRV_R16 (RxBufAddr),
1595 NETDRV_R16 (RxBufPtr), NETDRV_R8 (ChipCmd));
1596
1597 tp->cur_rx = cur_rx;
1598 }
1599
1600
1601 static void netdrv_weird_interrupt (struct net_device *dev,
1602 struct netdrv_private *tp,
1603 void *ioaddr,
1604 int status, int link_changed)
1605 {
1606 printk (KERN_DEBUG "%s: Abnormal interrupt, status %8.8x.\n",
1607 dev->name, status);
1608
1609 assert (dev != NULL);
1610 assert (tp != NULL);
1611 assert (ioaddr != NULL);
1612
1613 /* Update the error count. */
1614 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1615 NETDRV_W32 (RxMissed, 0);
1616
1617 if ((status & RxUnderrun) && link_changed &&
1618 (tp->drv_flags & HAS_LNK_CHNG)) {
1619 /* Really link-change on new chips. */
1620 int lpar = NETDRV_R16 (NWayLPAR);
1621 int duplex = (lpar & 0x0100) || (lpar & 0x01C0) == 0x0040
1622 || tp->duplex_lock;
1623 if (tp->full_duplex != duplex) {
1624 tp->full_duplex = duplex;
1625 NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1626 NETDRV_W8 (Config1, tp->full_duplex ? 0x60 : 0x20);
1627 NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1628 }
1629 status &= ~RxUnderrun;
1630 }
1631
1632 /* XXX along with netdrv_rx_err, are we double-counting errors? */
1633 if (status &
1634 (RxUnderrun | RxOverflow | RxErr | RxFIFOOver))
1635 tp->stats.rx_errors++;
1636
1637 if (status & (PCSTimeout))
1638 tp->stats.rx_length_errors++;
1639 if (status & (RxUnderrun | RxFIFOOver))
1640 tp->stats.rx_fifo_errors++;
1641 if (status & RxOverflow) {
1642 tp->stats.rx_over_errors++;
1643 tp->cur_rx = NETDRV_R16 (RxBufAddr) % RX_BUF_LEN;
1644 NETDRV_W16_F (RxBufPtr, tp->cur_rx - 16);
1645 }
1646 if (status & PCIErr) {
1647 u16 pci_cmd_status;
1648 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
1649
1650 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
1651 dev->name, pci_cmd_status);
1652 }
1653 }
1654
1655
1656 /* The interrupt handler does all of the Rx thread work and cleans up
1657 after the Tx thread. */
1658 static irqreturn_t netdrv_interrupt (int irq, void *dev_instance,
1659 struct pt_regs *regs)
1660 {
1661 struct net_device *dev = (struct net_device *) dev_instance;
1662 struct netdrv_private *tp = dev->priv;
1663 int boguscnt = max_interrupt_work;
1664 void *ioaddr = tp->mmio_addr;
1665 int status = 0, link_changed = 0; /* avoid bogus "uninit" warning */
1666 int handled = 0;
1667
1668 spin_lock (&tp->lock);
1669
1670 do {
1671 status = NETDRV_R16 (IntrStatus);
1672
1673 /* h/w no longer present (hotplug?) or major error, bail */
1674 if (status == 0xFFFF)
1675 break;
1676
1677 handled = 1;
1678 /* Acknowledge all of the current interrupt sources ASAP */
1679 NETDRV_W16_F (IntrStatus, status);
1680
1681 DPRINTK ("%s: interrupt status=%#4.4x new intstat=%#4.4x.\n",
1682 dev->name, status,
1683 NETDRV_R16 (IntrStatus));
1684
1685 if ((status &
1686 (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
1687 RxFIFOOver | TxErr | TxOK | RxErr | RxOK)) == 0)
1688 break;
1689
1690 /* Check uncommon events with one test. */
1691 if (status & (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
1692 RxFIFOOver | TxErr | RxErr))
1693 netdrv_weird_interrupt (dev, tp, ioaddr,
1694 status, link_changed);
1695
1696 if (status & (RxOK | RxUnderrun | RxOverflow | RxFIFOOver)) /* Rx interrupt */
1697 netdrv_rx_interrupt (dev, tp, ioaddr);
1698
1699 if (status & (TxOK | TxErr))
1700 netdrv_tx_interrupt (dev, tp, ioaddr);
1701
1702 boguscnt--;
1703 } while (boguscnt > 0);
1704
1705 if (boguscnt <= 0) {
1706 printk (KERN_WARNING
1707 "%s: Too much work at interrupt, "
1708 "IntrStatus=0x%4.4x.\n", dev->name,
1709 status);
1710
1711 /* Clear all interrupt sources. */
1712 NETDRV_W16 (IntrStatus, 0xffff);
1713 }
1714
1715 spin_unlock (&tp->lock);
1716
1717 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
1718 dev->name, NETDRV_R16 (IntrStatus));
1719 return IRQ_RETVAL(handled);
1720 }
1721
1722
1723 static int netdrv_close (struct net_device *dev)
1724 {
1725 struct netdrv_private *tp = dev->priv;
1726 void *ioaddr = tp->mmio_addr;
1727 unsigned long flags;
1728
1729 DPRINTK ("ENTER\n");
1730
1731 netif_stop_queue (dev);
1732
1733 DPRINTK ("%s: Shutting down ethercard, status was 0x%4.4x.\n",
1734 dev->name, NETDRV_R16 (IntrStatus));
1735
1736 del_timer_sync (&tp->timer);
1737
1738 spin_lock_irqsave (&tp->lock, flags);
1739
1740 /* Stop the chip's Tx and Rx DMA processes. */
1741 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear));
1742
1743 /* Disable interrupts by clearing the interrupt mask. */
1744 NETDRV_W16 (IntrMask, 0x0000);
1745
1746 /* Update the error counts. */
1747 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1748 NETDRV_W32 (RxMissed, 0);
1749
1750 spin_unlock_irqrestore (&tp->lock, flags);
1751
1752 synchronize_irq ();
1753 free_irq (dev->irq, dev);
1754
1755 netdrv_tx_clear (tp);
1756
1757 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1758 tp->rx_ring, tp->rx_ring_dma);
1759 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1760 tp->tx_bufs, tp->tx_bufs_dma);
1761 tp->rx_ring = NULL;
1762 tp->tx_bufs = NULL;
1763
1764 /* Green! Put the chip in low-power mode. */
1765 NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1766 NETDRV_W8 (Config1, 0x03);
1767 NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1768
1769 DPRINTK ("EXIT\n");
1770 return 0;
1771 }
1772
1773
1774 static int netdrv_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1775 {
1776 struct netdrv_private *tp = dev->priv;
1777 struct mii_ioctl_data *data = if_mii(rq);
1778 unsigned long flags;
1779 int rc = 0;
1780
1781 DPRINTK ("ENTER\n");
1782
1783 switch (cmd) {
1784 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1785 data->phy_id = tp->phys[0] & 0x3f;
1786 /* Fall Through */
1787
1788 case SIOCGMIIREG: /* Read MII PHY register. */
1789 spin_lock_irqsave (&tp->lock, flags);
1790 data->val_out = mdio_read (dev, data->phy_id & 0x1f, data->reg_num & 0x1f);
1791 spin_unlock_irqrestore (&tp->lock, flags);
1792 break;
1793
1794 case SIOCSMIIREG: /* Write MII PHY register. */
1795 if (!capable (CAP_NET_ADMIN)) {
1796 rc = -EPERM;
1797 break;
1798 }
1799
1800 spin_lock_irqsave (&tp->lock, flags);
1801 mdio_write (dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1802 spin_unlock_irqrestore (&tp->lock, flags);
1803 break;
1804
1805 default:
1806 rc = -EOPNOTSUPP;
1807 break;
1808 }
1809
1810 DPRINTK ("EXIT, returning %d\n", rc);
1811 return rc;
1812 }
1813
1814
1815 static struct net_device_stats *netdrv_get_stats (struct net_device *dev)
1816 {
1817 struct netdrv_private *tp = dev->priv;
1818 void *ioaddr = tp->mmio_addr;
1819
1820 DPRINTK ("ENTER\n");
1821
1822 assert (tp != NULL);
1823
1824 if (netif_running(dev)) {
1825 unsigned long flags;
1826
1827 spin_lock_irqsave (&tp->lock, flags);
1828
1829 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1830 NETDRV_W32 (RxMissed, 0);
1831
1832 spin_unlock_irqrestore (&tp->lock, flags);
1833 }
1834
1835 DPRINTK ("EXIT\n");
1836 return &tp->stats;
1837 }
1838
1839 /* Set or clear the multicast filter for this adaptor.
1840 This routine is not state sensitive and need not be SMP locked. */
1841
1842 static void netdrv_set_rx_mode (struct net_device *dev)
1843 {
1844 struct netdrv_private *tp = dev->priv;
1845 void *ioaddr = tp->mmio_addr;
1846 u32 mc_filter[2]; /* Multicast hash filter */
1847 int i, rx_mode;
1848 u32 tmp;
1849
1850 DPRINTK ("ENTER\n");
1851
1852 DPRINTK ("%s: netdrv_set_rx_mode(%4.4x) done -- Rx config %8.8x.\n",
1853 dev->name, dev->flags, NETDRV_R32 (RxConfig));
1854
1855 /* Note: do not reorder, GCC is clever about common statements. */
1856 if (dev->flags & IFF_PROMISC) {
1857 /* Unconditionally log net taps. */
1858 printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n",
1859 dev->name);
1860 rx_mode =
1861 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
1862 AcceptAllPhys;
1863 mc_filter[1] = mc_filter[0] = 0xffffffff;
1864 } else if ((dev->mc_count > multicast_filter_limit)
1865 || (dev->flags & IFF_ALLMULTI)) {
1866 /* Too many to filter perfectly -- accept all multicasts. */
1867 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1868 mc_filter[1] = mc_filter[0] = 0xffffffff;
1869 } else {
1870 struct dev_mc_list *mclist;
1871 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1872 mc_filter[1] = mc_filter[0] = 0;
1873 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1874 i++, mclist = mclist->next) {
1875 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1876
1877 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1878 }
1879 }
1880
1881 /* if called from irq handler, lock already acquired */
1882 if (!in_irq ())
1883 spin_lock_irq (&tp->lock);
1884
1885 /* We can safely update without stopping the chip. */
1886 tmp = netdrv_rx_config | rx_mode |
1887 (NETDRV_R32 (RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1888 NETDRV_W32_F (RxConfig, tmp);
1889 NETDRV_W32_F (MAR0 + 0, mc_filter[0]);
1890 NETDRV_W32_F (MAR0 + 4, mc_filter[1]);
1891
1892 if (!in_irq ())
1893 spin_unlock_irq (&tp->lock);
1894
1895 DPRINTK ("EXIT\n");
1896 }
1897
1898
1899 #ifdef CONFIG_PM
1900
1901 static int netdrv_suspend (struct pci_dev *pdev, u32 state)
1902 {
1903 struct net_device *dev = pci_get_drvdata (pdev);
1904 struct netdrv_private *tp = dev->priv;
1905 void *ioaddr = tp->mmio_addr;
1906 unsigned long flags;
1907
1908 if (!netif_running(dev))
1909 return 0;
1910 netif_device_detach (dev);
1911
1912 spin_lock_irqsave (&tp->lock, flags);
1913
1914 /* Disable interrupts, stop Tx and Rx. */
1915 NETDRV_W16 (IntrMask, 0x0000);
1916 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear));
1917
1918 /* Update the error counts. */
1919 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1920 NETDRV_W32 (RxMissed, 0);
1921
1922 spin_unlock_irqrestore (&tp->lock, flags);
1923
1924 pci_save_state (pdev, tp->pci_state);
1925 pci_set_power_state (pdev, 3);
1926
1927 return 0;
1928 }
1929
1930
1931 static int netdrv_resume (struct pci_dev *pdev)
1932 {
1933 struct net_device *dev = pci_get_drvdata (pdev);
1934 struct netdrv_private *tp = dev->priv;
1935
1936 if (!netif_running(dev))
1937 return 0;
1938 pci_set_power_state (pdev, 0);
1939 pci_restore_state (pdev, tp->pci_state);
1940 netif_device_attach (dev);
1941 netdrv_hw_start (dev);
1942
1943 return 0;
1944 }
1945
1946 #endif /* CONFIG_PM */
1947
1948
1949 static struct pci_driver netdrv_pci_driver = {
1950 .name = MODNAME,
1951 .id_table = netdrv_pci_tbl,
1952 .probe = netdrv_init_one,
1953 .remove = __devexit_p(netdrv_remove_one),
1954 #ifdef CONFIG_PM
1955 .suspend = netdrv_suspend,
1956 .resume = netdrv_resume,
1957 #endif /* CONFIG_PM */
1958 };
1959
1960
1961 static int __init netdrv_init_module (void)
1962 {
1963 /* when a module, this is printed whether or not devices are found in probe */
1964 #ifdef MODULE
1965 printk(version);
1966 #endif
1967 return pci_module_init (&netdrv_pci_driver);
1968 }
1969
1970
1971 static void __exit netdrv_cleanup_module (void)
1972 {
1973 pci_unregister_driver (&netdrv_pci_driver);
1974 }
1975
1976
1977 module_init(netdrv_init_module);
1978 module_exit(netdrv_cleanup_module);
MOXA 2.6.9 from sdlinux-moxaart.tgz