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MOXA linux-2.6.x / linux-2.6.9-uc0 from sdlinux-moxaart.tgz
[linux-2.6.9-moxart.git] / drivers / net / r8169.c
blob98cd7d8888e780a75366740f0361b950df5ba9cd
1 /*
2 =========================================================================
3 r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver for Linux kernel 2.4.x.
4 --------------------------------------------------------------------
5
6 History:
7 Feb 4 2002 - created initially by ShuChen <shuchen@realtek.com.tw>.
8 May 20 2002 - Add link status force-mode and TBI mode support.
9 =========================================================================
10 1. [DEPRECATED: use ethtool instead] The media can be forced in 5 modes.
11 Command: 'insmod r8169 media = SET_MEDIA'
12 Ex: 'insmod r8169 media = 0x04' will force PHY to operate in 100Mpbs Half-duplex.
13
14 SET_MEDIA can be:
15 _10_Half = 0x01
16 _10_Full = 0x02
17 _100_Half = 0x04
18 _100_Full = 0x08
19 _1000_Full = 0x10
20
21 2. Support TBI mode.
22 =========================================================================
23 VERSION 1.1 <2002/10/4>
24
25 The bit4:0 of MII register 4 is called "selector field", and have to be
26 00001b to indicate support of IEEE std 802.3 during NWay process of
27 exchanging Link Code Word (FLP).
28
29 VERSION 1.2 <2002/11/30>
30
31 - Large style cleanup
32 - Use ether_crc in stock kernel (linux/crc32.h)
33 - Copy mc_filter setup code from 8139cp
34 (includes an optimization, and avoids set_bit use)
35
36 */
37
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/netdevice.h>
41 #include <linux/etherdevice.h>
42 #include <linux/delay.h>
43 #include <linux/ethtool.h>
44 #include <linux/mii.h>
45 #include <linux/crc32.h>
46 #include <linux/init.h>
47 #include <linux/dma-mapping.h>
48
49 #include <asm/io.h>
50
51 #define RTL8169_VERSION "1.2"
52 #define MODULENAME "r8169"
53 #define RTL8169_DRIVER_NAME MODULENAME " Gigabit Ethernet driver " RTL8169_VERSION
54 #define PFX MODULENAME ": "
55
56 #ifdef RTL8169_DEBUG
57 #define assert(expr) \
58 if(!(expr)) { \
59 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
60 #expr,__FILE__,__FUNCTION__,__LINE__); \
61 }
62 #define dprintk(fmt, args...) do { printk(PFX fmt, ## args) } while (0)
63 #else
64 #define assert(expr) do {} while (0)
65 #define dprintk(fmt, args...) do {} while (0)
66 #endif /* RTL8169_DEBUG */
67
68 #ifdef CONFIG_R8169_NAPI
69 #define rtl8169_rx_skb netif_receive_skb
70 #define rtl8169_rx_quota(count, quota) min(count, quota)
71 #else
72 #define rtl8169_rx_skb netif_rx
73 #define rtl8169_rx_quota(count, quota) count
74 #endif
75
76 /* media options */
77 #define MAX_UNITS 8
78 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
79
80 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
81 static int max_interrupt_work = 20;
82
83 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
84 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
85 static int multicast_filter_limit = 32;
86
87 /* MAC address length*/
88 #define MAC_ADDR_LEN 6
89
90 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
91 #define MAX_ETH_FRAME_SIZE 1536
92
93 #define TX_FIFO_THRESH 256 /* In bytes */
94
95 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
96 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
97 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
98 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
99 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */
100 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
101
102 #define R8169_NAPI_WEIGHT 64
103 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
104 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
105 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
106 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
107 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
108
109 #define RTL_MIN_IO_SIZE 0x80
110 #define RTL8169_TX_TIMEOUT (6*HZ)
111 #define RTL8169_PHY_TIMEOUT (10*HZ)
112
113 /* write/read MMIO register */
114 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
115 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
116 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
117 #define RTL_R8(reg) readb (ioaddr + (reg))
118 #define RTL_R16(reg) readw (ioaddr + (reg))
119 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
120
121 enum mac_version {
122 RTL_GIGA_MAC_VER_B = 0x00,
123 /* RTL_GIGA_MAC_VER_C = 0x03, */
124 RTL_GIGA_MAC_VER_D = 0x01,
125 RTL_GIGA_MAC_VER_E = 0x02
126 };
127
128 enum phy_version {
129 RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
130 RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
131 RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
132 RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
133 RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
134 };
135
136
137 #define _R(NAME,MAC,MASK) \
138 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
139
140 const static struct {
141 const char *name;
142 u8 mac_version;
143 u32 RxConfigMask; /* Clears the bits supported by this chip */
144 } rtl_chip_info[] = {
145 _R("RTL8169", RTL_GIGA_MAC_VER_B, 0xff7e1880),
146 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_D, 0xff7e1880),
147 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_E, 0xff7e1880)
148 };
149 #undef _R
150
151 static struct pci_device_id rtl8169_pci_tbl[] = {
152 {0x10ec, 0x8169, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
153 {0,},
154 };
155
156 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
157
158 static int rx_copybreak = 200;
159 static int use_dac;
160
161 enum RTL8169_registers {
162 MAC0 = 0, /* Ethernet hardware address. */
163 MAR0 = 8, /* Multicast filter. */
164 TxDescStartAddrLow = 0x20,
165 TxDescStartAddrHigh = 0x24,
166 TxHDescStartAddrLow = 0x28,
167 TxHDescStartAddrHigh = 0x2c,
168 FLASH = 0x30,
169 ERSR = 0x36,
170 ChipCmd = 0x37,
171 TxPoll = 0x38,
172 IntrMask = 0x3C,
173 IntrStatus = 0x3E,
174 TxConfig = 0x40,
175 RxConfig = 0x44,
176 RxMissed = 0x4C,
177 Cfg9346 = 0x50,
178 Config0 = 0x51,
179 Config1 = 0x52,
180 Config2 = 0x53,
181 Config3 = 0x54,
182 Config4 = 0x55,
183 Config5 = 0x56,
184 MultiIntr = 0x5C,
185 PHYAR = 0x60,
186 TBICSR = 0x64,
187 TBI_ANAR = 0x68,
188 TBI_LPAR = 0x6A,
189 PHYstatus = 0x6C,
190 RxMaxSize = 0xDA,
191 CPlusCmd = 0xE0,
192 RxDescAddrLow = 0xE4,
193 RxDescAddrHigh = 0xE8,
194 EarlyTxThres = 0xEC,
195 FuncEvent = 0xF0,
196 FuncEventMask = 0xF4,
197 FuncPresetState = 0xF8,
198 FuncForceEvent = 0xFC,
199 };
200
201 enum RTL8169_register_content {
202 /*InterruptStatusBits */
203 SYSErr = 0x8000,
204 PCSTimeout = 0x4000,
205 SWInt = 0x0100,
206 TxDescUnavail = 0x80,
207 RxFIFOOver = 0x40,
208 LinkChg = 0x20,
209 RxOverflow = 0x10,
210 TxErr = 0x08,
211 TxOK = 0x04,
212 RxErr = 0x02,
213 RxOK = 0x01,
214
215 /*RxStatusDesc */
216 RxRES = 0x00200000,
217 RxCRC = 0x00080000,
218 RxRUNT = 0x00100000,
219 RxRWT = 0x00400000,
220
221 /*ChipCmdBits */
222 CmdReset = 0x10,
223 CmdRxEnb = 0x08,
224 CmdTxEnb = 0x04,
225 RxBufEmpty = 0x01,
226
227 /*Cfg9346Bits */
228 Cfg9346_Lock = 0x00,
229 Cfg9346_Unlock = 0xC0,
230
231 /*rx_mode_bits */
232 AcceptErr = 0x20,
233 AcceptRunt = 0x10,
234 AcceptBroadcast = 0x08,
235 AcceptMulticast = 0x04,
236 AcceptMyPhys = 0x02,
237 AcceptAllPhys = 0x01,
238
239 /*RxConfigBits */
240 RxCfgFIFOShift = 13,
241 RxCfgDMAShift = 8,
242
243 /*TxConfigBits */
244 TxInterFrameGapShift = 24,
245 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
246
247 /* TBICSR p.28 */
248 TBIReset = 0x80000000,
249 TBILoopback = 0x40000000,
250 TBINwEnable = 0x20000000,
251 TBINwRestart = 0x10000000,
252 TBILinkOk = 0x02000000,
253 TBINwComplete = 0x01000000,
254
255 /* CPlusCmd p.31 */
256 RxVlan = (1 << 6),
257 RxChkSum = (1 << 5),
258 PCIDAC = (1 << 4),
259 PCIMulRW = (1 << 3),
260
261 /*rtl8169_PHYstatus */
262 TBI_Enable = 0x80,
263 TxFlowCtrl = 0x40,
264 RxFlowCtrl = 0x20,
265 _1000bpsF = 0x10,
266 _100bps = 0x08,
267 _10bps = 0x04,
268 LinkStatus = 0x02,
269 FullDup = 0x01,
270
271 /*GIGABIT_PHY_registers */
272 PHY_CTRL_REG = 0,
273 PHY_STAT_REG = 1,
274 PHY_AUTO_NEGO_REG = 4,
275 PHY_1000_CTRL_REG = 9,
276
277 /*GIGABIT_PHY_REG_BIT */
278 PHY_Restart_Auto_Nego = 0x0200,
279 PHY_Enable_Auto_Nego = 0x1000,
280
281 //PHY_STAT_REG = 1;
282 PHY_Auto_Neco_Comp = 0x0020,
283
284 //PHY_AUTO_NEGO_REG = 4;
285 PHY_Cap_10_Half = 0x0020,
286 PHY_Cap_10_Full = 0x0040,
287 PHY_Cap_100_Half = 0x0080,
288 PHY_Cap_100_Full = 0x0100,
289
290 //PHY_1000_CTRL_REG = 9;
291 PHY_Cap_1000_Full = 0x0200,
292
293 PHY_Cap_Null = 0x0,
294
295 /*_MediaType*/
296 _10_Half = 0x01,
297 _10_Full = 0x02,
298 _100_Half = 0x04,
299 _100_Full = 0x08,
300 _1000_Full = 0x10,
301
302 /*_TBICSRBit*/
303 TBILinkOK = 0x02000000,
304 };
305
306 enum _DescStatusBit {
307 OWNbit = 0x80000000,
308 EORbit = 0x40000000,
309 FSbit = 0x20000000,
310 LSbit = 0x10000000,
311 };
312
313 #define RsvdMask 0x3fffc000
314
315 struct TxDesc {
316 u32 status;
317 u32 vlan_tag;
318 u64 addr;
319 };
320
321 struct RxDesc {
322 u32 status;
323 u32 vlan_tag;
324 u64 addr;
325 };
326
327 struct rtl8169_private {
328 void *mmio_addr; /* memory map physical address */
329 struct pci_dev *pci_dev; /* Index of PCI device */
330 struct net_device_stats stats; /* statistics of net device */
331 spinlock_t lock; /* spin lock flag */
332 int chipset;
333 int mac_version;
334 int phy_version;
335 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
336 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
337 u32 dirty_rx;
338 u32 dirty_tx;
339 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
340 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
341 dma_addr_t TxPhyAddr;
342 dma_addr_t RxPhyAddr;
343 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
344 struct sk_buff *Tx_skbuff[NUM_TX_DESC]; /* Tx data buffers */
345 struct timer_list timer;
346 u16 cp_cmd;
347 u16 intr_mask;
348 int phy_auto_nego_reg;
349 int phy_1000_ctrl_reg;
350
351 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
352 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
353 void (*phy_reset_enable)(void *);
354 unsigned int (*phy_reset_pending)(void *);
355 unsigned int (*link_ok)(void *);
356 };
357
358 MODULE_AUTHOR("Realtek");
359 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
360 MODULE_PARM(media, "1-" __MODULE_STRING(MAX_UNITS) "i");
361 MODULE_PARM(rx_copybreak, "i");
362 MODULE_PARM(use_dac, "i");
363 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
364 MODULE_LICENSE("GPL");
365
366 static int rtl8169_open(struct net_device *dev);
367 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
368 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance,
369 struct pt_regs *regs);
370 static int rtl8169_init_ring(struct net_device *dev);
371 static void rtl8169_hw_start(struct net_device *dev);
372 static int rtl8169_close(struct net_device *dev);
373 static void rtl8169_set_rx_mode(struct net_device *dev);
374 static void rtl8169_tx_timeout(struct net_device *dev);
375 static struct net_device_stats *rtl8169_get_stats(struct net_device *netdev);
376 #ifdef CONFIG_R8169_NAPI
377 static int rtl8169_poll(struct net_device *dev, int *budget);
378 #endif
379
380 static const u16 rtl8169_intr_mask =
381 SYSErr | LinkChg | RxOverflow | RxFIFOOver | TxErr | TxOK | RxErr | RxOK;
382 static const u16 rtl8169_napi_event =
383 RxOK | RxOverflow | RxFIFOOver | TxOK | TxErr;
384 static const unsigned int rtl8169_rx_config =
385 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
386
387 #define PHY_Cap_10_Half_Or_Less PHY_Cap_10_Half
388 #define PHY_Cap_10_Full_Or_Less PHY_Cap_10_Full | PHY_Cap_10_Half_Or_Less
389 #define PHY_Cap_100_Half_Or_Less PHY_Cap_100_Half | PHY_Cap_10_Full_Or_Less
390 #define PHY_Cap_100_Full_Or_Less PHY_Cap_100_Full | PHY_Cap_100_Half_Or_Less
391
392 static void mdio_write(void *ioaddr, int RegAddr, int value)
393 {
394 int i;
395
396 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
397 udelay(1000);
398
399 for (i = 2000; i > 0; i--) {
400 // Check if the RTL8169 has completed writing to the specified MII register
401 if (!(RTL_R32(PHYAR) & 0x80000000))
402 break;
403 udelay(100);
404 }
405 }
406
407 static int mdio_read(void *ioaddr, int RegAddr)
408 {
409 int i, value = -1;
410
411 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
412 udelay(1000);
413
414 for (i = 2000; i > 0; i--) {
415 // Check if the RTL8169 has completed retrieving data from the specified MII register
416 if (RTL_R32(PHYAR) & 0x80000000) {
417 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
418 break;
419 }
420 udelay(100);
421 }
422 return value;
423 }
424
425 static unsigned int rtl8169_tbi_reset_pending(void *ioaddr)
426 {
427 return RTL_R32(TBICSR) & TBIReset;
428 }
429
430 static unsigned int rtl8169_xmii_reset_pending(void *ioaddr)
431 {
432 return mdio_read(ioaddr, 0) & 0x8000;
433 }
434
435 static unsigned int rtl8169_tbi_link_ok(void *ioaddr)
436 {
437 return RTL_R32(TBICSR) & TBILinkOk;
438 }
439
440 static unsigned int rtl8169_xmii_link_ok(void *ioaddr)
441 {
442 return RTL_R8(PHYstatus) & LinkStatus;
443 }
444
445 static void rtl8169_tbi_reset_enable(void *ioaddr)
446 {
447 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
448 }
449
450 static void rtl8169_xmii_reset_enable(void *ioaddr)
451 {
452 unsigned int val;
453
454 val = (mdio_read(ioaddr, PHY_CTRL_REG) | 0x8000) & 0xffff;
455 mdio_write(ioaddr, PHY_CTRL_REG, val);
456 }
457
458 static void rtl8169_check_link_status(struct net_device *dev,
459 struct rtl8169_private *tp, void *ioaddr)
460 {
461 unsigned long flags;
462
463 spin_lock_irqsave(&tp->lock, flags);
464 if (tp->link_ok(ioaddr)) {
465 netif_carrier_on(dev);
466 printk(KERN_INFO PFX "%s: link up\n", dev->name);
467 } else
468 netif_carrier_off(dev);
469 spin_unlock_irqrestore(&tp->lock, flags);
470 }
471
472 static void rtl8169_link_option(int idx, u8 *autoneg, u16 *speed, u8 *duplex)
473 {
474 struct {
475 u16 speed;
476 u8 duplex;
477 u8 autoneg;
478 u8 media;
479 } link_settings[] = {
480 { SPEED_10, DUPLEX_HALF, AUTONEG_DISABLE, _10_Half },
481 { SPEED_10, DUPLEX_FULL, AUTONEG_DISABLE, _10_Full },
482 { SPEED_100, DUPLEX_HALF, AUTONEG_DISABLE, _100_Half },
483 { SPEED_100, DUPLEX_FULL, AUTONEG_DISABLE, _100_Full },
484 { SPEED_1000, DUPLEX_FULL, AUTONEG_DISABLE, _1000_Full },
485 /* Make TBI happy */
486 { SPEED_1000, DUPLEX_FULL, AUTONEG_ENABLE, 0xff }
487 }, *p;
488 unsigned char option;
489
490 option = ((idx < MAX_UNITS) && (idx >= 0)) ? media[idx] : 0xff;
491
492 if ((option != 0xff) && !idx)
493 printk(KERN_WARNING PFX "media option is deprecated.\n");
494
495 for (p = link_settings; p->media != 0xff; p++) {
496 if (p->media == option)
497 break;
498 }
499 *autoneg = p->autoneg;
500 *speed = p->speed;
501 *duplex = p->duplex;
502 }
503
504 static void rtl8169_get_drvinfo(struct net_device *dev,
505 struct ethtool_drvinfo *info)
506 {
507 struct rtl8169_private *tp = netdev_priv(dev);
508
509 strcpy(info->driver, RTL8169_DRIVER_NAME);
510 strcpy(info->version, RTL8169_VERSION );
511 strcpy(info->bus_info, pci_name(tp->pci_dev));
512 }
513
514 static int rtl8169_set_speed_tbi(struct net_device *dev,
515 u8 autoneg, u16 speed, u8 duplex)
516 {
517 struct rtl8169_private *tp = netdev_priv(dev);
518 void *ioaddr = tp->mmio_addr;
519 int ret = 0;
520 u32 reg;
521
522 reg = RTL_R32(TBICSR);
523 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
524 (duplex == DUPLEX_FULL)) {
525 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
526 } else if (autoneg == AUTONEG_ENABLE)
527 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
528 else {
529 printk(KERN_WARNING PFX
530 "%s: incorrect speed setting refused in TBI mode\n",
531 dev->name);
532 ret = -EOPNOTSUPP;
533 }
534
535 return ret;
536 }
537
538 static int rtl8169_set_speed_xmii(struct net_device *dev,
539 u8 autoneg, u16 speed, u8 duplex)
540 {
541 struct rtl8169_private *tp = netdev_priv(dev);
542 void *ioaddr = tp->mmio_addr;
543 int auto_nego, giga_ctrl;
544
545 auto_nego = mdio_read(ioaddr, PHY_AUTO_NEGO_REG);
546 auto_nego &= ~(PHY_Cap_10_Half | PHY_Cap_10_Full |
547 PHY_Cap_100_Half | PHY_Cap_100_Full);
548 giga_ctrl = mdio_read(ioaddr, PHY_1000_CTRL_REG);
549 giga_ctrl &= ~(PHY_Cap_1000_Full | PHY_Cap_Null);
550
551 if (autoneg == AUTONEG_ENABLE) {
552 auto_nego |= (PHY_Cap_10_Half | PHY_Cap_10_Full |
553 PHY_Cap_100_Half | PHY_Cap_100_Full);
554 giga_ctrl |= PHY_Cap_1000_Full;
555 } else {
556 if (speed == SPEED_10)
557 auto_nego |= PHY_Cap_10_Half | PHY_Cap_10_Full;
558 else if (speed == SPEED_100)
559 auto_nego |= PHY_Cap_100_Half | PHY_Cap_100_Full;
560 else if (speed == SPEED_1000)
561 giga_ctrl |= PHY_Cap_1000_Full;
562
563 if (duplex == DUPLEX_HALF)
564 auto_nego &= ~(PHY_Cap_10_Full | PHY_Cap_100_Full);
565 }
566
567 tp->phy_auto_nego_reg = auto_nego;
568 tp->phy_1000_ctrl_reg = giga_ctrl;
569
570 mdio_write(ioaddr, PHY_AUTO_NEGO_REG, auto_nego);
571 mdio_write(ioaddr, PHY_1000_CTRL_REG, giga_ctrl);
572 mdio_write(ioaddr, PHY_CTRL_REG, PHY_Enable_Auto_Nego |
573 PHY_Restart_Auto_Nego);
574 return 0;
575 }
576
577 static int rtl8169_set_speed(struct net_device *dev,
578 u8 autoneg, u16 speed, u8 duplex)
579 {
580 struct rtl8169_private *tp = netdev_priv(dev);
581 int ret;
582
583 ret = tp->set_speed(dev, autoneg, speed, duplex);
584
585 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full))
586 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
587
588 return ret;
589 }
590
591 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
592 {
593 struct rtl8169_private *tp = netdev_priv(dev);
594 unsigned long flags;
595 int ret;
596
597 spin_lock_irqsave(&tp->lock, flags);
598 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
599 spin_unlock_irqrestore(&tp->lock, flags);
600
601 return ret;
602 }
603
604 static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
605 {
606 struct rtl8169_private *tp = netdev_priv(dev);
607 void *ioaddr = tp->mmio_addr;
608 u32 status;
609
610 cmd->supported =
611 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
612 cmd->port = PORT_FIBRE;
613 cmd->transceiver = XCVR_INTERNAL;
614
615 status = RTL_R32(TBICSR);
616 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
617 cmd->autoneg = !!(status & TBINwEnable);
618
619 cmd->speed = SPEED_1000;
620 cmd->duplex = DUPLEX_FULL; /* Always set */
621 }
622
623 static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
624 {
625 struct rtl8169_private *tp = netdev_priv(dev);
626 void *ioaddr = tp->mmio_addr;
627 u8 status;
628
629 cmd->supported = SUPPORTED_10baseT_Half |
630 SUPPORTED_10baseT_Full |
631 SUPPORTED_100baseT_Half |
632 SUPPORTED_100baseT_Full |
633 SUPPORTED_1000baseT_Full |
634 SUPPORTED_Autoneg |
635 SUPPORTED_TP;
636
637 cmd->autoneg = 1;
638 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
639
640 if (tp->phy_auto_nego_reg & PHY_Cap_10_Half)
641 cmd->advertising |= ADVERTISED_10baseT_Half;
642 if (tp->phy_auto_nego_reg & PHY_Cap_10_Full)
643 cmd->advertising |= ADVERTISED_10baseT_Full;
644 if (tp->phy_auto_nego_reg & PHY_Cap_100_Half)
645 cmd->advertising |= ADVERTISED_100baseT_Half;
646 if (tp->phy_auto_nego_reg & PHY_Cap_100_Full)
647 cmd->advertising |= ADVERTISED_100baseT_Full;
648 if (tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full)
649 cmd->advertising |= ADVERTISED_1000baseT_Full;
650
651 status = RTL_R8(PHYstatus);
652
653 if (status & _1000bpsF)
654 cmd->speed = SPEED_1000;
655 else if (status & _100bps)
656 cmd->speed = SPEED_100;
657 else if (status & _10bps)
658 cmd->speed = SPEED_10;
659
660 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
661 DUPLEX_FULL : DUPLEX_HALF;
662 }
663
664 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
665 {
666 struct rtl8169_private *tp = netdev_priv(dev);
667 unsigned long flags;
668
669 spin_lock_irqsave(&tp->lock, flags);
670
671 tp->get_settings(dev, cmd);
672
673 spin_unlock_irqrestore(&tp->lock, flags);
674 return 0;
675 }
676
677
678 static struct ethtool_ops rtl8169_ethtool_ops = {
679 .get_drvinfo = rtl8169_get_drvinfo,
680 .get_link = ethtool_op_get_link,
681 .get_settings = rtl8169_get_settings,
682 .set_settings = rtl8169_set_settings,
683 };
684
685 static void rtl8169_write_gmii_reg_bit(void *ioaddr, int reg, int bitnum,
686 int bitval)
687 {
688 int val;
689
690 val = mdio_read(ioaddr, reg);
691 val = (bitval == 1) ?
692 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
693 mdio_write(ioaddr, reg, val & 0xffff);
694 }
695
696 static void rtl8169_get_mac_version(struct rtl8169_private *tp, void *ioaddr)
697 {
698 const struct {
699 u32 mask;
700 int mac_version;
701 } mac_info[] = {
702 { 0x1 << 26, RTL_GIGA_MAC_VER_E },
703 { 0x1 << 23, RTL_GIGA_MAC_VER_D },
704 { 0x00000000, RTL_GIGA_MAC_VER_B } /* Catch-all */
705 }, *p = mac_info;
706 u32 reg;
707
708 reg = RTL_R32(TxConfig) & 0x7c800000;
709 while ((reg & p->mask) != p->mask)
710 p++;
711 tp->mac_version = p->mac_version;
712 }
713
714 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
715 {
716 struct {
717 int version;
718 char *msg;
719 } mac_print[] = {
720 { RTL_GIGA_MAC_VER_E, "RTL_GIGA_MAC_VER_E" },
721 { RTL_GIGA_MAC_VER_D, "RTL_GIGA_MAC_VER_D" },
722 { RTL_GIGA_MAC_VER_B, "RTL_GIGA_MAC_VER_B" },
723 { 0, NULL }
724 }, *p;
725
726 for (p = mac_print; p->msg; p++) {
727 if (tp->mac_version == p->version) {
728 dprintk("mac_version == %s (%04d)\n", p->msg,
729 p->version);
730 return;
731 }
732 }
733 dprintk("mac_version == Unknown\n");
734 }
735
736 static void rtl8169_get_phy_version(struct rtl8169_private *tp, void *ioaddr)
737 {
738 const struct {
739 u16 mask;
740 u16 set;
741 int phy_version;
742 } phy_info[] = {
743 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
744 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
745 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
746 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
747 }, *p = phy_info;
748 u16 reg;
749
750 reg = mdio_read(ioaddr, 3) & 0xffff;
751 while ((reg & p->mask) != p->set)
752 p++;
753 tp->phy_version = p->phy_version;
754 }
755
756 static void rtl8169_print_phy_version(struct rtl8169_private *tp)
757 {
758 struct {
759 int version;
760 char *msg;
761 u32 reg;
762 } phy_print[] = {
763 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
764 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
765 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
766 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
767 { 0, NULL, 0x0000 }
768 }, *p;
769
770 for (p = phy_print; p->msg; p++) {
771 if (tp->phy_version == p->version) {
772 dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
773 return;
774 }
775 }
776 dprintk("phy_version == Unknown\n");
777 }
778
779 static void rtl8169_hw_phy_config(struct net_device *dev)
780 {
781 struct rtl8169_private *tp = netdev_priv(dev);
782 void *ioaddr = tp->mmio_addr;
783 struct {
784 u16 regs[5]; /* Beware of bit-sign propagation */
785 } phy_magic[5] = { {
786 { 0x0000, //w 4 15 12 0
787 0x00a1, //w 3 15 0 00a1
788 0x0008, //w 2 15 0 0008
789 0x1020, //w 1 15 0 1020
790 0x1000 } },{ //w 0 15 0 1000
791 { 0x7000, //w 4 15 12 7
792 0xff41, //w 3 15 0 ff41
793 0xde60, //w 2 15 0 de60
794 0x0140, //w 1 15 0 0140
795 0x0077 } },{ //w 0 15 0 0077
796 { 0xa000, //w 4 15 12 a
797 0xdf01, //w 3 15 0 df01
798 0xdf20, //w 2 15 0 df20
799 0xff95, //w 1 15 0 ff95
800 0xfa00 } },{ //w 0 15 0 fa00
801 { 0xb000, //w 4 15 12 b
802 0xff41, //w 3 15 0 ff41
803 0xde20, //w 2 15 0 de20
804 0x0140, //w 1 15 0 0140
805 0x00bb } },{ //w 0 15 0 00bb
806 { 0xf000, //w 4 15 12 f
807 0xdf01, //w 3 15 0 df01
808 0xdf20, //w 2 15 0 df20
809 0xff95, //w 1 15 0 ff95
810 0xbf00 } //w 0 15 0 bf00
811 }
812 }, *p = phy_magic;
813 int i;
814
815 rtl8169_print_mac_version(tp);
816 rtl8169_print_phy_version(tp);
817
818 if (tp->mac_version <= RTL_GIGA_MAC_VER_B)
819 return;
820 if (tp->phy_version >= RTL_GIGA_PHY_VER_F)
821 return;
822
823 dprintk("MAC version != 0 && PHY version == 0 or 1\n");
824 dprintk("Do final_reg2.cfg\n");
825
826 /* Shazam ! */
827
828 // phy config for RTL8169s mac_version C chip
829 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
830 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
831 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
832 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
833
834 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
835 int val, pos = 4;
836
837 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
838 mdio_write(ioaddr, pos, val);
839 while (--pos >= 0)
840 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
841 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
842 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
843 }
844 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
845 }
846
847 static void rtl8169_phy_timer(unsigned long __opaque)
848 {
849 struct net_device *dev = (struct net_device *)__opaque;
850 struct rtl8169_private *tp = netdev_priv(dev);
851 struct timer_list *timer = &tp->timer;
852 void *ioaddr = tp->mmio_addr;
853 unsigned long timeout = RTL8169_PHY_TIMEOUT;
854
855 assert(tp->mac_version > RTL_GIGA_MAC_VER_B);
856 assert(tp->phy_version < RTL_GIGA_PHY_VER_G);
857
858 if (!(tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full))
859 return;
860
861 spin_lock_irq(&tp->lock);
862
863 if (tp->phy_reset_pending(ioaddr)) {
864 /*
865 * A busy loop could burn quite a few cycles on nowadays CPU.
866 * Let's delay the execution of the timer for a few ticks.
867 */
868 timeout = HZ/10;
869 goto out_mod_timer;
870 }
871
872 if (tp->link_ok(ioaddr))
873 goto out_unlock;
874
875 printk(KERN_WARNING PFX "%s: PHY reset until link up\n", dev->name);
876
877 tp->phy_reset_enable(ioaddr);
878
879 out_mod_timer:
880 mod_timer(timer, jiffies + timeout);
881 out_unlock:
882 spin_unlock_irq(&tp->lock);
883 }
884
885 static inline void rtl8169_delete_timer(struct net_device *dev)
886 {
887 struct rtl8169_private *tp = netdev_priv(dev);
888 struct timer_list *timer = &tp->timer;
889
890 if ((tp->mac_version <= RTL_GIGA_MAC_VER_B) ||
891 (tp->phy_version >= RTL_GIGA_PHY_VER_G))
892 return;
893
894 del_timer_sync(timer);
895 }
896
897 static inline void rtl8169_request_timer(struct net_device *dev)
898 {
899 struct rtl8169_private *tp = netdev_priv(dev);
900 struct timer_list *timer = &tp->timer;
901
902 if ((tp->mac_version <= RTL_GIGA_MAC_VER_B) ||
903 (tp->phy_version >= RTL_GIGA_PHY_VER_G))
904 return;
905
906 init_timer(timer);
907 timer->expires = jiffies + RTL8169_PHY_TIMEOUT;
908 timer->data = (unsigned long)(dev);
909 timer->function = rtl8169_phy_timer;
910 add_timer(timer);
911 }
912
913 static int __devinit
914 rtl8169_init_board(struct pci_dev *pdev, struct net_device **dev_out,
915 void **ioaddr_out)
916 {
917 void *ioaddr = NULL;
918 struct net_device *dev;
919 struct rtl8169_private *tp;
920 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
921 int rc, i, acpi_idle_state = 0, pm_cap;
922
923
924 assert(pdev != NULL);
925 assert(ioaddr_out != NULL);
926
927 *ioaddr_out = NULL;
928 *dev_out = NULL;
929
930 // dev zeroed in alloc_etherdev
931 dev = alloc_etherdev(sizeof (*tp));
932 if (dev == NULL) {
933 printk(KERN_ERR PFX "unable to alloc new ethernet\n");
934 return -ENOMEM;
935 }
936
937 SET_MODULE_OWNER(dev);
938 SET_NETDEV_DEV(dev, &pdev->dev);
939 tp = dev->priv;
940
941 // enable device (incl. PCI PM wakeup and hotplug setup)
942 rc = pci_enable_device(pdev);
943 if (rc) {
944 printk(KERN_ERR PFX "%s: enable failure\n", pdev->slot_name);
945 goto err_out;
946 }
947
948 /* save power state before pci_enable_device overwrites it */
949 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
950 if (pm_cap) {
951 u16 pwr_command;
952
953 pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pwr_command);
954 acpi_idle_state = pwr_command & PCI_PM_CTRL_STATE_MASK;
955 } else {
956 printk(KERN_ERR PFX
957 "Cannot find PowerManagement capability, aborting.\n");
958 goto err_out_free_res;
959 }
960
961 mmio_start = pci_resource_start(pdev, 1);
962 mmio_end = pci_resource_end(pdev, 1);
963 mmio_flags = pci_resource_flags(pdev, 1);
964 mmio_len = pci_resource_len(pdev, 1);
965
966 // make sure PCI base addr 1 is MMIO
967 if (!(mmio_flags & IORESOURCE_MEM)) {
968 printk(KERN_ERR PFX
969 "region #1 not an MMIO resource, aborting\n");
970 rc = -ENODEV;
971 goto err_out_disable;
972 }
973 // check for weird/broken PCI region reporting
974 if (mmio_len < RTL_MIN_IO_SIZE) {
975 printk(KERN_ERR PFX "Invalid PCI region size(s), aborting\n");
976 rc = -ENODEV;
977 goto err_out_disable;
978 }
979
980 rc = pci_request_regions(pdev, MODULENAME);
981 if (rc) {
982 printk(KERN_ERR PFX "%s: could not request regions.\n",
983 pdev->slot_name);
984 goto err_out_disable;
985 }
986
987 tp->cp_cmd = PCIMulRW | RxChkSum;
988
989 if ((sizeof(dma_addr_t) > 4) &&
990 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac)
991 tp->cp_cmd |= PCIDAC;
992 else {
993 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
994 if (rc < 0) {
995 printk(KERN_ERR PFX "DMA configuration failed.\n");
996 goto err_out_free_res;
997 }
998 }
999
1000
1001 // enable PCI bus-mastering
1002 pci_set_master(pdev);
1003
1004 // ioremap MMIO region
1005 ioaddr = ioremap(mmio_start, mmio_len);
1006 if (ioaddr == NULL) {
1007 printk(KERN_ERR PFX "cannot remap MMIO, aborting\n");
1008 rc = -EIO;
1009 goto err_out_free_res;
1010 }
1011
1012 // Soft reset the chip.
1013 RTL_W8(ChipCmd, CmdReset);
1014
1015 // Check that the chip has finished the reset.
1016 for (i = 1000; i > 0; i--) {
1017 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1018 break;
1019 udelay(10);
1020 }
1021
1022 // Identify chip attached to board
1023 rtl8169_get_mac_version(tp, ioaddr);
1024 rtl8169_get_phy_version(tp, ioaddr);
1025
1026 rtl8169_print_mac_version(tp);
1027 rtl8169_print_phy_version(tp);
1028
1029 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1030 if (tp->mac_version == rtl_chip_info[i].mac_version)
1031 break;
1032 }
1033 if (i < 0) {
1034 /* Unknown chip: assume array element #0, original RTL-8169 */
1035 printk(KERN_DEBUG PFX
1036 "PCI device %s: unknown chip version, assuming %s\n",
1037 pci_name(pdev), rtl_chip_info[0].name);
1038 i++;
1039 }
1040 tp->chipset = i;
1041
1042 *ioaddr_out = ioaddr;
1043 *dev_out = dev;
1044 return 0;
1045
1046 err_out_free_res:
1047 pci_release_regions(pdev);
1048
1049 err_out_disable:
1050 pci_disable_device(pdev);
1051
1052 err_out:
1053 free_netdev(dev);
1054 return rc;
1055 }
1056
1057 static int __devinit
1058 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1059 {
1060 struct net_device *dev = NULL;
1061 struct rtl8169_private *tp = NULL;
1062 void *ioaddr = NULL;
1063 static int board_idx = -1;
1064 static int printed_version = 0;
1065 u8 autoneg, duplex;
1066 u16 speed;
1067 int i, rc;
1068
1069 assert(pdev != NULL);
1070 assert(ent != NULL);
1071
1072 board_idx++;
1073
1074 if (!printed_version) {
1075 printk(KERN_INFO RTL8169_DRIVER_NAME " loaded\n");
1076 printed_version = 1;
1077 }
1078
1079 rc = rtl8169_init_board(pdev, &dev, &ioaddr);
1080 if (rc)
1081 return rc;
1082
1083 tp = dev->priv;
1084 assert(ioaddr != NULL);
1085 assert(dev != NULL);
1086 assert(tp != NULL);
1087
1088 if (RTL_R8(PHYstatus) & TBI_Enable) {
1089 tp->set_speed = rtl8169_set_speed_tbi;
1090 tp->get_settings = rtl8169_gset_tbi;
1091 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1092 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1093 tp->link_ok = rtl8169_tbi_link_ok;
1094
1095 tp->phy_1000_ctrl_reg = PHY_Cap_1000_Full; /* Implied by TBI */
1096 } else {
1097 tp->set_speed = rtl8169_set_speed_xmii;
1098 tp->get_settings = rtl8169_gset_xmii;
1099 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1100 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1101 tp->link_ok = rtl8169_xmii_link_ok;
1102 }
1103
1104 // Get MAC address. FIXME: read EEPROM
1105 for (i = 0; i < MAC_ADDR_LEN; i++)
1106 dev->dev_addr[i] = RTL_R8(MAC0 + i);
1107
1108 dev->open = rtl8169_open;
1109 dev->hard_start_xmit = rtl8169_start_xmit;
1110 dev->get_stats = rtl8169_get_stats;
1111 dev->ethtool_ops = &rtl8169_ethtool_ops;
1112 dev->stop = rtl8169_close;
1113 dev->tx_timeout = rtl8169_tx_timeout;
1114 dev->set_multicast_list = rtl8169_set_rx_mode;
1115 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1116 dev->irq = pdev->irq;
1117 dev->base_addr = (unsigned long) ioaddr;
1118 #ifdef CONFIG_R8169_NAPI
1119 dev->poll = rtl8169_poll;
1120 dev->weight = R8169_NAPI_WEIGHT;
1121 printk(KERN_INFO PFX "NAPI enabled\n");
1122 #endif
1123 tp->intr_mask = 0xffff;
1124 tp->pci_dev = pdev;
1125 tp->mmio_addr = ioaddr;
1126
1127 spin_lock_init(&tp->lock);
1128
1129 rc = register_netdev(dev);
1130 if (rc) {
1131 iounmap(ioaddr);
1132 pci_release_regions(pdev);
1133 pci_disable_device(pdev);
1134 free_netdev(dev);
1135 return rc;
1136 }
1137
1138 printk(KERN_DEBUG "%s: Identified chip type is '%s'.\n", dev->name,
1139 rtl_chip_info[tp->chipset].name);
1140
1141 pci_set_drvdata(pdev, dev);
1142
1143 printk(KERN_INFO "%s: %s at 0x%lx, "
1144 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1145 "IRQ %d\n",
1146 dev->name,
1147 rtl_chip_info[ent->driver_data].name,
1148 dev->base_addr,
1149 dev->dev_addr[0], dev->dev_addr[1],
1150 dev->dev_addr[2], dev->dev_addr[3],
1151 dev->dev_addr[4], dev->dev_addr[5], dev->irq);
1152
1153 rtl8169_hw_phy_config(dev);
1154
1155 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1156 RTL_W8(0x82, 0x01);
1157
1158 if (tp->mac_version < RTL_GIGA_MAC_VER_E) {
1159 dprintk("Set PCI Latency=0x40\n");
1160 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
1161 }
1162
1163 if (tp->mac_version == RTL_GIGA_MAC_VER_D) {
1164 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1165 RTL_W8(0x82, 0x01);
1166 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1167 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1168 }
1169
1170 rtl8169_link_option(board_idx, &autoneg, &speed, &duplex);
1171
1172 rtl8169_set_speed(dev, autoneg, speed, duplex);
1173
1174 if (RTL_R8(PHYstatus) & TBI_Enable)
1175 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1176
1177 return 0;
1178 }
1179
1180 static void __devexit
1181 rtl8169_remove_one(struct pci_dev *pdev)
1182 {
1183 struct net_device *dev = pci_get_drvdata(pdev);
1184 struct rtl8169_private *tp = netdev_priv(dev);
1185
1186 assert(dev != NULL);
1187 assert(tp != NULL);
1188
1189 unregister_netdev(dev);
1190 iounmap(tp->mmio_addr);
1191 pci_release_regions(pdev);
1192
1193 pci_disable_device(pdev);
1194 free_netdev(dev);
1195 pci_set_drvdata(pdev, NULL);
1196 }
1197
1198 #ifdef CONFIG_PM
1199
1200 static int rtl8169_suspend(struct pci_dev *pdev, u32 state)
1201 {
1202 struct net_device *dev = pci_get_drvdata(pdev);
1203 struct rtl8169_private *tp = netdev_priv(dev);
1204 void *ioaddr = tp->mmio_addr;
1205 unsigned long flags;
1206
1207 if (!netif_running(dev))
1208 return 0;
1209
1210 netif_device_detach(dev);
1211 netif_stop_queue(dev);
1212 spin_lock_irqsave(&tp->lock, flags);
1213
1214 /* Disable interrupts, stop Rx and Tx */
1215 RTL_W16(IntrMask, 0);
1216 RTL_W8(ChipCmd, 0);
1217
1218 /* Update the error counts. */
1219 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
1220 RTL_W32(RxMissed, 0);
1221 spin_unlock_irqrestore(&tp->lock, flags);
1222
1223 return 0;
1224 }
1225
1226 static int rtl8169_resume(struct pci_dev *pdev)
1227 {
1228 struct net_device *dev = pci_get_drvdata(pdev);
1229
1230 if (!netif_running(dev))
1231 return 0;
1232
1233 netif_device_attach(dev);
1234 rtl8169_hw_start(dev);
1235
1236 return 0;
1237 }
1238
1239 #endif /* CONFIG_PM */
1240
1241 static int
1242 rtl8169_open(struct net_device *dev)
1243 {
1244 struct rtl8169_private *tp = netdev_priv(dev);
1245 struct pci_dev *pdev = tp->pci_dev;
1246 int retval;
1247
1248 retval =
1249 request_irq(dev->irq, rtl8169_interrupt, SA_SHIRQ, dev->name, dev);
1250 if (retval < 0)
1251 goto out;
1252
1253 retval = -ENOMEM;
1254
1255 /*
1256 * Rx and Tx desscriptors needs 256 bytes alignment.
1257 * pci_alloc_consistent provides more.
1258 */
1259 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1260 &tp->TxPhyAddr);
1261 if (!tp->TxDescArray)
1262 goto err_free_irq;
1263
1264 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1265 &tp->RxPhyAddr);
1266 if (!tp->RxDescArray)
1267 goto err_free_tx;
1268
1269 retval = rtl8169_init_ring(dev);
1270 if (retval < 0)
1271 goto err_free_rx;
1272
1273 rtl8169_hw_start(dev);
1274
1275 rtl8169_request_timer(dev);
1276
1277 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1278 out:
1279 return retval;
1280
1281 err_free_rx:
1282 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1283 tp->RxPhyAddr);
1284 err_free_tx:
1285 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1286 tp->TxPhyAddr);
1287 err_free_irq:
1288 free_irq(dev->irq, dev);
1289 goto out;
1290 }
1291
1292 static void
1293 rtl8169_hw_start(struct net_device *dev)
1294 {
1295 struct rtl8169_private *tp = netdev_priv(dev);
1296 void *ioaddr = tp->mmio_addr;
1297 u32 i;
1298
1299 /* Soft reset the chip. */
1300 RTL_W8(ChipCmd, CmdReset);
1301
1302 /* Check that the chip has finished the reset. */
1303 for (i = 1000; i > 0; i--) {
1304 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1305 break;
1306 udelay(10);
1307 }
1308
1309 RTL_W8(Cfg9346, Cfg9346_Unlock);
1310 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1311 RTL_W8(EarlyTxThres, EarlyTxThld);
1312
1313 // For gigabit rtl8169
1314 RTL_W16(RxMaxSize, RxPacketMaxSize);
1315
1316 // Set Rx Config register
1317 i = rtl8169_rx_config |
1318 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1319 RTL_W32(RxConfig, i);
1320
1321 /* Set DMA burst size and Interframe Gap Time */
1322 RTL_W32(TxConfig,
1323 (TX_DMA_BURST << TxDMAShift) | (InterFrameGap <<
1324 TxInterFrameGapShift));
1325 tp->cp_cmd |= RTL_R16(CPlusCmd);
1326 RTL_W16(CPlusCmd, tp->cp_cmd);
1327
1328 if (tp->mac_version == RTL_GIGA_MAC_VER_D) {
1329 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
1330 "Bit-3 and bit-14 MUST be 1\n");
1331 tp->cp_cmd |= (1 << 14) | PCIMulRW;
1332 RTL_W16(CPlusCmd, tp->cp_cmd);
1333 }
1334
1335 tp->cur_rx = 0;
1336
1337 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr & DMA_32BIT_MASK));
1338 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr >> 32));
1339 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK));
1340 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32));
1341 RTL_W8(Cfg9346, Cfg9346_Lock);
1342 udelay(10);
1343
1344 RTL_W32(RxMissed, 0);
1345
1346 rtl8169_set_rx_mode(dev);
1347
1348 /* no early-rx interrupts */
1349 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1350
1351 /* Enable all known interrupts by setting the interrupt mask. */
1352 RTL_W16(IntrMask, rtl8169_intr_mask);
1353
1354 netif_start_queue(dev);
1355 }
1356
1357 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
1358 {
1359 desc->addr = 0x0badbadbadbadbadull;
1360 desc->status &= ~cpu_to_le32(OWNbit | RsvdMask);
1361 }
1362
1363 static void rtl8169_free_rx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff,
1364 struct RxDesc *desc)
1365 {
1366 pci_unmap_single(pdev, le64_to_cpu(desc->addr), RX_BUF_SIZE,
1367 PCI_DMA_FROMDEVICE);
1368 dev_kfree_skb(*sk_buff);
1369 *sk_buff = NULL;
1370 rtl8169_make_unusable_by_asic(desc);
1371 }
1372
1373 static inline void rtl8169_return_to_asic(struct RxDesc *desc)
1374 {
1375 desc->status |= cpu_to_le32(OWNbit + RX_BUF_SIZE);
1376 }
1377
1378 static inline void rtl8169_give_to_asic(struct RxDesc *desc, dma_addr_t mapping)
1379 {
1380 desc->addr = cpu_to_le64(mapping);
1381 desc->status |= cpu_to_le32(OWNbit + RX_BUF_SIZE);
1382 }
1383
1384 static int rtl8169_alloc_rx_skb(struct pci_dev *pdev, struct net_device *dev,
1385 struct sk_buff **sk_buff, struct RxDesc *desc)
1386 {
1387 struct sk_buff *skb;
1388 dma_addr_t mapping;
1389 int ret = 0;
1390
1391 skb = dev_alloc_skb(RX_BUF_SIZE);
1392 if (!skb)
1393 goto err_out;
1394
1395 skb->dev = dev;
1396 skb_reserve(skb, 2);
1397 *sk_buff = skb;
1398
1399 mapping = pci_map_single(pdev, skb->tail, RX_BUF_SIZE,
1400 PCI_DMA_FROMDEVICE);
1401
1402 rtl8169_give_to_asic(desc, mapping);
1403
1404 out:
1405 return ret;
1406
1407 err_out:
1408 ret = -ENOMEM;
1409 rtl8169_make_unusable_by_asic(desc);
1410 goto out;
1411 }
1412
1413 static void rtl8169_rx_clear(struct rtl8169_private *tp)
1414 {
1415 int i;
1416
1417 for (i = 0; i < NUM_RX_DESC; i++) {
1418 if (tp->Rx_skbuff[i]) {
1419 rtl8169_free_rx_skb(tp->pci_dev, tp->Rx_skbuff + i,
1420 tp->RxDescArray + i);
1421 }
1422 }
1423 }
1424
1425 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
1426 u32 start, u32 end)
1427 {
1428 u32 cur;
1429
1430 for (cur = start; end - cur > 0; cur++) {
1431 int ret, i = cur % NUM_RX_DESC;
1432
1433 if (tp->Rx_skbuff[i])
1434 continue;
1435
1436 ret = rtl8169_alloc_rx_skb(tp->pci_dev, dev, tp->Rx_skbuff + i,
1437 tp->RxDescArray + i);
1438 if (ret < 0)
1439 break;
1440 }
1441 return cur - start;
1442 }
1443
1444 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1445 {
1446 desc->status |= cpu_to_le32(EORbit);
1447 }
1448
1449 static int rtl8169_init_ring(struct net_device *dev)
1450 {
1451 struct rtl8169_private *tp = netdev_priv(dev);
1452
1453 tp->cur_rx = tp->dirty_rx = 0;
1454 tp->cur_tx = tp->dirty_tx = 0;
1455 memset(tp->TxDescArray, 0x0, NUM_TX_DESC * sizeof (struct TxDesc));
1456 memset(tp->RxDescArray, 0x0, NUM_RX_DESC * sizeof (struct RxDesc));
1457
1458 memset(tp->Tx_skbuff, 0x0, NUM_TX_DESC * sizeof(struct sk_buff *));
1459 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
1460
1461 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
1462 goto err_out;
1463
1464 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
1465
1466 return 0;
1467
1468 err_out:
1469 rtl8169_rx_clear(tp);
1470 return -ENOMEM;
1471 }
1472
1473 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff,
1474 struct TxDesc *desc)
1475 {
1476 u32 len = sk_buff[0]->len;
1477
1478 pci_unmap_single(pdev, le64_to_cpu(desc->addr),
1479 len < ETH_ZLEN ? ETH_ZLEN : len, PCI_DMA_TODEVICE);
1480 desc->addr = 0x00;
1481 *sk_buff = NULL;
1482 }
1483
1484 static void
1485 rtl8169_tx_clear(struct rtl8169_private *tp)
1486 {
1487 int i;
1488
1489 tp->cur_tx = 0;
1490 for (i = 0; i < NUM_TX_DESC; i++) {
1491 struct sk_buff *skb = tp->Tx_skbuff[i];
1492
1493 if (skb) {
1494 rtl8169_unmap_tx_skb(tp->pci_dev, tp->Tx_skbuff + i,
1495 tp->TxDescArray + i);
1496 dev_kfree_skb(skb);
1497 tp->stats.tx_dropped++;
1498 }
1499 }
1500 }
1501
1502 static void
1503 rtl8169_tx_timeout(struct net_device *dev)
1504 {
1505 struct rtl8169_private *tp = netdev_priv(dev);
1506 void *ioaddr = tp->mmio_addr;
1507 u8 tmp8;
1508
1509 printk(KERN_INFO "%s: TX Timeout\n", dev->name);
1510 /* disable Tx, if not already */
1511 tmp8 = RTL_R8(ChipCmd);
1512 if (tmp8 & CmdTxEnb)
1513 RTL_W8(ChipCmd, tmp8 & ~CmdTxEnb);
1514
1515 /* Disable interrupts by clearing the interrupt mask. */
1516 RTL_W16(IntrMask, 0x0000);
1517
1518 /* Stop a shared interrupt from scavenging while we are. */
1519 spin_lock_irq(&tp->lock);
1520 rtl8169_tx_clear(tp);
1521 spin_unlock_irq(&tp->lock);
1522
1523 /* ...and finally, reset everything */
1524 rtl8169_hw_start(dev);
1525
1526 netif_wake_queue(dev);
1527 }
1528
1529 static int
1530 rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
1531 {
1532 struct rtl8169_private *tp = netdev_priv(dev);
1533 void *ioaddr = tp->mmio_addr;
1534 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1535 u32 len = skb->len;
1536
1537 if (unlikely(skb->len < ETH_ZLEN)) {
1538 skb = skb_padto(skb, ETH_ZLEN);
1539 if (!skb)
1540 goto err_update_stats;
1541 len = ETH_ZLEN;
1542 }
1543
1544 if (!(le32_to_cpu(tp->TxDescArray[entry].status) & OWNbit)) {
1545 dma_addr_t mapping;
1546 u32 status;
1547
1548 mapping = pci_map_single(tp->pci_dev, skb->data, len,
1549 PCI_DMA_TODEVICE);
1550
1551 tp->Tx_skbuff[entry] = skb;
1552 tp->TxDescArray[entry].addr = cpu_to_le64(mapping);
1553
1554 /* anti gcc 2.95.3 bugware */
1555 status = OWNbit | FSbit | LSbit | len |
1556 (EORbit * !((entry + 1) % NUM_TX_DESC));
1557 tp->TxDescArray[entry].status = cpu_to_le32(status);
1558
1559 RTL_W8(TxPoll, 0x40); //set polling bit
1560
1561 dev->trans_start = jiffies;
1562
1563 tp->cur_tx++;
1564 smp_wmb();
1565 } else
1566 goto err_drop;
1567
1568 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx) {
1569 u32 dirty = tp->dirty_tx;
1570
1571 netif_stop_queue(dev);
1572 smp_rmb();
1573 if (dirty != tp->dirty_tx)
1574 netif_wake_queue(dev);
1575 }
1576
1577 out:
1578 return 0;
1579
1580 err_drop:
1581 dev_kfree_skb(skb);
1582 err_update_stats:
1583 tp->stats.tx_dropped++;
1584 goto out;
1585 }
1586
1587 static void
1588 rtl8169_tx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
1589 void *ioaddr)
1590 {
1591 unsigned int dirty_tx, tx_left;
1592
1593 assert(dev != NULL);
1594 assert(tp != NULL);
1595 assert(ioaddr != NULL);
1596
1597 dirty_tx = tp->dirty_tx;
1598 smp_rmb();
1599 tx_left = tp->cur_tx - dirty_tx;
1600
1601 while (tx_left > 0) {
1602 unsigned int entry = dirty_tx % NUM_TX_DESC;
1603 struct sk_buff *skb = tp->Tx_skbuff[entry];
1604 u32 status;
1605
1606 rmb();
1607 status = le32_to_cpu(tp->TxDescArray[entry].status);
1608 if (status & OWNbit)
1609 break;
1610
1611 /* FIXME: is it really accurate for TxErr ? */
1612 tp->stats.tx_bytes += skb->len >= ETH_ZLEN ?
1613 skb->len : ETH_ZLEN;
1614 tp->stats.tx_packets++;
1615 rtl8169_unmap_tx_skb(tp->pci_dev, tp->Tx_skbuff + entry,
1616 tp->TxDescArray + entry);
1617 dev_kfree_skb_irq(skb);
1618 tp->Tx_skbuff[entry] = NULL;
1619 dirty_tx++;
1620 tx_left--;
1621 }
1622
1623 if (tp->dirty_tx != dirty_tx) {
1624 tp->dirty_tx = dirty_tx;
1625 smp_wmb();
1626 if (netif_queue_stopped(dev))
1627 netif_wake_queue(dev);
1628 }
1629 }
1630
1631 static inline int rtl8169_try_rx_copy(struct sk_buff **sk_buff, int pkt_size,
1632 struct RxDesc *desc,
1633 struct net_device *dev)
1634 {
1635 int ret = -1;
1636
1637 if (pkt_size < rx_copybreak) {
1638 struct sk_buff *skb;
1639
1640 skb = dev_alloc_skb(pkt_size + 2);
1641 if (skb) {
1642 skb->dev = dev;
1643 skb_reserve(skb, 2);
1644 eth_copy_and_sum(skb, sk_buff[0]->tail, pkt_size, 0);
1645 *sk_buff = skb;
1646 rtl8169_return_to_asic(desc);
1647 ret = 0;
1648 }
1649 }
1650 return ret;
1651 }
1652
1653 static int
1654 rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
1655 void *ioaddr)
1656 {
1657 unsigned int cur_rx, rx_left, count;
1658 int delta;
1659
1660 assert(dev != NULL);
1661 assert(tp != NULL);
1662 assert(ioaddr != NULL);
1663
1664 cur_rx = tp->cur_rx;
1665 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
1666 rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota);
1667
1668 while (rx_left > 0) {
1669 unsigned int entry = cur_rx % NUM_RX_DESC;
1670 u32 status;
1671
1672 rmb();
1673 status = le32_to_cpu(tp->RxDescArray[entry].status);
1674
1675 if (status & OWNbit)
1676 break;
1677 if (status & RxRES) {
1678 printk(KERN_INFO "%s: Rx ERROR!!!\n", dev->name);
1679 tp->stats.rx_errors++;
1680 if (status & (RxRWT | RxRUNT))
1681 tp->stats.rx_length_errors++;
1682 if (status & RxCRC)
1683 tp->stats.rx_crc_errors++;
1684 } else {
1685 struct RxDesc *desc = tp->RxDescArray + entry;
1686 struct sk_buff *skb = tp->Rx_skbuff[entry];
1687 int pkt_size = (status & 0x00001FFF) - 4;
1688 void (*pci_action)(struct pci_dev *, dma_addr_t,
1689 size_t, int) = pci_dma_sync_single_for_device;
1690
1691
1692 pci_dma_sync_single_for_cpu(tp->pci_dev,
1693 le64_to_cpu(desc->addr), RX_BUF_SIZE,
1694 PCI_DMA_FROMDEVICE);
1695
1696 if (rtl8169_try_rx_copy(&skb, pkt_size, desc, dev)) {
1697 pci_action = pci_unmap_single;
1698 tp->Rx_skbuff[entry] = NULL;
1699 }
1700
1701 pci_action(tp->pci_dev, le64_to_cpu(desc->addr),
1702 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1703
1704 skb_put(skb, pkt_size);
1705 skb->protocol = eth_type_trans(skb, dev);
1706 rtl8169_rx_skb(skb);
1707
1708 dev->last_rx = jiffies;
1709 tp->stats.rx_bytes += pkt_size;
1710 tp->stats.rx_packets++;
1711 }
1712
1713 cur_rx++;
1714 rx_left--;
1715 }
1716
1717 count = cur_rx - tp->cur_rx;
1718 tp->cur_rx = cur_rx;
1719
1720 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
1721 if (delta < 0) {
1722 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
1723 delta = 0;
1724 }
1725 tp->dirty_rx += delta;
1726
1727 /*
1728 * FIXME: until there is periodic timer to try and refill the ring,
1729 * a temporary shortage may definitely kill the Rx process.
1730 * - disable the asic to try and avoid an overflow and kick it again
1731 * after refill ?
1732 * - how do others driver handle this condition (Uh oh...).
1733 */
1734 if (tp->dirty_rx + NUM_RX_DESC == tp->cur_rx)
1735 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
1736
1737 return count;
1738 }
1739
1740 /* The interrupt handler does all of the Rx thread work and cleans up after the Tx thread. */
1741 static irqreturn_t
1742 rtl8169_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
1743 {
1744 struct net_device *dev = (struct net_device *) dev_instance;
1745 struct rtl8169_private *tp = netdev_priv(dev);
1746 int boguscnt = max_interrupt_work;
1747 void *ioaddr = tp->mmio_addr;
1748 int status = 0;
1749 int handled = 0;
1750
1751 do {
1752 status = RTL_R16(IntrStatus);
1753
1754 /* hotplug/major error/no more work/shared irq */
1755 if ((status == 0xFFFF) || !status)
1756 break;
1757
1758 handled = 1;
1759
1760 status &= tp->intr_mask;
1761 RTL_W16(IntrStatus,
1762 (status & RxFIFOOver) ? (status | RxOverflow) : status);
1763
1764 if (!(status & rtl8169_intr_mask))
1765 break;
1766
1767 if (unlikely(status & SYSErr)) {
1768 printk(KERN_ERR PFX "%s: PCI error (status: 0x%04x)."
1769 " Device disabled.\n", dev->name, status);
1770 RTL_W8(ChipCmd, 0x00);
1771 RTL_W16(IntrMask, 0x0000);
1772 RTL_R16(IntrMask);
1773 break;
1774 }
1775
1776 if (status & LinkChg)
1777 rtl8169_check_link_status(dev, tp, ioaddr);
1778
1779 #ifdef CONFIG_R8169_NAPI
1780 RTL_W16(IntrMask, rtl8169_intr_mask & ~rtl8169_napi_event);
1781 tp->intr_mask = ~rtl8169_napi_event;
1782
1783 if (likely(netif_rx_schedule_prep(dev)))
1784 __netif_rx_schedule(dev);
1785 else {
1786 printk(KERN_INFO "%s: interrupt %x taken in poll\n",
1787 dev->name, status);
1788 }
1789 break;
1790 #else
1791 // Rx interrupt
1792 if (status & (RxOK | RxOverflow | RxFIFOOver)) {
1793 rtl8169_rx_interrupt(dev, tp, ioaddr);
1794 }
1795 // Tx interrupt
1796 if (status & (TxOK | TxErr))
1797 rtl8169_tx_interrupt(dev, tp, ioaddr);
1798 #endif
1799
1800 boguscnt--;
1801 } while (boguscnt > 0);
1802
1803 if (boguscnt <= 0) {
1804 printk(KERN_WARNING "%s: Too much work at interrupt!\n",
1805 dev->name);
1806 /* Clear all interrupt sources. */
1807 RTL_W16(IntrStatus, 0xffff);
1808 }
1809 return IRQ_RETVAL(handled);
1810 }
1811
1812 #ifdef CONFIG_R8169_NAPI
1813 static int rtl8169_poll(struct net_device *dev, int *budget)
1814 {
1815 unsigned int work_done, work_to_do = min(*budget, dev->quota);
1816 struct rtl8169_private *tp = netdev_priv(dev);
1817 void *ioaddr = tp->mmio_addr;
1818
1819 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr);
1820 rtl8169_tx_interrupt(dev, tp, ioaddr);
1821
1822 *budget -= work_done;
1823 dev->quota -= work_done;
1824
1825 if ((work_done < work_to_do) || !netif_running(dev)) {
1826 netif_rx_complete(dev);
1827 tp->intr_mask = 0xffff;
1828 /*
1829 * 20040426: the barrier is not strictly required but the
1830 * behavior of the irq handler could be less predictable
1831 * without it. Btw, the lack of flush for the posted pci
1832 * write is safe - FR
1833 */
1834 smp_wmb();
1835 RTL_W16(IntrMask, rtl8169_intr_mask);
1836 }
1837
1838 return (work_done >= work_to_do);
1839 }
1840 #endif
1841
1842 static int
1843 rtl8169_close(struct net_device *dev)
1844 {
1845 struct rtl8169_private *tp = netdev_priv(dev);
1846 struct pci_dev *pdev = tp->pci_dev;
1847 void *ioaddr = tp->mmio_addr;
1848
1849 netif_stop_queue(dev);
1850
1851 rtl8169_delete_timer(dev);
1852
1853 spin_lock_irq(&tp->lock);
1854
1855 /* Stop the chip's Tx and Rx DMA processes. */
1856 RTL_W8(ChipCmd, 0x00);
1857
1858 /* Disable interrupts by clearing the interrupt mask. */
1859 RTL_W16(IntrMask, 0x0000);
1860
1861 /* Update the error counts. */
1862 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
1863 RTL_W32(RxMissed, 0);
1864
1865 spin_unlock_irq(&tp->lock);
1866
1867 synchronize_irq(dev->irq);
1868 free_irq(dev->irq, dev);
1869
1870 rtl8169_tx_clear(tp);
1871
1872 rtl8169_rx_clear(tp);
1873
1874 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1875 tp->RxPhyAddr);
1876 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1877 tp->TxPhyAddr);
1878 tp->TxDescArray = NULL;
1879 tp->RxDescArray = NULL;
1880
1881 return 0;
1882 }
1883
1884 static void
1885 rtl8169_set_rx_mode(struct net_device *dev)
1886 {
1887 struct rtl8169_private *tp = netdev_priv(dev);
1888 void *ioaddr = tp->mmio_addr;
1889 unsigned long flags;
1890 u32 mc_filter[2]; /* Multicast hash filter */
1891 int i, rx_mode;
1892 u32 tmp = 0;
1893
1894 if (dev->flags & IFF_PROMISC) {
1895 /* Unconditionally log net taps. */
1896 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
1897 dev->name);
1898 rx_mode =
1899 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
1900 AcceptAllPhys;
1901 mc_filter[1] = mc_filter[0] = 0xffffffff;
1902 } else if ((dev->mc_count > multicast_filter_limit)
1903 || (dev->flags & IFF_ALLMULTI)) {
1904 /* Too many to filter perfectly -- accept all multicasts. */
1905 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1906 mc_filter[1] = mc_filter[0] = 0xffffffff;
1907 } else {
1908 struct dev_mc_list *mclist;
1909 rx_mode = AcceptBroadcast | AcceptMyPhys;
1910 mc_filter[1] = mc_filter[0] = 0;
1911 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1912 i++, mclist = mclist->next) {
1913 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1914 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1915 rx_mode |= AcceptMulticast;
1916 }
1917 }
1918
1919 spin_lock_irqsave(&tp->lock, flags);
1920
1921 tmp = rtl8169_rx_config | rx_mode |
1922 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1923
1924 RTL_W32(RxConfig, tmp);
1925 RTL_W32(MAR0 + 0, mc_filter[0]);
1926 RTL_W32(MAR0 + 4, mc_filter[1]);
1927
1928 spin_unlock_irqrestore(&tp->lock, flags);
1929 }
1930
1931 /**
1932 * rtl8169_get_stats - Get rtl8169 read/write statistics
1933 * @dev: The Ethernet Device to get statistics for
1934 *
1935 * Get TX/RX statistics for rtl8169
1936 */
1937 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
1938 {
1939 struct rtl8169_private *tp = netdev_priv(dev);
1940 void *ioaddr = tp->mmio_addr;
1941 unsigned long flags;
1942
1943 if (netif_running(dev)) {
1944 spin_lock_irqsave(&tp->lock, flags);
1945 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
1946 RTL_W32(RxMissed, 0);
1947 spin_unlock_irqrestore(&tp->lock, flags);
1948 }
1949
1950 return &tp->stats;
1951 }
1952
1953 static struct pci_driver rtl8169_pci_driver = {
1954 .name = MODULENAME,
1955 .id_table = rtl8169_pci_tbl,
1956 .probe = rtl8169_init_one,
1957 .remove = __devexit_p(rtl8169_remove_one),
1958 #ifdef CONFIG_PM
1959 .suspend = rtl8169_suspend,
1960 .resume = rtl8169_resume,
1961 #endif
1962 };
1963
1964 static int __init
1965 rtl8169_init_module(void)
1966 {
1967 return pci_module_init(&rtl8169_pci_driver);
1968 }
1969
1970 static void __exit
1971 rtl8169_cleanup_module(void)
1972 {
1973 pci_unregister_driver(&rtl8169_pci_driver);
1974 }
1975
1976 module_init(rtl8169_init_module);
1977 module_exit(rtl8169_cleanup_module);
MOXA 2.6.9 from sdlinux-moxaart.tgz