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MOXA linux-2.6.x / linux-2.6.9-uc0 from sdlinux-moxaart.tgz
[linux-2.6.9-moxart.git] / drivers / net / sungem.c
blobc78811b0082e67f44c6606f0b9b0be95e062084d
1 /* $Id: sungem.c,v 1.44.2.22 2002/03/13 01:18:12 davem Exp $
2 * sungem.c: Sun GEM ethernet driver.
3 *
4 * Copyright (C) 2000, 2001, 2002, 2003 David S. Miller (davem@redhat.com)
5 *
6 * Support for Apple GMAC and assorted PHYs by
7 * Benjamin Herrenscmidt (benh@kernel.crashing.org)
8 *
9 * NAPI and NETPOLL support
10 * (C) 2004 by Eric Lemoine (eric.lemoine@gmail.com)
11 *
12 * TODO:
13 * - Get rid of all those nasty mdelay's and replace them
14 * with schedule_timeout.
15 * - Implement WOL
16 */
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/types.h>
21 #include <linux/fcntl.h>
22 #include <linux/interrupt.h>
23 #include <linux/ioport.h>
24 #include <linux/in.h>
25 #include <linux/slab.h>
26 #include <linux/string.h>
27 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/errno.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/mii.h>
35 #include <linux/ethtool.h>
36 #include <linux/crc32.h>
37 #include <linux/random.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40
41 #include <asm/system.h>
42 #include <asm/bitops.h>
43 #include <asm/io.h>
44 #include <asm/byteorder.h>
45 #include <asm/uaccess.h>
46 #include <asm/irq.h>
47
48 #ifdef __sparc__
49 #include <asm/idprom.h>
50 #include <asm/openprom.h>
51 #include <asm/oplib.h>
52 #include <asm/pbm.h>
53 #endif
54
55 #ifdef CONFIG_PPC_PMAC
56 #include <asm/pci-bridge.h>
57 #include <asm/prom.h>
58 #include <asm/machdep.h>
59 #include <asm/pmac_feature.h>
60 #endif
61
62 #include "sungem_phy.h"
63 #include "sungem.h"
64
65 /* Stripping FCS is causing problems, disabled for now */
66 #undef STRIP_FCS
67
68 #define DEFAULT_MSG (NETIF_MSG_DRV | \
69 NETIF_MSG_PROBE | \
70 NETIF_MSG_LINK)
71
72 #define ADVERTISE_MASK (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
73 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
74 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)
75
76 #define DRV_NAME "sungem"
77 #define DRV_VERSION "0.98"
78 #define DRV_RELDATE "8/24/03"
79 #define DRV_AUTHOR "David S. Miller (davem@redhat.com)"
80
81 static char version[] __devinitdata =
82 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
83
84 MODULE_AUTHOR(DRV_AUTHOR);
85 MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver");
86 MODULE_LICENSE("GPL");
87
88 #define GEM_MODULE_NAME "gem"
89 #define PFX GEM_MODULE_NAME ": "
90
91 static struct pci_device_id gem_pci_tbl[] = {
92 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_GEM,
93 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
94
95 /* These models only differ from the original GEM in
96 * that their tx/rx fifos are of a different size and
97 * they only support 10/100 speeds. -DaveM
98 *
99 * Apple's GMAC does support gigabit on machines with
100 * the BCM54xx PHYs. -BenH
101 */
102 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_RIO_GEM,
103 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
104 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC,
105 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
106 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMACP,
107 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
108 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC2,
109 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
110 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_GMAC,
111 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
112 {0, }
113 };
114
115 MODULE_DEVICE_TABLE(pci, gem_pci_tbl);
116
117 static u16 __phy_read(struct gem *gp, int phy_addr, int reg)
118 {
119 u32 cmd;
120 int limit = 10000;
121
122 cmd = (1 << 30);
123 cmd |= (2 << 28);
124 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
125 cmd |= (reg << 18) & MIF_FRAME_REGAD;
126 cmd |= (MIF_FRAME_TAMSB);
127 writel(cmd, gp->regs + MIF_FRAME);
128
129 while (limit--) {
130 cmd = readl(gp->regs + MIF_FRAME);
131 if (cmd & MIF_FRAME_TALSB)
132 break;
133
134 udelay(10);
135 }
136
137 if (!limit)
138 cmd = 0xffff;
139
140 return cmd & MIF_FRAME_DATA;
141 }
142
143 static inline int _phy_read(struct net_device *dev, int mii_id, int reg)
144 {
145 struct gem *gp = dev->priv;
146 return __phy_read(gp, mii_id, reg);
147 }
148
149 static inline u16 phy_read(struct gem *gp, int reg)
150 {
151 return __phy_read(gp, gp->mii_phy_addr, reg);
152 }
153
154 static void __phy_write(struct gem *gp, int phy_addr, int reg, u16 val)
155 {
156 u32 cmd;
157 int limit = 10000;
158
159 cmd = (1 << 30);
160 cmd |= (1 << 28);
161 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
162 cmd |= (reg << 18) & MIF_FRAME_REGAD;
163 cmd |= (MIF_FRAME_TAMSB);
164 cmd |= (val & MIF_FRAME_DATA);
165 writel(cmd, gp->regs + MIF_FRAME);
166
167 while (limit--) {
168 cmd = readl(gp->regs + MIF_FRAME);
169 if (cmd & MIF_FRAME_TALSB)
170 break;
171
172 udelay(10);
173 }
174 }
175
176 static inline void _phy_write(struct net_device *dev, int mii_id, int reg, int val)
177 {
178 struct gem *gp = dev->priv;
179 __phy_write(gp, mii_id, reg, val & 0xffff);
180 }
181
182 static inline void phy_write(struct gem *gp, int reg, u16 val)
183 {
184 __phy_write(gp, gp->mii_phy_addr, reg, val);
185 }
186
187 static inline void gem_enable_ints(struct gem *gp)
188 {
189 /* Enable all interrupts but TXDONE */
190 writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
191 }
192
193 static inline void gem_disable_ints(struct gem *gp)
194 {
195 /* Disable all interrupts, including TXDONE */
196 writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
197 }
198
199 static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits)
200 {
201 if (netif_msg_intr(gp))
202 printk(KERN_DEBUG "%s: mif interrupt\n", gp->dev->name);
203 }
204
205 static int gem_pcs_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
206 {
207 u32 pcs_istat = readl(gp->regs + PCS_ISTAT);
208 u32 pcs_miistat;
209
210 if (netif_msg_intr(gp))
211 printk(KERN_DEBUG "%s: pcs interrupt, pcs_istat: 0x%x\n",
212 gp->dev->name, pcs_istat);
213
214 if (!(pcs_istat & PCS_ISTAT_LSC)) {
215 printk(KERN_ERR "%s: PCS irq but no link status change???\n",
216 dev->name);
217 return 0;
218 }
219
220 /* The link status bit latches on zero, so you must
221 * read it twice in such a case to see a transition
222 * to the link being up.
223 */
224 pcs_miistat = readl(gp->regs + PCS_MIISTAT);
225 if (!(pcs_miistat & PCS_MIISTAT_LS))
226 pcs_miistat |=
227 (readl(gp->regs + PCS_MIISTAT) &
228 PCS_MIISTAT_LS);
229
230 if (pcs_miistat & PCS_MIISTAT_ANC) {
231 /* The remote-fault indication is only valid
232 * when autoneg has completed.
233 */
234 if (pcs_miistat & PCS_MIISTAT_RF)
235 printk(KERN_INFO "%s: PCS AutoNEG complete, "
236 "RemoteFault\n", dev->name);
237 else
238 printk(KERN_INFO "%s: PCS AutoNEG complete.\n",
239 dev->name);
240 }
241
242 if (pcs_miistat & PCS_MIISTAT_LS) {
243 printk(KERN_INFO "%s: PCS link is now up.\n",
244 dev->name);
245 netif_carrier_on(gp->dev);
246 } else {
247 printk(KERN_INFO "%s: PCS link is now down.\n",
248 dev->name);
249 netif_carrier_off(gp->dev);
250 /* If this happens and the link timer is not running,
251 * reset so we re-negotiate.
252 */
253 if (!timer_pending(&gp->link_timer))
254 return 1;
255 }
256
257 return 0;
258 }
259
260 static int gem_txmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
261 {
262 u32 txmac_stat = readl(gp->regs + MAC_TXSTAT);
263
264 if (netif_msg_intr(gp))
265 printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
266 gp->dev->name, txmac_stat);
267
268 /* Defer timer expiration is quite normal,
269 * don't even log the event.
270 */
271 if ((txmac_stat & MAC_TXSTAT_DTE) &&
272 !(txmac_stat & ~MAC_TXSTAT_DTE))
273 return 0;
274
275 if (txmac_stat & MAC_TXSTAT_URUN) {
276 printk(KERN_ERR "%s: TX MAC xmit underrun.\n",
277 dev->name);
278 gp->net_stats.tx_fifo_errors++;
279 }
280
281 if (txmac_stat & MAC_TXSTAT_MPE) {
282 printk(KERN_ERR "%s: TX MAC max packet size error.\n",
283 dev->name);
284 gp->net_stats.tx_errors++;
285 }
286
287 /* The rest are all cases of one of the 16-bit TX
288 * counters expiring.
289 */
290 if (txmac_stat & MAC_TXSTAT_NCE)
291 gp->net_stats.collisions += 0x10000;
292
293 if (txmac_stat & MAC_TXSTAT_ECE) {
294 gp->net_stats.tx_aborted_errors += 0x10000;
295 gp->net_stats.collisions += 0x10000;
296 }
297
298 if (txmac_stat & MAC_TXSTAT_LCE) {
299 gp->net_stats.tx_aborted_errors += 0x10000;
300 gp->net_stats.collisions += 0x10000;
301 }
302
303 /* We do not keep track of MAC_TXSTAT_FCE and
304 * MAC_TXSTAT_PCE events.
305 */
306 return 0;
307 }
308
309 /* When we get a RX fifo overflow, the RX unit in GEM is probably hung
310 * so we do the following.
311 *
312 * If any part of the reset goes wrong, we return 1 and that causes the
313 * whole chip to be reset.
314 */
315 static int gem_rxmac_reset(struct gem *gp)
316 {
317 struct net_device *dev = gp->dev;
318 int limit, i;
319 u64 desc_dma;
320 u32 val;
321
322 /* First, reset MAC RX. */
323 writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB,
324 gp->regs + MAC_RXCFG);
325 for (limit = 0; limit < 5000; limit++) {
326 if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB))
327 break;
328 udelay(10);
329 }
330 if (limit == 5000) {
331 printk(KERN_ERR "%s: RX MAC will not disable, resetting whole "
332 "chip.\n", dev->name);
333 return 1;
334 }
335
336 /* Second, disable RX DMA. */
337 writel(0, gp->regs + RXDMA_CFG);
338 for (limit = 0; limit < 5000; limit++) {
339 if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE))
340 break;
341 udelay(10);
342 }
343 if (limit == 5000) {
344 printk(KERN_ERR "%s: RX DMA will not disable, resetting whole "
345 "chip.\n", dev->name);
346 return 1;
347 }
348
349 udelay(5000);
350
351 /* Execute RX reset command. */
352 writel(gp->swrst_base | GREG_SWRST_RXRST,
353 gp->regs + GREG_SWRST);
354 for (limit = 0; limit < 5000; limit++) {
355 if (!(readl(gp->regs + GREG_SWRST) & GREG_SWRST_RXRST))
356 break;
357 udelay(10);
358 }
359 if (limit == 5000) {
360 printk(KERN_ERR "%s: RX reset command will not execute, resetting "
361 "whole chip.\n", dev->name);
362 return 1;
363 }
364
365 /* Refresh the RX ring. */
366 for (i = 0; i < RX_RING_SIZE; i++) {
367 struct gem_rxd *rxd = &gp->init_block->rxd[i];
368
369 if (gp->rx_skbs[i] == NULL) {
370 printk(KERN_ERR "%s: Parts of RX ring empty, resetting "
371 "whole chip.\n", dev->name);
372 return 1;
373 }
374
375 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
376 }
377 gp->rx_new = gp->rx_old = 0;
378
379 /* Now we must reprogram the rest of RX unit. */
380 desc_dma = (u64) gp->gblock_dvma;
381 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
382 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
383 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
384 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
385 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
386 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
387 writel(val, gp->regs + RXDMA_CFG);
388 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
389 writel(((5 & RXDMA_BLANK_IPKTS) |
390 ((8 << 12) & RXDMA_BLANK_ITIME)),
391 gp->regs + RXDMA_BLANK);
392 else
393 writel(((5 & RXDMA_BLANK_IPKTS) |
394 ((4 << 12) & RXDMA_BLANK_ITIME)),
395 gp->regs + RXDMA_BLANK);
396 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
397 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
398 writel(val, gp->regs + RXDMA_PTHRESH);
399 val = readl(gp->regs + RXDMA_CFG);
400 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
401 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
402 val = readl(gp->regs + MAC_RXCFG);
403 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
404
405 return 0;
406 }
407
408 static int gem_rxmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
409 {
410 u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT);
411 int ret = 0;
412
413 if (netif_msg_intr(gp))
414 printk(KERN_DEBUG "%s: rxmac interrupt, rxmac_stat: 0x%x\n",
415 gp->dev->name, rxmac_stat);
416
417 if (rxmac_stat & MAC_RXSTAT_OFLW) {
418 u32 smac = readl(gp->regs + MAC_SMACHINE);
419
420 printk(KERN_ERR "%s: RX MAC fifo overflow smac[%08x].\n",
421 dev->name, smac);
422 gp->net_stats.rx_over_errors++;
423 gp->net_stats.rx_fifo_errors++;
424
425 ret = gem_rxmac_reset(gp);
426 }
427
428 if (rxmac_stat & MAC_RXSTAT_ACE)
429 gp->net_stats.rx_frame_errors += 0x10000;
430
431 if (rxmac_stat & MAC_RXSTAT_CCE)
432 gp->net_stats.rx_crc_errors += 0x10000;
433
434 if (rxmac_stat & MAC_RXSTAT_LCE)
435 gp->net_stats.rx_length_errors += 0x10000;
436
437 /* We do not track MAC_RXSTAT_FCE and MAC_RXSTAT_VCE
438 * events.
439 */
440 return ret;
441 }
442
443 static int gem_mac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
444 {
445 u32 mac_cstat = readl(gp->regs + MAC_CSTAT);
446
447 if (netif_msg_intr(gp))
448 printk(KERN_DEBUG "%s: mac interrupt, mac_cstat: 0x%x\n",
449 gp->dev->name, mac_cstat);
450
451 /* This interrupt is just for pause frame and pause
452 * tracking. It is useful for diagnostics and debug
453 * but probably by default we will mask these events.
454 */
455 if (mac_cstat & MAC_CSTAT_PS)
456 gp->pause_entered++;
457
458 if (mac_cstat & MAC_CSTAT_PRCV)
459 gp->pause_last_time_recvd = (mac_cstat >> 16);
460
461 return 0;
462 }
463
464 static int gem_mif_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
465 {
466 u32 mif_status = readl(gp->regs + MIF_STATUS);
467 u32 reg_val, changed_bits;
468
469 reg_val = (mif_status & MIF_STATUS_DATA) >> 16;
470 changed_bits = (mif_status & MIF_STATUS_STAT);
471
472 gem_handle_mif_event(gp, reg_val, changed_bits);
473
474 return 0;
475 }
476
477 static int gem_pci_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
478 {
479 u32 pci_estat = readl(gp->regs + GREG_PCIESTAT);
480
481 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
482 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
483 printk(KERN_ERR "%s: PCI error [%04x] ",
484 dev->name, pci_estat);
485
486 if (pci_estat & GREG_PCIESTAT_BADACK)
487 printk("<No ACK64# during ABS64 cycle> ");
488 if (pci_estat & GREG_PCIESTAT_DTRTO)
489 printk("<Delayed transaction timeout> ");
490 if (pci_estat & GREG_PCIESTAT_OTHER)
491 printk("<other>");
492 printk("\n");
493 } else {
494 pci_estat |= GREG_PCIESTAT_OTHER;
495 printk(KERN_ERR "%s: PCI error\n", dev->name);
496 }
497
498 if (pci_estat & GREG_PCIESTAT_OTHER) {
499 u16 pci_cfg_stat;
500
501 /* Interrogate PCI config space for the
502 * true cause.
503 */
504 pci_read_config_word(gp->pdev, PCI_STATUS,
505 &pci_cfg_stat);
506 printk(KERN_ERR "%s: Read PCI cfg space status [%04x]\n",
507 dev->name, pci_cfg_stat);
508 if (pci_cfg_stat & PCI_STATUS_PARITY)
509 printk(KERN_ERR "%s: PCI parity error detected.\n",
510 dev->name);
511 if (pci_cfg_stat & PCI_STATUS_SIG_TARGET_ABORT)
512 printk(KERN_ERR "%s: PCI target abort.\n",
513 dev->name);
514 if (pci_cfg_stat & PCI_STATUS_REC_TARGET_ABORT)
515 printk(KERN_ERR "%s: PCI master acks target abort.\n",
516 dev->name);
517 if (pci_cfg_stat & PCI_STATUS_REC_MASTER_ABORT)
518 printk(KERN_ERR "%s: PCI master abort.\n",
519 dev->name);
520 if (pci_cfg_stat & PCI_STATUS_SIG_SYSTEM_ERROR)
521 printk(KERN_ERR "%s: PCI system error SERR#.\n",
522 dev->name);
523 if (pci_cfg_stat & PCI_STATUS_DETECTED_PARITY)
524 printk(KERN_ERR "%s: PCI parity error.\n",
525 dev->name);
526
527 /* Write the error bits back to clear them. */
528 pci_cfg_stat &= (PCI_STATUS_PARITY |
529 PCI_STATUS_SIG_TARGET_ABORT |
530 PCI_STATUS_REC_TARGET_ABORT |
531 PCI_STATUS_REC_MASTER_ABORT |
532 PCI_STATUS_SIG_SYSTEM_ERROR |
533 PCI_STATUS_DETECTED_PARITY);
534 pci_write_config_word(gp->pdev,
535 PCI_STATUS, pci_cfg_stat);
536 }
537
538 /* For all PCI errors, we should reset the chip. */
539 return 1;
540 }
541
542 /* All non-normal interrupt conditions get serviced here.
543 * Returns non-zero if we should just exit the interrupt
544 * handler right now (ie. if we reset the card which invalidates
545 * all of the other original irq status bits).
546 */
547 static int gem_abnormal_irq(struct net_device *dev, struct gem *gp, u32 gem_status)
548 {
549 if (gem_status & GREG_STAT_RXNOBUF) {
550 /* Frame arrived, no free RX buffers available. */
551 if (netif_msg_rx_err(gp))
552 printk(KERN_DEBUG "%s: no buffer for rx frame\n",
553 gp->dev->name);
554 gp->net_stats.rx_dropped++;
555 }
556
557 if (gem_status & GREG_STAT_RXTAGERR) {
558 /* corrupt RX tag framing */
559 if (netif_msg_rx_err(gp))
560 printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
561 gp->dev->name);
562 gp->net_stats.rx_errors++;
563
564 goto do_reset;
565 }
566
567 if (gem_status & GREG_STAT_PCS) {
568 if (gem_pcs_interrupt(dev, gp, gem_status))
569 goto do_reset;
570 }
571
572 if (gem_status & GREG_STAT_TXMAC) {
573 if (gem_txmac_interrupt(dev, gp, gem_status))
574 goto do_reset;
575 }
576
577 if (gem_status & GREG_STAT_RXMAC) {
578 if (gem_rxmac_interrupt(dev, gp, gem_status))
579 goto do_reset;
580 }
581
582 if (gem_status & GREG_STAT_MAC) {
583 if (gem_mac_interrupt(dev, gp, gem_status))
584 goto do_reset;
585 }
586
587 if (gem_status & GREG_STAT_MIF) {
588 if (gem_mif_interrupt(dev, gp, gem_status))
589 goto do_reset;
590 }
591
592 if (gem_status & GREG_STAT_PCIERR) {
593 if (gem_pci_interrupt(dev, gp, gem_status))
594 goto do_reset;
595 }
596
597 return 0;
598
599 do_reset:
600 gp->reset_task_pending = 2;
601 schedule_work(&gp->reset_task);
602
603 return 1;
604 }
605
606 static __inline__ void gem_tx(struct net_device *dev, struct gem *gp, u32 gem_status)
607 {
608 int entry, limit;
609
610 if (netif_msg_intr(gp))
611 printk(KERN_DEBUG "%s: tx interrupt, gem_status: 0x%x\n",
612 gp->dev->name, gem_status);
613
614 entry = gp->tx_old;
615 limit = ((gem_status & GREG_STAT_TXNR) >> GREG_STAT_TXNR_SHIFT);
616 while (entry != limit) {
617 struct sk_buff *skb;
618 struct gem_txd *txd;
619 dma_addr_t dma_addr;
620 u32 dma_len;
621 int frag;
622
623 if (netif_msg_tx_done(gp))
624 printk(KERN_DEBUG "%s: tx done, slot %d\n",
625 gp->dev->name, entry);
626 skb = gp->tx_skbs[entry];
627 if (skb_shinfo(skb)->nr_frags) {
628 int last = entry + skb_shinfo(skb)->nr_frags;
629 int walk = entry;
630 int incomplete = 0;
631
632 last &= (TX_RING_SIZE - 1);
633 for (;;) {
634 walk = NEXT_TX(walk);
635 if (walk == limit)
636 incomplete = 1;
637 if (walk == last)
638 break;
639 }
640 if (incomplete)
641 break;
642 }
643 gp->tx_skbs[entry] = NULL;
644 gp->net_stats.tx_bytes += skb->len;
645
646 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
647 txd = &gp->init_block->txd[entry];
648
649 dma_addr = le64_to_cpu(txd->buffer);
650 dma_len = le64_to_cpu(txd->control_word) & TXDCTRL_BUFSZ;
651
652 pci_unmap_page(gp->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
653 entry = NEXT_TX(entry);
654 }
655
656 gp->net_stats.tx_packets++;
657 dev_kfree_skb_irq(skb);
658 }
659 gp->tx_old = entry;
660
661 if (netif_queue_stopped(dev) &&
662 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
663 netif_wake_queue(dev);
664 }
665
666 static __inline__ void gem_post_rxds(struct gem *gp, int limit)
667 {
668 int cluster_start, curr, count, kick;
669
670 cluster_start = curr = (gp->rx_new & ~(4 - 1));
671 count = 0;
672 kick = -1;
673 wmb();
674 while (curr != limit) {
675 curr = NEXT_RX(curr);
676 if (++count == 4) {
677 struct gem_rxd *rxd =
678 &gp->init_block->rxd[cluster_start];
679 for (;;) {
680 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
681 rxd++;
682 cluster_start = NEXT_RX(cluster_start);
683 if (cluster_start == curr)
684 break;
685 }
686 kick = curr;
687 count = 0;
688 }
689 }
690 if (kick >= 0) {
691 mb();
692 writel(kick, gp->regs + RXDMA_KICK);
693 }
694 }
695
696 static int gem_rx(struct gem *gp, int work_to_do)
697 {
698 int entry, drops, work_done = 0;
699 u32 done;
700
701 if (netif_msg_rx_status(gp))
702 printk(KERN_DEBUG "%s: rx interrupt, done: %d, rx_new: %d\n",
703 gp->dev->name, readl(gp->regs + RXDMA_DONE), gp->rx_new);
704
705 entry = gp->rx_new;
706 drops = 0;
707 done = readl(gp->regs + RXDMA_DONE);
708 for (;;) {
709 struct gem_rxd *rxd = &gp->init_block->rxd[entry];
710 struct sk_buff *skb;
711 u64 status = cpu_to_le64(rxd->status_word);
712 dma_addr_t dma_addr;
713 int len;
714
715 if ((status & RXDCTRL_OWN) != 0)
716 break;
717
718 if (work_done >= RX_RING_SIZE || work_done >= work_to_do)
719 break;
720
721 /* When writing back RX descriptor, GEM writes status
722 * then buffer address, possibly in seperate transactions.
723 * If we don't wait for the chip to write both, we could
724 * post a new buffer to this descriptor then have GEM spam
725 * on the buffer address. We sync on the RX completion
726 * register to prevent this from happening.
727 */
728 if (entry == done) {
729 done = readl(gp->regs + RXDMA_DONE);
730 if (entry == done)
731 break;
732 }
733
734 /* We can now account for the work we're about to do */
735 work_done++;
736
737 skb = gp->rx_skbs[entry];
738
739 len = (status & RXDCTRL_BUFSZ) >> 16;
740 if ((len < ETH_ZLEN) || (status & RXDCTRL_BAD)) {
741 gp->net_stats.rx_errors++;
742 if (len < ETH_ZLEN)
743 gp->net_stats.rx_length_errors++;
744 if (len & RXDCTRL_BAD)
745 gp->net_stats.rx_crc_errors++;
746
747 /* We'll just return it to GEM. */
748 drop_it:
749 gp->net_stats.rx_dropped++;
750 goto next;
751 }
752
753 dma_addr = cpu_to_le64(rxd->buffer);
754 if (len > RX_COPY_THRESHOLD) {
755 struct sk_buff *new_skb;
756
757 new_skb = gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
758 if (new_skb == NULL) {
759 drops++;
760 goto drop_it;
761 }
762 pci_unmap_page(gp->pdev, dma_addr,
763 RX_BUF_ALLOC_SIZE(gp),
764 PCI_DMA_FROMDEVICE);
765 gp->rx_skbs[entry] = new_skb;
766 new_skb->dev = gp->dev;
767 skb_put(new_skb, (gp->rx_buf_sz + RX_OFFSET));
768 rxd->buffer = cpu_to_le64(pci_map_page(gp->pdev,
769 virt_to_page(new_skb->data),
770 offset_in_page(new_skb->data),
771 RX_BUF_ALLOC_SIZE(gp),
772 PCI_DMA_FROMDEVICE));
773 skb_reserve(new_skb, RX_OFFSET);
774
775 /* Trim the original skb for the netif. */
776 skb_trim(skb, len);
777 } else {
778 struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
779
780 if (copy_skb == NULL) {
781 drops++;
782 goto drop_it;
783 }
784
785 copy_skb->dev = gp->dev;
786 skb_reserve(copy_skb, 2);
787 skb_put(copy_skb, len);
788 pci_dma_sync_single_for_cpu(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
789 memcpy(copy_skb->data, skb->data, len);
790 pci_dma_sync_single_for_device(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
791
792 /* We'll reuse the original ring buffer. */
793 skb = copy_skb;
794 }
795
796 skb->csum = ntohs((status & RXDCTRL_TCPCSUM) ^ 0xffff);
797 skb->ip_summed = CHECKSUM_HW;
798 skb->protocol = eth_type_trans(skb, gp->dev);
799
800 netif_receive_skb(skb);
801
802 gp->net_stats.rx_packets++;
803 gp->net_stats.rx_bytes += len;
804 gp->dev->last_rx = jiffies;
805
806 next:
807 entry = NEXT_RX(entry);
808 }
809
810 gem_post_rxds(gp, entry);
811
812 gp->rx_new = entry;
813
814 if (drops)
815 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n",
816 gp->dev->name);
817
818 return work_done;
819 }
820
821 static int gem_poll(struct net_device *dev, int *budget)
822 {
823 struct gem *gp = dev->priv;
824 unsigned long flags;
825
826 spin_lock_irqsave(&gp->lock, flags);
827
828 do {
829 int work_to_do, work_done;
830
831 /* Handle anomalies */
832 if (gp->status & GREG_STAT_ABNORMAL) {
833 if (gem_abnormal_irq(dev, gp, gp->status))
834 break;
835 }
836
837 /* Run TX completion thread */
838 spin_lock(&gp->tx_lock);
839 gem_tx(dev, gp, gp->status);
840 spin_unlock(&gp->tx_lock);
841
842 spin_unlock_irqrestore(&gp->lock, flags);
843
844 /* Run RX thread. We don't use any locking here,
845 * code willing to do bad things - like cleaning the
846 * rx ring - must call netif_poll_disable(), which
847 * schedule_timeout()'s if polling is already disabled.
848 */
849 work_to_do = min(*budget, dev->quota);
850
851 work_done = gem_rx(gp, work_to_do);
852
853 *budget -= work_done;
854 dev->quota -= work_done;
855
856 if (work_done >= work_to_do)
857 return 1;
858
859 spin_lock_irqsave(&gp->lock, flags);
860
861 gp->status = readl(gp->regs + GREG_STAT);
862 } while (gp->status & GREG_STAT_NAPI);
863
864 __netif_rx_complete(dev);
865 gem_enable_ints(gp);
866
867 spin_unlock_irqrestore(&gp->lock, flags);
868 return 0;
869 }
870
871 static irqreturn_t gem_interrupt(int irq, void *dev_id, struct pt_regs *regs)
872 {
873 struct net_device *dev = dev_id;
874 struct gem *gp = dev->priv;
875 unsigned long flags;
876
877 /* Swallow interrupts when shutting the chip down */
878 if (!gp->hw_running)
879 return IRQ_HANDLED;
880
881 spin_lock_irqsave(&gp->lock, flags);
882
883 if (netif_rx_schedule_prep(dev)) {
884 u32 gem_status = readl(gp->regs + GREG_STAT);
885
886 if (gem_status == 0) {
887 spin_unlock_irqrestore(&gp->lock, flags);
888 return IRQ_NONE;
889 }
890 gp->status = gem_status;
891 gem_disable_ints(gp);
892 __netif_rx_schedule(dev);
893 }
894
895 spin_unlock_irqrestore(&gp->lock, flags);
896
897 /* If polling was disabled at the time we received that
898 * interrupt, we may return IRQ_HANDLED here while we
899 * should return IRQ_NONE. No big deal...
900 */
901 return IRQ_HANDLED;
902 }
903
904 #ifdef CONFIG_NET_POLL_CONTROLLER
905 static void gem_poll_controller(struct net_device *dev)
906 {
907 /* gem_interrupt is safe to reentrance so no need
908 * to disable_irq here.
909 */
910 gem_interrupt(dev->irq, dev, NULL);
911 }
912 #endif
913
914 static void gem_tx_timeout(struct net_device *dev)
915 {
916 struct gem *gp = dev->priv;
917
918 printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
919 if (!gp->hw_running) {
920 printk("%s: hrm.. hw not running !\n", dev->name);
921 return;
922 }
923 printk(KERN_ERR "%s: TX_STATE[%08x:%08x:%08x]\n",
924 dev->name,
925 readl(gp->regs + TXDMA_CFG),
926 readl(gp->regs + MAC_TXSTAT),
927 readl(gp->regs + MAC_TXCFG));
928 printk(KERN_ERR "%s: RX_STATE[%08x:%08x:%08x]\n",
929 dev->name,
930 readl(gp->regs + RXDMA_CFG),
931 readl(gp->regs + MAC_RXSTAT),
932 readl(gp->regs + MAC_RXCFG));
933
934 spin_lock_irq(&gp->lock);
935 spin_lock(&gp->tx_lock);
936
937 gp->reset_task_pending = 2;
938 schedule_work(&gp->reset_task);
939
940 spin_unlock(&gp->tx_lock);
941 spin_unlock_irq(&gp->lock);
942 }
943
944 static __inline__ int gem_intme(int entry)
945 {
946 /* Algorithm: IRQ every 1/2 of descriptors. */
947 if (!(entry & ((TX_RING_SIZE>>1)-1)))
948 return 1;
949
950 return 0;
951 }
952
953 static int gem_start_xmit(struct sk_buff *skb, struct net_device *dev)
954 {
955 struct gem *gp = dev->priv;
956 int entry;
957 u64 ctrl;
958 unsigned long flags;
959
960 ctrl = 0;
961 if (skb->ip_summed == CHECKSUM_HW) {
962 u64 csum_start_off, csum_stuff_off;
963
964 csum_start_off = (u64) (skb->h.raw - skb->data);
965 csum_stuff_off = (u64) ((skb->h.raw + skb->csum) - skb->data);
966
967 ctrl = (TXDCTRL_CENAB |
968 (csum_start_off << 15) |
969 (csum_stuff_off << 21));
970 }
971
972 local_irq_save(flags);
973 if (!spin_trylock(&gp->tx_lock)) {
974 /* Tell upper layer to requeue */
975 local_irq_restore(flags);
976 return NETDEV_TX_LOCKED;
977 }
978
979 /* This is a hard error, log it. */
980 if (TX_BUFFS_AVAIL(gp) <= (skb_shinfo(skb)->nr_frags + 1)) {
981 netif_stop_queue(dev);
982 spin_unlock_irqrestore(&gp->tx_lock, flags);
983 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
984 dev->name);
985 return NETDEV_TX_BUSY;
986 }
987
988 entry = gp->tx_new;
989 gp->tx_skbs[entry] = skb;
990
991 if (skb_shinfo(skb)->nr_frags == 0) {
992 struct gem_txd *txd = &gp->init_block->txd[entry];
993 dma_addr_t mapping;
994 u32 len;
995
996 len = skb->len;
997 mapping = pci_map_page(gp->pdev,
998 virt_to_page(skb->data),
999 offset_in_page(skb->data),
1000 len, PCI_DMA_TODEVICE);
1001 ctrl |= TXDCTRL_SOF | TXDCTRL_EOF | len;
1002 if (gem_intme(entry))
1003 ctrl |= TXDCTRL_INTME;
1004 txd->buffer = cpu_to_le64(mapping);
1005 wmb();
1006 txd->control_word = cpu_to_le64(ctrl);
1007 entry = NEXT_TX(entry);
1008 } else {
1009 struct gem_txd *txd;
1010 u32 first_len;
1011 u64 intme;
1012 dma_addr_t first_mapping;
1013 int frag, first_entry = entry;
1014
1015 intme = 0;
1016 if (gem_intme(entry))
1017 intme |= TXDCTRL_INTME;
1018
1019 /* We must give this initial chunk to the device last.
1020 * Otherwise we could race with the device.
1021 */
1022 first_len = skb_headlen(skb);
1023 first_mapping = pci_map_page(gp->pdev, virt_to_page(skb->data),
1024 offset_in_page(skb->data),
1025 first_len, PCI_DMA_TODEVICE);
1026 entry = NEXT_TX(entry);
1027
1028 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1029 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1030 u32 len;
1031 dma_addr_t mapping;
1032 u64 this_ctrl;
1033
1034 len = this_frag->size;
1035 mapping = pci_map_page(gp->pdev,
1036 this_frag->page,
1037 this_frag->page_offset,
1038 len, PCI_DMA_TODEVICE);
1039 this_ctrl = ctrl;
1040 if (frag == skb_shinfo(skb)->nr_frags - 1)
1041 this_ctrl |= TXDCTRL_EOF;
1042
1043 txd = &gp->init_block->txd[entry];
1044 txd->buffer = cpu_to_le64(mapping);
1045 wmb();
1046 txd->control_word = cpu_to_le64(this_ctrl | len);
1047
1048 if (gem_intme(entry))
1049 intme |= TXDCTRL_INTME;
1050
1051 entry = NEXT_TX(entry);
1052 }
1053 txd = &gp->init_block->txd[first_entry];
1054 txd->buffer = cpu_to_le64(first_mapping);
1055 wmb();
1056 txd->control_word =
1057 cpu_to_le64(ctrl | TXDCTRL_SOF | intme | first_len);
1058 }
1059
1060 gp->tx_new = entry;
1061 if (TX_BUFFS_AVAIL(gp) <= (MAX_SKB_FRAGS + 1))
1062 netif_stop_queue(dev);
1063
1064 if (netif_msg_tx_queued(gp))
1065 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
1066 dev->name, entry, skb->len);
1067 mb();
1068 writel(gp->tx_new, gp->regs + TXDMA_KICK);
1069 spin_unlock_irqrestore(&gp->tx_lock, flags);
1070
1071 dev->trans_start = jiffies;
1072
1073 return NETDEV_TX_OK;
1074 }
1075
1076 /* Jumbo-grams don't seem to work :-( */
1077 #define GEM_MIN_MTU 68
1078 #if 1
1079 #define GEM_MAX_MTU 1500
1080 #else
1081 #define GEM_MAX_MTU 9000
1082 #endif
1083
1084 static int gem_change_mtu(struct net_device *dev, int new_mtu)
1085 {
1086 struct gem *gp = dev->priv;
1087
1088 if (new_mtu < GEM_MIN_MTU || new_mtu > GEM_MAX_MTU)
1089 return -EINVAL;
1090
1091 if (!netif_running(dev) || !netif_device_present(dev)) {
1092 /* We'll just catch it later when the
1093 * device is up'd or resumed.
1094 */
1095 dev->mtu = new_mtu;
1096 return 0;
1097 }
1098
1099 spin_lock_irq(&gp->lock);
1100 spin_lock(&gp->tx_lock);
1101 dev->mtu = new_mtu;
1102 gp->reset_task_pending = 1;
1103 schedule_work(&gp->reset_task);
1104 spin_unlock(&gp->tx_lock);
1105 spin_unlock_irq(&gp->lock);
1106
1107 flush_scheduled_work();
1108
1109 return 0;
1110 }
1111
1112 #define STOP_TRIES 32
1113
1114 /* Must be invoked under gp->lock and gp->tx_lock. */
1115 static void gem_stop(struct gem *gp)
1116 {
1117 int limit;
1118 u32 val;
1119
1120 /* Make sure we won't get any more interrupts */
1121 writel(0xffffffff, gp->regs + GREG_IMASK);
1122
1123 /* Reset the chip */
1124 writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST,
1125 gp->regs + GREG_SWRST);
1126
1127 limit = STOP_TRIES;
1128
1129 do {
1130 udelay(20);
1131 val = readl(gp->regs + GREG_SWRST);
1132 if (limit-- <= 0)
1133 break;
1134 } while (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST));
1135
1136 if (limit <= 0)
1137 printk(KERN_ERR "%s: SW reset is ghetto.\n", gp->dev->name);
1138 }
1139
1140 /* Must be invoked under gp->lock and gp->tx_lock. */
1141 static void gem_start_dma(struct gem *gp)
1142 {
1143 unsigned long val;
1144
1145 /* We are ready to rock, turn everything on. */
1146 val = readl(gp->regs + TXDMA_CFG);
1147 writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1148 val = readl(gp->regs + RXDMA_CFG);
1149 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1150 val = readl(gp->regs + MAC_TXCFG);
1151 writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1152 val = readl(gp->regs + MAC_RXCFG);
1153 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1154
1155 (void) readl(gp->regs + MAC_RXCFG);
1156 udelay(100);
1157
1158 writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
1159
1160 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1161
1162 }
1163
1164
1165 /* Must be invoked under gp->lock and gp->tx_lock. */
1166 // XXX dbl check what that function should do when called on PCS PHY
1167 static void gem_begin_auto_negotiation(struct gem *gp, struct ethtool_cmd *ep)
1168 {
1169 u32 advertise, features;
1170 int autoneg;
1171 int speed;
1172 int duplex;
1173
1174 if (gp->phy_type != phy_mii_mdio0 &&
1175 gp->phy_type != phy_mii_mdio1)
1176 goto non_mii;
1177
1178 /* Setup advertise */
1179 if (found_mii_phy(gp))
1180 features = gp->phy_mii.def->features;
1181 else
1182 features = 0;
1183
1184 advertise = features & ADVERTISE_MASK;
1185 if (gp->phy_mii.advertising != 0)
1186 advertise &= gp->phy_mii.advertising;
1187
1188 autoneg = gp->want_autoneg;
1189 speed = gp->phy_mii.speed;
1190 duplex = gp->phy_mii.duplex;
1191
1192 /* Setup link parameters */
1193 if (!ep)
1194 goto start_aneg;
1195 if (ep->autoneg == AUTONEG_ENABLE) {
1196 advertise = ep->advertising;
1197 autoneg = 1;
1198 } else {
1199 autoneg = 0;
1200 speed = ep->speed;
1201 duplex = ep->duplex;
1202 }
1203
1204 start_aneg:
1205 /* Sanitize settings based on PHY capabilities */
1206 if ((features & SUPPORTED_Autoneg) == 0)
1207 autoneg = 0;
1208 if (speed == SPEED_1000 &&
1209 !(features & (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)))
1210 speed = SPEED_100;
1211 if (speed == SPEED_100 &&
1212 !(features & (SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full)))
1213 speed = SPEED_10;
1214 if (duplex == DUPLEX_FULL &&
1215 !(features & (SUPPORTED_1000baseT_Full |
1216 SUPPORTED_100baseT_Full |
1217 SUPPORTED_10baseT_Full)))
1218 duplex = DUPLEX_HALF;
1219 if (speed == 0)
1220 speed = SPEED_10;
1221
1222 /* If HW is down, we don't try to actually setup the PHY, we
1223 * just store the settings
1224 */
1225 if (!gp->hw_running) {
1226 gp->phy_mii.autoneg = gp->want_autoneg = autoneg;
1227 gp->phy_mii.speed = speed;
1228 gp->phy_mii.duplex = duplex;
1229 return;
1230 }
1231
1232 /* Configure PHY & start aneg */
1233 gp->want_autoneg = autoneg;
1234 if (autoneg) {
1235 if (found_mii_phy(gp))
1236 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, advertise);
1237 gp->lstate = link_aneg;
1238 } else {
1239 if (found_mii_phy(gp))
1240 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, speed, duplex);
1241 gp->lstate = link_force_ok;
1242 }
1243
1244 non_mii:
1245 gp->timer_ticks = 0;
1246 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1247 }
1248
1249 /* A link-up condition has occurred, initialize and enable the
1250 * rest of the chip.
1251 *
1252 * Must be invoked under gp->lock and gp->tx_lock.
1253 */
1254 static int gem_set_link_modes(struct gem *gp)
1255 {
1256 u32 val;
1257 int full_duplex, speed, pause;
1258
1259 full_duplex = 0;
1260 speed = SPEED_10;
1261 pause = 0;
1262
1263 if (found_mii_phy(gp)) {
1264 if (gp->phy_mii.def->ops->read_link(&gp->phy_mii))
1265 return 1;
1266 full_duplex = (gp->phy_mii.duplex == DUPLEX_FULL);
1267 speed = gp->phy_mii.speed;
1268 pause = gp->phy_mii.pause;
1269 } else if (gp->phy_type == phy_serialink ||
1270 gp->phy_type == phy_serdes) {
1271 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1272
1273 if (pcs_lpa & PCS_MIIADV_FD)
1274 full_duplex = 1;
1275 speed = SPEED_1000;
1276 }
1277
1278 if (netif_msg_link(gp))
1279 printk(KERN_INFO "%s: Link is up at %d Mbps, %s-duplex.\n",
1280 gp->dev->name, speed, (full_duplex ? "full" : "half"));
1281
1282 val = (MAC_TXCFG_EIPG0 | MAC_TXCFG_NGU);
1283 if (full_duplex) {
1284 val |= (MAC_TXCFG_ICS | MAC_TXCFG_ICOLL);
1285 } else {
1286 /* MAC_TXCFG_NBO must be zero. */
1287 }
1288 writel(val, gp->regs + MAC_TXCFG);
1289
1290 val = (MAC_XIFCFG_OE | MAC_XIFCFG_LLED);
1291 if (!full_duplex &&
1292 (gp->phy_type == phy_mii_mdio0 ||
1293 gp->phy_type == phy_mii_mdio1)) {
1294 val |= MAC_XIFCFG_DISE;
1295 } else if (full_duplex) {
1296 val |= MAC_XIFCFG_FLED;
1297 }
1298
1299 if (speed == SPEED_1000)
1300 val |= (MAC_XIFCFG_GMII);
1301
1302 writel(val, gp->regs + MAC_XIFCFG);
1303
1304 /* If gigabit and half-duplex, enable carrier extension
1305 * mode. Else, disable it.
1306 */
1307 if (speed == SPEED_1000 && !full_duplex) {
1308 val = readl(gp->regs + MAC_TXCFG);
1309 writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1310
1311 val = readl(gp->regs + MAC_RXCFG);
1312 writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1313 } else {
1314 val = readl(gp->regs + MAC_TXCFG);
1315 writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1316
1317 val = readl(gp->regs + MAC_RXCFG);
1318 writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1319 }
1320
1321 if (gp->phy_type == phy_serialink ||
1322 gp->phy_type == phy_serdes) {
1323 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1324
1325 if (pcs_lpa & (PCS_MIIADV_SP | PCS_MIIADV_AP))
1326 pause = 1;
1327 }
1328
1329 if (netif_msg_link(gp)) {
1330 if (pause) {
1331 printk(KERN_INFO "%s: Pause is enabled "
1332 "(rxfifo: %d off: %d on: %d)\n",
1333 gp->dev->name,
1334 gp->rx_fifo_sz,
1335 gp->rx_pause_off,
1336 gp->rx_pause_on);
1337 } else {
1338 printk(KERN_INFO "%s: Pause is disabled\n",
1339 gp->dev->name);
1340 }
1341 }
1342
1343 if (!full_duplex)
1344 writel(512, gp->regs + MAC_STIME);
1345 else
1346 writel(64, gp->regs + MAC_STIME);
1347 val = readl(gp->regs + MAC_MCCFG);
1348 if (pause)
1349 val |= (MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1350 else
1351 val &= ~(MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1352 writel(val, gp->regs + MAC_MCCFG);
1353
1354 gem_start_dma(gp);
1355
1356 return 0;
1357 }
1358
1359 /* Must be invoked under gp->lock and gp->tx_lock. */
1360 static int gem_mdio_link_not_up(struct gem *gp)
1361 {
1362 switch (gp->lstate) {
1363 case link_force_ret:
1364 if (netif_msg_link(gp))
1365 printk(KERN_INFO "%s: Autoneg failed again, keeping"
1366 " forced mode\n", gp->dev->name);
1367 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii,
1368 gp->last_forced_speed, DUPLEX_HALF);
1369 gp->timer_ticks = 5;
1370 gp->lstate = link_force_ok;
1371 return 0;
1372 case link_aneg:
1373 /* We try forced modes after a failed aneg only on PHYs that don't
1374 * have "magic_aneg" bit set, which means they internally do the
1375 * while forced-mode thingy. On these, we just restart aneg
1376 */
1377 if (gp->phy_mii.def->magic_aneg)
1378 return 1;
1379 if (netif_msg_link(gp))
1380 printk(KERN_INFO "%s: switching to forced 100bt\n",
1381 gp->dev->name);
1382 /* Try forced modes. */
1383 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_100,
1384 DUPLEX_HALF);
1385 gp->timer_ticks = 5;
1386 gp->lstate = link_force_try;
1387 return 0;
1388 case link_force_try:
1389 /* Downgrade from 100 to 10 Mbps if necessary.
1390 * If already at 10Mbps, warn user about the
1391 * situation every 10 ticks.
1392 */
1393 if (gp->phy_mii.speed == SPEED_100) {
1394 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_10,
1395 DUPLEX_HALF);
1396 gp->timer_ticks = 5;
1397 if (netif_msg_link(gp))
1398 printk(KERN_INFO "%s: switching to forced 10bt\n",
1399 gp->dev->name);
1400 return 0;
1401 } else
1402 return 1;
1403 default:
1404 return 0;
1405 }
1406 }
1407
1408 static void gem_init_rings(struct gem *);
1409 static void gem_init_hw(struct gem *, int);
1410
1411 static void gem_reset_task(void *data)
1412 {
1413 struct gem *gp = (struct gem *) data;
1414
1415 netif_poll_disable(gp->dev);
1416 spin_lock_irq(&gp->lock);
1417 spin_lock(&gp->tx_lock);
1418
1419 if (gp->hw_running && gp->opened) {
1420 netif_stop_queue(gp->dev);
1421
1422 /* Reset the chip & rings */
1423 gem_stop(gp);
1424 gem_init_rings(gp);
1425
1426 gem_init_hw(gp,
1427 (gp->reset_task_pending == 2));
1428
1429 netif_wake_queue(gp->dev);
1430 }
1431 gp->reset_task_pending = 0;
1432
1433 spin_unlock(&gp->tx_lock);
1434 spin_unlock_irq(&gp->lock);
1435 netif_poll_enable(gp->dev);
1436 }
1437
1438 static void gem_link_timer(unsigned long data)
1439 {
1440 struct gem *gp = (struct gem *) data;
1441 int restart_aneg = 0;
1442
1443 if (!gp->hw_running)
1444 return;
1445
1446 spin_lock_irq(&gp->lock);
1447 spin_lock(&gp->tx_lock);
1448
1449 /* If the link of task is still pending, we just
1450 * reschedule the link timer
1451 */
1452 if (gp->reset_task_pending)
1453 goto restart;
1454
1455 if (gp->phy_type == phy_serialink ||
1456 gp->phy_type == phy_serdes) {
1457 u32 val = readl(gp->regs + PCS_MIISTAT);
1458
1459 if (!(val & PCS_MIISTAT_LS))
1460 val = readl(gp->regs + PCS_MIISTAT);
1461
1462 if ((val & PCS_MIISTAT_LS) != 0) {
1463 gp->lstate = link_up;
1464 netif_carrier_on(gp->dev);
1465 if (gp->opened)
1466 (void)gem_set_link_modes(gp);
1467 }
1468 goto restart;
1469 }
1470 if (found_mii_phy(gp) && gp->phy_mii.def->ops->poll_link(&gp->phy_mii)) {
1471 /* Ok, here we got a link. If we had it due to a forced
1472 * fallback, and we were configured for autoneg, we do
1473 * retry a short autoneg pass. If you know your hub is
1474 * broken, use ethtool ;)
1475 */
1476 if (gp->lstate == link_force_try && gp->want_autoneg) {
1477 gp->lstate = link_force_ret;
1478 gp->last_forced_speed = gp->phy_mii.speed;
1479 gp->timer_ticks = 5;
1480 if (netif_msg_link(gp))
1481 printk(KERN_INFO "%s: Got link after fallback, retrying"
1482 " autoneg once...\n", gp->dev->name);
1483 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, gp->phy_mii.advertising);
1484 } else if (gp->lstate != link_up) {
1485 gp->lstate = link_up;
1486 netif_carrier_on(gp->dev);
1487 if (gp->opened && gem_set_link_modes(gp))
1488 restart_aneg = 1;
1489 }
1490 } else {
1491 /* If the link was previously up, we restart the
1492 * whole process
1493 */
1494 if (gp->lstate == link_up) {
1495 gp->lstate = link_down;
1496 if (netif_msg_link(gp))
1497 printk(KERN_INFO "%s: Link down\n",
1498 gp->dev->name);
1499 netif_carrier_off(gp->dev);
1500 gp->reset_task_pending = 2;
1501 schedule_work(&gp->reset_task);
1502 restart_aneg = 1;
1503 } else if (++gp->timer_ticks > 10) {
1504 if (found_mii_phy(gp))
1505 restart_aneg = gem_mdio_link_not_up(gp);
1506 else
1507 restart_aneg = 1;
1508 }
1509 }
1510 if (restart_aneg) {
1511 gem_begin_auto_negotiation(gp, NULL);
1512 goto out_unlock;
1513 }
1514 restart:
1515 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1516 out_unlock:
1517 spin_unlock(&gp->tx_lock);
1518 spin_unlock_irq(&gp->lock);
1519 }
1520
1521 /* Must be invoked under gp->lock and gp->tx_lock. */
1522 static void gem_clean_rings(struct gem *gp)
1523 {
1524 struct gem_init_block *gb = gp->init_block;
1525 struct sk_buff *skb;
1526 int i;
1527 dma_addr_t dma_addr;
1528
1529 for (i = 0; i < RX_RING_SIZE; i++) {
1530 struct gem_rxd *rxd;
1531
1532 rxd = &gb->rxd[i];
1533 if (gp->rx_skbs[i] != NULL) {
1534 skb = gp->rx_skbs[i];
1535 dma_addr = le64_to_cpu(rxd->buffer);
1536 pci_unmap_page(gp->pdev, dma_addr,
1537 RX_BUF_ALLOC_SIZE(gp),
1538 PCI_DMA_FROMDEVICE);
1539 dev_kfree_skb_any(skb);
1540 gp->rx_skbs[i] = NULL;
1541 }
1542 rxd->status_word = 0;
1543 wmb();
1544 rxd->buffer = 0;
1545 }
1546
1547 for (i = 0; i < TX_RING_SIZE; i++) {
1548 if (gp->tx_skbs[i] != NULL) {
1549 struct gem_txd *txd;
1550 int frag;
1551
1552 skb = gp->tx_skbs[i];
1553 gp->tx_skbs[i] = NULL;
1554
1555 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1556 int ent = i & (TX_RING_SIZE - 1);
1557
1558 txd = &gb->txd[ent];
1559 dma_addr = le64_to_cpu(txd->buffer);
1560 pci_unmap_page(gp->pdev, dma_addr,
1561 le64_to_cpu(txd->control_word) &
1562 TXDCTRL_BUFSZ, PCI_DMA_TODEVICE);
1563
1564 if (frag != skb_shinfo(skb)->nr_frags)
1565 i++;
1566 }
1567 dev_kfree_skb_any(skb);
1568 }
1569 }
1570 }
1571
1572 /* Must be invoked under gp->lock and gp->tx_lock. */
1573 static void gem_init_rings(struct gem *gp)
1574 {
1575 struct gem_init_block *gb = gp->init_block;
1576 struct net_device *dev = gp->dev;
1577 int i;
1578 dma_addr_t dma_addr;
1579
1580 gp->rx_new = gp->rx_old = gp->tx_new = gp->tx_old = 0;
1581
1582 gem_clean_rings(gp);
1583
1584 gp->rx_buf_sz = max(dev->mtu + ETH_HLEN + VLAN_HLEN,
1585 (unsigned)VLAN_ETH_FRAME_LEN);
1586
1587 for (i = 0; i < RX_RING_SIZE; i++) {
1588 struct sk_buff *skb;
1589 struct gem_rxd *rxd = &gb->rxd[i];
1590
1591 skb = gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
1592 if (!skb) {
1593 rxd->buffer = 0;
1594 rxd->status_word = 0;
1595 continue;
1596 }
1597
1598 gp->rx_skbs[i] = skb;
1599 skb->dev = dev;
1600 skb_put(skb, (gp->rx_buf_sz + RX_OFFSET));
1601 dma_addr = pci_map_page(gp->pdev,
1602 virt_to_page(skb->data),
1603 offset_in_page(skb->data),
1604 RX_BUF_ALLOC_SIZE(gp),
1605 PCI_DMA_FROMDEVICE);
1606 rxd->buffer = cpu_to_le64(dma_addr);
1607 wmb();
1608 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
1609 skb_reserve(skb, RX_OFFSET);
1610 }
1611
1612 for (i = 0; i < TX_RING_SIZE; i++) {
1613 struct gem_txd *txd = &gb->txd[i];
1614
1615 txd->control_word = 0;
1616 wmb();
1617 txd->buffer = 0;
1618 }
1619 wmb();
1620 }
1621
1622 /* Must be invoked under gp->lock and gp->tx_lock. */
1623 static void gem_init_phy(struct gem *gp)
1624 {
1625 u32 mifcfg;
1626
1627 /* Revert MIF CFG setting done on stop_phy */
1628 mifcfg = readl(gp->regs + MIF_CFG);
1629 mifcfg &= ~MIF_CFG_BBMODE;
1630 writel(mifcfg, gp->regs + MIF_CFG);
1631
1632 #ifdef CONFIG_PPC_PMAC
1633 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
1634 int i, j;
1635
1636 /* Those delay sucks, the HW seem to love them though, I'll
1637 * serisouly consider breaking some locks here to be able
1638 * to schedule instead
1639 */
1640 pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0);
1641 for (j = 0; j < 3; j++) {
1642 /* Some PHYs used by apple have problem getting back to us,
1643 * we _know_ it's actually at addr 0 or 1, that's a hack, but
1644 * it helps to do that reset now. I suspect some motherboards
1645 * don't wire the PHY reset line properly, thus the PHY doesn't
1646 * come back with the above pmac_call_feature.
1647 */
1648 gp->mii_phy_addr = 0;
1649 phy_write(gp, MII_BMCR, BMCR_RESET);
1650 gp->mii_phy_addr = 1;
1651 phy_write(gp, MII_BMCR, BMCR_RESET);
1652 /* We should probably break some locks here and schedule... */
1653 mdelay(10);
1654
1655 /* On K2, we only probe the internal PHY at address 1, other
1656 * addresses tend to return garbage.
1657 */
1658 if (gp->pdev->device == PCI_DEVICE_ID_APPLE_K2_GMAC)
1659 break;
1660
1661 for (i = 0; i < 32; i++) {
1662 gp->mii_phy_addr = i;
1663 if (phy_read(gp, MII_BMCR) != 0xffff)
1664 break;
1665 }
1666 if (i == 32) {
1667 printk(KERN_WARNING "%s: GMAC PHY not responding !\n",
1668 gp->dev->name);
1669 gp->mii_phy_addr = 0;
1670 } else
1671 break;
1672 }
1673 }
1674 #endif /* CONFIG_PPC_PMAC */
1675
1676 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
1677 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
1678 u32 val;
1679
1680 /* Init datapath mode register. */
1681 if (gp->phy_type == phy_mii_mdio0 ||
1682 gp->phy_type == phy_mii_mdio1) {
1683 val = PCS_DMODE_MGM;
1684 } else if (gp->phy_type == phy_serialink) {
1685 val = PCS_DMODE_SM | PCS_DMODE_GMOE;
1686 } else {
1687 val = PCS_DMODE_ESM;
1688 }
1689
1690 writel(val, gp->regs + PCS_DMODE);
1691 }
1692
1693 if (gp->phy_type == phy_mii_mdio0 ||
1694 gp->phy_type == phy_mii_mdio1) {
1695 // XXX check for errors
1696 mii_phy_probe(&gp->phy_mii, gp->mii_phy_addr);
1697
1698 /* Init PHY */
1699 if (gp->phy_mii.def && gp->phy_mii.def->ops->init)
1700 gp->phy_mii.def->ops->init(&gp->phy_mii);
1701 } else {
1702 u32 val;
1703 int limit;
1704
1705 /* Reset PCS unit. */
1706 val = readl(gp->regs + PCS_MIICTRL);
1707 val |= PCS_MIICTRL_RST;
1708 writeb(val, gp->regs + PCS_MIICTRL);
1709
1710 limit = 32;
1711 while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) {
1712 udelay(100);
1713 if (limit-- <= 0)
1714 break;
1715 }
1716 if (limit <= 0)
1717 printk(KERN_WARNING "%s: PCS reset bit would not clear.\n",
1718 gp->dev->name);
1719
1720 /* Make sure PCS is disabled while changing advertisement
1721 * configuration.
1722 */
1723 val = readl(gp->regs + PCS_CFG);
1724 val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO);
1725 writel(val, gp->regs + PCS_CFG);
1726
1727 /* Advertise all capabilities except assymetric
1728 * pause.
1729 */
1730 val = readl(gp->regs + PCS_MIIADV);
1731 val |= (PCS_MIIADV_FD | PCS_MIIADV_HD |
1732 PCS_MIIADV_SP | PCS_MIIADV_AP);
1733 writel(val, gp->regs + PCS_MIIADV);
1734
1735 /* Enable and restart auto-negotiation, disable wrapback/loopback,
1736 * and re-enable PCS.
1737 */
1738 val = readl(gp->regs + PCS_MIICTRL);
1739 val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE);
1740 val &= ~PCS_MIICTRL_WB;
1741 writel(val, gp->regs + PCS_MIICTRL);
1742
1743 val = readl(gp->regs + PCS_CFG);
1744 val |= PCS_CFG_ENABLE;
1745 writel(val, gp->regs + PCS_CFG);
1746
1747 /* Make sure serialink loopback is off. The meaning
1748 * of this bit is logically inverted based upon whether
1749 * you are in Serialink or SERDES mode.
1750 */
1751 val = readl(gp->regs + PCS_SCTRL);
1752 if (gp->phy_type == phy_serialink)
1753 val &= ~PCS_SCTRL_LOOP;
1754 else
1755 val |= PCS_SCTRL_LOOP;
1756 writel(val, gp->regs + PCS_SCTRL);
1757 }
1758 }
1759
1760 /* Must be invoked under gp->lock and gp->tx_lock. */
1761 static void gem_init_dma(struct gem *gp)
1762 {
1763 u64 desc_dma = (u64) gp->gblock_dvma;
1764 u32 val;
1765
1766 val = (TXDMA_CFG_BASE | (0x7ff << 10) | TXDMA_CFG_PMODE);
1767 writel(val, gp->regs + TXDMA_CFG);
1768
1769 writel(desc_dma >> 32, gp->regs + TXDMA_DBHI);
1770 writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW);
1771 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
1772
1773 writel(0, gp->regs + TXDMA_KICK);
1774
1775 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
1776 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
1777 writel(val, gp->regs + RXDMA_CFG);
1778
1779 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
1780 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
1781
1782 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1783
1784 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
1785 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
1786 writel(val, gp->regs + RXDMA_PTHRESH);
1787
1788 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
1789 writel(((5 & RXDMA_BLANK_IPKTS) |
1790 ((8 << 12) & RXDMA_BLANK_ITIME)),
1791 gp->regs + RXDMA_BLANK);
1792 else
1793 writel(((5 & RXDMA_BLANK_IPKTS) |
1794 ((4 << 12) & RXDMA_BLANK_ITIME)),
1795 gp->regs + RXDMA_BLANK);
1796 }
1797
1798 /* Must be invoked under gp->lock and gp->tx_lock. */
1799 static u32
1800 gem_setup_multicast(struct gem *gp)
1801 {
1802 u32 rxcfg = 0;
1803 int i;
1804
1805 if ((gp->dev->flags & IFF_ALLMULTI) ||
1806 (gp->dev->mc_count > 256)) {
1807 for (i=0; i<16; i++)
1808 writel(0xffff, gp->regs + MAC_HASH0 + (i << 2));
1809 rxcfg |= MAC_RXCFG_HFE;
1810 } else if (gp->dev->flags & IFF_PROMISC) {
1811 rxcfg |= MAC_RXCFG_PROM;
1812 } else {
1813 u16 hash_table[16];
1814 u32 crc;
1815 struct dev_mc_list *dmi = gp->dev->mc_list;
1816 int i;
1817
1818 for (i = 0; i < 16; i++)
1819 hash_table[i] = 0;
1820
1821 for (i = 0; i < gp->dev->mc_count; i++) {
1822 char *addrs = dmi->dmi_addr;
1823
1824 dmi = dmi->next;
1825
1826 if (!(*addrs & 1))
1827 continue;
1828
1829 crc = ether_crc_le(6, addrs);
1830 crc >>= 24;
1831 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
1832 }
1833 for (i=0; i<16; i++)
1834 writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2));
1835 rxcfg |= MAC_RXCFG_HFE;
1836 }
1837
1838 return rxcfg;
1839 }
1840
1841 /* Must be invoked under gp->lock and gp->tx_lock. */
1842 static void gem_init_mac(struct gem *gp)
1843 {
1844 unsigned char *e = &gp->dev->dev_addr[0];
1845
1846 writel(0x1bf0, gp->regs + MAC_SNDPAUSE);
1847
1848 writel(0x00, gp->regs + MAC_IPG0);
1849 writel(0x08, gp->regs + MAC_IPG1);
1850 writel(0x04, gp->regs + MAC_IPG2);
1851 writel(0x40, gp->regs + MAC_STIME);
1852 writel(0x40, gp->regs + MAC_MINFSZ);
1853
1854 /* Ethernet payload + header + FCS + optional VLAN tag. */
1855 writel(0x20000000 | (gp->rx_buf_sz + 4), gp->regs + MAC_MAXFSZ);
1856
1857 writel(0x07, gp->regs + MAC_PASIZE);
1858 writel(0x04, gp->regs + MAC_JAMSIZE);
1859 writel(0x10, gp->regs + MAC_ATTLIM);
1860 writel(0x8808, gp->regs + MAC_MCTYPE);
1861
1862 writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED);
1863
1864 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
1865 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
1866 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
1867
1868 writel(0, gp->regs + MAC_ADDR3);
1869 writel(0, gp->regs + MAC_ADDR4);
1870 writel(0, gp->regs + MAC_ADDR5);
1871
1872 writel(0x0001, gp->regs + MAC_ADDR6);
1873 writel(0xc200, gp->regs + MAC_ADDR7);
1874 writel(0x0180, gp->regs + MAC_ADDR8);
1875
1876 writel(0, gp->regs + MAC_AFILT0);
1877 writel(0, gp->regs + MAC_AFILT1);
1878 writel(0, gp->regs + MAC_AFILT2);
1879 writel(0, gp->regs + MAC_AF21MSK);
1880 writel(0, gp->regs + MAC_AF0MSK);
1881
1882 gp->mac_rx_cfg = gem_setup_multicast(gp);
1883 #ifdef STRIP_FCS
1884 gp->mac_rx_cfg |= MAC_RXCFG_SFCS;
1885 #endif
1886 writel(0, gp->regs + MAC_NCOLL);
1887 writel(0, gp->regs + MAC_FASUCC);
1888 writel(0, gp->regs + MAC_ECOLL);
1889 writel(0, gp->regs + MAC_LCOLL);
1890 writel(0, gp->regs + MAC_DTIMER);
1891 writel(0, gp->regs + MAC_PATMPS);
1892 writel(0, gp->regs + MAC_RFCTR);
1893 writel(0, gp->regs + MAC_LERR);
1894 writel(0, gp->regs + MAC_AERR);
1895 writel(0, gp->regs + MAC_FCSERR);
1896 writel(0, gp->regs + MAC_RXCVERR);
1897
1898 /* Clear RX/TX/MAC/XIF config, we will set these up and enable
1899 * them once a link is established.
1900 */
1901 writel(0, gp->regs + MAC_TXCFG);
1902 writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG);
1903 writel(0, gp->regs + MAC_MCCFG);
1904 writel(0, gp->regs + MAC_XIFCFG);
1905
1906 /* Setup MAC interrupts. We want to get all of the interesting
1907 * counter expiration events, but we do not want to hear about
1908 * normal rx/tx as the DMA engine tells us that.
1909 */
1910 writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK);
1911 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
1912
1913 /* Don't enable even the PAUSE interrupts for now, we
1914 * make no use of those events other than to record them.
1915 */
1916 writel(0xffffffff, gp->regs + MAC_MCMASK);
1917 }
1918
1919 /* Must be invoked under gp->lock and gp->tx_lock. */
1920 static void gem_init_pause_thresholds(struct gem *gp)
1921 {
1922 u32 cfg;
1923
1924 /* Calculate pause thresholds. Setting the OFF threshold to the
1925 * full RX fifo size effectively disables PAUSE generation which
1926 * is what we do for 10/100 only GEMs which have FIFOs too small
1927 * to make real gains from PAUSE.
1928 */
1929 if (gp->rx_fifo_sz <= (2 * 1024)) {
1930 gp->rx_pause_off = gp->rx_pause_on = gp->rx_fifo_sz;
1931 } else {
1932 int max_frame = (gp->rx_buf_sz + 4 + 64) & ~63;
1933 int off = (gp->rx_fifo_sz - (max_frame * 2));
1934 int on = off - max_frame;
1935
1936 gp->rx_pause_off = off;
1937 gp->rx_pause_on = on;
1938 }
1939
1940
1941 /* Configure the chip "burst" DMA mode & enable some
1942 * HW bug fixes on Apple version
1943 */
1944 cfg = 0;
1945 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
1946 cfg |= GREG_CFG_RONPAULBIT | GREG_CFG_ENBUG2FIX;
1947 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
1948 cfg |= GREG_CFG_IBURST;
1949 #endif
1950 cfg |= ((31 << 1) & GREG_CFG_TXDMALIM);
1951 cfg |= ((31 << 6) & GREG_CFG_RXDMALIM);
1952 writel(cfg, gp->regs + GREG_CFG);
1953
1954 /* If Infinite Burst didn't stick, then use different
1955 * thresholds (and Apple bug fixes don't exist)
1956 */
1957 if (!(readl(gp->regs + GREG_CFG) & GREG_CFG_IBURST)) {
1958 cfg = ((2 << 1) & GREG_CFG_TXDMALIM);
1959 cfg |= ((8 << 6) & GREG_CFG_RXDMALIM);
1960 writel(cfg, gp->regs + GREG_CFG);
1961 }
1962 }
1963
1964 static int gem_check_invariants(struct gem *gp)
1965 {
1966 struct pci_dev *pdev = gp->pdev;
1967 u32 mif_cfg;
1968
1969 /* On Apple's sungem, we can't rely on registers as the chip
1970 * was been powered down by the firmware. The PHY is looked
1971 * up later on.
1972 */
1973 if (pdev->vendor == PCI_VENDOR_ID_APPLE) {
1974 gp->phy_type = phy_mii_mdio0;
1975 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
1976 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
1977 gp->swrst_base = 0;
1978 return 0;
1979 }
1980
1981 mif_cfg = readl(gp->regs + MIF_CFG);
1982
1983 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
1984 pdev->device == PCI_DEVICE_ID_SUN_RIO_GEM) {
1985 /* One of the MII PHYs _must_ be present
1986 * as this chip has no gigabit PHY.
1987 */
1988 if ((mif_cfg & (MIF_CFG_MDI0 | MIF_CFG_MDI1)) == 0) {
1989 printk(KERN_ERR PFX "RIO GEM lacks MII phy, mif_cfg[%08x]\n",
1990 mif_cfg);
1991 return -1;
1992 }
1993 }
1994
1995 /* Determine initial PHY interface type guess. MDIO1 is the
1996 * external PHY and thus takes precedence over MDIO0.
1997 */
1998
1999 if (mif_cfg & MIF_CFG_MDI1) {
2000 gp->phy_type = phy_mii_mdio1;
2001 mif_cfg |= MIF_CFG_PSELECT;
2002 writel(mif_cfg, gp->regs + MIF_CFG);
2003 } else if (mif_cfg & MIF_CFG_MDI0) {
2004 gp->phy_type = phy_mii_mdio0;
2005 mif_cfg &= ~MIF_CFG_PSELECT;
2006 writel(mif_cfg, gp->regs + MIF_CFG);
2007 } else {
2008 gp->phy_type = phy_serialink;
2009 }
2010 if (gp->phy_type == phy_mii_mdio1 ||
2011 gp->phy_type == phy_mii_mdio0) {
2012 int i;
2013
2014 for (i = 0; i < 32; i++) {
2015 gp->mii_phy_addr = i;
2016 if (phy_read(gp, MII_BMCR) != 0xffff)
2017 break;
2018 }
2019 if (i == 32) {
2020 if (pdev->device != PCI_DEVICE_ID_SUN_GEM) {
2021 printk(KERN_ERR PFX "RIO MII phy will not respond.\n");
2022 return -1;
2023 }
2024 gp->phy_type = phy_serdes;
2025 }
2026 }
2027
2028 /* Fetch the FIFO configurations now too. */
2029 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
2030 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
2031
2032 if (pdev->vendor == PCI_VENDOR_ID_SUN) {
2033 if (pdev->device == PCI_DEVICE_ID_SUN_GEM) {
2034 if (gp->tx_fifo_sz != (9 * 1024) ||
2035 gp->rx_fifo_sz != (20 * 1024)) {
2036 printk(KERN_ERR PFX "GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2037 gp->tx_fifo_sz, gp->rx_fifo_sz);
2038 return -1;
2039 }
2040 gp->swrst_base = 0;
2041 } else {
2042 if (gp->tx_fifo_sz != (2 * 1024) ||
2043 gp->rx_fifo_sz != (2 * 1024)) {
2044 printk(KERN_ERR PFX "RIO GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2045 gp->tx_fifo_sz, gp->rx_fifo_sz);
2046 return -1;
2047 }
2048 gp->swrst_base = (64 / 4) << GREG_SWRST_CACHE_SHIFT;
2049 }
2050 }
2051
2052 return 0;
2053 }
2054
2055 /* Must be invoked under gp->lock and gp->tx_lock. */
2056 static void gem_init_hw(struct gem *gp, int restart_link)
2057 {
2058 /* On Apple's gmac, I initialize the PHY only after
2059 * setting up the chip. It appears the gigabit PHYs
2060 * don't quite like beeing talked to on the GII when
2061 * the chip is not running, I suspect it might not
2062 * be clocked at that point. --BenH
2063 */
2064 if (restart_link)
2065 gem_init_phy(gp);
2066 gem_init_pause_thresholds(gp);
2067 gem_init_dma(gp);
2068 gem_init_mac(gp);
2069
2070 if (restart_link) {
2071 /* Default aneg parameters */
2072 gp->timer_ticks = 0;
2073 gp->lstate = link_down;
2074 netif_carrier_off(gp->dev);
2075
2076 /* Can I advertise gigabit here ? I'd need BCM PHY docs... */
2077 gem_begin_auto_negotiation(gp, NULL);
2078 } else {
2079 if (gp->lstate == link_up) {
2080 netif_carrier_on(gp->dev);
2081 gem_set_link_modes(gp);
2082 }
2083 }
2084 }
2085
2086 #ifdef CONFIG_PPC_PMAC
2087 /* Enable the chip's clock and make sure it's config space is
2088 * setup properly. There appear to be no need to restore the
2089 * base addresses.
2090 */
2091 static void gem_apple_powerup(struct gem *gp)
2092 {
2093 u32 mif_cfg;
2094
2095 mb();
2096 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 1);
2097
2098 udelay(3);
2099
2100 mif_cfg = readl(gp->regs + MIF_CFG);
2101 mif_cfg &= ~(MIF_CFG_PSELECT|MIF_CFG_POLL|MIF_CFG_BBMODE|MIF_CFG_MDI1);
2102 mif_cfg |= MIF_CFG_MDI0;
2103 writel(mif_cfg, gp->regs + MIF_CFG);
2104 writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE);
2105 writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG);
2106 }
2107
2108 /* Turn off the chip's clock */
2109 static void gem_apple_powerdown(struct gem *gp)
2110 {
2111 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 0);
2112 }
2113
2114 #endif /* CONFIG_PPC_PMAC */
2115
2116 /* Must be invoked with no lock held. */
2117 static void gem_stop_phy(struct gem *gp)
2118 {
2119 u32 mifcfg;
2120 unsigned long flags;
2121
2122 /* Let the chip settle down a bit, it seems that helps
2123 * for sleep mode on some models
2124 */
2125 msleep(10);
2126
2127 /* Make sure we aren't polling PHY status change. We
2128 * don't currently use that feature though
2129 */
2130 mifcfg = readl(gp->regs + MIF_CFG);
2131 mifcfg &= ~MIF_CFG_POLL;
2132 writel(mifcfg, gp->regs + MIF_CFG);
2133
2134 if (gp->wake_on_lan) {
2135 /* Setup wake-on-lan */
2136 } else {
2137 writel(0, gp->regs + MAC_RXCFG);
2138 (void)readl(gp->regs + MAC_RXCFG);
2139 /* Machine sleep will die in strange ways if we
2140 * dont wait a bit here, looks like the chip takes
2141 * some time to really shut down
2142 */
2143 msleep(10);
2144 }
2145
2146 writel(0, gp->regs + MAC_TXCFG);
2147 writel(0, gp->regs + MAC_XIFCFG);
2148 writel(0, gp->regs + TXDMA_CFG);
2149 writel(0, gp->regs + RXDMA_CFG);
2150
2151 if (!gp->wake_on_lan) {
2152 spin_lock_irqsave(&gp->lock, flags);
2153 spin_lock(&gp->tx_lock);
2154 gem_stop(gp);
2155 writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST);
2156 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
2157 spin_unlock(&gp->tx_lock);
2158 spin_unlock_irqrestore(&gp->lock, flags);
2159 }
2160
2161 if (found_mii_phy(gp) && gp->phy_mii.def->ops->suspend)
2162 gp->phy_mii.def->ops->suspend(&gp->phy_mii, 0 /* wake on lan options */);
2163
2164 if (!gp->wake_on_lan) {
2165 /* According to Apple, we must set the MDIO pins to this begnign
2166 * state or we may 1) eat more current, 2) damage some PHYs
2167 */
2168 writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG);
2169 writel(0, gp->regs + MIF_BBCLK);
2170 writel(0, gp->regs + MIF_BBDATA);
2171 writel(0, gp->regs + MIF_BBOENAB);
2172 writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG);
2173 (void) readl(gp->regs + MAC_XIFCFG);
2174 }
2175 }
2176
2177 /* Shut down the chip, must be called with pm_sem held. */
2178 static void gem_shutdown(struct gem *gp)
2179 {
2180 /* Make us not-running to avoid timers respawning
2181 * and swallow irqs
2182 */
2183 gp->hw_running = 0;
2184 wmb();
2185
2186 /* Stop the link timer */
2187 del_timer_sync(&gp->link_timer);
2188
2189 /* Stop the reset task */
2190 while (gp->reset_task_pending)
2191 yield();
2192
2193 /* Actually stop the chip */
2194 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
2195 gem_stop_phy(gp);
2196
2197 #ifdef CONFIG_PPC_PMAC
2198 /* Power down the chip */
2199 gem_apple_powerdown(gp);
2200 #endif /* CONFIG_PPC_PMAC */
2201 } else{
2202 unsigned long flags;
2203
2204 spin_lock_irqsave(&gp->lock, flags);
2205 spin_lock(&gp->tx_lock);
2206 gem_stop(gp);
2207 spin_unlock(&gp->tx_lock);
2208 spin_unlock_irqrestore(&gp->lock, flags);
2209 }
2210 }
2211
2212 static void gem_pm_task(void *data)
2213 {
2214 struct gem *gp = (struct gem *) data;
2215
2216 /* We assume if we can't lock the pm_sem, then open() was
2217 * called again (or suspend()), and we can safely ignore
2218 * the PM request
2219 */
2220 if (down_trylock(&gp->pm_sem))
2221 return;
2222
2223 /* Driver was re-opened or already shut down */
2224 if (gp->opened || !gp->hw_running) {
2225 up(&gp->pm_sem);
2226 return;
2227 }
2228
2229 gem_shutdown(gp);
2230
2231 up(&gp->pm_sem);
2232 }
2233
2234 static void gem_pm_timer(unsigned long data)
2235 {
2236 struct gem *gp = (struct gem *) data;
2237
2238 schedule_work(&gp->pm_task);
2239 }
2240
2241 static int gem_open(struct net_device *dev)
2242 {
2243 struct gem *gp = dev->priv;
2244 int hw_was_up;
2245
2246 down(&gp->pm_sem);
2247
2248 hw_was_up = gp->hw_running;
2249
2250 /* Stop the PM timer/task */
2251 del_timer(&gp->pm_timer);
2252 flush_scheduled_work();
2253
2254 /* The power-management semaphore protects the hw_running
2255 * etc. state so it is safe to do this bit without gp->lock
2256 */
2257 if (!gp->hw_running) {
2258 #ifdef CONFIG_PPC_PMAC
2259 /* First, we need to bring up the chip */
2260 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
2261 gem_apple_powerup(gp);
2262 gem_check_invariants(gp);
2263 }
2264 #endif /* CONFIG_PPC_PMAC */
2265
2266 /* Reset the chip */
2267 spin_lock_irq(&gp->lock);
2268 spin_lock(&gp->tx_lock);
2269 gem_stop(gp);
2270 spin_unlock(&gp->tx_lock);
2271 spin_unlock_irq(&gp->lock);
2272
2273 gp->hw_running = 1;
2274 }
2275
2276 /* We can now request the interrupt as we know it's masked
2277 * on the controller
2278 */
2279 if (request_irq(gp->pdev->irq, gem_interrupt,
2280 SA_SHIRQ, dev->name, (void *)dev)) {
2281 printk(KERN_ERR "%s: failed to request irq !\n", gp->dev->name);
2282
2283 spin_lock_irq(&gp->lock);
2284 spin_lock(&gp->tx_lock);
2285 #ifdef CONFIG_PPC_PMAC
2286 if (!hw_was_up && gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
2287 gem_apple_powerdown(gp);
2288 #endif /* CONFIG_PPC_PMAC */
2289 /* Fire the PM timer that will shut us down in about 10 seconds */
2290 gp->pm_timer.expires = jiffies + 10*HZ;
2291 add_timer(&gp->pm_timer);
2292 up(&gp->pm_sem);
2293 spin_unlock(&gp->tx_lock);
2294 spin_unlock_irq(&gp->lock);
2295
2296 return -EAGAIN;
2297 }
2298
2299 spin_lock_irq(&gp->lock);
2300 spin_lock(&gp->tx_lock);
2301
2302 /* Allocate & setup ring buffers */
2303 gem_init_rings(gp);
2304
2305 /* Init & setup chip hardware */
2306 gem_init_hw(gp, !hw_was_up);
2307
2308 gp->opened = 1;
2309
2310 spin_unlock(&gp->tx_lock);
2311 spin_unlock_irq(&gp->lock);
2312
2313 up(&gp->pm_sem);
2314
2315 return 0;
2316 }
2317
2318 static int gem_close(struct net_device *dev)
2319 {
2320 struct gem *gp = dev->priv;
2321
2322 /* Make sure we don't get distracted by suspend/resume */
2323 down(&gp->pm_sem);
2324
2325 /* Note: we don't need to call netif_poll_disable() here because
2326 * our caller (dev_close) already did it for us
2327 */
2328
2329 /* Stop traffic, mark us closed */
2330 spin_lock_irq(&gp->lock);
2331 spin_lock(&gp->tx_lock);
2332
2333 gp->opened = 0;
2334
2335 netif_stop_queue(dev);
2336
2337 /* Stop chip */
2338 gem_stop(gp);
2339
2340 /* Get rid of rings */
2341 gem_clean_rings(gp);
2342
2343 /* Bye, the pm timer will finish the job */
2344 free_irq(gp->pdev->irq, (void *) dev);
2345
2346 spin_unlock(&gp->tx_lock);
2347 spin_unlock_irq(&gp->lock);
2348
2349 /* Fire the PM timer that will shut us down in about 10 seconds */
2350 gp->pm_timer.expires = jiffies + 10*HZ;
2351 add_timer(&gp->pm_timer);
2352
2353 up(&gp->pm_sem);
2354
2355 return 0;
2356 }
2357
2358 #ifdef CONFIG_PM
2359 static int gem_suspend(struct pci_dev *pdev, u32 state)
2360 {
2361 struct net_device *dev = pci_get_drvdata(pdev);
2362 struct gem *gp = dev->priv;
2363
2364 netif_poll_disable(dev);
2365
2366 /* We hold the PM semaphore during entire driver
2367 * sleep time
2368 */
2369 down(&gp->pm_sem);
2370
2371 printk(KERN_INFO "%s: suspending, WakeOnLan %s\n",
2372 dev->name, gp->wake_on_lan ? "enabled" : "disabled");
2373
2374 /* If the driver is opened, we stop the DMA */
2375 if (gp->opened) {
2376 spin_lock_irq(&gp->lock);
2377 spin_lock(&gp->tx_lock);
2378
2379 /* Stop traffic, mark us closed */
2380 netif_device_detach(dev);
2381
2382 /* Stop chip */
2383 gem_stop(gp);
2384
2385 /* Get rid of ring buffers */
2386 gem_clean_rings(gp);
2387
2388 spin_unlock(&gp->tx_lock);
2389 spin_unlock_irq(&gp->lock);
2390
2391 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
2392 disable_irq(gp->pdev->irq);
2393 }
2394
2395 if (gp->hw_running) {
2396 /* Kill PM timer if any */
2397 del_timer_sync(&gp->pm_timer);
2398 flush_scheduled_work();
2399
2400 gem_shutdown(gp);
2401 }
2402
2403 return 0;
2404 }
2405
2406 static int gem_resume(struct pci_dev *pdev)
2407 {
2408 struct net_device *dev = pci_get_drvdata(pdev);
2409 struct gem *gp = dev->priv;
2410
2411 printk(KERN_INFO "%s: resuming\n", dev->name);
2412
2413 if (gp->opened) {
2414 #ifdef CONFIG_PPC_PMAC
2415 /* First, we need to bring up the chip */
2416 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
2417 gem_apple_powerup(gp);
2418 gem_check_invariants(gp);
2419 }
2420 #endif /* CONFIG_PPC_PMAC */
2421 spin_lock_irq(&gp->lock);
2422 spin_lock(&gp->tx_lock);
2423
2424 gem_stop(gp);
2425 gp->hw_running = 1;
2426 gem_init_rings(gp);
2427 gem_init_hw(gp, 1);
2428
2429 spin_unlock(&gp->tx_lock);
2430 spin_unlock_irq(&gp->lock);
2431
2432 netif_device_attach(dev);
2433 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
2434 enable_irq(gp->pdev->irq);
2435 }
2436 up(&gp->pm_sem);
2437
2438 netif_poll_enable(dev);
2439
2440 return 0;
2441 }
2442 #endif /* CONFIG_PM */
2443
2444 static struct net_device_stats *gem_get_stats(struct net_device *dev)
2445 {
2446 struct gem *gp = dev->priv;
2447 struct net_device_stats *stats = &gp->net_stats;
2448
2449 spin_lock_irq(&gp->lock);
2450 spin_lock(&gp->tx_lock);
2451
2452 if (gp->hw_running) {
2453 stats->rx_crc_errors += readl(gp->regs + MAC_FCSERR);
2454 writel(0, gp->regs + MAC_FCSERR);
2455
2456 stats->rx_frame_errors += readl(gp->regs + MAC_AERR);
2457 writel(0, gp->regs + MAC_AERR);
2458
2459 stats->rx_length_errors += readl(gp->regs + MAC_LERR);
2460 writel(0, gp->regs + MAC_LERR);
2461
2462 stats->tx_aborted_errors += readl(gp->regs + MAC_ECOLL);
2463 stats->collisions +=
2464 (readl(gp->regs + MAC_ECOLL) +
2465 readl(gp->regs + MAC_LCOLL));
2466 writel(0, gp->regs + MAC_ECOLL);
2467 writel(0, gp->regs + MAC_LCOLL);
2468 }
2469
2470 spin_unlock(&gp->tx_lock);
2471 spin_unlock_irq(&gp->lock);
2472
2473 return &gp->net_stats;
2474 }
2475
2476 static void gem_set_multicast(struct net_device *dev)
2477 {
2478 struct gem *gp = dev->priv;
2479 u32 rxcfg, rxcfg_new;
2480 int limit = 10000;
2481
2482 if (!gp->hw_running)
2483 return;
2484
2485 spin_lock_irq(&gp->lock);
2486 spin_lock(&gp->tx_lock);
2487
2488 netif_stop_queue(dev);
2489
2490 rxcfg = readl(gp->regs + MAC_RXCFG);
2491 rxcfg_new = gem_setup_multicast(gp);
2492 #ifdef STRIP_FCS
2493 rxcfg_new |= MAC_RXCFG_SFCS;
2494 #endif
2495 gp->mac_rx_cfg = rxcfg_new;
2496
2497 writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
2498 while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) {
2499 if (!limit--)
2500 break;
2501 udelay(10);
2502 }
2503
2504 rxcfg &= ~(MAC_RXCFG_PROM | MAC_RXCFG_HFE);
2505 rxcfg |= rxcfg_new;
2506
2507 writel(rxcfg, gp->regs + MAC_RXCFG);
2508
2509 netif_wake_queue(dev);
2510
2511 spin_unlock(&gp->tx_lock);
2512 spin_unlock_irq(&gp->lock);
2513 }
2514
2515 static void gem_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2516 {
2517 struct gem *gp = dev->priv;
2518
2519 strcpy(info->driver, DRV_NAME);
2520 strcpy(info->version, DRV_VERSION);
2521 strcpy(info->bus_info, pci_name(gp->pdev));
2522 }
2523
2524 static int gem_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2525 {
2526 struct gem *gp = dev->priv;
2527
2528 if (gp->phy_type == phy_mii_mdio0 ||
2529 gp->phy_type == phy_mii_mdio1) {
2530 if (gp->phy_mii.def)
2531 cmd->supported = gp->phy_mii.def->features;
2532 else
2533 cmd->supported = (SUPPORTED_10baseT_Half |
2534 SUPPORTED_10baseT_Full);
2535
2536 /* XXX hardcoded stuff for now */
2537 cmd->port = PORT_MII;
2538 cmd->transceiver = XCVR_EXTERNAL;
2539 cmd->phy_address = 0; /* XXX fixed PHYAD */
2540
2541 /* Return current PHY settings */
2542 spin_lock_irq(&gp->lock);
2543 spin_lock(&gp->tx_lock);
2544 cmd->autoneg = gp->want_autoneg;
2545 cmd->speed = gp->phy_mii.speed;
2546 cmd->duplex = gp->phy_mii.duplex;
2547 cmd->advertising = gp->phy_mii.advertising;
2548
2549 /* If we started with a forced mode, we don't have a default
2550 * advertise set, we need to return something sensible so
2551 * userland can re-enable autoneg properly.
2552 */
2553 if (cmd->advertising == 0)
2554 cmd->advertising = cmd->supported;
2555 spin_unlock(&gp->tx_lock);
2556 spin_unlock_irq(&gp->lock);
2557 } else { // XXX PCS ?
2558 cmd->supported =
2559 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2560 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2561 SUPPORTED_Autoneg);
2562 cmd->advertising = cmd->supported;
2563 cmd->speed = 0;
2564 cmd->duplex = cmd->port = cmd->phy_address =
2565 cmd->transceiver = cmd->autoneg = 0;
2566 }
2567 cmd->maxtxpkt = cmd->maxrxpkt = 0;
2568
2569 return 0;
2570 }
2571
2572 static int gem_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2573 {
2574 struct gem *gp = dev->priv;
2575
2576 /* Verify the settings we care about. */
2577 if (cmd->autoneg != AUTONEG_ENABLE &&
2578 cmd->autoneg != AUTONEG_DISABLE)
2579 return -EINVAL;
2580
2581 if (cmd->autoneg == AUTONEG_ENABLE &&
2582 cmd->advertising == 0)
2583 return -EINVAL;
2584
2585 if (cmd->autoneg == AUTONEG_DISABLE &&
2586 ((cmd->speed != SPEED_1000 &&
2587 cmd->speed != SPEED_100 &&
2588 cmd->speed != SPEED_10) ||
2589 (cmd->duplex != DUPLEX_HALF &&
2590 cmd->duplex != DUPLEX_FULL)))
2591 return -EINVAL;
2592
2593 /* Apply settings and restart link process. */
2594 spin_lock_irq(&gp->lock);
2595 spin_lock(&gp->tx_lock);
2596 gem_begin_auto_negotiation(gp, cmd);
2597 spin_unlock(&gp->tx_lock);
2598 spin_unlock_irq(&gp->lock);
2599
2600 return 0;
2601 }
2602
2603 static int gem_nway_reset(struct net_device *dev)
2604 {
2605 struct gem *gp = dev->priv;
2606
2607 if (!gp->want_autoneg)
2608 return -EINVAL;
2609
2610 /* Restart link process. */
2611 spin_lock_irq(&gp->lock);
2612 spin_lock(&gp->tx_lock);
2613 gem_begin_auto_negotiation(gp, NULL);
2614 spin_unlock(&gp->tx_lock);
2615 spin_unlock_irq(&gp->lock);
2616
2617 return 0;
2618 }
2619
2620 static u32 gem_get_msglevel(struct net_device *dev)
2621 {
2622 struct gem *gp = dev->priv;
2623 return gp->msg_enable;
2624 }
2625
2626 static void gem_set_msglevel(struct net_device *dev, u32 value)
2627 {
2628 struct gem *gp = dev->priv;
2629 gp->msg_enable = value;
2630 }
2631
2632 static struct ethtool_ops gem_ethtool_ops = {
2633 .get_drvinfo = gem_get_drvinfo,
2634 .get_link = ethtool_op_get_link,
2635 .get_settings = gem_get_settings,
2636 .set_settings = gem_set_settings,
2637 .nway_reset = gem_nway_reset,
2638 .get_msglevel = gem_get_msglevel,
2639 .set_msglevel = gem_set_msglevel,
2640 };
2641
2642 static int gem_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2643 {
2644 struct gem *gp = dev->priv;
2645 struct mii_ioctl_data *data = if_mii(ifr);
2646 int rc = -EOPNOTSUPP;
2647
2648 /* Hold the PM semaphore while doing ioctl's or we may collide
2649 * with open/close and power management and oops.
2650 */
2651 down(&gp->pm_sem);
2652
2653 switch (cmd) {
2654 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
2655 data->phy_id = gp->mii_phy_addr;
2656 /* Fallthrough... */
2657
2658 case SIOCGMIIREG: /* Read MII PHY register. */
2659 if (!gp->hw_running)
2660 rc = -EIO;
2661 else {
2662 data->val_out = __phy_read(gp, data->phy_id & 0x1f, data->reg_num & 0x1f);
2663 rc = 0;
2664 }
2665 break;
2666
2667 case SIOCSMIIREG: /* Write MII PHY register. */
2668 if (!capable(CAP_NET_ADMIN))
2669 rc = -EPERM;
2670 else if (!gp->hw_running)
2671 rc = -EIO;
2672 else {
2673 __phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
2674 rc = 0;
2675 }
2676 break;
2677 };
2678
2679 up(&gp->pm_sem);
2680
2681 return rc;
2682 }
2683
2684 #if (!defined(__sparc__) && !defined(CONFIG_PPC))
2685 /* Fetch MAC address from vital product data of PCI ROM. */
2686 static void find_eth_addr_in_vpd(void *rom_base, int len, unsigned char *dev_addr)
2687 {
2688 int this_offset;
2689
2690 for (this_offset = 0x20; this_offset < len; this_offset++) {
2691 void *p = rom_base + this_offset;
2692 int i;
2693
2694 if (readb(p + 0) != 0x90 ||
2695 readb(p + 1) != 0x00 ||
2696 readb(p + 2) != 0x09 ||
2697 readb(p + 3) != 0x4e ||
2698 readb(p + 4) != 0x41 ||
2699 readb(p + 5) != 0x06)
2700 continue;
2701
2702 this_offset += 6;
2703 p += 6;
2704
2705 for (i = 0; i < 6; i++)
2706 dev_addr[i] = readb(p + i);
2707 break;
2708 }
2709 }
2710
2711 static void get_gem_mac_nonobp(struct pci_dev *pdev, unsigned char *dev_addr)
2712 {
2713 u32 rom_reg_orig;
2714 void __iomem *p;
2715
2716 if (pdev->resource[PCI_ROM_RESOURCE].parent == NULL) {
2717 if (pci_assign_resource(pdev, PCI_ROM_RESOURCE) < 0)
2718 goto use_random;
2719 }
2720
2721 pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_reg_orig);
2722 pci_write_config_dword(pdev, pdev->rom_base_reg,
2723 rom_reg_orig | PCI_ROM_ADDRESS_ENABLE);
2724
2725 p = ioremap(pci_resource_start(pdev, PCI_ROM_RESOURCE), (64 * 1024));
2726 if (p != NULL && readb(p) == 0x55 && readb(p + 1) == 0xaa)
2727 find_eth_addr_in_vpd(p, (64 * 1024), dev_addr);
2728
2729 if (p != NULL)
2730 iounmap(p);
2731
2732 pci_write_config_dword(pdev, pdev->rom_base_reg, rom_reg_orig);
2733 return;
2734
2735 use_random:
2736 /* Sun MAC prefix then 3 random bytes. */
2737 dev_addr[0] = 0x08;
2738 dev_addr[1] = 0x00;
2739 dev_addr[2] = 0x20;
2740 get_random_bytes(dev_addr + 3, 3);
2741 return;
2742 }
2743 #endif /* not Sparc and not PPC */
2744
2745 static int __devinit gem_get_device_address(struct gem *gp)
2746 {
2747 #if defined(__sparc__) || defined(CONFIG_PPC_PMAC)
2748 struct net_device *dev = gp->dev;
2749 #endif
2750
2751 #if defined(__sparc__)
2752 struct pci_dev *pdev = gp->pdev;
2753 struct pcidev_cookie *pcp = pdev->sysdata;
2754 int node = -1;
2755
2756 if (pcp != NULL) {
2757 node = pcp->prom_node;
2758 if (prom_getproplen(node, "local-mac-address") == 6)
2759 prom_getproperty(node, "local-mac-address",
2760 dev->dev_addr, 6);
2761 else
2762 node = -1;
2763 }
2764 if (node == -1)
2765 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2766 #elif defined(CONFIG_PPC_PMAC)
2767 unsigned char *addr;
2768
2769 addr = get_property(gp->of_node, "local-mac-address", NULL);
2770 if (addr == NULL) {
2771 printk("\n");
2772 printk(KERN_ERR "%s: can't get mac-address\n", dev->name);
2773 return -1;
2774 }
2775 memcpy(dev->dev_addr, addr, 6);
2776 #else
2777 get_gem_mac_nonobp(gp->pdev, gp->dev->dev_addr);
2778 #endif
2779 return 0;
2780 }
2781
2782 static int __devinit gem_init_one(struct pci_dev *pdev,
2783 const struct pci_device_id *ent)
2784 {
2785 static int gem_version_printed = 0;
2786 unsigned long gemreg_base, gemreg_len;
2787 struct net_device *dev;
2788 struct gem *gp;
2789 int i, err, pci_using_dac;
2790
2791 if (gem_version_printed++ == 0)
2792 printk(KERN_INFO "%s", version);
2793
2794 /* Apple gmac note: during probe, the chip is powered up by
2795 * the arch code to allow the code below to work (and to let
2796 * the chip be probed on the config space. It won't stay powered
2797 * up until the interface is brought up however, so we can't rely
2798 * on register configuration done at this point.
2799 */
2800 err = pci_enable_device(pdev);
2801 if (err) {
2802 printk(KERN_ERR PFX "Cannot enable MMIO operation, "
2803 "aborting.\n");
2804 return err;
2805 }
2806 pci_set_master(pdev);
2807
2808 /* Configure DMA attributes. */
2809
2810 /* All of the GEM documentation states that 64-bit DMA addressing
2811 * is fully supported and should work just fine. However the
2812 * front end for RIO based GEMs is different and only supports
2813 * 32-bit addressing.
2814 *
2815 * For now we assume the various PPC GEMs are 32-bit only as well.
2816 */
2817 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
2818 pdev->device == PCI_DEVICE_ID_SUN_GEM &&
2819 !pci_set_dma_mask(pdev, (u64) 0xffffffffffffffffULL)) {
2820 pci_using_dac = 1;
2821 } else {
2822 err = pci_set_dma_mask(pdev, (u64) 0xffffffff);
2823 if (err) {
2824 printk(KERN_ERR PFX "No usable DMA configuration, "
2825 "aborting.\n");
2826 goto err_disable_device;
2827 }
2828 pci_using_dac = 0;
2829 }
2830
2831 gemreg_base = pci_resource_start(pdev, 0);
2832 gemreg_len = pci_resource_len(pdev, 0);
2833
2834 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
2835 printk(KERN_ERR PFX "Cannot find proper PCI device "
2836 "base address, aborting.\n");
2837 err = -ENODEV;
2838 goto err_disable_device;
2839 }
2840
2841 dev = alloc_etherdev(sizeof(*gp));
2842 if (!dev) {
2843 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
2844 err = -ENOMEM;
2845 goto err_disable_device;
2846 }
2847 SET_MODULE_OWNER(dev);
2848 SET_NETDEV_DEV(dev, &pdev->dev);
2849
2850 gp = dev->priv;
2851
2852 err = pci_request_regions(pdev, DRV_NAME);
2853 if (err) {
2854 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
2855 "aborting.\n");
2856 goto err_out_free_netdev;
2857 }
2858
2859 gp->pdev = pdev;
2860 dev->base_addr = (long) pdev;
2861 gp->dev = dev;
2862
2863 gp->msg_enable = DEFAULT_MSG;
2864
2865 spin_lock_init(&gp->lock);
2866 spin_lock_init(&gp->tx_lock);
2867 init_MUTEX(&gp->pm_sem);
2868
2869 init_timer(&gp->link_timer);
2870 gp->link_timer.function = gem_link_timer;
2871 gp->link_timer.data = (unsigned long) gp;
2872
2873 init_timer(&gp->pm_timer);
2874 gp->pm_timer.function = gem_pm_timer;
2875 gp->pm_timer.data = (unsigned long) gp;
2876
2877 INIT_WORK(&gp->pm_task, gem_pm_task, gp);
2878 INIT_WORK(&gp->reset_task, gem_reset_task, gp);
2879
2880 gp->lstate = link_down;
2881 gp->timer_ticks = 0;
2882 netif_carrier_off(dev);
2883
2884 gp->regs = ioremap(gemreg_base, gemreg_len);
2885 if (gp->regs == 0UL) {
2886 printk(KERN_ERR PFX "Cannot map device registers, "
2887 "aborting.\n");
2888 err = -EIO;
2889 goto err_out_free_res;
2890 }
2891
2892 /* On Apple, we power the chip up now in order for check
2893 * invariants to work, but also because the firmware might
2894 * not have properly shut down the PHY.
2895 */
2896 #ifdef CONFIG_PPC_PMAC
2897 gp->of_node = pci_device_to_OF_node(pdev);
2898 if (pdev->vendor == PCI_VENDOR_ID_APPLE)
2899 gem_apple_powerup(gp);
2900 #endif
2901 spin_lock_irq(&gp->lock);
2902 spin_lock(&gp->tx_lock);
2903 gem_stop(gp);
2904 spin_unlock(&gp->tx_lock);
2905 spin_unlock_irq(&gp->lock);
2906
2907 /* Fill up the mii_phy structure (even if we won't use it) */
2908 gp->phy_mii.dev = dev;
2909 gp->phy_mii.mdio_read = _phy_read;
2910 gp->phy_mii.mdio_write = _phy_write;
2911
2912 /* By default, we start with autoneg */
2913 gp->want_autoneg = 1;
2914
2915 if (gem_check_invariants(gp)) {
2916 err = -ENODEV;
2917 goto err_out_iounmap;
2918 }
2919
2920 /* It is guaranteed that the returned buffer will be at least
2921 * PAGE_SIZE aligned.
2922 */
2923 gp->init_block = (struct gem_init_block *)
2924 pci_alloc_consistent(pdev, sizeof(struct gem_init_block),
2925 &gp->gblock_dvma);
2926 if (!gp->init_block) {
2927 printk(KERN_ERR PFX "Cannot allocate init block, "
2928 "aborting.\n");
2929 err = -ENOMEM;
2930 goto err_out_iounmap;
2931 }
2932
2933 if (gem_get_device_address(gp))
2934 goto err_out_free_consistent;
2935
2936 dev->open = gem_open;
2937 dev->stop = gem_close;
2938 dev->hard_start_xmit = gem_start_xmit;
2939 dev->get_stats = gem_get_stats;
2940 dev->set_multicast_list = gem_set_multicast;
2941 dev->do_ioctl = gem_ioctl;
2942 dev->poll = gem_poll;
2943 dev->weight = 64;
2944 dev->ethtool_ops = &gem_ethtool_ops;
2945 dev->tx_timeout = gem_tx_timeout;
2946 dev->watchdog_timeo = 5 * HZ;
2947 dev->change_mtu = gem_change_mtu;
2948 dev->irq = pdev->irq;
2949 dev->dma = 0;
2950 #ifdef CONFIG_NET_POLL_CONTROLLER
2951 dev->poll_controller = gem_poll_controller;
2952 #endif
2953
2954 if (register_netdev(dev)) {
2955 printk(KERN_ERR PFX "Cannot register net device, "
2956 "aborting.\n");
2957 err = -ENOMEM;
2958 goto err_out_free_consistent;
2959 }
2960
2961 printk(KERN_INFO "%s: Sun GEM (PCI) 10/100/1000BaseT Ethernet ",
2962 dev->name);
2963 for (i = 0; i < 6; i++)
2964 printk("%2.2x%c", dev->dev_addr[i],
2965 i == 5 ? ' ' : ':');
2966 printk("\n");
2967
2968 /* Detect & init PHY, start autoneg */
2969 spin_lock_irq(&gp->lock);
2970 spin_lock(&gp->tx_lock);
2971 gp->hw_running = 1;
2972 gem_init_phy(gp);
2973 gem_begin_auto_negotiation(gp, NULL);
2974 spin_unlock(&gp->tx_lock);
2975 spin_unlock_irq(&gp->lock);
2976
2977 if (gp->phy_type == phy_mii_mdio0 ||
2978 gp->phy_type == phy_mii_mdio1)
2979 printk(KERN_INFO "%s: Found %s PHY\n", dev->name,
2980 gp->phy_mii.def ? gp->phy_mii.def->name : "no");
2981
2982 pci_set_drvdata(pdev, dev);
2983
2984 /* GEM can do it all... */
2985 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_LLTX;
2986 if (pci_using_dac)
2987 dev->features |= NETIF_F_HIGHDMA;
2988
2989 /* Fire the PM timer that will shut us down in about 10 seconds */
2990 gp->pm_timer.expires = jiffies + 10*HZ;
2991 add_timer(&gp->pm_timer);
2992
2993 return 0;
2994
2995 err_out_free_consistent:
2996 pci_free_consistent(pdev,
2997 sizeof(struct gem_init_block),
2998 gp->init_block,
2999 gp->gblock_dvma);
3000
3001 err_out_iounmap:
3002 down(&gp->pm_sem);
3003 /* Stop the PM timer & task */
3004 del_timer_sync(&gp->pm_timer);
3005 flush_scheduled_work();
3006 if (gp->hw_running)
3007 gem_shutdown(gp);
3008 up(&gp->pm_sem);
3009
3010 iounmap(gp->regs);
3011
3012 err_out_free_res:
3013 pci_release_regions(pdev);
3014
3015 err_out_free_netdev:
3016 free_netdev(dev);
3017 err_disable_device:
3018 pci_disable_device(pdev);
3019 return err;
3020
3021 }
3022
3023 static void __devexit gem_remove_one(struct pci_dev *pdev)
3024 {
3025 struct net_device *dev = pci_get_drvdata(pdev);
3026
3027 if (dev) {
3028 struct gem *gp = dev->priv;
3029
3030 unregister_netdev(dev);
3031
3032 down(&gp->pm_sem);
3033 /* Stop the PM timer & task */
3034 del_timer_sync(&gp->pm_timer);
3035 flush_scheduled_work();
3036 if (gp->hw_running)
3037 gem_shutdown(gp);
3038 up(&gp->pm_sem);
3039
3040 pci_free_consistent(pdev,
3041 sizeof(struct gem_init_block),
3042 gp->init_block,
3043 gp->gblock_dvma);
3044 iounmap(gp->regs);
3045 pci_release_regions(pdev);
3046 free_netdev(dev);
3047
3048 pci_set_drvdata(pdev, NULL);
3049 }
3050 }
3051
3052 static struct pci_driver gem_driver = {
3053 .name = GEM_MODULE_NAME,
3054 .id_table = gem_pci_tbl,
3055 .probe = gem_init_one,
3056 .remove = __devexit_p(gem_remove_one),
3057 #ifdef CONFIG_PM
3058 .suspend = gem_suspend,
3059 .resume = gem_resume,
3060 #endif /* CONFIG_PM */
3061 };
3062
3063 static int __init gem_init(void)
3064 {
3065 return pci_module_init(&gem_driver);
3066 }
3067
3068 static void __exit gem_cleanup(void)
3069 {
3070 pci_unregister_driver(&gem_driver);
3071 }
3072
3073 module_init(gem_init);
3074 module_exit(gem_cleanup);
MOXA 2.6.9 from sdlinux-moxaart.tgz