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MOXA linux-2.6.x / linux-2.6.9-uc0 from sdlinux-moxaart.tgz
[linux-2.6.9-moxart.git] / drivers / net / wireless / rtlink.org / rt2560.h
blob8a5afd8f96d0f192ed913d5dbf3ee6a417fa3608
1 /*
2 ***************************************************************************
3 * Ralink Tech Inc.
4 * 4F, No. 2 Technology 5th Rd.
5 * Science-based Industrial Park
6 * Hsin-chu, Taiwan, R.O.C.
7 *
8 * (c) Copyright 2002, Ralink Technology, Inc.
9 *
10 * All rights reserved. Ralink's source code is an unpublished work and the
11 * use of a copyright notice does not imply otherwise. This source code
12 * contains confidential trade secret material of Ralink Tech. Any attemp
13 * or participation in deciphering, decoding, reverse engineering or in any
14 * way altering the source code is stricitly prohibited, unless the prior
15 * written consent of Ralink Technology, Inc. is obtained.
16 ***************************************************************************
17
18 Module Name:
19 rt2560.h
20
21 Abstract:
22 RT2560 ASIC related definition & structures
23
24 Revision History:
25 Who When What
26 -------- ---------- ----------------------------------------------
27
28 */
29
30 #ifndef __RT2560_H__
31 #define __RT2560_H__
32
33 //
34 // Control/Status Registers (CSR)
35 //
36 #define CSR0 0x0000 // ASIC revision number
37 #define CSR1 0x0004 // System control register
38 #define CSR2 0x0008 // System admin status register (invalid)
39 #define CSR3 0x000C // STA MAC address register 0
40 #define CSR4 0x0010 // STA MAC address register 1
41 #define CSR5 0x0014 // BSSID register 0
42 #define CSR6 0x0018 // BSSID register 1
43 #define CSR7 0x001C // Interrupt source register
44 #define CSR8 0x0020 // Interrupt mask register
45 #define CSR9 0x0024 // Maximum frame length register
46 #define CSR11 0x002C // Back-off control register
47 #define CSR12 0x0030 // Synchronization configuration register 0
48 #define CSR13 0x0034 // Synchronization configuration register 1
49 #define CSR14 0x0038 // Synchronization control register
50 #define CSR15 0x003C // Synchronization status register
51 #define CSR16 0x0040 // TSF timer register 0
52 #define CSR17 0x0044 // TSF timer register 1
53 #define CSR18 0x0048 // IFS timer register 0
54 #define CSR19 0x004C // IFS timer register 1
55 #define CSR20 0x0050 // WakeUp register
56 #define CSR21 0x0054 // EEPROM control register
57 #define CSR22 0x0058 // CFP Control Register
58
59 // Security coprocessor registers
60 #define SECCSR0 0x0028 // WEP control register
61 #define SECCSR1 0x0158 // WEP control register
62 #define SECCSR3 0x00fc // AES control register
63
64 // Transmit related CSRs
65 #define TXCSR0 0x0060 // TX cintrol register
66 #define TXCSR1 0x0064 // TX configuration register
67 #define TXCSR2 0x0068 // TX descriptor configuratioon register
68 #define TXCSR3 0x006C // TX Ring Base address register
69 #define TXCSR4 0x0070 // Atim Ring Base address register
70 #define TXCSR5 0x0074 // Prio Ring Base address register
71 #define TXCSR6 0x0078 // Beacon base address
72 #define TXCSR7 0x007C // AutoResponder Control Register
73 #define TXCSR8 0x0098 // CCK TX BBP registers
74 #define TXCSR9 0x0094 // OFDM TX BBP registers
75
76 // Receive related CSRs
77 #define RXCSR0 0x0080 // RX control register
78 #define RXCSR1 0x0084 // RX descriptorconfiguration register
79 #define RXCSR2 0x0088 // RX Ring base address register
80 #define RXCSR3 0x0090 // BBP ID register 0
81 //#define RXCSR4 0x0094 // BBP ID register 1
82 //#define ARCSR0 0x0098 // Auto responder PLCP config register 1
83 #define ARCSR1 0x009C // Auto responder PLCP config register 1
84
85 // PCI control CSRs
86 #define PCICSR 0x008C // PCI control register
87
88 //
89 // Alias to all ring base registers. Easier to understand constant definition
90 // within codes.
91 //
92 #define RX_RING_BASE_REG (RXCSR2)
93 #define TX_RING_BASE_REG (TXCSR3)
94 #define ATIM_RING_BASE_REG (TXCSR4)
95 #define PRIO_RING_BASE_REG (TXCSR5)
96 #define BEACON_BASE_REG (TXCSR6)
97
98 // Statistic Register
99 #define CNT0 0x00A0 // Dot11 FCS error count
100 #define CNT1 0x00AC // Dot11 PLCP error count
101 #define CNT2 0x00B0 // Dot11 long error count
102 #define CNT3 0x00B8 // Dot11 CCA false alarm count
103 #define CNT4 0x00BC // Dot11 Rx FIFO overflow count
104 #define CNT5 0x00C0 // Dot11 Tx FIFO underrun count
105
106 // Baseband Control Register
107 #define PWRCSR0 0x00C4
108 #define PSCSR0 0x00C8
109 #define PSCSR1 0x00CC
110 #define PSCSR2 0x00D0
111 #define PSCSR3 0x00D4
112 #define PWRCSR1 0x00D8
113 #define TIMECSR 0x00DC
114 #define MACCSR0 0x00E0
115 #define MACCSR1 0x00E4
116 #define RALINKCSR 0x00E8 // Ralink Auto-reset register
117 #define BCNCSR 0x00EC
118
119 // BBP/RF/IF Control Register
120 #define BBPCSR 0x00F0
121 #define RFCSR 0x00F4
122 #define LEDCSR 0x00F8
123
124 // ASIC pointer information
125 #define RXPTR 0x0100 // Current RX ring address
126 #define TXPTR 0x0104 // Current Tx ring address
127 #define PRIPTR 0x0108 // Current Priority ring address
128 #define ATIMPTR 0x010c // Current ATIM ring address
129
130 // some others
131 #define TXACKCSR0 0x0110 // TX ACK timeout
132 #define ACKCNT0 0x0114 // TX ACK timeout count
133 #define ACKCNT1 0x0118 // RX ACK timeout count
134
135 // GPIO and others
136 #define GPIOCSR 0x0120 // GPIO direction & in/out
137 #define FIFOCSR0 0x0128 // TX FIFO pointer
138 #define FIFOCSR1 0x012C // RX FIFO pointer
139 #define BCNCSR1 0x0130 // Tx BEACON offset time, unit: 1 usec
140 #define MACCSR2 0x0134 // TX_PE to RX_PE delay time, unit: 1 PCI clock cycle
141 #define TESTCSR 0x0138 // TEST mode selection register
142
143 #define PLCP1MCSR 0x013c // 1 Mbps ACK/CTS PLCP
144 #define PLCP2MCSR 0x0140 // 2 Mbps ACK/CTS PLCP
145 #define PLCP5MCSR 0x0144 // 5.5 Mbps ACK/CTS PLCP
146 #define PLCP11MCSR 0x0148 // 11 Mbps ACK/CTS PLCP
147
148 #define ARTCSR0 0x014c // ACK/CTS payload consumed time for 1/2/5.5/11 mbps
149 #define ARTCSR1 0x0150 // OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps
150 #define ARTCSR2 0x0154 // OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps
151 #define SECCSR1 0x0158 // security control register
152 #define BBPCSR1 0x015c // BBP TX configuration
153
154 #define DBANDCSR0 0x0160 // Dual band configuration register 0
155 #define DBANDCSR1 0x0164 // Dual band configuration register 1
156 #define BBPPCSR 0x0168 // BBP pin control register
157 #define DBGSEL0 0x016c // MAC special debug mode selection register 0
158 #define DBGSEL1 0x0170 // MAC special debug mode selection register 1
159 #define BISTCSR 0x0174 // BBP BIST register
160
161 #define MCAST0 0x0178 // multicast filter register 0
162 #define MCAST1 0x017c // multicast filter register 1
163
164 #define UARTCSR0 0x0180 // UART1 TX register
165 #define UARTCSR1 0x0184 // UART1 RX register
166 #define UARTCSR3 0x0188 // UART1 frame control register
167 #define UARTCSR4 0x018c // UART1 buffer control register
168 #define UART2CSR0 0x0190 // UART2 TX register
169 #define UART2CSR1 0x0194 // UART2 RX register
170 #define UART2CSR3 0x0198 // UART2 frame control register
171 #define UART2CSR4 0x019c // UART2 buffer control register
172
173 #define TIMECSR2 0x00a8
174 #define TIMECSR3 0x00b4
175
176 //
177 // Tx / Rx / Prio / Atim ring descriptor definition
178 //
179 #define DESC_OWN_HOST 0
180 #define DESC_OWN_NIC 1
181 #define DESC_VALID_TRUE 1
182 #define DESC_VALID_FALSE 0
183
184 //
185 // BBP & RF definition
186 //
187 #define BUSY 1
188 #define IDLE 0
189
190 #define BBP_Version 0x00
191 #define BBP_Tx_Configure 2 // R2
192 #define BBP_Tx_Tssi 1 // R1
193 #define BBP_Rx_Configure 14 // R14
194
195 #define PHY_TR_SWITCH_TIME 5 // usec
196
197 #define RT2560_VER_B 2
198 #define RT2560_VER_C 3
199 #define RT2560_VER_D 4
200 #define BBP_R17_LOW_SENSIBILITY 0x50
201 #define BBP_R17_MID_SENSIBILITY 0x41
202 #define BBP_R17_DYNAMIC_UP_BOUND 0x40
203 #define RSSI_FOR_LOW_SENSIBILITY -58
204 #define RSSI_FOR_MID_SENSIBILITY -74
205 //#define RSSI_HIGH_WATERMARK -53
206 //#define RSSI_LOW_WATERMARK -58
207
208 //-------------------------------------------------------------------------
209 // EEPROM definition
210 //-------------------------------------------------------------------------
211 #define EEDO 0x10
212 #define EEDI 0x08
213 #define EECS 0x04
214 #define EESK 0x02
215 #define EERL 0x01
216
217 #define EEPROM_WRITE_OPCODE 0x05
218 #define EEPROM_READ_OPCODE 0x06
219 #define EEPROM_EWDS_OPCODE 0x10
220 #define EEPROM_EWEN_OPCODE 0x13
221
222 #define NUM_EEPROM_BBP_PARMS 19
223 #define NUM_EEPROM_TX_PARMS 7
224 #define EEPROM_BBP_BASE_OFFSET 0x20 // 0x16
225 #define EEPROM_TX_PWR_OFFSET 0x46 // 0x3c
226 #define EEPROM_TSSI_REF_OFFSET 0x54
227 #define EEPROM_TSSI_DELTA_OFFSET 0x24
228 #define EEPROM_VERSION_OFFSET 0x7e
229 #define VALID_EEPROM_VERSION 1
230
231 // =================================================================================
232 // TX / RX ring descriptor format
233 // =================================================================================
234
235 //
236 // TX descriptor format, Tx ring, Atim ring & Priority Ring
237 //
238 typedef struct _TXD_STRUC {
239 // Word 0
240 #ifdef BIG_ENDIAN
241 ULONG CipherAlg:3;
242 ULONG Rsv1:1; //RTS:1;
243 ULONG DataByteCnt:12;
244 ULONG RetryMd:1;
245 ULONG IFS:2;
246 ULONG CipherOwn:1;
247 ULONG Ofdm:1;
248 ULONG Timestamp:1;
249 ULONG ACK:1;
250 ULONG MoreFrag:1; // More fragment following this tx ring
251 ULONG RetryCount:3; // Retry result
252 ULONG TxResult:3; // Filled by MAC ASIC
253 ULONG Valid:1; // Entry valid bit
254 ULONG Owner:1; // Descriptor owner bit
255 #else
256 ULONG Owner:1; // Descriptor owner bit
257 ULONG Valid:1; // Entry valid bit
258 ULONG TxResult:3; // Filled by MAC ASIC
259 ULONG RetryCount:3; // Retry result
260 ULONG MoreFrag:1; // More fragment following this tx ring
261 ULONG ACK:1;
262 ULONG Timestamp:1;
263 ULONG Ofdm:1;
264 ULONG CipherOwn:1;
265 ULONG IFS:2;
266 ULONG RetryMd:1;
267 ULONG DataByteCnt:12;
268 ULONG Rsv1:1; //RTS:1;
269 ULONG CipherAlg:3;
270 #endif
271
272 // Word 1
273 ULONG BufferAddressPa;
274
275 // Word 2
276 #ifdef BIG_ENDIAN
277 ULONG Rsv2:16;
278 ULONG CWmax:4;
279 ULONG CWmin:4;
280 ULONG Aifs:2;
281 ULONG IvOffset:6;
282 #else
283 ULONG IvOffset:6;
284 ULONG Aifs:2;
285 ULONG CWmin:4;
286 ULONG CWmax:4;
287 ULONG Rsv2:16;
288 #endif
289
290 // Word 3
291 ULONG PlcpSignal:8;
292 ULONG PlcpService:8;
293 ULONG PlcpLengthLow:8;
294 ULONG PlcpLengthHigh:8;
295
296 // Word 4
297 ULONG Iv;
298
299 // Word 5
300 ULONG Eiv;
301
302 // Word 6-9
303 UCHAR Key[16];
304
305 // Word 10 - 11 Reserved, not necessary to put into the structure.
306 #ifdef BIG_ENDIAN
307 ULONG Rsv3:24;
308 ULONG TxRate:7; // for software use to track per-rate TX result, RATE_1, ...
309 ULONG RTS:1;
310 #else
311 ULONG RTS:1;
312 ULONG TxRate:7; // software use only. keep record of the Tx rate, RATE_1,...
313 ULONG Rsv3:24;
314 #endif
315 } TXD_STRUC, *PTXD_STRUC;
316
317 //
318 // Rx descriptor format, Rx Ring
319 //
320 typedef struct _RXD_STRUC {
321 // Word 0
322 #ifdef BIG_ENDIAN
323 ULONG CipherAlg:3;
324 ULONG Rsv1:1; // Drop:1; // Drop this frame after NULL cipher operation
325 ULONG DataByteCnt:12;
326 ULONG IvOffset:6;
327 ULONG IcvError:1;
328 ULONG CipherOwner:1;
329 ULONG PhyErr:1;
330 ULONG Ofdm:1;
331 ULONG Crc:1;
332 ULONG MyBss:1;
333 ULONG Bcast:1;
334 ULONG Mcast:1;
335 ULONG U2M:1;
336 ULONG Owner:1;
337 #else
338 ULONG Owner:1;
339 ULONG U2M:1;
340 ULONG Mcast:1;
341 ULONG Bcast:1;
342 ULONG MyBss:1;
343 ULONG Crc:1;
344 ULONG Ofdm:1;
345 ULONG PhyErr:1;
346 ULONG CipherOwner:1;
347 ULONG IcvError:1;
348 ULONG IvOffset:6;
349 ULONG DataByteCnt:12;
350 ULONG Rsv1:1; // Drop:1; // Drop this frame after NULL cipher operation
351 ULONG CipherAlg:3;
352 #endif
353
354 // Word 1
355 ULONG BufferAddressPa;
356
357 // Word 2 - 3
358 UCHAR BBR0;
359 UCHAR BBR1; // suppose to read back RSSI
360 UCHAR TA[6];
361
362 // Word 4
363 ULONG Iv;
364
365 // Word 5
366 ULONG Eiv;
367
368 // Word 6-9
369 UCHAR Key[16];
370
371 // Word 10 - 11 Reserved, not necessary to put into the structure.
372 #ifdef BIG_ENDIAN
373 ULONG Rsv2:31;
374 ULONG Drop:1; // Drop this frame after NULL cipher operation
375 #else
376 ULONG Drop:1; // Drop this frame after NULL cipher operation
377 ULONG Rsv2:31;
378 #endif
379 } RXD_STRUC, *PRXD_STRUC;
380
381 // =================================================================================
382 // CSR Registers
383 // =================================================================================
384
385 //
386 // CSR1: System control register
387 //
388 typedef union _CSR1_STRUC {
389 struct {
390 #ifdef BIG_ENDIAN
391 ULONG Rsvd1:29;
392 ULONG HostReady:1; // Host is ready after initialization, 1: ready
393 ULONG BbpReset:1; // Hardware reset BBP
394 ULONG SoftReset:1; // Software reset bit, 1: reset, 0: normal
395 #else
396 ULONG SoftReset:1; // Software reset bit, 1: reset, 0: normal
397 ULONG BbpReset:1; // Hardware reset BBP
398 ULONG HostReady:1; // Host is ready after initialization, 1: ready
399 ULONG Rsvd1:29;
400 #endif
401 } field;
402 ULONG word;
403 } CSR1_STRUC, *PCSR1_STRUC;
404
405 //
406 // CSR3: STA MAC register 0
407 //
408 typedef union _CSR3_STRUC {
409 struct {
410 #ifdef BIG_ENDIAN
411 UCHAR Byte3; // MAC address byte 3
412 UCHAR Byte2; // MAC address byte 2
413 UCHAR Byte1; // MAC address byte 1
414 UCHAR Byte0; // MAC address byte 0
415 #else
416 UCHAR Byte0; // MAC address byte 0
417 UCHAR Byte1; // MAC address byte 1
418 UCHAR Byte2; // MAC address byte 2
419 UCHAR Byte3; // MAC address byte 3
420 #endif
421 } field;
422 ULONG word;
423 } CSR3_STRUC, *PCSR3_STRUC;
424
425 //
426 // CSR4: STA MAC register 1
427 //
428 typedef union _CSR4_STRUC {
429 struct {
430 #ifdef BIG_ENDIAN
431 UCHAR Rsvd1;
432 UCHAR Rsvd0;
433 UCHAR Byte5; // MAC address byte 5
434 UCHAR Byte4; // MAC address byte 4
435 #else
436 UCHAR Byte4; // MAC address byte 4
437 UCHAR Byte5; // MAC address byte 5
438 UCHAR Rsvd0;
439 UCHAR Rsvd1;
440 #endif
441 } field;
442 ULONG word;
443 } CSR4_STRUC, *PCSR4_STRUC;
444
445 //
446 // CSR5: BSSID register 0
447 //
448 typedef union _CSR5_STRUC {
449 struct {
450 #ifdef BIG_ENDIAN
451 UCHAR Byte3; // BSSID byte 3
452 UCHAR Byte2; // BSSID byte 2
453 UCHAR Byte1; // BSSID byte 1
454 UCHAR Byte0; // BSSID byte 0
455 #else
456 UCHAR Byte0; // BSSID byte 0
457 UCHAR Byte1; // BSSID byte 1
458 UCHAR Byte2; // BSSID byte 2
459 UCHAR Byte3; // BSSID byte 3
460 #endif
461 } field;
462 ULONG word;
463 } CSR5_STRUC, *PCSR5_STRUC;
464
465 //
466 // CSR6: BSSID register 1
467 //
468 typedef union _CSR6_STRUC {
469 struct {
470 #ifdef BIG_ENDIAN
471 UCHAR Rsvd1;
472 UCHAR Rsvd0;
473 UCHAR Byte5; // BSSID byte 5
474 UCHAR Byte4; // BSSID byte 4
475 #else
476 UCHAR Byte4; // BSSID byte 4
477 UCHAR Byte5; // BSSID byte 5
478 UCHAR Rsvd0;
479 UCHAR Rsvd1;
480 #endif
481 } field;
482 ULONG word;
483 } CSR6_STRUC, *PCSR6_STRUC;
484
485 //
486 // CSR7: Interrupt source register
487 // Write one to clear corresponding bit
488 //
489 typedef union _CSR7_STRUC {
490 struct {
491 #ifdef BIG_ENDIAN
492 ULONG Rsvd:12;
493 ULONG Timecsr3Expired:1; // TIMECSR3 hardware timer expired (for 802.1H quiet period)
494 ULONG Uart2RxBufferError:1; // UART2 RX buffer error
495 ULONG Uart2TxBufferError:1; // UART2 TX buffer error
496 ULONG Uart2IdleThreshold:1; // UART2 IDLE over threshold
497 ULONG Uart2RxThreshold:1; // UART2 RX reaches threshold
498 ULONG Uart2TxThreshold:1; // UART2 TX reaches threshold
499 ULONG UartRxBufferError:1; // UART1 RX buffer error
500 ULONG UartTxBufferError:1; // UART1 TX buffer error
501 ULONG UartIdleThreshold:1; // UART1 IDLE over threshold
502 ULONG UartRxThreshold:1; // UART1 RX reaches threshold
503 ULONG UartTxThreshold:1; // UART1 TX reaches threshold
504 ULONG EncryptionDone:1; // Encryption done interrupt
505 ULONG DecryptionDone:1; // Decryption done interrupt
506 ULONG RxDone:1; // Receive done interrupt
507 ULONG PrioRingTxDone:1; // Priority ring transmit done interrupt
508 ULONG AtimRingTxDone:1; // Atim ring transmit done interrupt
509 ULONG TxRingTxDone:1; // Tx ring transmit done interrupt
510 ULONG TatimwExpire:1; // Timer of atim window expired interrupt
511 ULONG TwakeExpire:1; // Wakeup timer expired interrupt
512 ULONG TbcnExpire:1; // Beacon timer expired interrupt
513 #else
514 ULONG TbcnExpire:1; // Beacon timer expired interrupt
515 ULONG TwakeExpire:1; // Wakeup timer expired interrupt
516 ULONG TatimwExpire:1; // Timer of atim window expired interrupt
517 ULONG TxRingTxDone:1; // Tx ring transmit done interrupt
518 ULONG AtimRingTxDone:1; // Atim ring transmit done interrupt
519 ULONG PrioRingTxDone:1; // Priority ring transmit done interrupt
520 ULONG RxDone:1; // Receive done interrupt
521 ULONG DecryptionDone:1; // Decryption done interrupt
522 ULONG EncryptionDone:1; // Encryption done interrupt
523 ULONG UartTxThreshold:1; // UART1 TX reaches threshold
524 ULONG UartRxThreshold:1; // UART1 RX reaches threshold
525 ULONG UartIdleThreshold:1; // UART1 IDLE over threshold
526 ULONG UartTxBufferError:1; // UART1 TX buffer error
527 ULONG UartRxBufferError:1; // UART1 RX buffer error
528 ULONG Uart2TxThreshold:1; // UART2 TX reaches threshold
529 ULONG Uart2RxThreshold:1; // UART2 RX reaches threshold
530 ULONG Uart2IdleThreshold:1; // UART2 IDLE over threshold
531 ULONG Uart2TxBufferError:1; // UART2 TX buffer error
532 ULONG Uart2RxBufferError:1; // UART2 RX buffer error
533 ULONG Timecsr3Expired:1; // TIMECSR3 hardware timer expired (for 802.1H quiet period)
534 ULONG Rsvd:12;
535 #endif
536 } field;
537 ULONG word;
538 } CSR7_STRUC, *PCSR7_STRUC, INTSRC_STRUC, *PINTSRC_STRUC;
539
540 //
541 // CSR8: Interrupt Mask register
542 // Write one to mask off interrupt
543 //
544 typedef union _CSR8_STRUC {
545 struct {
546 #ifdef BIG_ENDIAN
547 ULONG Rsvd:12;
548 ULONG Timecsr3Expired:1; // TIMECSR3 hardware timer expired (for 802.1H quiet period)
549 ULONG Uart2RxBufferError:1; // UART2 RX buffer error
550 ULONG Uart2TxBufferError:1; // UART2 TX buffer error
551 ULONG Uart2IdleThreshold:1; // UART2 IDLE over threshold
552 ULONG Uart2RxThreshold:1; // UART2 RX reaches threshold
553 ULONG Uart2TxThreshold:1; // UART2 TX reaches threshold
554 ULONG UartRxBufferError:1; // UART1 RX buffer error
555 ULONG UartTxBufferError:1; // UART1 TX buffer error
556 ULONG UartIdleThreshold:1; // UART1 IDLE over threshold
557 ULONG UartRxThreshold:1; // UART1 RX reaches threshold
558 ULONG UartTxThreshold:1; // UART1 TX reaches threshold
559 ULONG EncryptionDone:1; // Encryption done interrupt
560 ULONG DecryptionDone:1; // Decryption done interrupt
561 ULONG RxDone:1; // Receive done interrupt mask
562 ULONG PrioRingTxDone:1; // Priority ring transmit done interrupt mask
563 ULONG AtimRingTxDone:1; // Atim ring transmit done interrupt mask
564 ULONG TxRingTxDone:1; // Tx ring transmit done interrupt mask
565 ULONG TatimwExpire:1; // Timer of atim window expired interrupt mask
566 ULONG TwakeExpire:1; // Wakeup timer expired interrupt mask
567 ULONG TbcnExpire:1; // Beacon timer expired interrupt mask
568 #else
569 ULONG TbcnExpire:1; // Beacon timer expired interrupt mask
570 ULONG TwakeExpire:1; // Wakeup timer expired interrupt mask
571 ULONG TatimwExpire:1; // Timer of atim window expired interrupt mask
572 ULONG TxRingTxDone:1; // Tx ring transmit done interrupt mask
573 ULONG AtimRingTxDone:1; // Atim ring transmit done interrupt mask
574 ULONG PrioRingTxDone:1; // Priority ring transmit done interrupt mask
575 ULONG RxDone:1; // Receive done interrupt mask
576 ULONG DecryptionDone:1; // Decryption done interrupt
577 ULONG EncryptionDone:1; // Encryption done interrupt
578 ULONG UartTxThreshold:1; // UART1 TX reaches threshold
579 ULONG UartRxThreshold:1; // UART1 RX reaches threshold
580 ULONG UartIdleThreshold:1; // UART1 IDLE over threshold
581 ULONG UartTxBufferError:1; // UART1 TX buffer error
582 ULONG UartRxBufferError:1; // UART1 RX buffer error
583 ULONG Uart2TxThreshold:1; // UART2 TX reaches threshold
584 ULONG Uart2RxThreshold:1; // UART2 RX reaches threshold
585 ULONG Uart2IdleThreshold:1; // UART2 IDLE over threshold
586 ULONG Uart2TxBufferError:1; // UART2 TX buffer error
587 ULONG Uart2RxBufferError:1; // UART2 RX buffer error
588 ULONG Timecsr3Expired:1; // TIMECSR3 hardware timer expired (for 802.1H quiet period)
589 ULONG Rsvd:12;
590 #endif
591 } field;
592 ULONG word;
593 } CSR8_STRUC, *PCSR8_STRUC, INTMSK_STRUC, *PINTMSK_STRUC;
594
595 //
596 // CSR9: Maximum frame length register
597 //
598 typedef union _CSR9_STRUC {
599 struct {
600 #ifdef BIG_ENDIAN
601 ULONG Rsvd1:20;
602 ULONG MaxFrameUnit:5; // Maximum frame legth in 128B unit, default is 12 = 0xC.
603 ULONG Rsvd0:7;
604 #else
605 ULONG Rsvd0:7;
606 ULONG MaxFrameUnit:5; // Maximum frame legth in 128B unit, default is 12 = 0xC.
607 ULONG Rsvd1:20;
608 #endif
609 } field;
610 ULONG word;
611 } CSR9_STRUC, *PCSR9_STRUC;
612
613 //
614 // SECCSR0: WEP control register
615 //
616 typedef union _SECCSR0_STRUC {
617 struct {
618 #ifdef BIG_ENDIAN
619 ULONG DescAddress:30; // Descriptor physical address of frame in one-shot-mode.
620 ULONG OneShotMode:1; // 1: One shot only mode, 0: ring mode
621 ULONG KickDecypt:1; // Kick decryption engine, self-clear
622 #else
623 ULONG KickDecypt:1; // Kick decryption engine, self-clear
624 ULONG OneShotMode:1; // 1: One shot only mode, 0: ring mode
625 ULONG DescAddress:30; // Descriptor physical address of frame in one-shot-mode.
626 #endif
627 } field;
628 ULONG word;
629 } SECCSR0_STRUC, *PSECCSR0_STRUC;
630
631 //
632 // SECCSR1: WEP control register
633 //
634 typedef union _SECCSR1_STRUC {
635 struct {
636 #ifdef BIG_ENDIAN
637 ULONG DescAddress:30; // Descriptor physical address of frame in one-shot-mode.
638 ULONG OneShotMode:1; // 1: One shot only mode, 0: ring mode
639 ULONG KickEncypt:1; // Kick encryption engine, self-clear
640 #else
641 ULONG KickEncypt:1; // Kick encryption engine, self-clear
642 ULONG OneShotMode:1; // 1: One shot only mode, 0: ring mode
643 ULONG DescAddress:30; // Descriptor physical address of frame in one-shot-mode.
644 #endif
645 } field;
646 ULONG word;
647 } SECCSR1_STRUC, *PSECCSR1_STRUC;
648
649 //
650 // CSR11: Back-Off control register
651 //
652 typedef union _CSR11_STRUC {
653 struct {
654 #ifdef BIG_ENDIAN
655 ULONG ShortRetry:8; // Short retry count
656 ULONG LongRetry:8; // Long retry count
657 ULONG Rsvd:2;
658 ULONG CWSelect:1; // 1: CWmin/CWmax select from register, 0: select from TxD
659 ULONG SlotTime:5; // Slot time, default is 20us for 802.11B
660 ULONG CWMax:4; // Bit for Cwmax, default Cwmax is 1023 (2^10 - 1).
661 ULONG CWMin:4; // Bit for Cwmin. default Cwmin is 31 (2^5 - 1).
662 #else
663 ULONG CWMin:4; // Bit for Cwmin. default Cwmin is 31 (2^5 - 1).
664 ULONG CWMax:4; // Bit for Cwmax, default Cwmax is 1023 (2^10 - 1).
665 ULONG SlotTime:5; // Slot time, default is 20us for 802.11B
666 ULONG CWSelect:1; // 1: CWmin/Cwmax select from register, 0:select from TxD
667 ULONG Rsvd:2;
668 ULONG LongRetry:8; // Long retry count
669 ULONG ShortRetry:8; // Short retry count
670 #endif
671 } field;
672 ULONG word;
673 } CSR11_STRUC, *PCSR11_STRUC;
674
675 //
676 // CSR12: Synchronization configuration register 0
677 // All uint in 1/16 TU
678 //
679 typedef union _CSR12_STRUC {
680 struct {
681 #ifdef BIG_ENDIAN
682 ULONG CfpMaxDuration:16; // Beacon interval, default is 100 TU
683 ULONG BeaconInterval:16; // CFP maximum duration, default is 100 TU
684 #else
685 ULONG BeaconInterval:16; // CFP maximum duration, default is 100 TU
686 ULONG CfpMaxDuration:16; // Beacon interval, default is 100 TU
687 #endif
688 } field;
689 ULONG word;
690 } CSR12_STRUC, *PCSR12_STRUC;
691
692 //
693 // CSR13: Synchronization configuration register 1
694 // All uint in 1/16 TU
695 //
696 typedef union _CSR13_STRUC {
697 struct {
698 #ifdef BIG_ENDIAN
699 ULONG Rsvd:8;
700 ULONG CfpPeriod:8; // CFP period, default is 0 TU
701 ULONG AtimwDuration:16; // ATIM window duration, default is 10 TU
702 #else
703 ULONG AtimwDuration:16; // ATIM window duration, default is 10 TU
704 ULONG CfpPeriod:8; // CFP period, default is 0 TU
705 ULONG Rsvd:8;
706 #endif
707 } field;
708 ULONG word;
709 } CSR13_STRUC, *PCSR13_STRUC;
710
711 //
712 // CSR14: Synchronization control register
713 //
714 typedef union _CSR14_STRUC {
715 struct {
716 #ifdef BIG_ENDIAN
717 ULONG TbcnPreload:16; // Tbcn preload value
718 ULONG CfpCntPreload:8; // Cfp count preload value
719 ULONG Rsvd:1;
720 ULONG BeaconGen:1; // Enable beacon generator
721 ULONG Tatimw:1; // Enable Tatimw & ATIM window switching
722 ULONG Tcfp:1; // Enable Tcfp & CFP / CP switching
723 ULONG Tbcn:1; // Enable Tbcn with reload value
724 ULONG TsfSync:2; // Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
725 ULONG TsfCount:1; // Enable TSF auto counting
726 #else
727 ULONG TsfCount:1; // Enable TSF auto counting
728 ULONG TsfSync:2; // Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
729 ULONG Tbcn:1; // Enable Tbcn with reload value
730 ULONG Tcfp:1; // Enable Tcfp & CFP / CP switching
731 ULONG Tatimw:1; // Enable Tatimw & ATIM window switching
732 ULONG BeaconGen:1; // Enable beacon generator
733 ULONG Rsvd:1;
734 ULONG CfpCntPreload:8; // Cfp count preload value
735 ULONG TbcnPreload:16; // Tbcn preload value
736 #endif
737 } field;
738 ULONG word;
739 } CSR14_STRUC, *PCSR14_STRUC;
740
741 //
742 // CSR15: Synchronization status register
743 //
744 typedef union _CSR15_STRUC {
745 struct {
746 #ifdef BIG_ENDIAN
747 ULONG Rsvd:29;
748 ULONG BeaconSent:1; // Beacon sent
749 ULONG Atimw:1; // Atim window period
750 ULONG Cfp:1; // CFP period
751 #else
752 ULONG Cfp:1; // CFP period
753 ULONG Atimw:1; // Atim window period
754 ULONG BeaconSent:1; // Beacon sent
755 ULONG Rsvd:29;
756 #endif
757 } field;
758 ULONG word;
759 } CSR15_STRUC, *PCSR15_STRUC;
760
761 //
762 // CSR18: IFS Timer register 0
763 //
764 typedef union _CSR18_STRUC {
765 struct {
766 #ifdef BIG_ENDIAN
767 ULONG Rsvd1:7;
768 ULONG PIFS:9; // PIFS, default is 30 TU
769 ULONG Rsvd0:7;
770 ULONG SIFS:9; // SIFS, default is 10 TU
771 #else
772 ULONG SIFS:9; // SIFS, default is 10 TU
773 ULONG Rsvd0:7;
774 ULONG PIFS:9; // PIFS, default is 30 TU
775 ULONG Rsvd1:7;
776 #endif
777 } field;
778 ULONG word;
779 } CSR18_STRUC, *PCSR18_STRUC;
780
781 //
782 // CSR19: IFS Timer register 1
783 //
784 typedef union _CSR19_STRUC {
785 struct {
786 #ifdef BIG_ENDIAN
787 ULONG EIFS:16; // EIFS, default is 364 TU
788 ULONG DIFS:16; // DIFS, default is 50 TU
789 #else
790 ULONG DIFS:16; // DIFS, default is 50 TU
791 ULONG EIFS:16; // EIFS, default is 364 TU
792 #endif
793 } field;
794 ULONG word;
795 } CSR19_STRUC, *PCSR19_STRUC;
796
797 //
798 // CSR20: Wakeup timer register
799 //
800 typedef union _CSR20_STRUC {
801 struct {
802 #ifdef BIG_ENDIAN
803 ULONG Rsvd:7;
804 ULONG AutoWake:1; // Enable auto wakeup / sleep mechanism
805 ULONG NumBcnBeforeWakeup:8; // Number of beacon before wakeup
806 ULONG DelayAfterBcn:16; // Delay after Tbcn expired in units of 1/16 TU
807 #else
808 ULONG DelayAfterBcn:16; // Delay after Tbcn expired in units of 1/16 TU
809 ULONG NumBcnBeforeWakeup:8; // Number of beacon before wakeup
810 ULONG AutoWake:1; // Enable auto wakeup / sleep mechanism
811 ULONG Rsvd:7;
812 #endif
813 } field;
814 ULONG word;
815 } CSR20_STRUC, *PCSR20_STRUC;
816
817 //
818 // CSR21: EEPROM control register
819 //
820 typedef union _CSR21_STRUC {
821 struct {
822 #ifdef BIG_ENDIAN
823 ULONG Rsvd:26;
824 ULONG Type:1; // 1: 93C46, 0:93C66
825 ULONG EepromDO:1;
826 ULONG EepromDI:1;
827 ULONG EepromCS:1;
828 ULONG EepromSK:1;
829 ULONG Reload:1; // Reload EEPROM content, write one to reload, self-cleared.
830 #else
831 ULONG Reload:1; // Reload EEPROM content, write one to reload, self-cleared.
832 ULONG EepromSK:1;
833 ULONG EepromCS:1;
834 ULONG EepromDI:1;
835 ULONG EepromDO:1;
836 ULONG Type:1; // 1: 93C46, 0:93C66
837 ULONG Rsvd:26;
838 #endif
839 } field;
840 ULONG word;
841 } CSR21_STRUC, *PCSR21_STRUC;
842
843 //
844 // CSR22: CFP control register
845 //
846 typedef union _CSR22_STRUC {
847 struct {
848 #ifdef BIG_ENDIAN
849 ULONG Rsvd:15;
850 ULONG ReloadCfpDurRemain:1; // Reload CFP duration remain, write one to reload, self-cleared
851 ULONG CfpDurRemain:16; // CFP duration remain, in units of TU
852 #else
853 ULONG CfpDurRemain:16; // CFP duration remain, in units of TU
854 ULONG ReloadCfpDurRemain:1; // Reload CFP duration remain, write one to reload, self-cleared
855 ULONG Rsvd:15;
856 #endif
857 } field;
858 ULONG word;
859 } CSR22_STRUC, *PCSR22_STRUC;
860
861 // =================================================================================
862 // TX / RX Registers
863 // =================================================================================
864
865 //
866 // TXCSR0 <0x0060> : TX Control Register
867 //
868 typedef union _TXCSR0_STRUC {
869 struct {
870 #ifdef BIG_ENDIAN
871 ULONG Rsvd:28;
872 ULONG Abort:1; // Abort all transmit related ring operation
873 ULONG KickPrio:1; // Kick priority ring
874 ULONG KickAtim:1; // Kick ATIM ring
875 ULONG KickTx:1; // Kick Tx ring
876 #else
877 ULONG KickTx:1; // Kick Tx ring
878 ULONG KickAtim:1; // Kick ATIM ring
879 ULONG KickPrio:1; // Kick priority ring
880 ULONG Abort:1; // Abort all transmit related ring operation
881 ULONG Rsvd:28;
882 #endif
883 } field;
884 ULONG word;
885 } TXCSR0_STRUC, *PTXCSR0_STRUC;
886
887 //
888 // TXCSR1 <0x0064> : TX Configuration Register
889 //
890 typedef union _TXCSR1_STRUC {
891 struct {
892 #ifdef BIG_ENDIAN
893 ULONG Reserved:7;
894 ULONG AutoResponder:1; // enable auto responder which include ACK & CTS
895 ULONG TsFOffset:6; // Insert Tsf offset
896 ULONG AckConsumeTime:9; // ACK consume time, default = SIFS + ACKtime @ 1Mbps
897 ULONG AckTimeOut:9; // Ack timeout, default = SIFS + 2*SLOT_ACKtime @ 1Mbps
898 #else
899 ULONG AckTimeOut:9; // Ack timeout, default = SIFS + 2*SLOT_ACKtime @ 1Mbps
900 ULONG AckConsumeTime:9; // ACK consume time, default = SIFS + ACKtime @ 1Mbps
901 ULONG TsFOffset:6; // Insert Tsf offset
902 ULONG AutoResponder:1; // enable auto responder which include ACK & CTS
903 ULONG Reserved:7;
904 #endif
905 } field;
906 ULONG word;
907 } TXCSR1_STRUC, *PTXCSR1_STRUC;
908
909 //
910 // TXCSR2: Tx descriptor configuration register
911 //
912 typedef union _TXCSR2_STRUC {
913 struct {
914 #ifdef BIG_ENDIAN
915 ULONG NumPrioD:8; // Number of PriorityD in ring
916 ULONG NumAtimD:8; // Number of AtimD in ring
917 ULONG NumTxD:8; // Number of TxD in ring
918 ULONG TxDSize:8; // Tx descriptor size, default is 48
919 #else
920 ULONG TxDSize:8; // Tx descriptor size, default is 48
921 ULONG NumTxD:8; // Number of TxD in ring
922 ULONG NumAtimD:8; // Number of AtimD in ring
923 ULONG NumPrioD:8; // Number of PriorityD in ring
924 #endif
925 } field;
926 ULONG word;
927 } TXCSR2_STRUC, *PTXCSR2_STRUC;
928
929 //
930 // TXCSR7: Auto responder control register
931 //
932 typedef union _TXCSR7_STRUC {
933 struct {
934 #ifdef BIG_ENDIAN
935 ULONG Rsvd:31;
936 ULONG ARPowerManage:1; // Auto responder power management bit
937 #else
938 ULONG ARPowerManage:1; // Auto responder power management bit
939 ULONG Rsvd:31;
940 #endif
941 } field;
942 ULONG word;
943 } TXCSR7_STRUC, *PTXCSR7_STRUC;
944
945 //
946 // TXCSR8: CCK Tx BBP register
947 //
948 typedef union _TXCSR8_STRUC {
949 struct {
950 #ifdef BIG_ENDIAN
951 ULONG CckLenHigh:8; // BBP length high byte address for CCK
952 ULONG CckLenLow:8; // BBP length low byte address for CCK
953 ULONG CckService:8; // BBP service field address for CCK
954 ULONG CckSignal:8; // BBP signal field address for CCK
955 #else
956 ULONG CckSignal:8; // BBP signal field address for CCK
957 ULONG CckService:8; // BBP service field address for CCK
958 ULONG CckLenLow:8; // BBP length low byte address for CCK
959 ULONG CckLenHigh:8; // BBP length high byte address for CCK
960 #endif
961 } field;
962 ULONG word;
963 } TXCSR8_STRUC, *PTXCSR8_STRUC;
964
965 //
966 // TXCSR9: OFDM Tx BBP register
967 //
968 typedef union _TXCSR9_STRUC {
969 struct {
970 #ifdef BIG_ENDIAN
971 ULONG OfdmLenHigh:8; // BBP length high byte address for OFDM
972 ULONG OfdmLenLow:8; // BBP length low byte address for OFDM
973 ULONG OfdmService:8; // BBP service field address for OFDM
974 ULONG OfdmRate:8; // BBP rate field address for OFDM
975 #else
976 ULONG OfdmRate:8; // BBP rate field address for OFDM
977 ULONG OfdmService:8; // BBP service field address for OFDM
978 ULONG OfdmLenLow:8; // BBP length low byte address for OFDM
979 ULONG OfdmLenHigh:8; // BBP length high byte address for OFDM
980 #endif
981 } field;
982 ULONG word;
983 } TXCSR9_STRUC, *PTXCSR9_STRUC;
984
985 //
986 // RXCSR0 <0x0080> : RX Control Register
987 //
988 typedef union _RXCSR0_STRUC {
989 struct {
990 #ifdef BIG_ENDIAN
991 ULONG Reserved:20;
992 ULONG EnableQos:1; // 1: accept QOS data frame format and parse the QOS field
993 ULONG DropBcast:1; // Drop broadcast frames
994 ULONG DropMcast:1; // Drop multicast frames
995 ULONG PassPlcp:1; // Pass all receive packet with 4 bytes PLCP attached
996 ULONG PassCRC:1; // Pass all receive packet to host with CRC attached
997 ULONG DropVersionErr:1; // Drop version error frame
998 ULONG DropToDs:1; // Drop fram ToDs bit is true
999 ULONG DropNotToMe:1; // Drop not to me unicast frame
1000 ULONG DropControl:1; // Drop control frame
1001 ULONG DropPhysical:1; // Drop physical error
1002 ULONG DropCRC:1; // Drop CRC error
1003 ULONG DisableRx:1; // Disable Rx engine
1004 #else
1005 ULONG DisableRx:1; // Disable Rx engine
1006 ULONG DropCRC:1; // Drop CRC error
1007 ULONG DropPhysical:1; // Drop physical error
1008 ULONG DropControl:1; // Drop control frame
1009 ULONG DropNotToMe:1; // Drop not to me unicast frame
1010 ULONG DropToDs:1; // Drop fram ToDs bit is true
1011 ULONG DropVersionErr:1; // Drop version error frame
1012 ULONG PassCRC:1; // Pass all receive packet to host with CRC attached
1013 ULONG PassPlcp:1; // Pass all receive packet with 4 bytes PLCP attached
1014 ULONG DropMcast:1; // Drop multicast frames
1015 ULONG DropBcast:1; // Drop broadcast frames
1016 ULONG EnableQos:1; // 1: accept QOS data frame format and parse the QOS field
1017 ULONG Reserved:20;
1018 #endif
1019 } field;
1020 ULONG word;
1021 } RXCSR0_STRUC, *PRXCSR0_STRUC;
1022
1023 //
1024 // RXCSR1: RX descriptor configuration register
1025 //
1026 typedef union _RXCSR1_STRUC {
1027 struct {
1028 #ifdef BIG_ENDIAN
1029 ULONG Rsvd:16;
1030 ULONG NumRxD:8; // Number of RxD in ring.
1031 ULONG RxDSize:8; // Rx descriptor size, default is 32B.
1032 #else
1033 ULONG RxDSize:8; // Rx descriptor size, default is 32B.
1034 ULONG NumRxD:8; // Number of RxD in ring.
1035 ULONG Rsvd:16;
1036 #endif
1037 } field;
1038 ULONG word;
1039 } RXCSR1_STRUC, *PRXCSR1_STRUC;
1040
1041 //
1042 // RXCSR3: BBP ID register for Rx operation
1043 //
1044 typedef union _RXCSR3_STRUC {
1045 struct {
1046 #ifdef BIG_ENDIAN
1047 ULONG ValidBbp3:1; // BBP register 3 ID is valid or not
1048 ULONG IdBbp3:7; // BBP register 3 ID
1049 ULONG ValidBbp2:1; // BBP register 2 ID is valid or not
1050 ULONG IdBbp2:7; // BBP register 2 ID
1051 ULONG ValidBbp1:1; // BBP register 1 ID is valid or not
1052 ULONG IdBbp1:7; // BBP register 1 ID
1053 ULONG ValidBbp0:1; // BBP register 0 ID is valid or not
1054 ULONG IdBbp0:7; // BBP register 0 ID
1055 #else
1056 ULONG IdBbp0:7; // BBP register 0 ID
1057 ULONG ValidBbp0:1; // BBP register 0 ID is valid or not
1058 ULONG IdBbp1:7; // BBP register 1 ID
1059 ULONG ValidBbp1:1; // BBP register 1 ID is valid or not
1060 ULONG IdBbp2:7; // BBP register 2 ID
1061 ULONG ValidBbp2:1; // BBP register 2 ID is valid or not
1062 ULONG IdBbp3:7; // BBP register 3 ID
1063 ULONG ValidBbp3:1; // BBP register 3 ID is valid or not
1064 #endif
1065 } field;
1066 ULONG word;
1067 } RXCSR3_STRUC, *PRXCSR3_STRUC;
1068 #if 0
1069 //
1070 // RXCSR4: BBP ID register for Rx operation
1071 //
1072 typedef union _RXCSR4_STRUC {
1073 struct {
1074 ULONG IdBbp4:7; // BBP register 4 ID
1075 ULONG ValidBbp4:1; // BBP register 4 ID is valid or not
1076 ULONG IdBbp5:7; // BBP register 5 ID
1077 ULONG ValidBbp5:1; // BBP register 5 ID is valid or not
1078 ULONG Rsvd:16;
1079 } field;
1080 ULONG word;
1081 } RXCSR4_STRUC, *PRXCSR4_STRUC;
1082
1083 //
1084 // ARCSR0: Auto Responder PLCP value register 0
1085 //
1086 typedef union _ARCSR0_STRUC {
1087 struct {
1088 ULONG ArBbpData0:8; // Auto responder BBP register 0 data
1089 ULONG ArBbpId0:8; // Auto responder BBP register 0 Id
1090 ULONG ArBbpData1:8; // Auto responder BBP register 1 data
1091 ULONG ArBbpId1:8; // Auto responder BBP register 1 Id
1092 } field;
1093 ULONG word;
1094 } ARCSR0_STRUC, *PARCSR0_STRUC;
1095
1096 //
1097 // ARCSR0: Auto Responder PLCP value register 1
1098 //
1099 typedef union _ARCSR1_STRUC {
1100 struct {
1101 ULONG ArBbpData2:8; // Auto responder BBP register 2 data
1102 ULONG ArBbpId2:8; // Auto responder BBP register 2 Id
1103 ULONG ArBbpData3:8; // Auto responder BBP register 3 data
1104 ULONG ArBbpId3:8; // Auto responder BBP register 3 Id
1105 } field;
1106 ULONG word;
1107 } ARCSR1_STRUC, *PARCSR1_STRUC;
1108 #endif
1109 // =================================================================================
1110 // Miscellaneous Registers
1111 // =================================================================================
1112
1113 //
1114 // PCISR: PCI control register
1115 //
1116 typedef union _PCICSR_STRUC {
1117 struct {
1118 #ifdef BIG_ENDIAN
1119 ULONG Rsvd:22;
1120 ULONG WriteInvalid:1; // Enable memory write & invalid
1121 ULONG ReadMultiple:1; // Enable memory read multiple
1122 ULONG EnableClk:1; // Enable CLK_RUN, PCI clock can't going down to non-operational
1123 ULONG BurstLength:2; // PCI burst length
1124 // 01: 8DW, 10: 16DW, 11:32DW, default 00: 4DW
1125 ULONG TxThreshold:2; // Tx threshold in DW to start PCI access
1126 // 01: 1DW, 10: 4DW, 11: store & forward, default 00: 0DW
1127 ULONG RxThreshold:2; // Rx threshold in DW to start PCI access
1128 // 01: 8DW, 10: 4DW, 11: 32DW, default 00: 16DW
1129 ULONG BigEndian:1; // 1: big endian, 0: little endian
1130 #else
1131 ULONG BigEndian:1; // 1: big endian, 0: little endian
1132 ULONG RxThreshold:2; // Rx threshold in DW to start PCI access
1133 // 01: 8DW, 10: 4DW, 11: 32DW, default 00: 16DW
1134 ULONG TxThreshold:2; // Tx threshold in DW to start PCI access
1135 // 01: 1DW, 10: 4DW, 11: store & forward, default 00: 0DW
1136 ULONG BurstLength:2; // PCI burst length
1137 // 01: 8DW, 10: 16DW, 11:32DW, default 00: 4DW
1138 ULONG EnableClk:1; // Enable CLK_RUN, PCI clock can't going down to non-operational
1139 ULONG ReadMultiple:1; // Enable memory read multiple
1140 ULONG WriteInvalid:1; // Enable memory write & invalid
1141 ULONG Rsvd:22;
1142 #endif
1143 } field;
1144 ULONG word;
1145 } PCICSR_STRUC, *PPCICSR_STRUC;
1146
1147 //
1148 // PWRCSR0: Power mode configuration register
1149 // Driver did not control it for now.
1150
1151 //
1152 // PSCSR0: Power saving delay time register 0
1153 // Driver did not control it for now.
1154
1155 //
1156 // PSCSR1: Power saving delay time register 1
1157 // Driver did not control it for now.
1158
1159 //
1160 // PSCSR2: Power saving delay time register 2
1161 // Driver did not control it for now.
1162
1163 //
1164 // PSCSR3: Power saving delay time register 3
1165 // Driver did not control it for now.
1166
1167 //
1168 // PWRCSR1: Manual power control / status register
1169 //
1170 typedef union _PWRCSR1_STRUC {
1171 struct {
1172 #ifdef BIG_ENDIAN
1173 ULONG Rsvd:22;
1174 ULONG PutToSleep:1;
1175 ULONG RfCurrState:2;
1176 ULONG BbpCurrState:2;
1177 ULONG RfDesireState:2;
1178 ULONG BbpDesireState:2;
1179 ULONG SetState:1;
1180 #else
1181 ULONG SetState:1;
1182 ULONG BbpDesireState:2;
1183 ULONG RfDesireState:2;
1184 ULONG BbpCurrState:2;
1185 ULONG RfCurrState:2;
1186 ULONG PutToSleep:1;
1187 ULONG Rsvd:22;
1188 #endif
1189 } field;
1190 ULONG word;
1191 } PWRCSR1_STRUC, *PPWRCSR1_STRUC;
1192
1193 //
1194 // TIMECSR: Timer control register
1195 //
1196 typedef union _TIMECSR_STRUC {
1197 struct {
1198 #ifdef BIG_ENDIAN
1199 ULONG Rsvd:13;
1200 ULONG BeaconExpect:3; // Beacon expect window
1201 ULONG Us64Cnt:8; // 64 us timer count in units of 1 us timer
1202 ULONG UsCnt:8; // 1 us timer count in units of clock cycles
1203 #else
1204 ULONG UsCnt:8; // 1 us timer count in units of clock cycles
1205 ULONG Us64Cnt:8; // 64 us timer count in units of 1 us timer
1206 ULONG BeaconExpect:3; // Beacon expect window
1207 ULONG Rsvd:13;
1208 #endif
1209 } field;
1210 ULONG word;
1211 } TIMECSR_STRUC, *PTIMECSR_STRUC;
1212
1213 //
1214 // MACCSR0: MAC configuration register 0
1215 //
1216
1217 //
1218 // MACCSR1: MAC configuration register 1
1219 //
1220 typedef union _MACCSR1_STRUC {
1221 struct {
1222 #ifdef BIG_ENDIAN
1223 ULONG Rsvd:24;
1224 ULONG IntersilIF:1; // Intersil IF calibration pin
1225 ULONG LoopBack:2; // Loopback mode. 00: normal, 01: internal, 10: external, 11:rsvd.
1226 ULONG AutoRxBbp:1; // Auto Rx logic access BBP control register
1227 ULONG AutoTxBbp:1; // Auto Tx logic access BBP control register
1228 ULONG BbpRxResetMode:1; // Ralink BBP RX reset mode
1229 ULONG OneShotRxMode:1; // Enable one-shot Rx mode for debugging
1230 ULONG KickRx:1; // Kick one-shot Rx in one-shot Rx mode
1231 #else
1232 ULONG KickRx:1; // Kick one-shot Rx in one-shot Rx mode
1233 ULONG OneShotRxMode:1; // Enable one-shot Rx mode for debugging
1234 ULONG BbpRxResetMode:1; // Ralink BBP RX reset mode
1235 ULONG AutoTxBbp:1; // Auto Tx logic access BBP control register
1236 ULONG AutoRxBbp:1; // Auto Rx logic access BBP control register
1237 ULONG LoopBack:2; // Loopback mode. 00: normal, 01: internal, 10: external, 11:rsvd.
1238 ULONG IntersilIF:1; // Intersil IF calibration pin
1239 ULONG Rsvd:24;
1240 #endif
1241 } field;
1242 ULONG word;
1243 } MACCSR1_STRUC, *PMACCSR1_STRUC;
1244
1245 //
1246 // RALINKCSR: Ralink Rx auto-reset BBCR
1247 //
1248 typedef union _RALINKCSR_STRUC {
1249 struct {
1250 #ifdef BIG_ENDIAN
1251 ULONG ArBbpValid1:1; // Auto reset BBP register 1 is valid
1252 ULONG ArBbpId1:7; // Auto reset BBP register 1 Id
1253 ULONG ArBbpData1:8; // Auto reset BBP register 1 data
1254 ULONG ArBbpValid0:1; // Auto reset BBP register 0 is valid
1255 ULONG ArBbpId0:7; // Auto reset BBP register 0 Id
1256 ULONG ArBbpData0:8; // Auto reset BBP register 0 data
1257 #else
1258 ULONG ArBbpData0:8; // Auto reset BBP register 0 data
1259 ULONG ArBbpId0:7; // Auto reset BBP register 0 Id
1260 ULONG ArBbpValid0:1; // Auto reset BBP register 0 is valid
1261 ULONG ArBbpData1:8; // Auto reset BBP register 1 data
1262 ULONG ArBbpId1:7; // Auto reset BBP register 1 Id
1263 ULONG ArBbpValid1:1; // Auto reset BBP register 1 is valid
1264 #endif
1265 } field;
1266 ULONG word;
1267 } RALINKCSR_STRUC, *PRALINKCSR_STRUC;
1268
1269 //
1270 // BCNCSR: Beacon interval control register
1271 //
1272 typedef union _BCNCSR_STRUC {
1273 struct {
1274 #ifdef BIG_ENDIAN
1275 ULONG Rsvd:16;
1276 ULONG Plus:1; // plus or minus delta time value
1277 ULONG Mode:2; // please refer to ASIC specs.
1278 ULONG NumBcn:8; // Delta time value or number of beacon according to mode
1279 ULONG DeltaTime:4; // The delta time value
1280 ULONG Change:1; // Write one to change beacon interval
1281 #else
1282 ULONG Change:1; // Write one to change beacon interval
1283 ULONG DeltaTime:4; // The delta time value
1284 ULONG NumBcn:8; // Delta time value or number of beacon according to mode
1285 ULONG Mode:2; // please refer to ASIC specs.
1286 ULONG Plus:1; // plus or minus delta time value
1287 ULONG Rsvd:16;
1288 #endif
1289 } field;
1290 ULONG word;
1291 } BCNCSR_STRUC, *PBCNCSR_STRUC;
1292
1293 //
1294 // BBPCSR: BBP serial control register
1295 //
1296 typedef union _BBPCSR_STRUC {
1297 struct {
1298 #ifdef BIG_ENDIAN
1299 ULONG Rsvd:15;
1300 ULONG WriteControl:1; // 1: Write BBP, 0: Read BBP
1301 ULONG Busy:1; // 1: ASIC is busy execute BBP programming.
1302 ULONG RegNum:7; // Selected BBP register
1303 ULONG Value:8; // Register value to program into BBP
1304 #else
1305 ULONG Value:8; // Register value to program into BBP
1306 ULONG RegNum:7; // Selected BBP register
1307 ULONG Busy:1; // 1: ASIC is busy execute BBP programming.
1308 ULONG WriteControl:1; // 1: Write BBP, 0: Read BBP
1309 ULONG Rsvd:15;
1310 #endif
1311 } field;
1312 ULONG word;
1313 } BBPCSR_STRUC, *PBBPCSR_STRUC;
1314
1315 //
1316 // RFCSR: RF serial control register
1317 //
1318 typedef union _RFCSR_STRUC {
1319 struct {
1320 #ifdef BIG_ENDIAN
1321 ULONG Busy:1; // 1: ASIC is busy execute RF programming.
1322 ULONG PLL_LD:1; // RF PLL_LD status
1323 ULONG IFSelect:1; // 1: select IF to program, 0: select RF to program
1324 ULONG NumberOfBits:5; // Number of bits used in RFRegValue (I:20, RFMD:22)
1325 ULONG RFRegValue:24; // Register value (include register id) serial out to RF/IF chip.
1326 #else
1327 ULONG RFRegValue:24; // Register value (include register id) serial out to RF/IF chip.
1328 ULONG NumberOfBits:5; // Number of bits used in RFRegValue (I:20, RFMD:22)
1329 ULONG IFSelect:1; // 1: select IF to program, 0: select RF to program
1330 ULONG PLL_LD:1; // RF PLL_LD status
1331 ULONG Busy:1; // 1: ASIC is busy execute RF programming.
1332 #endif
1333 } field;
1334 ULONG word;
1335 } RFCSR_STRUC, *PRFCSR_STRUC;
1336
1337 //
1338 // LEDCSR: LED control register
1339 //
1340 typedef union _LEDCSR_STRUC {
1341 struct {
1342 #ifdef BIG_ENDIAN
1343 ULONG Rsvd:11;
1344 ULONG LedADefault:1; // LED A default value for "enable" state. 0: LED ON, 1: LED OFF
1345 ULONG LedBPolarity:1; // 0: active low, 1: active high
1346 ULONG LedAPolarity:1; // 0: active low, 1: active high
1347 ULONG LedB:1; // controlled by software, 1: ON, 0: OFF
1348 ULONG LedA:1; // indicate TX activity, 1: enable, 0: disable
1349 ULONG OffPeriod:8; // Off period, default 30ms
1350 ULONG OnPeriod:8; // On period, default 70ms
1351 #else
1352 ULONG OnPeriod:8; // On period, default 70ms
1353 ULONG OffPeriod:8; // Off period, default 30ms
1354 ULONG LedA:1; // indicate TX activity, 1: enable, 0: disable
1355 ULONG LedB:1; // controlled by software, 1: ON, 0: OFF
1356 ULONG LedAPolarity:1; // 0: active low, 1: active high
1357 ULONG LedBPolarity:1; // 0: active low, 1: active high
1358 ULONG LedADefault:1; // LED A default value for "enable" state. 0: LED ON, 1: LED OFF
1359 ULONG Rsvd:11;
1360 #endif
1361 } field;
1362 ULONG word;
1363 } LEDCSR_STRUC, *PLEDCSR_STRUC;
1364
1365 //
1366 // GPIOCSR: GPIO control register
1367 //
1368 typedef union _GPIOCSR_STRUC {
1369 struct {
1370 #ifdef BIG_ENDIAN
1371 ULONG Rsvd:16;
1372 ULONG Dir7:1;
1373 ULONG Dir6:1;
1374 ULONG Dir5:1;
1375 ULONG Dir4:1;
1376 ULONG Dir3:1;
1377 ULONG Dir2:1;
1378 ULONG Dir1:1;
1379 ULONG Dir0:1;
1380 ULONG Bit7:1;
1381 ULONG Bit6:1;
1382 ULONG Bit5:1;
1383 ULONG Bit4:1;
1384 ULONG Bit3:1;
1385 ULONG Bit2:1;
1386 ULONG Bit1:1;
1387 ULONG Bit0:1;
1388 #else
1389 ULONG Bit0:1;
1390 ULONG Bit1:1;
1391 ULONG Bit2:1;
1392 ULONG Bit3:1;
1393 ULONG Bit4:1;
1394 ULONG Bit5:1;
1395 ULONG Bit6:1;
1396 ULONG Bit7:1;
1397 ULONG Dir0:1;
1398 ULONG Dir1:1;
1399 ULONG Dir2:1;
1400 ULONG Dir3:1;
1401 ULONG Dir4:1;
1402 ULONG Dir5:1;
1403 ULONG Dir6:1;
1404 ULONG Dir7:1;
1405 ULONG Rsvd:16;
1406 #endif
1407 } field;
1408 ULONG word;
1409 } GPIOCSR_STRUC, *PGPIOCSR_STRUC;
1410
1411 //
1412 // BCNCSR1: Tx BEACON offset time control register
1413 //
1414 typedef union _BCNCSR1_STRUC {
1415 struct {
1416 #ifdef BIG_ENDIAN
1417 ULONG Rsvd:12;
1418 ULONG BeaconCwMin:4; // 2^CwMin
1419 ULONG Preload:16; // in units of usec
1420 #else
1421 ULONG Preload:16; // in units of usec
1422 ULONG BeaconCwMin:4; // 2^CwMin
1423 ULONG Rsvd:12;
1424 #endif
1425 } field;
1426 ULONG word;
1427 } BCNCSR1_STRUC, *PBCNCSR1_STRUC;
1428
1429 //
1430 // MACCSR2: TX_PE to RX_PE turn-around time control register
1431 //
1432 typedef union _MACCSR2_STRUC {
1433 struct {
1434 #ifdef BIG_ENDIAN
1435 ULONG Rsvd:24;
1436 ULONG Delay:8; // in units of PCI clock cycle
1437 #else
1438 ULONG Delay:8; // in units of PCI clock cycle
1439 ULONG Rsvd:24;
1440 #endif
1441 } field;
1442 ULONG word;
1443 } MACCSR2_STRUC, *PMACCSR2_STRUC;
1444
1445 //
1446 // EEPROM antenna select format
1447 //
1448 typedef union _EEPROM_ANTENNA_STRUC {
1449 struct {
1450 #ifdef BIG_ENDIAN
1451 USHORT RfType:5; // see E2PROM document for RF IC selection
1452 USHORT HardwareRadioControl:1; // 1: Hardware controlled radio enabled, Read GPIO0 required.
1453 USHORT DynamicTxAgcControl:1;
1454 USHORT LedMode:3; // 0-default mode, 1:TX/RX activity mode, 2: Single LED (didn't care about link), 3: reserved
1455 USHORT RxDefaultAntenna:2; // default of antenna, 0: diversity, 1:antenna-A, 2:antenna-B reserved (default = 0)
1456 USHORT TxDefaultAntenna:2; // default of antenna, 0: diversity, 1:antenna-A, 2:antenna-B reserved (default = 0)
1457 USHORT NumOfAntenna:2; // Number of antenna
1458 #else
1459 USHORT NumOfAntenna:2; // Number of antenna
1460 USHORT TxDefaultAntenna:2; // default of antenna, 0: diversity, 1:antenna-A, 2:antenna-B reserved (default = 0)
1461 USHORT RxDefaultAntenna:2; // default of antenna, 0: diversity, 1:antenna-A, 2:antenna-B reserved (default = 0)
1462 USHORT LedMode:3; // 0-default mode, 1:TX/RX activity mode, 2: Single LED (didn't care about link), 3: reserved
1463 USHORT DynamicTxAgcControl:1;
1464 USHORT HardwareRadioControl:1; // 1: Hardware controlled radio enabled, Read GPIO0 required.
1465 USHORT RfType:5; // see E2PROM document for RF IC selection
1466 #endif
1467 } field;
1468 USHORT word;
1469 } EEPROM_ANTENNA_STRUC, *PEEPROM_ANTENNA_STRUC;
1470
1471 typedef union _EEPROM_NIC_CINFIG2_STRUC {
1472 struct {
1473 #ifdef BIG_ENDIAN
1474 USHORT Rsv:12; // must be 0
1475 USHORT CckTxPower:2; // CCK TX power compensation
1476 USHORT DynamicBbpTuning:1; // !!! NOTE: 0 - enable, 1 - disable
1477 USHORT CardbusAcceleration:1; // !!! NOTE: 0 - enable, 1 - disable
1478 #else
1479 USHORT CardbusAcceleration:1; // !!! NOTE: 0 - enable, 1 - disable
1480 USHORT DynamicBbpTuning:1; // !!! NOTE: 0 - enable, 1 - disable
1481 USHORT CckTxPower:2; // CCK TX power compensation
1482 USHORT Rsv:12; // must be 0
1483 #endif
1484 } field;
1485 USHORT word;
1486 } EEPROM_NIC_CONFIG2_STRUC, *PEEPROM_NIC_CONFIG2_STRUC;
1487
1488 typedef union _EEPROM_TX_PWR_STRUC {
1489 struct {
1490 #ifdef BIG_ENDIAN
1491 UCHAR Byte1; // High Byte
1492 UCHAR Byte0; // Low Byte
1493 #else
1494 UCHAR Byte0; // Low Byte
1495 UCHAR Byte1; // High Byte
1496 #endif
1497 } field;
1498 USHORT word;
1499 } EEPROM_TX_PWR_STRUC, *PEEPROM_TX_PWR_STRUC;
1500
1501 typedef union _EEPROM_VERSION_STRUC {
1502 struct {
1503 #ifdef BIG_ENDIAN
1504 UCHAR Version; // High Byte
1505 UCHAR FaeReleaseNumber; // Low Byte
1506 #else
1507 UCHAR FaeReleaseNumber; // Low Byte
1508 UCHAR Version; // High Byte
1509 #endif
1510 } field;
1511 USHORT word;
1512 } EEPROM_VERSION_STRUC, *PEEPROM_VERSION_STRUC;
1513
1514 #endif // __RT2560_H__
MOXA 2.6.9 from sdlinux-moxaart.tgz