drivers/scsi/53c700.h

   1 /* -*- mode: c; c-basic-offset: 8 -*- */
   2
   3 /* Driver for 53c700 and 53c700-66 chips from NCR and Symbios
   4  *
   5  * Copyright (C) 2001 by James.Bottomley@HansenPartnership.com
   6  */
   7
   8 #ifndef _53C700_H
   9 #define _53C700_H
  10
  11 #include <linux/interrupt.h>
  12 #include <asm/io.h>
  13
  14 #include <scsi/scsi_device.h>
  15
  16
  17 #if defined(CONFIG_53C700_MEM_MAPPED) && defined(CONFIG_53C700_IO_MAPPED)
  18 #define CONFIG_53C700_BOTH_MAPPED
  19 #endif
  20
  21 /* Turn on for general debugging---too verbose for normal use */
  22 #undef  NCR_700_DEBUG
  23 /* Debug the tag queues, checking hash queue allocation and deallocation
  24  * and search for duplicate tags */
  25 #undef NCR_700_TAG_DEBUG
  26
  27 #ifdef NCR_700_DEBUG
  28 #define DEBUG(x)        printk x
  29 #else
  30 #define DEBUG(x)
  31 #endif
  32
  33 /* The number of available command slots */
  34 #define NCR_700_COMMAND_SLOTS_PER_HOST  64
  35 /* The maximum number of Scatter Gathers we allow */
  36 #define NCR_700_SG_SEGMENTS             32
  37 /* The maximum number of luns (make this of the form 2^n) */
  38 #define NCR_700_MAX_LUNS                32
  39 #define NCR_700_LUN_MASK                (NCR_700_MAX_LUNS - 1)
  40 /* Maximum number of tags the driver ever allows per device */
  41 #define NCR_700_MAX_TAGS                16
  42 /* Tag depth the driver starts out with (can be altered in sysfs) */
  43 #define NCR_700_DEFAULT_TAGS            4
  44 /* This is the default number of commands per LUN in the untagged case.
  45  * two is a good value because it means we can have one command active and
  46  * one command fully prepared and waiting
  47  */
  48 #define NCR_700_CMD_PER_LUN             2
  49 /* magic byte identifying an internally generated REQUEST_SENSE command */
  50 #define NCR_700_INTERNAL_SENSE_MAGIC    0x42
  51
  52 /* WARNING: Leave this in for now: the dependency preprocessor doesn't
  53  * pick up file specific flags, so must define here if they are not
  54  * set */
  55 #if !defined(CONFIG_53C700_IO_MAPPED) && !defined(CONFIG_53C700_MEM_MAPPED)
  56 #error "Config.in must define either CONFIG_53C700_IO_MAPPED or CONFIG_53C700_MEM_MAPPED to use this scsi core."
  57 #endif
  58
  59 struct NCR_700_Host_Parameters;
  60
  61 /* These are the externally used routines */
  62 struct Scsi_Host *NCR_700_detect(struct scsi_host_template *,
  63                 struct NCR_700_Host_Parameters *);
  64 int NCR_700_release(struct Scsi_Host *host);
  65 irqreturn_t NCR_700_intr(int, void *, struct pt_regs *);
  66
  67
  68 enum NCR_700_Host_State {
  69         NCR_700_HOST_BUSY,
  70         NCR_700_HOST_FREE,
  71 };
  72
  73 struct NCR_700_SG_List {
  74         /* The following is a script fragment to move the buffer onto the
  75          * bus and then link the next fragment or return */
  76         #define SCRIPT_MOVE_DATA_IN             0x09000000
  77         #define SCRIPT_MOVE_DATA_OUT            0x08000000
  78         __u32   ins;
  79         __u32   pAddr;
  80         #define SCRIPT_NOP                      0x80000000
  81         #define SCRIPT_RETURN                   0x90080000
  82 };
  83
  84 /* We use device->hostdata to store negotiated parameters.  This is
  85  * supposed to be a pointer to a device private area, but we cannot
  86  * really use it as such since it will never be freed, so just use the
  87  * 32 bits to cram the information.  The SYNC negotiation sequence looks
  88  * like:
  89  *
  90  * If DEV_NEGOTIATED_SYNC not set, tack and SDTR message on to the
  91  * initial identify for the device and set DEV_BEGIN_SYNC_NEGOTATION
  92  * If we get an SDTR reply, work out the SXFER parameters, squirrel
  93  * them away here, clear DEV_BEGIN_SYNC_NEGOTIATION and set
  94  * DEV_NEGOTIATED_SYNC.  If we get a REJECT msg, squirrel
  95  *
  96  *
  97  * 0:7  SXFER_REG negotiated value for this device
  98  * 8:15 Current queue depth
  99  * 16   negotiated SYNC flag
 100  * 17 begin SYNC negotiation flag
 101  * 18 device supports tag queueing */
 102 #define NCR_700_DEV_NEGOTIATED_SYNC     (1<<16)
 103 #define NCR_700_DEV_BEGIN_SYNC_NEGOTIATION      (1<<17)
 104 #define NCR_700_DEV_BEGIN_TAG_QUEUEING  (1<<18)
 105 #define NCR_700_DEV_PRINT_SYNC_NEGOTIATION (1<<19)
 106
 107 static inline void
 108 NCR_700_set_depth(struct scsi_device *SDp, __u8 depth)
 109 {
 110         long l = (long)SDp->hostdata;
 111
 112         l &= 0xffff00ff;
 113         l |= 0xff00 & (depth << 8);
 114         SDp->hostdata = (void *)l;
 115 }
 116 static inline __u8
 117 NCR_700_get_depth(struct scsi_device *SDp)
 118 {
 119         return ((((unsigned long)SDp->hostdata) & 0xff00)>>8);
 120 }
 121 static inline int
 122 NCR_700_is_flag_set(struct scsi_device *SDp, __u32 flag)
 123 {
 124         return (((unsigned long)SDp->hostdata) & flag) == flag;
 125 }
 126 static inline int
 127 NCR_700_is_flag_clear(struct scsi_device *SDp, __u32 flag)
 128 {
 129         return (((unsigned long)SDp->hostdata) & flag) == 0;
 130 }
 131 static inline void
 132 NCR_700_set_flag(struct scsi_device *SDp, __u32 flag)
 133 {
 134         SDp->hostdata = (void *)((long)SDp->hostdata | (flag & 0xffff0000));
 135 }
 136 static inline void
 137 NCR_700_clear_flag(struct scsi_device *SDp, __u32 flag)
 138 {
 139         SDp->hostdata = (void *)((long)SDp->hostdata & ~(flag & 0xffff0000));
 140 }
 141
 142 struct NCR_700_command_slot {
 143         struct NCR_700_SG_List  SG[NCR_700_SG_SEGMENTS+1];
 144         struct NCR_700_SG_List  *pSG;
 145         #define NCR_700_SLOT_MASK 0xFC
 146         #define NCR_700_SLOT_MAGIC 0xb8
 147         #define NCR_700_SLOT_FREE (0|NCR_700_SLOT_MAGIC) /* slot may be used */
 148         #define NCR_700_SLOT_BUSY (1|NCR_700_SLOT_MAGIC) /* slot has command active on HA */
 149         #define NCR_700_SLOT_QUEUED (2|NCR_700_SLOT_MAGIC) /* slot has command to be made active on HA */
 150         __u8    state;
 151         int     tag;
 152         __u32   resume_offset;
 153         struct scsi_cmnd *cmnd;
 154         /* The pci_mapped address of the actual command in cmnd */
 155         dma_addr_t      pCmd;
 156         __u32           temp;
 157         /* if this command is a pci_single mapping, holds the dma address
 158          * for later unmapping in the done routine */
 159         dma_addr_t      dma_handle;
 160         /* historical remnant, now used to link free commands */
 161         struct NCR_700_command_slot *ITL_forw;
 162 };
 163
 164 struct NCR_700_Host_Parameters {
 165         /* These must be filled in by the calling driver */
 166         int     clock;                  /* board clock speed in MHz */
 167         unsigned long   base;           /* the base for the port (copied to host) */
 168         struct device   *dev;
 169         __u32   dmode_extra;    /* adjustable bus settings */
 170         __u32   differential:1; /* if we are differential */
 171 #ifdef CONFIG_53C700_LE_ON_BE
 172         /* This option is for HP only.  Set it if your chip is wired for
 173          * little endian on this platform (which is big endian) */
 174         __u32   force_le_on_be:1;
 175 #endif
 176         __u32   chip710:1;      /* set if really a 710 not 700 */
 177         __u32   burst_disable:1;        /* set to 1 to disable 710 bursting */
 178
 179         /* NOTHING BELOW HERE NEEDS ALTERING */
 180         __u32   fast:1;         /* if we can alter the SCSI bus clock
 181                                    speed (so can negiotiate sync) */
 182 #ifdef CONFIG_53C700_BOTH_MAPPED
 183         __u32   mem_mapped;     /* set if memory mapped */
 184 #endif
 185         int     sync_clock;     /* The speed of the SYNC core */
 186
 187         __u32   *script;                /* pointer to script location */
 188         __u32   pScript;                /* physical mem addr of script */
 189
 190         enum NCR_700_Host_State state; /* protected by state lock */
 191         struct scsi_cmnd *cmd;
 192         /* Note: pScript contains the single consistent block of
 193          * memory.  All the msgin, msgout and status are allocated in
 194          * this memory too (at separate cache lines).  TOTAL_MEM_SIZE
 195          * represents the total size of this area */
 196 #define MSG_ARRAY_SIZE  8
 197 #define MSGOUT_OFFSET   (L1_CACHE_ALIGN(sizeof(SCRIPT)))
 198         __u8    *msgout;
 199 #define MSGIN_OFFSET    (MSGOUT_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
 200         __u8    *msgin;
 201 #define STATUS_OFFSET   (MSGIN_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
 202         __u8    *status;
 203 #define SLOTS_OFFSET    (STATUS_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
 204         struct NCR_700_command_slot     *slots;
 205 #define TOTAL_MEM_SIZE  (SLOTS_OFFSET + L1_CACHE_ALIGN(sizeof(struct NCR_700_command_slot) * NCR_700_COMMAND_SLOTS_PER_HOST))
 206         int     saved_slot_position;
 207         int     command_slot_count; /* protected by state lock */
 208         __u8    tag_negotiated;
 209         __u8    rev;
 210         __u8    reselection_id;
 211         __u8    min_period;
 212
 213         /* Free list, singly linked by ITL_forw elements */
 214         struct NCR_700_command_slot *free_list;
 215         /* Completion for waited for ops, like reset, abort or
 216          * device reset.
 217          *
 218          * NOTE: relies on single threading in the error handler to
 219          * have only one outstanding at once */
 220         struct completion *eh_complete;
 221 };
 222
 223 /*
 224  *      53C700 Register Interface - the offset from the Selected base
 225  *      I/O address */
 226 #ifdef CONFIG_53C700_LE_ON_BE
 227 #define bE      (hostdata->force_le_on_be ? 0 : 3)
 228 #define bSWAP   (hostdata->force_le_on_be)
 229 #elif defined(__BIG_ENDIAN)
 230 #define bE      3
 231 #define bSWAP   0
 232 #elif defined(__LITTLE_ENDIAN)
 233 #define bE      0
 234 #define bSWAP   0
 235 #else
 236 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined, did you include byteorder.h?"
 237 #endif
 238 #define bS_to_cpu(x)    (bSWAP ? le32_to_cpu(x) : (x))
 239 #define bS_to_host(x)   (bSWAP ? cpu_to_le32(x) : (x))
 240
 241 /* NOTE: These registers are in the LE register space only, the required byte
 242  * swapping is done by the NCR_700_{read|write}[b] functions */
 243 #define SCNTL0_REG                      0x00
 244 #define         FULL_ARBITRATION        0xc0
 245 #define         PARITY                  0x08
 246 #define         ENABLE_PARITY           0x04
 247 #define         AUTO_ATN                0x02
 248 #define SCNTL1_REG                      0x01
 249 #define         SLOW_BUS                0x80
 250 #define         ENABLE_SELECT           0x20
 251 #define         ASSERT_RST              0x08
 252 #define         ASSERT_EVEN_PARITY      0x04
 253 #define SDID_REG                        0x02
 254 #define SIEN_REG                        0x03
 255 #define         PHASE_MM_INT            0x80
 256 #define         FUNC_COMP_INT           0x40
 257 #define         SEL_TIMEOUT_INT         0x20
 258 #define         SELECT_INT              0x10
 259 #define         GROSS_ERR_INT           0x08
 260 #define         UX_DISC_INT             0x04
 261 #define         RST_INT                 0x02
 262 #define         PAR_ERR_INT             0x01
 263 #define SCID_REG                        0x04
 264 #define SXFER_REG                       0x05
 265 #define         ASYNC_OPERATION         0x00
 266 #define SODL_REG                        0x06
 267 #define SOCL_REG                        0x07
 268 #define SFBR_REG                        0x08
 269 #define SIDL_REG                        0x09
 270 #define SBDL_REG                        0x0A
 271 #define SBCL_REG                        0x0B
 272 /* read bits */
 273 #define         SBCL_IO                 0x01
 274 /*write bits */
 275 #define         SYNC_DIV_AS_ASYNC       0x00
 276 #define         SYNC_DIV_1_0            0x01
 277 #define         SYNC_DIV_1_5            0x02
 278 #define         SYNC_DIV_2_0            0x03
 279 #define DSTAT_REG                       0x0C
 280 #define         ILGL_INST_DETECTED      0x01
 281 #define         WATCH_DOG_INTERRUPT     0x02
 282 #define         SCRIPT_INT_RECEIVED     0x04
 283 #define         ABORTED                 0x10
 284 #define SSTAT0_REG                      0x0D
 285 #define         PARITY_ERROR            0x01
 286 #define         SCSI_RESET_DETECTED     0x02
 287 #define         UNEXPECTED_DISCONNECT   0x04
 288 #define         SCSI_GROSS_ERROR        0x08
 289 #define         SELECTED                0x10
 290 #define         SELECTION_TIMEOUT       0x20
 291 #define         FUNCTION_COMPLETE       0x40
 292 #define         PHASE_MISMATCH          0x80
 293 #define SSTAT1_REG                      0x0E
 294 #define         SIDL_REG_FULL           0x80
 295 #define         SODR_REG_FULL           0x40
 296 #define         SODL_REG_FULL           0x20
 297 #define SSTAT2_REG                      0x0F
 298 #define CTEST0_REG                      0x14
 299 #define         BTB_TIMER_DISABLE       0x40
 300 #define CTEST1_REG                      0x15
 301 #define CTEST2_REG                      0x16
 302 #define CTEST3_REG                      0x17
 303 #define CTEST4_REG                      0x18
 304 #define         DISABLE_FIFO            0x00
 305 #define         SLBE                    0x10
 306 #define         SFWR                    0x08
 307 #define         BYTE_LANE0              0x04
 308 #define         BYTE_LANE1              0x05
 309 #define         BYTE_LANE2              0x06
 310 #define         BYTE_LANE3              0x07
 311 #define         SCSI_ZMODE              0x20
 312 #define         ZMODE                   0x40
 313 #define CTEST5_REG                      0x19
 314 #define         MASTER_CONTROL          0x10
 315 #define         DMA_DIRECTION           0x08
 316 #define CTEST7_REG                      0x1B
 317 #define         BURST_DISABLE           0x80 /* 710 only */
 318 #define         SEL_TIMEOUT_DISABLE     0x10 /* 710 only */
 319 #define         DFP                     0x08
 320 #define         EVP                     0x04
 321 #define         DIFF                    0x01
 322 #define CTEST6_REG                      0x1A
 323 #define TEMP_REG                        0x1C
 324 #define DFIFO_REG                       0x20
 325 #define         FLUSH_DMA_FIFO          0x80
 326 #define         CLR_FIFO                0x40
 327 #define ISTAT_REG                       0x21
 328 #define         ABORT_OPERATION         0x80
 329 #define         SOFTWARE_RESET_710      0x40
 330 #define         DMA_INT_PENDING         0x01
 331 #define         SCSI_INT_PENDING        0x02
 332 #define         CONNECTED               0x08
 333 #define CTEST8_REG                      0x22
 334 #define         LAST_DIS_ENBL           0x01
 335 #define         SHORTEN_FILTERING       0x04
 336 #define         ENABLE_ACTIVE_NEGATION  0x10
 337 #define         GENERATE_RECEIVE_PARITY 0x20
 338 #define         CLR_FIFO_710            0x04
 339 #define         FLUSH_DMA_FIFO_710      0x08
 340 #define CTEST9_REG                      0x23
 341 #define DBC_REG                         0x24
 342 #define DCMD_REG                        0x27
 343 #define DNAD_REG                        0x28
 344 #define DIEN_REG                        0x39
 345 #define         BUS_FAULT               0x20
 346 #define         ABORT_INT               0x10
 347 #define         INT_INST_INT            0x04
 348 #define         WD_INT                  0x02
 349 #define         ILGL_INST_INT           0x01
 350 #define DCNTL_REG                       0x3B
 351 #define         SOFTWARE_RESET          0x01
 352 #define         COMPAT_700_MODE         0x01
 353 #define         SCRPTS_16BITS           0x20
 354 #define         ASYNC_DIV_2_0           0x00
 355 #define         ASYNC_DIV_1_5           0x40
 356 #define         ASYNC_DIV_1_0           0x80
 357 #define         ASYNC_DIV_3_0           0xc0
 358 #define DMODE_710_REG                   0x38
 359 #define DMODE_700_REG                   0x34
 360 #define         BURST_LENGTH_1          0x00
 361 #define         BURST_LENGTH_2          0x40
 362 #define         BURST_LENGTH_4          0x80
 363 #define         BURST_LENGTH_8          0xC0
 364 #define         DMODE_FC1               0x10
 365 #define         DMODE_FC2               0x20
 366 #define         BW16                    32
 367 #define         MODE_286                16
 368 #define         IO_XFER                 8
 369 #define         FIXED_ADDR              4
 370
 371 #define DSP_REG                         0x2C
 372 #define DSPS_REG                        0x30
 373
 374 /* Parameters to begin SDTR negotiations.  Empirically, I find that
 375  * the 53c700-66 cannot handle an offset >8, so don't change this  */
 376 #define NCR_700_MAX_OFFSET      8
 377 /* Was hoping the max offset would be greater for the 710, but
 378  * empirically it seems to be 8 also */
 379 #define NCR_710_MAX_OFFSET      8
 380 #define NCR_700_MIN_XFERP       1
 381 #define NCR_710_MIN_XFERP       0
 382 #define NCR_700_MIN_PERIOD      25 /* for SDTR message, 100ns */
 383
 384 #define script_patch_32(script, symbol, value) \
 385 { \
 386         int i; \
 387         for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
 388                 __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]) + value; \
 389                 (script)[A_##symbol##_used[i]] = bS_to_host(val); \
 390                 dma_cache_sync(&(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \
 391                 DEBUG((" script, patching %s at %d to 0x%lx\n", \
 392                        #symbol, A_##symbol##_used[i], (value))); \
 393         } \
 394 }
 395
 396 #define script_patch_32_abs(script, symbol, value) \
 397 { \
 398         int i; \
 399         for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
 400                 (script)[A_##symbol##_used[i]] = bS_to_host(value); \
 401                 dma_cache_sync(&(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \
 402                 DEBUG((" script, patching %s at %d to 0x%lx\n", \
 403                        #symbol, A_##symbol##_used[i], (value))); \
 404         } \
 405 }
 406
 407 /* Used for patching the SCSI ID in the SELECT instruction */
 408 #define script_patch_ID(script, symbol, value) \
 409 { \
 410         int i; \
 411         for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
 412                 __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \
 413                 val &= 0xff00ffff; \
 414                 val |= ((value) & 0xff) << 16; \
 415                 (script)[A_##symbol##_used[i]] = bS_to_host(val); \
 416                 dma_cache_sync(&(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \
 417                 DEBUG((" script, patching ID field %s at %d to 0x%x\n", \
 418                        #symbol, A_##symbol##_used[i], val)); \
 419         } \
 420 }
 421
 422 #define script_patch_16(script, symbol, value) \
 423 { \
 424         int i; \
 425         for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
 426                 __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \
 427                 val &= 0xffff0000; \
 428                 val |= ((value) & 0xffff); \
 429                 (script)[A_##symbol##_used[i]] = bS_to_host(val); \
 430                 dma_cache_sync(&(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \
 431                 DEBUG((" script, patching short field %s at %d to 0x%x\n", \
 432                        #symbol, A_##symbol##_used[i], val)); \
 433         } \
 434 }
 435
 436
 437 static inline __u8
 438 NCR_700_mem_readb(struct Scsi_Host *host, __u32 reg)
 439 {
 440         const struct NCR_700_Host_Parameters *hostdata __attribute__((unused))
 441                 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
 442
 443         return readb(host->base + (reg^bE));
 444 }
 445
 446 static inline __u32
 447 NCR_700_mem_readl(struct Scsi_Host *host, __u32 reg)
 448 {
 449         __u32 value = __raw_readl(host->base + reg);
 450         const struct NCR_700_Host_Parameters *hostdata __attribute__((unused))
 451                 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
 452 #if 1
 453         /* sanity check the register */
 454         if((reg & 0x3) != 0)
 455                 BUG();
 456 #endif
 457
 458         return bS_to_cpu(value);
 459 }
 460
 461 static inline void
 462 NCR_700_mem_writeb(__u8 value, struct Scsi_Host *host, __u32 reg)
 463 {
 464         const struct NCR_700_Host_Parameters *hostdata __attribute__((unused))
 465                 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
 466
 467         writeb(value, host->base + (reg^bE));
 468 }
 469
 470 static inline void
 471 NCR_700_mem_writel(__u32 value, struct Scsi_Host *host, __u32 reg)
 472 {
 473         const struct NCR_700_Host_Parameters *hostdata __attribute__((unused))
 474                 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
 475
 476 #if 1
 477         /* sanity check the register */
 478         if((reg & 0x3) != 0)
 479                 BUG();
 480 #endif
 481
 482         __raw_writel(bS_to_host(value), host->base + reg);
 483 }
 484
 485 static inline __u8
 486 NCR_700_io_readb(struct Scsi_Host *host, __u32 reg)
 487 {
 488         const struct NCR_700_Host_Parameters *hostdata __attribute__((unused))
 489                 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
 490
 491         return inb(host->base + (reg^bE));
 492 }
 493
 494 static inline __u32
 495 NCR_700_io_readl(struct Scsi_Host *host, __u32 reg)
 496 {
 497         __u32 value = inl(host->base + reg);
 498         const struct NCR_700_Host_Parameters *hostdata __attribute__((unused))
 499                 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
 500
 501 #if 1
 502         /* sanity check the register */
 503         if((reg & 0x3) != 0)
 504                 BUG();
 505 #endif
 506
 507         return bS_to_cpu(value);
 508 }
 509
 510 static inline void
 511 NCR_700_io_writeb(__u8 value, struct Scsi_Host *host, __u32 reg)
 512 {
 513         const struct NCR_700_Host_Parameters *hostdata __attribute__((unused))
 514                 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
 515
 516         outb(value, host->base + (reg^bE));
 517 }
 518
 519 static inline void
 520 NCR_700_io_writel(__u32 value, struct Scsi_Host *host, __u32 reg)
 521 {
 522         const struct NCR_700_Host_Parameters *hostdata __attribute__((unused))
 523                 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
 524
 525 #if 1
 526         /* sanity check the register */
 527         if((reg & 0x3) != 0)
 528                 BUG();
 529 #endif
 530
 531         outl(bS_to_host(value), host->base + reg);
 532 }
 533
 534 #ifdef CONFIG_53C700_BOTH_MAPPED
 535
 536 static inline __u8
 537 NCR_700_readb(struct Scsi_Host *host, __u32 reg)
 538 {
 539         __u8 val;
 540
 541         const struct NCR_700_Host_Parameters *hostdata __attribute__((unused))
 542                 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
 543
 544         if(hostdata->mem_mapped)
 545                 val = NCR_700_mem_readb(host, reg);
 546         else
 547                 val = NCR_700_io_readb(host, reg);
 548
 549         return val;
 550 }
 551
 552 static inline __u32
 553 NCR_700_readl(struct Scsi_Host *host, __u32 reg)
 554 {
 555         __u32 val;
 556
 557         const struct NCR_700_Host_Parameters *hostdata __attribute__((unused))
 558                 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
 559
 560         if(hostdata->mem_mapped)
 561                 val = NCR_700_mem_readl(host, reg);
 562         else
 563                 val = NCR_700_io_readl(host, reg);
 564
 565         return val;
 566 }
 567
 568 static inline void
 569 NCR_700_writeb(__u8 value, struct Scsi_Host *host, __u32 reg)
 570 {
 571         const struct NCR_700_Host_Parameters *hostdata __attribute__((unused))
 572                 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
 573
 574         if(hostdata->mem_mapped)
 575                 NCR_700_mem_writeb(value, host, reg);
 576         else
 577                 NCR_700_io_writeb(value, host, reg);
 578 }
 579
 580 static inline void
 581 NCR_700_writel(__u32 value, struct Scsi_Host *host, __u32 reg)
 582 {
 583         const struct NCR_700_Host_Parameters *hostdata __attribute__((unused))
 584                 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
 585
 586         if(hostdata->mem_mapped)
 587                 NCR_700_mem_writel(value, host, reg);
 588         else
 589                 NCR_700_io_writel(value, host, reg);
 590 }
 591
 592 static inline void
 593 NCR_700_set_mem_mapped(struct NCR_700_Host_Parameters *hostdata)
 594 {
 595         hostdata->mem_mapped = 1;
 596 }
 597
 598 static inline void
 599 NCR_700_set_io_mapped(struct NCR_700_Host_Parameters *hostdata)
 600 {
 601         hostdata->mem_mapped = 0;
 602 }
 603
 604
 605 #elif defined(CONFIG_53C700_IO_MAPPED)
 606
 607 #define NCR_700_readb NCR_700_io_readb
 608 #define NCR_700_readl NCR_700_io_readl
 609 #define NCR_700_writeb NCR_700_io_writeb
 610 #define NCR_700_writel NCR_700_io_writel
 611
 612 #define NCR_700_set_io_mapped(x)
 613 #define NCR_700_set_mem_mapped(x)       error I/O mapped only
 614
 615 #elif defined(CONFIG_53C700_MEM_MAPPED)
 616
 617 #define NCR_700_readb NCR_700_mem_readb
 618 #define NCR_700_readl NCR_700_mem_readl
 619 #define NCR_700_writeb NCR_700_mem_writeb
 620 #define NCR_700_writel NCR_700_mem_writel
 621
 622 #define NCR_700_set_io_mapped(x)        error MEM mapped only
 623 #define NCR_700_set_mem_mapped(x)
 624
 625 #else
 626 #error neither CONFIG_53C700_MEM_MAPPED nor CONFIG_53C700_IO_MAPPED is set
 627 #endif
 628
 629 #endif