?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
MOXA linux-2.6.x / linux-2.6.9-uc0 from sdlinux-moxaart.tgz
[linux-2.6.9-moxart.git] / drivers / scsi / sym53c8xx_2 / sym_fw2.h
blob025f266a87498c36179f6e5a14630f7096cbd3f8
1 /*
2 * Device driver for the SYMBIOS/LSILOGIC 53C8XX and 53C1010 family
3 * of PCI-SCSI IO processors.
4 *
5 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr>
6 *
7 * This driver is derived from the Linux sym53c8xx driver.
8 * Copyright (C) 1998-2000 Gerard Roudier
9 *
10 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been
11 * a port of the FreeBSD ncr driver to Linux-1.2.13.
12 *
13 * The original ncr driver has been written for 386bsd and FreeBSD by
14 * Wolfgang Stanglmeier <wolf@cologne.de>
15 * Stefan Esser <se@mi.Uni-Koeln.de>
16 * Copyright (C) 1994 Wolfgang Stanglmeier
17 *
18 * Other major contributions:
19 *
20 * NVRAM detection and reading.
21 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
22 *
23 *-----------------------------------------------------------------------------
24 *
25 * Redistribution and use in source and binary forms, with or without
26 * modification, are permitted provided that the following conditions
27 * are met:
28 * 1. Redistributions of source code must retain the above copyright
29 * notice, this list of conditions and the following disclaimer.
30 * 2. The name of the author may not be used to endorse or promote products
31 * derived from this software without specific prior written permission.
32 *
33 * Where this Software is combined with software released under the terms of
34 * the GNU Public License ("GPL") and the terms of the GPL would require the
35 * combined work to also be released under the terms of the GPL, the terms
36 * and conditions of this License will apply in addition to those of the
37 * GPL with the exception of any terms or conditions of this License that
38 * conflict with, or are expressly prohibited by, the GPL.
39 *
40 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
44 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
50 * SUCH DAMAGE.
51 */
52
53 /*
54 * Scripts for SYMBIOS-Processor
55 *
56 * We have to know the offsets of all labels before we reach
57 * them (for forward jumps). Therefore we declare a struct
58 * here. If you make changes inside the script,
59 *
60 * DONT FORGET TO CHANGE THE LENGTHS HERE!
61 */
62
63 /*
64 * Script fragments which are loaded into the on-chip RAM
65 * of 825A, 875, 876, 895, 895A, 896 and 1010 chips.
66 * Must not exceed 4K bytes.
67 */
68 struct SYM_FWA_SCR {
69 u32 start [ 14];
70 u32 getjob_begin [ 4];
71 u32 getjob_end [ 4];
72 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
73 u32 select [ 6];
74 #else
75 u32 select [ 4];
76 #endif
77 #if SYM_CONF_DMA_ADDRESSING_MODE == 2
78 u32 is_dmap_dirty [ 4];
79 #endif
80 u32 wf_sel_done [ 2];
81 u32 sel_done [ 2];
82 u32 send_ident [ 2];
83 #ifdef SYM_CONF_IARB_SUPPORT
84 u32 select2 [ 8];
85 #else
86 u32 select2 [ 2];
87 #endif
88 u32 command [ 2];
89 u32 dispatch [ 28];
90 u32 sel_no_cmd [ 10];
91 u32 init [ 6];
92 u32 clrack [ 4];
93 u32 datai_done [ 10];
94 u32 datai_done_wsr [ 20];
95 u32 datao_done [ 10];
96 u32 datao_done_wss [ 6];
97 u32 datai_phase [ 4];
98 u32 datao_phase [ 6];
99 u32 msg_in [ 2];
100 u32 msg_in2 [ 10];
101 #ifdef SYM_CONF_IARB_SUPPORT
102 u32 status [ 14];
103 #else
104 u32 status [ 10];
105 #endif
106 u32 complete [ 6];
107 u32 complete2 [ 12];
108 u32 done [ 14];
109 u32 done_end [ 2];
110 u32 complete_error [ 4];
111 u32 save_dp [ 12];
112 u32 restore_dp [ 8];
113 u32 disconnect [ 12];
114 #ifdef SYM_CONF_IARB_SUPPORT
115 u32 idle [ 4];
116 #else
117 u32 idle [ 2];
118 #endif
119 #ifdef SYM_CONF_IARB_SUPPORT
120 u32 ungetjob [ 6];
121 #else
122 u32 ungetjob [ 4];
123 #endif
124 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
125 u32 reselect [ 4];
126 #else
127 u32 reselect [ 2];
128 #endif
129 u32 reselected [ 22];
130 u32 resel_scntl4 [ 20];
131 u32 resel_lun0 [ 6];
132 #if SYM_CONF_MAX_TASK*4 > 512
133 u32 resel_tag [ 26];
134 #elif SYM_CONF_MAX_TASK*4 > 256
135 u32 resel_tag [ 20];
136 #else
137 u32 resel_tag [ 16];
138 #endif
139 u32 resel_dsa [ 2];
140 u32 resel_dsa1 [ 4];
141 u32 resel_no_tag [ 6];
142 u32 data_in [SYM_CONF_MAX_SG * 2];
143 u32 data_in2 [ 4];
144 u32 data_out [SYM_CONF_MAX_SG * 2];
145 u32 data_out2 [ 4];
146 u32 pm0_data [ 12];
147 u32 pm0_data_out [ 6];
148 u32 pm0_data_end [ 6];
149 u32 pm1_data [ 12];
150 u32 pm1_data_out [ 6];
151 u32 pm1_data_end [ 6];
152 };
153
154 /*
155 * Script fragments which stay in main memory for all chips
156 * except for chips that support 8K on-chip RAM.
157 */
158 struct SYM_FWB_SCR {
159 u32 start64 [ 2];
160 u32 no_data [ 2];
161 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
162 u32 sel_for_abort [ 18];
163 #else
164 u32 sel_for_abort [ 16];
165 #endif
166 u32 sel_for_abort_1 [ 2];
167 u32 msg_in_etc [ 12];
168 u32 msg_received [ 4];
169 u32 msg_weird_seen [ 4];
170 u32 msg_extended [ 20];
171 u32 msg_bad [ 6];
172 u32 msg_weird [ 4];
173 u32 msg_weird1 [ 8];
174
175 u32 wdtr_resp [ 6];
176 u32 send_wdtr [ 4];
177 u32 sdtr_resp [ 6];
178 u32 send_sdtr [ 4];
179 u32 ppr_resp [ 6];
180 u32 send_ppr [ 4];
181 u32 nego_bad_phase [ 4];
182 u32 msg_out [ 4];
183 u32 msg_out_done [ 4];
184 u32 data_ovrun [ 2];
185 u32 data_ovrun1 [ 22];
186 u32 data_ovrun2 [ 8];
187 u32 abort_resel [ 16];
188 u32 resend_ident [ 4];
189 u32 ident_break [ 4];
190 u32 ident_break_atn [ 4];
191 u32 sdata_in [ 6];
192 u32 resel_bad_lun [ 4];
193 u32 bad_i_t_l [ 4];
194 u32 bad_i_t_l_q [ 4];
195 u32 bad_status [ 6];
196 u32 pm_handle [ 20];
197 u32 pm_handle1 [ 4];
198 u32 pm_save [ 4];
199 u32 pm0_save [ 12];
200 u32 pm_save_end [ 4];
201 u32 pm1_save [ 14];
202
203 /* WSR handling */
204 u32 pm_wsr_handle [ 38];
205 u32 wsr_ma_helper [ 4];
206
207 #ifdef SYM_OPT_HANDLE_DIR_UNKNOWN
208 /* Unknown direction handling */
209 u32 data_io [ 2];
210 u32 data_io_in [ 2];
211 u32 data_io_com [ 6];
212 u32 data_io_out [ 8];
213 #endif
214 /* Data area */
215 u32 zero [ 1];
216 u32 scratch [ 1];
217 u32 pm0_data_addr [ 1];
218 u32 pm1_data_addr [ 1];
219 u32 done_pos [ 1];
220 u32 startpos [ 1];
221 u32 targtbl [ 1];
222 };
223
224 /*
225 * Script fragments used at initialisations.
226 * Only runs out of main memory.
227 */
228 struct SYM_FWZ_SCR {
229 u32 snooptest [ 6];
230 u32 snoopend [ 2];
231 };
232
233 static struct SYM_FWA_SCR SYM_FWA_SCR = {
234 /*--------------------------< START >----------------------------*/ {
235 /*
236 * Switch the LED on.
237 * Will be patched with a NO_OP if LED
238 * not needed or not desired.
239 */
240 SCR_REG_REG (gpreg, SCR_AND, 0xfe),
241 0,
242 /*
243 * Clear SIGP.
244 */
245 SCR_FROM_REG (ctest2),
246 0,
247 /*
248 * Stop here if the C code wants to perform
249 * some error recovery procedure manually.
250 * (Indicate this by setting SEM in ISTAT)
251 */
252 SCR_FROM_REG (istat),
253 0,
254 /*
255 * Report to the C code the next position in
256 * the start queue the SCRIPTS will schedule.
257 * The C code must not change SCRATCHA.
258 */
259 SCR_LOAD_ABS (scratcha, 4),
260 PADDR_B (startpos),
261 SCR_INT ^ IFTRUE (MASK (SEM, SEM)),
262 SIR_SCRIPT_STOPPED,
263 /*
264 * Start the next job.
265 *
266 * @DSA = start point for this job.
267 * SCRATCHA = address of this job in the start queue.
268 *
269 * We will restore startpos with SCRATCHA if we fails the
270 * arbitration or if it is the idle job.
271 *
272 * The below GETJOB_BEGIN to GETJOB_END section of SCRIPTS
273 * is a critical path. If it is partially executed, it then
274 * may happen that the job address is not yet in the DSA
275 * and the next queue position points to the next JOB.
276 */
277 SCR_LOAD_ABS (dsa, 4),
278 PADDR_B (startpos),
279 SCR_LOAD_REL (temp, 4),
280 4,
281 }/*-------------------------< GETJOB_BEGIN >---------------------*/,{
282 SCR_STORE_ABS (temp, 4),
283 PADDR_B (startpos),
284 SCR_LOAD_REL (dsa, 4),
285 0,
286 }/*-------------------------< GETJOB_END >-----------------------*/,{
287 SCR_LOAD_REL (temp, 4),
288 0,
289 SCR_RETURN,
290 0,
291 }/*-------------------------< SELECT >---------------------------*/,{
292 /*
293 * DSA contains the address of a scheduled
294 * data structure.
295 *
296 * SCRATCHA contains the address of the start queue
297 * entry which points to the next job.
298 *
299 * Set Initiator mode.
300 *
301 * (Target mode is left as an exercise for the reader)
302 */
303 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
304 SCR_CLR (SCR_TRG),
305 0,
306 #endif
307 /*
308 * And try to select this target.
309 */
310 SCR_SEL_TBL_ATN ^ offsetof (struct sym_dsb, select),
311 PADDR_A (ungetjob),
312 /*
313 * Now there are 4 possibilities:
314 *
315 * (1) The chip loses arbitration.
316 * This is ok, because it will try again,
317 * when the bus becomes idle.
318 * (But beware of the timeout function!)
319 *
320 * (2) The chip is reselected.
321 * Then the script processor takes the jump
322 * to the RESELECT label.
323 *
324 * (3) The chip wins arbitration.
325 * Then it will execute SCRIPTS instruction until
326 * the next instruction that checks SCSI phase.
327 * Then will stop and wait for selection to be
328 * complete or selection time-out to occur.
329 *
330 * After having won arbitration, the SCRIPTS
331 * processor is able to execute instructions while
332 * the SCSI core is performing SCSI selection.
333 */
334 /*
335 * Initialize the status registers
336 */
337 SCR_LOAD_REL (scr0, 4),
338 offsetof (struct sym_ccb, phys.head.status),
339 /*
340 * We may need help from CPU if the DMA segment
341 * registers aren't up-to-date for this IO.
342 * Patched with NOOP for chips that donnot
343 * support DAC addressing.
344 */
345 #if SYM_CONF_DMA_ADDRESSING_MODE == 2
346 }/*-------------------------< IS_DMAP_DIRTY >--------------------*/,{
347 SCR_FROM_REG (HX_REG),
348 0,
349 SCR_INT ^ IFTRUE (MASK (HX_DMAP_DIRTY, HX_DMAP_DIRTY)),
350 SIR_DMAP_DIRTY,
351 #endif
352 }/*-------------------------< WF_SEL_DONE >----------------------*/,{
353 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT)),
354 SIR_SEL_ATN_NO_MSG_OUT,
355 }/*-------------------------< SEL_DONE >-------------------------*/,{
356 /*
357 * C1010-33 errata work-around.
358 * Due to a race, the SCSI core may not have
359 * loaded SCNTL3 on SEL_TBL instruction.
360 * We reload it once phase is stable.
361 * Patched with a NOOP for other chips.
362 */
363 SCR_LOAD_REL (scntl3, 1),
364 offsetof(struct sym_dsb, select.sel_scntl3),
365 }/*-------------------------< SEND_IDENT >-----------------------*/,{
366 /*
367 * Selection complete.
368 * Send the IDENTIFY and possibly the TAG message
369 * and negotiation message if present.
370 */
371 SCR_MOVE_TBL ^ SCR_MSG_OUT,
372 offsetof (struct sym_dsb, smsg),
373 }/*-------------------------< SELECT2 >--------------------------*/,{
374 #ifdef SYM_CONF_IARB_SUPPORT
375 /*
376 * Set IMMEDIATE ARBITRATION if we have been given
377 * a hint to do so. (Some job to do after this one).
378 */
379 SCR_FROM_REG (HF_REG),
380 0,
381 SCR_JUMPR ^ IFFALSE (MASK (HF_HINT_IARB, HF_HINT_IARB)),
382 8,
383 SCR_REG_REG (scntl1, SCR_OR, IARB),
384 0,
385 #endif
386 /*
387 * Anticipate the COMMAND phase.
388 * This is the PHASE we expect at this point.
389 */
390 SCR_JUMP ^ IFFALSE (WHEN (SCR_COMMAND)),
391 PADDR_A (sel_no_cmd),
392 }/*-------------------------< COMMAND >--------------------------*/,{
393 /*
394 * ... and send the command
395 */
396 SCR_MOVE_TBL ^ SCR_COMMAND,
397 offsetof (struct sym_dsb, cmd),
398 }/*-------------------------< DISPATCH >-------------------------*/,{
399 /*
400 * MSG_IN is the only phase that shall be
401 * entered at least once for each (re)selection.
402 * So we test it first.
403 */
404 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)),
405 PADDR_A (msg_in),
406 SCR_JUMP ^ IFTRUE (IF (SCR_DATA_OUT)),
407 PADDR_A (datao_phase),
408 SCR_JUMP ^ IFTRUE (IF (SCR_DATA_IN)),
409 PADDR_A (datai_phase),
410 SCR_JUMP ^ IFTRUE (IF (SCR_STATUS)),
411 PADDR_A (status),
412 SCR_JUMP ^ IFTRUE (IF (SCR_COMMAND)),
413 PADDR_A (command),
414 SCR_JUMP ^ IFTRUE (IF (SCR_MSG_OUT)),
415 PADDR_B (msg_out),
416 /*
417 * Discard as many illegal phases as
418 * required and tell the C code about.
419 */
420 SCR_JUMPR ^ IFFALSE (WHEN (SCR_ILG_OUT)),
421 16,
422 SCR_MOVE_ABS (1) ^ SCR_ILG_OUT,
423 HADDR_1 (scratch),
424 SCR_JUMPR ^ IFTRUE (WHEN (SCR_ILG_OUT)),
425 -16,
426 SCR_JUMPR ^ IFFALSE (WHEN (SCR_ILG_IN)),
427 16,
428 SCR_MOVE_ABS (1) ^ SCR_ILG_IN,
429 HADDR_1 (scratch),
430 SCR_JUMPR ^ IFTRUE (WHEN (SCR_ILG_IN)),
431 -16,
432 SCR_INT,
433 SIR_BAD_PHASE,
434 SCR_JUMP,
435 PADDR_A (dispatch),
436 }/*-------------------------< SEL_NO_CMD >-----------------------*/,{
437 /*
438 * The target does not switch to command
439 * phase after IDENTIFY has been sent.
440 *
441 * If it stays in MSG OUT phase send it
442 * the IDENTIFY again.
443 */
444 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)),
445 PADDR_B (resend_ident),
446 /*
447 * If target does not switch to MSG IN phase
448 * and we sent a negotiation, assert the
449 * failure immediately.
450 */
451 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)),
452 PADDR_A (dispatch),
453 SCR_FROM_REG (HS_REG),
454 0,
455 SCR_INT ^ IFTRUE (DATA (HS_NEGOTIATE)),
456 SIR_NEGO_FAILED,
457 /*
458 * Jump to dispatcher.
459 */
460 SCR_JUMP,
461 PADDR_A (dispatch),
462 }/*-------------------------< INIT >-----------------------------*/,{
463 /*
464 * Wait for the SCSI RESET signal to be
465 * inactive before restarting operations,
466 * since the chip may hang on SEL_ATN
467 * if SCSI RESET is active.
468 */
469 SCR_FROM_REG (sstat0),
470 0,
471 SCR_JUMPR ^ IFTRUE (MASK (IRST, IRST)),
472 -16,
473 SCR_JUMP,
474 PADDR_A (start),
475 }/*-------------------------< CLRACK >---------------------------*/,{
476 /*
477 * Terminate possible pending message phase.
478 */
479 SCR_CLR (SCR_ACK),
480 0,
481 SCR_JUMP,
482 PADDR_A (dispatch),
483 }/*-------------------------< DATAI_DONE >-----------------------*/,{
484 /*
485 * Save current pointer to LASTP.
486 */
487 SCR_STORE_REL (temp, 4),
488 offsetof (struct sym_ccb, phys.head.lastp),
489 /*
490 * If the SWIDE is not full, jump to dispatcher.
491 * We anticipate a STATUS phase.
492 */
493 SCR_FROM_REG (scntl2),
494 0,
495 SCR_JUMP ^ IFTRUE (MASK (WSR, WSR)),
496 PADDR_A (datai_done_wsr),
497 SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)),
498 PADDR_A (status),
499 SCR_JUMP,
500 PADDR_A (dispatch),
501 }/*-------------------------< DATAI_DONE_WSR >-------------------*/,{
502 /*
503 * The SWIDE is full.
504 * Clear this condition.
505 */
506 SCR_REG_REG (scntl2, SCR_OR, WSR),
507 0,
508 /*
509 * We are expecting an IGNORE RESIDUE message
510 * from the device, otherwise we are in data
511 * overrun condition. Check against MSG_IN phase.
512 */
513 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)),
514 SIR_SWIDE_OVERRUN,
515 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
516 PADDR_A (dispatch),
517 /*
518 * We are in MSG_IN phase,
519 * Read the first byte of the message.
520 * If it is not an IGNORE RESIDUE message,
521 * signal overrun and jump to message
522 * processing.
523 */
524 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
525 HADDR_1 (msgin[0]),
526 SCR_INT ^ IFFALSE (DATA (M_IGN_RESIDUE)),
527 SIR_SWIDE_OVERRUN,
528 SCR_JUMP ^ IFFALSE (DATA (M_IGN_RESIDUE)),
529 PADDR_A (msg_in2),
530 /*
531 * We got the message we expected.
532 * Read the 2nd byte, and jump to dispatcher.
533 */
534 SCR_CLR (SCR_ACK),
535 0,
536 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
537 HADDR_1 (msgin[1]),
538 SCR_CLR (SCR_ACK),
539 0,
540 SCR_JUMP,
541 PADDR_A (dispatch),
542 }/*-------------------------< DATAO_DONE >-----------------------*/,{
543 /*
544 * Save current pointer to LASTP.
545 */
546 SCR_STORE_REL (temp, 4),
547 offsetof (struct sym_ccb, phys.head.lastp),
548 /*
549 * If the SODL is not full jump to dispatcher.
550 * We anticipate a STATUS phase.
551 */
552 SCR_FROM_REG (scntl2),
553 0,
554 SCR_JUMP ^ IFTRUE (MASK (WSS, WSS)),
555 PADDR_A (datao_done_wss),
556 SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)),
557 PADDR_A (status),
558 SCR_JUMP,
559 PADDR_A (dispatch),
560 }/*-------------------------< DATAO_DONE_WSS >-------------------*/,{
561 /*
562 * The SODL is full, clear this condition.
563 */
564 SCR_REG_REG (scntl2, SCR_OR, WSS),
565 0,
566 /*
567 * And signal a DATA UNDERRUN condition
568 * to the C code.
569 */
570 SCR_INT,
571 SIR_SODL_UNDERRUN,
572 SCR_JUMP,
573 PADDR_A (dispatch),
574 }/*-------------------------< DATAI_PHASE >----------------------*/,{
575 /*
576 * Jump to current pointer.
577 */
578 SCR_LOAD_REL (temp, 4),
579 offsetof (struct sym_ccb, phys.head.lastp),
580 SCR_RETURN,
581 0,
582 }/*-------------------------< DATAO_PHASE >----------------------*/,{
583 /*
584 * C1010-66 errata work-around.
585 * Extra clocks of data hold must be inserted
586 * in DATA OUT phase on 33 MHz PCI BUS.
587 * Patched with a NOOP for other chips.
588 */
589 SCR_REG_REG (scntl4, SCR_OR, (XCLKH_DT|XCLKH_ST)),
590 0,
591 /*
592 * Jump to current pointer.
593 */
594 SCR_LOAD_REL (temp, 4),
595 offsetof (struct sym_ccb, phys.head.lastp),
596 SCR_RETURN,
597 0,
598 }/*-------------------------< MSG_IN >---------------------------*/,{
599 /*
600 * Get the first byte of the message.
601 *
602 * The script processor doesn't negate the
603 * ACK signal after this transfer.
604 */
605 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
606 HADDR_1 (msgin[0]),
607 }/*-------------------------< MSG_IN2 >--------------------------*/,{
608 /*
609 * Check first against 1 byte messages
610 * that we handle from SCRIPTS.
611 */
612 SCR_JUMP ^ IFTRUE (DATA (M_COMPLETE)),
613 PADDR_A (complete),
614 SCR_JUMP ^ IFTRUE (DATA (M_DISCONNECT)),
615 PADDR_A (disconnect),
616 SCR_JUMP ^ IFTRUE (DATA (M_SAVE_DP)),
617 PADDR_A (save_dp),
618 SCR_JUMP ^ IFTRUE (DATA (M_RESTORE_DP)),
619 PADDR_A (restore_dp),
620 /*
621 * We handle all other messages from the
622 * C code, so no need to waste on-chip RAM
623 * for those ones.
624 */
625 SCR_JUMP,
626 PADDR_B (msg_in_etc),
627 }/*-------------------------< STATUS >---------------------------*/,{
628 /*
629 * get the status
630 */
631 SCR_MOVE_ABS (1) ^ SCR_STATUS,
632 HADDR_1 (scratch),
633 #ifdef SYM_CONF_IARB_SUPPORT
634 /*
635 * If STATUS is not GOOD, clear IMMEDIATE ARBITRATION,
636 * since we may have to tamper the start queue from
637 * the C code.
638 */
639 SCR_JUMPR ^ IFTRUE (DATA (S_GOOD)),
640 8,
641 SCR_REG_REG (scntl1, SCR_AND, ~IARB),
642 0,
643 #endif
644 /*
645 * save status to scsi_status.
646 * mark as complete.
647 */
648 SCR_TO_REG (SS_REG),
649 0,
650 SCR_LOAD_REG (HS_REG, HS_COMPLETE),
651 0,
652 /*
653 * Anticipate the MESSAGE PHASE for
654 * the TASK COMPLETE message.
655 */
656 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)),
657 PADDR_A (msg_in),
658 SCR_JUMP,
659 PADDR_A (dispatch),
660 }/*-------------------------< COMPLETE >-------------------------*/,{
661 /*
662 * Complete message.
663 *
664 * When we terminate the cycle by clearing ACK,
665 * the target may disconnect immediately.
666 *
667 * We don't want to be told of an "unexpected disconnect",
668 * so we disable this feature.
669 */
670 SCR_REG_REG (scntl2, SCR_AND, 0x7f),
671 0,
672 /*
673 * Terminate cycle ...
674 */
675 SCR_CLR (SCR_ACK|SCR_ATN),
676 0,
677 /*
678 * ... and wait for the disconnect.
679 */
680 SCR_WAIT_DISC,
681 0,
682 }/*-------------------------< COMPLETE2 >------------------------*/,{
683 /*
684 * Save host status.
685 */
686 SCR_STORE_REL (scr0, 4),
687 offsetof (struct sym_ccb, phys.head.status),
688 /*
689 * Some bridges may reorder DMA writes to memory.
690 * We donnot want the CPU to deal with completions
691 * without all the posted write having been flushed
692 * to memory. This DUMMY READ should flush posted
693 * buffers prior to the CPU having to deal with
694 * completions.
695 */
696 SCR_LOAD_REL (scr0, 4), /* DUMMY READ */
697 offsetof (struct sym_ccb, phys.head.status),
698
699 /*
700 * If command resulted in not GOOD status,
701 * call the C code if needed.
702 */
703 SCR_FROM_REG (SS_REG),
704 0,
705 SCR_CALL ^ IFFALSE (DATA (S_GOOD)),
706 PADDR_B (bad_status),
707 /*
708 * If we performed an auto-sense, call
709 * the C code to synchronyze task aborts
710 * with UNIT ATTENTION conditions.
711 */
712 SCR_FROM_REG (HF_REG),
713 0,
714 SCR_JUMP ^ IFFALSE (MASK (0 ,(HF_SENSE|HF_EXT_ERR))),
715 PADDR_A (complete_error),
716 }/*-------------------------< DONE >-----------------------------*/,{
717 /*
718 * Copy the DSA to the DONE QUEUE and
719 * signal completion to the host.
720 * If we are interrupted between DONE
721 * and DONE_END, we must reset, otherwise
722 * the completed CCB may be lost.
723 */
724 SCR_STORE_ABS (dsa, 4),
725 PADDR_B (scratch),
726 SCR_LOAD_ABS (dsa, 4),
727 PADDR_B (done_pos),
728 SCR_LOAD_ABS (scratcha, 4),
729 PADDR_B (scratch),
730 SCR_STORE_REL (scratcha, 4),
731 0,
732 /*
733 * The instruction below reads the DONE QUEUE next
734 * free position from memory.
735 * In addition it ensures that all PCI posted writes
736 * are flushed and so the DSA value of the done
737 * CCB is visible by the CPU before INTFLY is raised.
738 */
739 SCR_LOAD_REL (scratcha, 4),
740 4,
741 SCR_INT_FLY,
742 0,
743 SCR_STORE_ABS (scratcha, 4),
744 PADDR_B (done_pos),
745 }/*-------------------------< DONE_END >-------------------------*/,{
746 SCR_JUMP,
747 PADDR_A (start),
748 }/*-------------------------< COMPLETE_ERROR >-------------------*/,{
749 SCR_LOAD_ABS (scratcha, 4),
750 PADDR_B (startpos),
751 SCR_INT,
752 SIR_COMPLETE_ERROR,
753 }/*-------------------------< SAVE_DP >--------------------------*/,{
754 /*
755 * Clear ACK immediately.
756 * No need to delay it.
757 */
758 SCR_CLR (SCR_ACK),
759 0,
760 /*
761 * Keep track we received a SAVE DP, so
762 * we will switch to the other PM context
763 * on the next PM since the DP may point
764 * to the current PM context.
765 */
766 SCR_REG_REG (HF_REG, SCR_OR, HF_DP_SAVED),
767 0,
768 /*
769 * SAVE_DP message:
770 * Copy LASTP to SAVEP.
771 */
772 SCR_LOAD_REL (scratcha, 4),
773 offsetof (struct sym_ccb, phys.head.lastp),
774 SCR_STORE_REL (scratcha, 4),
775 offsetof (struct sym_ccb, phys.head.savep),
776 /*
777 * Anticipate the MESSAGE PHASE for
778 * the DISCONNECT message.
779 */
780 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)),
781 PADDR_A (msg_in),
782 SCR_JUMP,
783 PADDR_A (dispatch),
784 }/*-------------------------< RESTORE_DP >-----------------------*/,{
785 /*
786 * Clear ACK immediately.
787 * No need to delay it.
788 */
789 SCR_CLR (SCR_ACK),
790 0,
791 /*
792 * Copy SAVEP to LASTP.
793 */
794 SCR_LOAD_REL (scratcha, 4),
795 offsetof (struct sym_ccb, phys.head.savep),
796 SCR_STORE_REL (scratcha, 4),
797 offsetof (struct sym_ccb, phys.head.lastp),
798 SCR_JUMP,
799 PADDR_A (dispatch),
800 }/*-------------------------< DISCONNECT >-----------------------*/,{
801 /*
802 * DISCONNECTing ...
803 *
804 * disable the "unexpected disconnect" feature,
805 * and remove the ACK signal.
806 */
807 SCR_REG_REG (scntl2, SCR_AND, 0x7f),
808 0,
809 SCR_CLR (SCR_ACK|SCR_ATN),
810 0,
811 /*
812 * Wait for the disconnect.
813 */
814 SCR_WAIT_DISC,
815 0,
816 /*
817 * Status is: DISCONNECTED.
818 */
819 SCR_LOAD_REG (HS_REG, HS_DISCONNECT),
820 0,
821 /*
822 * Save host status.
823 */
824 SCR_STORE_REL (scr0, 4),
825 offsetof (struct sym_ccb, phys.head.status),
826 SCR_JUMP,
827 PADDR_A (start),
828 }/*-------------------------< IDLE >-----------------------------*/,{
829 /*
830 * Nothing to do?
831 * Switch the LED off and wait for reselect.
832 * Will be patched with a NO_OP if LED
833 * not needed or not desired.
834 */
835 SCR_REG_REG (gpreg, SCR_OR, 0x01),
836 0,
837 #ifdef SYM_CONF_IARB_SUPPORT
838 SCR_JUMPR,
839 8,
840 #endif
841 }/*-------------------------< UNGETJOB >-------------------------*/,{
842 #ifdef SYM_CONF_IARB_SUPPORT
843 /*
844 * Set IMMEDIATE ARBITRATION, for the next time.
845 * This will give us better chance to win arbitration
846 * for the job we just wanted to do.
847 */
848 SCR_REG_REG (scntl1, SCR_OR, IARB),
849 0,
850 #endif
851 /*
852 * We are not able to restart the SCRIPTS if we are
853 * interrupted and these instruction haven't been
854 * all executed. BTW, this is very unlikely to
855 * happen, but we check that from the C code.
856 */
857 SCR_LOAD_REG (dsa, 0xff),
858 0,
859 SCR_STORE_ABS (scratcha, 4),
860 PADDR_B (startpos),
861 }/*-------------------------< RESELECT >-------------------------*/,{
862 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
863 /*
864 * Make sure we are in initiator mode.
865 */
866 SCR_CLR (SCR_TRG),
867 0,
868 #endif
869 /*
870 * Sleep waiting for a reselection.
871 */
872 SCR_WAIT_RESEL,
873 PADDR_A(start),
874 }/*-------------------------< RESELECTED >-----------------------*/,{
875 /*
876 * Switch the LED on.
877 * Will be patched with a NO_OP if LED
878 * not needed or not desired.
879 */
880 SCR_REG_REG (gpreg, SCR_AND, 0xfe),
881 0,
882 /*
883 * load the target id into the sdid
884 */
885 SCR_REG_SFBR (ssid, SCR_AND, 0x8F),
886 0,
887 SCR_TO_REG (sdid),
888 0,
889 /*
890 * Load the target control block address
891 */
892 SCR_LOAD_ABS (dsa, 4),
893 PADDR_B (targtbl),
894 SCR_SFBR_REG (dsa, SCR_SHL, 0),
895 0,
896 SCR_REG_REG (dsa, SCR_SHL, 0),
897 0,
898 SCR_REG_REG (dsa, SCR_AND, 0x3c),
899 0,
900 SCR_LOAD_REL (dsa, 4),
901 0,
902 /*
903 * We expect MESSAGE IN phase.
904 * If not, get help from the C code.
905 */
906 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)),
907 SIR_RESEL_NO_MSG_IN,
908 /*
909 * Load the legacy synchronous transfer registers.
910 */
911 SCR_LOAD_REL (scntl3, 1),
912 offsetof(struct sym_tcb, head.wval),
913 SCR_LOAD_REL (sxfer, 1),
914 offsetof(struct sym_tcb, head.sval),
915 }/*-------------------------< RESEL_SCNTL4 >---------------------*/,{
916 /*
917 * The C1010 uses a new synchronous timing scheme.
918 * Will be patched with a NO_OP if not a C1010.
919 */
920 SCR_LOAD_REL (scntl4, 1),
921 offsetof(struct sym_tcb, head.uval),
922 /*
923 * Get the IDENTIFY message.
924 */
925 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
926 HADDR_1 (msgin),
927 /*
928 * If IDENTIFY LUN #0, use a faster path
929 * to find the LCB structure.
930 */
931 SCR_JUMP ^ IFTRUE (MASK (0x80, 0xbf)),
932 PADDR_A (resel_lun0),
933 /*
934 * If message isn't an IDENTIFY,
935 * tell the C code about.
936 */
937 SCR_INT ^ IFFALSE (MASK (0x80, 0x80)),
938 SIR_RESEL_NO_IDENTIFY,
939 /*
940 * It is an IDENTIFY message,
941 * Load the LUN control block address.
942 */
943 SCR_LOAD_REL (dsa, 4),
944 offsetof(struct sym_tcb, head.luntbl_sa),
945 SCR_SFBR_REG (dsa, SCR_SHL, 0),
946 0,
947 SCR_REG_REG (dsa, SCR_SHL, 0),
948 0,
949 SCR_REG_REG (dsa, SCR_AND, 0xfc),
950 0,
951 SCR_LOAD_REL (dsa, 4),
952 0,
953 SCR_JUMPR,
954 8,
955 }/*-------------------------< RESEL_LUN0 >-----------------------*/,{
956 /*
957 * LUN 0 special case (but usual one :))
958 */
959 SCR_LOAD_REL (dsa, 4),
960 offsetof(struct sym_tcb, head.lun0_sa),
961 /*
962 * Jump indirectly to the reselect action for this LUN.
963 */
964 SCR_LOAD_REL (temp, 4),
965 offsetof(struct sym_lcb, head.resel_sa),
966 SCR_RETURN,
967 0,
968 /* In normal situations, we jump to RESEL_TAG or RESEL_NO_TAG */
969 }/*-------------------------< RESEL_TAG >------------------------*/,{
970 /*
971 * ACK the IDENTIFY previously received.
972 */
973 SCR_CLR (SCR_ACK),
974 0,
975 /*
976 * It shall be a tagged command.
977 * Read SIMPLE+TAG.
978 * The C code will deal with errors.
979 * Agressive optimization, is'nt it? :)
980 */
981 SCR_MOVE_ABS (2) ^ SCR_MSG_IN,
982 HADDR_1 (msgin),
983 /*
984 * Load the pointer to the tagged task
985 * table for this LUN.
986 */
987 SCR_LOAD_REL (dsa, 4),
988 offsetof(struct sym_lcb, head.itlq_tbl_sa),
989 /*
990 * The SIDL still contains the TAG value.
991 * Agressive optimization, isn't it? :):)
992 */
993 SCR_REG_SFBR (sidl, SCR_SHL, 0),
994 0,
995 #if SYM_CONF_MAX_TASK*4 > 512
996 SCR_JUMPR ^ IFFALSE (CARRYSET),
997 8,
998 SCR_REG_REG (dsa1, SCR_OR, 2),
999 0,
1000 SCR_REG_REG (sfbr, SCR_SHL, 0),
1001 0,
1002 SCR_JUMPR ^ IFFALSE (CARRYSET),
1003 8,
1004 SCR_REG_REG (dsa1, SCR_OR, 1),
1005 0,
1006 #elif SYM_CONF_MAX_TASK*4 > 256
1007 SCR_JUMPR ^ IFFALSE (CARRYSET),
1008 8,
1009 SCR_REG_REG (dsa1, SCR_OR, 1),
1010 0,
1011 #endif
1012 /*
1013 * Retrieve the DSA of this task.
1014 * JUMP indirectly to the restart point of the CCB.
1015 */
1016 SCR_SFBR_REG (dsa, SCR_AND, 0xfc),
1017 0,
1018 SCR_LOAD_REL (dsa, 4),
1019 0,
1020 SCR_LOAD_REL (temp, 4),
1021 offsetof(struct sym_ccb, phys.head.go.restart),
1022 SCR_RETURN,
1023 0,
1024 /* In normal situations we branch to RESEL_DSA */
1025 }/*-------------------------< RESEL_DSA >------------------------*/,{
1026 /*
1027 * ACK the IDENTIFY or TAG previously received.
1028 */
1029 SCR_CLR (SCR_ACK),
1030 0,
1031 }/*-------------------------< RESEL_DSA1 >-----------------------*/,{
1032 /*
1033 * Initialize the status registers
1034 */
1035 SCR_LOAD_REL (scr0, 4),
1036 offsetof (struct sym_ccb, phys.head.status),
1037 /*
1038 * Jump to dispatcher.
1039 */
1040 SCR_JUMP,
1041 PADDR_A (dispatch),
1042 }/*-------------------------< RESEL_NO_TAG >---------------------*/,{
1043 /*
1044 * Load the DSA with the unique ITL task.
1045 */
1046 SCR_LOAD_REL (dsa, 4),
1047 offsetof(struct sym_lcb, head.itl_task_sa),
1048 /*
1049 * JUMP indirectly to the restart point of the CCB.
1050 */
1051 SCR_LOAD_REL (temp, 4),
1052 offsetof(struct sym_ccb, phys.head.go.restart),
1053 SCR_RETURN,
1054 0,
1055 /* In normal situations we branch to RESEL_DSA */
1056 }/*-------------------------< DATA_IN >--------------------------*/,{
1057 /*
1058 * Because the size depends on the
1059 * #define SYM_CONF_MAX_SG parameter,
1060 * it is filled in at runtime.
1061 *
1062 * ##===========< i=0; i<SYM_CONF_MAX_SG >=========
1063 * || SCR_CHMOV_TBL ^ SCR_DATA_IN,
1064 * || offsetof (struct sym_dsb, data[ i]),
1065 * ##==========================================
1066 */
1067 0
1068 }/*-------------------------< DATA_IN2 >-------------------------*/,{
1069 SCR_CALL,
1070 PADDR_A (datai_done),
1071 SCR_JUMP,
1072 PADDR_B (data_ovrun),
1073 }/*-------------------------< DATA_OUT >-------------------------*/,{
1074 /*
1075 * Because the size depends on the
1076 * #define SYM_CONF_MAX_SG parameter,
1077 * it is filled in at runtime.
1078 *
1079 * ##===========< i=0; i<SYM_CONF_MAX_SG >=========
1080 * || SCR_CHMOV_TBL ^ SCR_DATA_OUT,
1081 * || offsetof (struct sym_dsb, data[ i]),
1082 * ##==========================================
1083 */
1084 0
1085 }/*-------------------------< DATA_OUT2 >------------------------*/,{
1086 SCR_CALL,
1087 PADDR_A (datao_done),
1088 SCR_JUMP,
1089 PADDR_B (data_ovrun),
1090 }/*-------------------------< PM0_DATA >-------------------------*/,{
1091 /*
1092 * Read our host flags to SFBR, so we will be able
1093 * to check against the data direction we expect.
1094 */
1095 SCR_FROM_REG (HF_REG),
1096 0,
1097 /*
1098 * Check against actual DATA PHASE.
1099 */
1100 SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)),
1101 PADDR_A (pm0_data_out),
1102 /*
1103 * Actual phase is DATA IN.
1104 * Check against expected direction.
1105 */
1106 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)),
1107 PADDR_B (data_ovrun),
1108 /*
1109 * Keep track we are moving data from the
1110 * PM0 DATA mini-script.
1111 */
1112 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM0),
1113 0,
1114 /*
1115 * Move the data to memory.
1116 */
1117 SCR_CHMOV_TBL ^ SCR_DATA_IN,
1118 offsetof (struct sym_ccb, phys.pm0.sg),
1119 SCR_JUMP,
1120 PADDR_A (pm0_data_end),
1121 }/*-------------------------< PM0_DATA_OUT >---------------------*/,{
1122 /*
1123 * Actual phase is DATA OUT.
1124 * Check against expected direction.
1125 */
1126 SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)),
1127 PADDR_B (data_ovrun),
1128 /*
1129 * Keep track we are moving data from the
1130 * PM0 DATA mini-script.
1131 */
1132 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM0),
1133 0,
1134 /*
1135 * Move the data from memory.
1136 */
1137 SCR_CHMOV_TBL ^ SCR_DATA_OUT,
1138 offsetof (struct sym_ccb, phys.pm0.sg),
1139 }/*-------------------------< PM0_DATA_END >---------------------*/,{
1140 /*
1141 * Clear the flag that told we were moving
1142 * data from the PM0 DATA mini-script.
1143 */
1144 SCR_REG_REG (HF_REG, SCR_AND, (~HF_IN_PM0)),
1145 0,
1146 /*
1147 * Return to the previous DATA script which
1148 * is guaranteed by design (if no bug) to be
1149 * the main DATA script for this transfer.
1150 */
1151 SCR_LOAD_REL (temp, 4),
1152 offsetof (struct sym_ccb, phys.pm0.ret),
1153 SCR_RETURN,
1154 0,
1155 }/*-------------------------< PM1_DATA >-------------------------*/,{
1156 /*
1157 * Read our host flags to SFBR, so we will be able
1158 * to check against the data direction we expect.
1159 */
1160 SCR_FROM_REG (HF_REG),
1161 0,
1162 /*
1163 * Check against actual DATA PHASE.
1164 */
1165 SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)),
1166 PADDR_A (pm1_data_out),
1167 /*
1168 * Actual phase is DATA IN.
1169 * Check against expected direction.
1170 */
1171 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)),
1172 PADDR_B (data_ovrun),
1173 /*
1174 * Keep track we are moving data from the
1175 * PM1 DATA mini-script.
1176 */
1177 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM1),
1178 0,
1179 /*
1180 * Move the data to memory.
1181 */
1182 SCR_CHMOV_TBL ^ SCR_DATA_IN,
1183 offsetof (struct sym_ccb, phys.pm1.sg),
1184 SCR_JUMP,
1185 PADDR_A (pm1_data_end),
1186 }/*-------------------------< PM1_DATA_OUT >---------------------*/,{
1187 /*
1188 * Actual phase is DATA OUT.
1189 * Check against expected direction.
1190 */
1191 SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)),
1192 PADDR_B (data_ovrun),
1193 /*
1194 * Keep track we are moving data from the
1195 * PM1 DATA mini-script.
1196 */
1197 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM1),
1198 0,
1199 /*
1200 * Move the data from memory.
1201 */
1202 SCR_CHMOV_TBL ^ SCR_DATA_OUT,
1203 offsetof (struct sym_ccb, phys.pm1.sg),
1204 }/*-------------------------< PM1_DATA_END >---------------------*/,{
1205 /*
1206 * Clear the flag that told we were moving
1207 * data from the PM1 DATA mini-script.
1208 */
1209 SCR_REG_REG (HF_REG, SCR_AND, (~HF_IN_PM1)),
1210 0,
1211 /*
1212 * Return to the previous DATA script which
1213 * is guaranteed by design (if no bug) to be
1214 * the main DATA script for this transfer.
1215 */
1216 SCR_LOAD_REL (temp, 4),
1217 offsetof (struct sym_ccb, phys.pm1.ret),
1218 SCR_RETURN,
1219 0,
1220 }/*-------------------------<>-----------------------------------*/
1221 };
1222
1223 static struct SYM_FWB_SCR SYM_FWB_SCR = {
1224 /*--------------------------< START64 >--------------------------*/ {
1225 /*
1226 * SCRIPT entry point for the 895A, 896 and 1010.
1227 * For now, there is no specific stuff for those
1228 * chips at this point, but this may come.
1229 */
1230 SCR_JUMP,
1231 PADDR_A (init),
1232 }/*-------------------------< NO_DATA >--------------------------*/,{
1233 SCR_JUMP,
1234 PADDR_B (data_ovrun),
1235 }/*-------------------------< SEL_FOR_ABORT >--------------------*/,{
1236 /*
1237 * We are jumped here by the C code, if we have
1238 * some target to reset or some disconnected
1239 * job to abort. Since error recovery is a serious
1240 * busyness, we will really reset the SCSI BUS, if
1241 * case of a SCSI interrupt occurring in this path.
1242 */
1243 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
1244 /*
1245 * Set initiator mode.
1246 */
1247 SCR_CLR (SCR_TRG),
1248 0,
1249 #endif
1250 /*
1251 * And try to select this target.
1252 */
1253 SCR_SEL_TBL_ATN ^ offsetof (struct sym_hcb, abrt_sel),
1254 PADDR_A (reselect),
1255 /*
1256 * Wait for the selection to complete or
1257 * the selection to time out.
1258 */
1259 SCR_JUMPR ^ IFFALSE (WHEN (SCR_MSG_OUT)),
1260 -8,
1261 /*
1262 * Call the C code.
1263 */
1264 SCR_INT,
1265 SIR_TARGET_SELECTED,
1266 /*
1267 * The C code should let us continue here.
1268 * Send the 'kiss of death' message.
1269 * We expect an immediate disconnect once
1270 * the target has eaten the message.
1271 */
1272 SCR_REG_REG (scntl2, SCR_AND, 0x7f),
1273 0,
1274 SCR_MOVE_TBL ^ SCR_MSG_OUT,
1275 offsetof (struct sym_hcb, abrt_tbl),
1276 SCR_CLR (SCR_ACK|SCR_ATN),
1277 0,
1278 SCR_WAIT_DISC,
1279 0,
1280 /*
1281 * Tell the C code that we are done.
1282 */
1283 SCR_INT,
1284 SIR_ABORT_SENT,
1285 }/*-------------------------< SEL_FOR_ABORT_1 >------------------*/,{
1286 /*
1287 * Jump at scheduler.
1288 */
1289 SCR_JUMP,
1290 PADDR_A (start),
1291 }/*-------------------------< MSG_IN_ETC >-----------------------*/,{
1292 /*
1293 * If it is an EXTENDED (variable size message)
1294 * Handle it.
1295 */
1296 SCR_JUMP ^ IFTRUE (DATA (M_EXTENDED)),
1297 PADDR_B (msg_extended),
1298 /*
1299 * Let the C code handle any other
1300 * 1 byte message.
1301 */
1302 SCR_JUMP ^ IFTRUE (MASK (0x00, 0xf0)),
1303 PADDR_B (msg_received),
1304 SCR_JUMP ^ IFTRUE (MASK (0x10, 0xf0)),
1305 PADDR_B (msg_received),
1306 /*
1307 * We donnot handle 2 bytes messages from SCRIPTS.
1308 * So, let the C code deal with these ones too.
1309 */
1310 SCR_JUMP ^ IFFALSE (MASK (0x20, 0xf0)),
1311 PADDR_B (msg_weird_seen),
1312 SCR_CLR (SCR_ACK),
1313 0,
1314 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
1315 HADDR_1 (msgin[1]),
1316 }/*-------------------------< MSG_RECEIVED >---------------------*/,{
1317 SCR_LOAD_REL (scratcha, 4), /* DUMMY READ */
1318 0,
1319 SCR_INT,
1320 SIR_MSG_RECEIVED,
1321 }/*-------------------------< MSG_WEIRD_SEEN >-------------------*/,{
1322 SCR_LOAD_REL (scratcha, 4), /* DUMMY READ */
1323 0,
1324 SCR_INT,
1325 SIR_MSG_WEIRD,
1326 }/*-------------------------< MSG_EXTENDED >---------------------*/,{
1327 /*
1328 * Clear ACK and get the next byte
1329 * assumed to be the message length.
1330 */
1331 SCR_CLR (SCR_ACK),
1332 0,
1333 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
1334 HADDR_1 (msgin[1]),
1335 /*
1336 * Try to catch some unlikely situations as 0 length
1337 * or too large the length.
1338 */
1339 SCR_JUMP ^ IFTRUE (DATA (0)),
1340 PADDR_B (msg_weird_seen),
1341 SCR_TO_REG (scratcha),
1342 0,
1343 SCR_REG_REG (sfbr, SCR_ADD, (256-8)),
1344 0,
1345 SCR_JUMP ^ IFTRUE (CARRYSET),
1346 PADDR_B (msg_weird_seen),
1347 /*
1348 * We donnot handle extended messages from SCRIPTS.
1349 * Read the amount of data correponding to the
1350 * message length and call the C code.
1351 */
1352 SCR_STORE_REL (scratcha, 1),
1353 offsetof (struct sym_dsb, smsg_ext.size),
1354 SCR_CLR (SCR_ACK),
1355 0,
1356 SCR_MOVE_TBL ^ SCR_MSG_IN,
1357 offsetof (struct sym_dsb, smsg_ext),
1358 SCR_JUMP,
1359 PADDR_B (msg_received),
1360 }/*-------------------------< MSG_BAD >--------------------------*/,{
1361 /*
1362 * unimplemented message - reject it.
1363 */
1364 SCR_INT,
1365 SIR_REJECT_TO_SEND,
1366 SCR_SET (SCR_ATN),
1367 0,
1368 SCR_JUMP,
1369 PADDR_A (clrack),
1370 }/*-------------------------< MSG_WEIRD >------------------------*/,{
1371 /*
1372 * weird message received
1373 * ignore all MSG IN phases and reject it.
1374 */
1375 SCR_INT,
1376 SIR_REJECT_TO_SEND,
1377 SCR_SET (SCR_ATN),
1378 0,
1379 }/*-------------------------< MSG_WEIRD1 >-----------------------*/,{
1380 SCR_CLR (SCR_ACK),
1381 0,
1382 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
1383 PADDR_A (dispatch),
1384 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
1385 HADDR_1 (scratch),
1386 SCR_JUMP,
1387 PADDR_B (msg_weird1),
1388 }/*-------------------------< WDTR_RESP >------------------------*/,{
1389 /*
1390 * let the target fetch our answer.
1391 */
1392 SCR_SET (SCR_ATN),
1393 0,
1394 SCR_CLR (SCR_ACK),
1395 0,
1396 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)),
1397 PADDR_B (nego_bad_phase),
1398 }/*-------------------------< SEND_WDTR >------------------------*/,{
1399 /*
1400 * Send the M_X_WIDE_REQ
1401 */
1402 SCR_MOVE_ABS (4) ^ SCR_MSG_OUT,
1403 HADDR_1 (msgout),
1404 SCR_JUMP,
1405 PADDR_B (msg_out_done),
1406 }/*-------------------------< SDTR_RESP >------------------------*/,{
1407 /*
1408 * let the target fetch our answer.
1409 */
1410 SCR_SET (SCR_ATN),
1411 0,
1412 SCR_CLR (SCR_ACK),
1413 0,
1414 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)),
1415 PADDR_B (nego_bad_phase),
1416 }/*-------------------------< SEND_SDTR >------------------------*/,{
1417 /*
1418 * Send the M_X_SYNC_REQ
1419 */
1420 SCR_MOVE_ABS (5) ^ SCR_MSG_OUT,
1421 HADDR_1 (msgout),
1422 SCR_JUMP,
1423 PADDR_B (msg_out_done),
1424 }/*-------------------------< PPR_RESP >-------------------------*/,{
1425 /*
1426 * let the target fetch our answer.
1427 */
1428 SCR_SET (SCR_ATN),
1429 0,
1430 SCR_CLR (SCR_ACK),
1431 0,
1432 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)),
1433 PADDR_B (nego_bad_phase),
1434 }/*-------------------------< SEND_PPR >-------------------------*/,{
1435 /*
1436 * Send the M_X_PPR_REQ
1437 */
1438 SCR_MOVE_ABS (8) ^ SCR_MSG_OUT,
1439 HADDR_1 (msgout),
1440 SCR_JUMP,
1441 PADDR_B (msg_out_done),
1442 }/*-------------------------< NEGO_BAD_PHASE >-------------------*/,{
1443 SCR_INT,
1444 SIR_NEGO_PROTO,
1445 SCR_JUMP,
1446 PADDR_A (dispatch),
1447 }/*-------------------------< MSG_OUT >--------------------------*/,{
1448 /*
1449 * The target requests a message.
1450 * We donnot send messages that may
1451 * require the device to go to bus free.
1452 */
1453 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT,
1454 HADDR_1 (msgout),
1455 /*
1456 * ... wait for the next phase
1457 * if it's a message out, send it again, ...
1458 */
1459 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)),
1460 PADDR_B (msg_out),
1461 }/*-------------------------< MSG_OUT_DONE >---------------------*/,{
1462 /*
1463 * Let the C code be aware of the
1464 * sent message and clear the message.
1465 */
1466 SCR_INT,
1467 SIR_MSG_OUT_DONE,
1468 /*
1469 * ... and process the next phase
1470 */
1471 SCR_JUMP,
1472 PADDR_A (dispatch),
1473 }/*-------------------------< DATA_OVRUN >-----------------------*/,{
1474 /*
1475 * Use scratcha to count the extra bytes.
1476 */
1477 SCR_LOAD_ABS (scratcha, 4),
1478 PADDR_B (zero),
1479 }/*-------------------------< DATA_OVRUN1 >----------------------*/,{
1480 /*
1481 * The target may want to transfer too much data.
1482 *
1483 * If phase is DATA OUT write 1 byte and count it.
1484 */
1485 SCR_JUMPR ^ IFFALSE (WHEN (SCR_DATA_OUT)),
1486 16,
1487 SCR_CHMOV_ABS (1) ^ SCR_DATA_OUT,
1488 HADDR_1 (scratch),
1489 SCR_JUMP,
1490 PADDR_B (data_ovrun2),
1491 /*
1492 * If WSR is set, clear this condition, and
1493 * count this byte.
1494 */
1495 SCR_FROM_REG (scntl2),
1496 0,
1497 SCR_JUMPR ^ IFFALSE (MASK (WSR, WSR)),
1498 16,
1499 SCR_REG_REG (scntl2, SCR_OR, WSR),
1500 0,
1501 SCR_JUMP,
1502 PADDR_B (data_ovrun2),
1503 /*
1504 * Finally check against DATA IN phase.
1505 * Signal data overrun to the C code
1506 * and jump to dispatcher if not so.
1507 * Read 1 byte otherwise and count it.
1508 */
1509 SCR_JUMPR ^ IFTRUE (WHEN (SCR_DATA_IN)),
1510 16,
1511 SCR_INT,
1512 SIR_DATA_OVERRUN,
1513 SCR_JUMP,
1514 PADDR_A (dispatch),
1515 SCR_CHMOV_ABS (1) ^ SCR_DATA_IN,
1516 HADDR_1 (scratch),
1517 }/*-------------------------< DATA_OVRUN2 >----------------------*/,{
1518 /*
1519 * Count this byte.
1520 * This will allow to return a negative
1521 * residual to user.
1522 */
1523 SCR_REG_REG (scratcha, SCR_ADD, 0x01),
1524 0,
1525 SCR_REG_REG (scratcha1, SCR_ADDC, 0),
1526 0,
1527 SCR_REG_REG (scratcha2, SCR_ADDC, 0),
1528 0,
1529 /*
1530 * .. and repeat as required.
1531 */
1532 SCR_JUMP,
1533 PADDR_B (data_ovrun1),
1534 }/*-------------------------< ABORT_RESEL >----------------------*/,{
1535 SCR_SET (SCR_ATN),
1536 0,
1537 SCR_CLR (SCR_ACK),
1538 0,
1539 /*
1540 * send the abort/abortag/reset message
1541 * we expect an immediate disconnect
1542 */
1543 SCR_REG_REG (scntl2, SCR_AND, 0x7f),
1544 0,
1545 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT,
1546 HADDR_1 (msgout),
1547 SCR_CLR (SCR_ACK|SCR_ATN),
1548 0,
1549 SCR_WAIT_DISC,
1550 0,
1551 SCR_INT,
1552 SIR_RESEL_ABORTED,
1553 SCR_JUMP,
1554 PADDR_A (start),
1555 }/*-------------------------< RESEND_IDENT >---------------------*/,{
1556 /*
1557 * The target stays in MSG OUT phase after having acked
1558 * Identify [+ Tag [+ Extended message ]]. Targets shall
1559 * behave this way on parity error.
1560 * We must send it again all the messages.
1561 */
1562 SCR_SET (SCR_ATN), /* Shall be asserted 2 deskew delays before the */
1563 0, /* 1rst ACK = 90 ns. Hope the chip isn't too fast */
1564 SCR_JUMP,
1565 PADDR_A (send_ident),
1566 }/*-------------------------< IDENT_BREAK >----------------------*/,{
1567 SCR_CLR (SCR_ATN),
1568 0,
1569 SCR_JUMP,
1570 PADDR_A (select2),
1571 }/*-------------------------< IDENT_BREAK_ATN >------------------*/,{
1572 SCR_SET (SCR_ATN),
1573 0,
1574 SCR_JUMP,
1575 PADDR_A (select2),
1576 }/*-------------------------< SDATA_IN >-------------------------*/,{
1577 SCR_CHMOV_TBL ^ SCR_DATA_IN,
1578 offsetof (struct sym_dsb, sense),
1579 SCR_CALL,
1580 PADDR_A (datai_done),
1581 SCR_JUMP,
1582 PADDR_B (data_ovrun),
1583 }/*-------------------------< RESEL_BAD_LUN >--------------------*/,{
1584 /*
1585 * Message is an IDENTIFY, but lun is unknown.
1586 * Signal problem to C code for logging the event.
1587 * Send a M_ABORT to clear all pending tasks.
1588 */
1589 SCR_INT,
1590 SIR_RESEL_BAD_LUN,
1591 SCR_JUMP,
1592 PADDR_B (abort_resel),
1593 }/*-------------------------< BAD_I_T_L >------------------------*/,{
1594 /*
1595 * We donnot have a task for that I_T_L.
1596 * Signal problem to C code for logging the event.
1597 * Send a M_ABORT message.
1598 */
1599 SCR_INT,
1600 SIR_RESEL_BAD_I_T_L,
1601 SCR_JUMP,
1602 PADDR_B (abort_resel),
1603 }/*-------------------------< BAD_I_T_L_Q >----------------------*/,{
1604 /*
1605 * We donnot have a task that matches the tag.
1606 * Signal problem to C code for logging the event.
1607 * Send a M_ABORTTAG message.
1608 */
1609 SCR_INT,
1610 SIR_RESEL_BAD_I_T_L_Q,
1611 SCR_JUMP,
1612 PADDR_B (abort_resel),
1613 }/*-------------------------< BAD_STATUS >-----------------------*/,{
1614 /*
1615 * Anything different from INTERMEDIATE
1616 * CONDITION MET should be a bad SCSI status,
1617 * given that GOOD status has already been tested.
1618 * Call the C code.
1619 */
1620 SCR_LOAD_ABS (scratcha, 4),
1621 PADDR_B (startpos),
1622 SCR_INT ^ IFFALSE (DATA (S_COND_MET)),
1623 SIR_BAD_SCSI_STATUS,
1624 SCR_RETURN,
1625 0,
1626 }/*-------------------------< PM_HANDLE >------------------------*/,{
1627 /*
1628 * Phase mismatch handling.
1629 *
1630 * Since we have to deal with 2 SCSI data pointers
1631 * (current and saved), we need at least 2 contexts.
1632 * Each context (pm0 and pm1) has a saved area, a
1633 * SAVE mini-script and a DATA phase mini-script.
1634 */
1635 /*
1636 * Get the PM handling flags.
1637 */
1638 SCR_FROM_REG (HF_REG),
1639 0,
1640 /*
1641 * If no flags (1rst PM for example), avoid
1642 * all the below heavy flags testing.
1643 * This makes the normal case a bit faster.
1644 */
1645 SCR_JUMP ^ IFTRUE (MASK (0, (HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED))),
1646 PADDR_B (pm_handle1),
1647 /*
1648 * If we received a SAVE DP, switch to the
1649 * other PM context since the savep may point
1650 * to the current PM context.
1651 */
1652 SCR_JUMPR ^ IFFALSE (MASK (HF_DP_SAVED, HF_DP_SAVED)),
1653 8,
1654 SCR_REG_REG (sfbr, SCR_XOR, HF_ACT_PM),
1655 0,
1656 /*
1657 * If we have been interrupt in a PM DATA mini-script,
1658 * we take the return address from the corresponding
1659 * saved area.
1660 * This ensure the return address always points to the
1661 * main DATA script for this transfer.
1662 */
1663 SCR_JUMP ^ IFTRUE (MASK (0, (HF_IN_PM0 | HF_IN_PM1))),
1664 PADDR_B (pm_handle1),
1665 SCR_JUMPR ^ IFFALSE (MASK (HF_IN_PM0, HF_IN_PM0)),
1666 16,
1667 SCR_LOAD_REL (ia, 4),
1668 offsetof(struct sym_ccb, phys.pm0.ret),
1669 SCR_JUMP,
1670 PADDR_B (pm_save),
1671 SCR_LOAD_REL (ia, 4),
1672 offsetof(struct sym_ccb, phys.pm1.ret),
1673 SCR_JUMP,
1674 PADDR_B (pm_save),
1675 }/*-------------------------< PM_HANDLE1 >-----------------------*/,{
1676 /*
1677 * Normal case.
1678 * Update the return address so that it
1679 * will point after the interrupted MOVE.
1680 */
1681 SCR_REG_REG (ia, SCR_ADD, 8),
1682 0,
1683 SCR_REG_REG (ia1, SCR_ADDC, 0),
1684 0,
1685 }/*-------------------------< PM_SAVE >--------------------------*/,{
1686 /*
1687 * Clear all the flags that told us if we were
1688 * interrupted in a PM DATA mini-script and/or
1689 * we received a SAVE DP.
1690 */
1691 SCR_SFBR_REG (HF_REG, SCR_AND, (~(HF_IN_PM0|HF_IN_PM1|HF_DP_SAVED))),
1692 0,
1693 /*
1694 * Choose the current PM context.
1695 */
1696 SCR_JUMP ^ IFTRUE (MASK (HF_ACT_PM, HF_ACT_PM)),
1697 PADDR_B (pm1_save),
1698 }/*-------------------------< PM0_SAVE >-------------------------*/,{
1699 SCR_STORE_REL (ia, 4),
1700 offsetof(struct sym_ccb, phys.pm0.ret),
1701 /*
1702 * If WSR bit is set, either UA and RBC may
1703 * have to be changed whether the device wants
1704 * to ignore this residue or not.
1705 */
1706 SCR_FROM_REG (scntl2),
1707 0,
1708 SCR_CALL ^ IFTRUE (MASK (WSR, WSR)),
1709 PADDR_B (pm_wsr_handle),
1710 /*
1711 * Save the remaining byte count, the updated
1712 * address and the return address.
1713 */
1714 SCR_STORE_REL (rbc, 4),
1715 offsetof(struct sym_ccb, phys.pm0.sg.size),
1716 SCR_STORE_REL (ua, 4),
1717 offsetof(struct sym_ccb, phys.pm0.sg.addr),
1718 /*
1719 * Set the current pointer at the PM0 DATA mini-script.
1720 */
1721 SCR_LOAD_ABS (ia, 4),
1722 PADDR_B (pm0_data_addr),
1723 }/*-------------------------< PM_SAVE_END >----------------------*/,{
1724 SCR_STORE_REL (ia, 4),
1725 offsetof(struct sym_ccb, phys.head.lastp),
1726 SCR_JUMP,
1727 PADDR_A (dispatch),
1728 }/*-------------------------< PM1_SAVE >-------------------------*/,{
1729 SCR_STORE_REL (ia, 4),
1730 offsetof(struct sym_ccb, phys.pm1.ret),
1731 /*
1732 * If WSR bit is set, either UA and RBC may
1733 * have to be changed whether the device wants
1734 * to ignore this residue or not.
1735 */
1736 SCR_FROM_REG (scntl2),
1737 0,
1738 SCR_CALL ^ IFTRUE (MASK (WSR, WSR)),
1739 PADDR_B (pm_wsr_handle),
1740 /*
1741 * Save the remaining byte count, the updated
1742 * address and the return address.
1743 */
1744 SCR_STORE_REL (rbc, 4),
1745 offsetof(struct sym_ccb, phys.pm1.sg.size),
1746 SCR_STORE_REL (ua, 4),
1747 offsetof(struct sym_ccb, phys.pm1.sg.addr),
1748 /*
1749 * Set the current pointer at the PM1 DATA mini-script.
1750 */
1751 SCR_LOAD_ABS (ia, 4),
1752 PADDR_B (pm1_data_addr),
1753 SCR_JUMP,
1754 PADDR_B (pm_save_end),
1755 }/*-------------------------< PM_WSR_HANDLE >--------------------*/,{
1756 /*
1757 * Phase mismatch handling from SCRIPT with WSR set.
1758 * Such a condition can occur if the chip wants to
1759 * execute a CHMOV(size > 1) when the WSR bit is
1760 * set and the target changes PHASE.
1761 *
1762 * We must move the residual byte to memory.
1763 *
1764 * UA contains bit 0..31 of the address to
1765 * move the residual byte.
1766 * Move it to the table indirect.
1767 */
1768 SCR_STORE_REL (ua, 4),
1769 offsetof (struct sym_ccb, phys.wresid.addr),
1770 /*
1771 * Increment UA (move address to next position).
1772 */
1773 SCR_REG_REG (ua, SCR_ADD, 1),
1774 0,
1775 SCR_REG_REG (ua1, SCR_ADDC, 0),
1776 0,
1777 SCR_REG_REG (ua2, SCR_ADDC, 0),
1778 0,
1779 SCR_REG_REG (ua3, SCR_ADDC, 0),
1780 0,
1781 /*
1782 * Compute SCRATCHA as:
1783 * - size to transfer = 1 byte.
1784 * - bit 24..31 = high address bit [32...39].
1785 */
1786 SCR_LOAD_ABS (scratcha, 4),
1787 PADDR_B (zero),
1788 SCR_REG_REG (scratcha, SCR_OR, 1),
1789 0,
1790 SCR_FROM_REG (rbc3),
1791 0,
1792 SCR_TO_REG (scratcha3),
1793 0,
1794 /*
1795 * Move this value to the table indirect.
1796 */
1797 SCR_STORE_REL (scratcha, 4),
1798 offsetof (struct sym_ccb, phys.wresid.size),
1799 /*
1800 * Wait for a valid phase.
1801 * While testing with bogus QUANTUM drives, the C1010
1802 * sometimes raised a spurious phase mismatch with
1803 * WSR and the CHMOV(1) triggered another PM.
1804 * Waiting explicitely for the PHASE seemed to avoid
1805 * the nested phase mismatch. Btw, this didn't happen
1806 * using my IBM drives.
1807 */
1808 SCR_JUMPR ^ IFFALSE (WHEN (SCR_DATA_IN)),
1809 0,
1810 /*
1811 * Perform the move of the residual byte.
1812 */
1813 SCR_CHMOV_TBL ^ SCR_DATA_IN,
1814 offsetof (struct sym_ccb, phys.wresid),
1815 /*
1816 * We can now handle the phase mismatch with UA fixed.
1817 * RBC[0..23]=0 is a special case that does not require
1818 * a PM context. The C code also checks against this.
1819 */
1820 SCR_FROM_REG (rbc),
1821 0,
1822 SCR_RETURN ^ IFFALSE (DATA (0)),
1823 0,
1824 SCR_FROM_REG (rbc1),
1825 0,
1826 SCR_RETURN ^ IFFALSE (DATA (0)),
1827 0,
1828 SCR_FROM_REG (rbc2),
1829 0,
1830 SCR_RETURN ^ IFFALSE (DATA (0)),
1831 0,
1832 /*
1833 * RBC[0..23]=0.
1834 * Not only we donnot need a PM context, but this would
1835 * lead to a bogus CHMOV(0). This condition means that
1836 * the residual was the last byte to move from this CHMOV.
1837 * So, we just have to move the current data script pointer
1838 * (i.e. TEMP) to the SCRIPTS address following the
1839 * interrupted CHMOV and jump to dispatcher.
1840 * IA contains the data pointer to save.
1841 */
1842 SCR_JUMP,
1843 PADDR_B (pm_save_end),
1844 }/*-------------------------< WSR_MA_HELPER >--------------------*/,{
1845 /*
1846 * Helper for the C code when WSR bit is set.
1847 * Perform the move of the residual byte.
1848 */
1849 SCR_CHMOV_TBL ^ SCR_DATA_IN,
1850 offsetof (struct sym_ccb, phys.wresid),
1851 SCR_JUMP,
1852 PADDR_A (dispatch),
1853
1854 #ifdef SYM_OPT_HANDLE_DIR_UNKNOWN
1855 }/*-------------------------< DATA_IO >--------------------------*/,{
1856 /*
1857 * We jump here if the data direction was unknown at the
1858 * time we had to queue the command to the scripts processor.
1859 * Pointers had been set as follow in this situation:
1860 * savep --> DATA_IO
1861 * lastp --> start pointer when DATA_IN
1862 * wlastp --> start pointer when DATA_OUT
1863 * This script sets savep and lastp according to the
1864 * direction chosen by the target.
1865 */
1866 SCR_JUMP ^ IFTRUE (WHEN (SCR_DATA_OUT)),
1867 PADDR_B (data_io_out),
1868 }/*-------------------------< DATA_IO_IN >-----------------------*/,{
1869 /*
1870 * Direction is DATA IN.
1871 */
1872 SCR_LOAD_REL (scratcha, 4),
1873 offsetof (struct sym_ccb, phys.head.lastp),
1874 }/*-------------------------< DATA_IO_COM >----------------------*/,{
1875 SCR_STORE_REL (scratcha, 4),
1876 offsetof (struct sym_ccb, phys.head.savep),
1877
1878 /*
1879 * Jump to the SCRIPTS according to actual direction.
1880 */
1881 SCR_LOAD_REL (temp, 4),
1882 offsetof (struct sym_ccb, phys.head.savep),
1883 SCR_RETURN,
1884 0,
1885 }/*-------------------------< DATA_IO_OUT >----------------------*/,{
1886 /*
1887 * Direction is DATA OUT.
1888 */
1889 SCR_REG_REG (HF_REG, SCR_AND, (~HF_DATA_IN)),
1890 0,
1891 SCR_LOAD_REL (scratcha, 4),
1892 offsetof (struct sym_ccb, phys.head.wlastp),
1893 SCR_STORE_REL (scratcha, 4),
1894 offsetof (struct sym_ccb, phys.head.lastp),
1895 SCR_JUMP,
1896 PADDR_B(data_io_com),
1897 #endif /* SYM_OPT_HANDLE_DIR_UNKNOWN */
1898
1899 }/*-------------------------< ZERO >-----------------------------*/,{
1900 SCR_DATA_ZERO,
1901 }/*-------------------------< SCRATCH >--------------------------*/,{
1902 SCR_DATA_ZERO,
1903 }/*-------------------------< PM0_DATA_ADDR >--------------------*/,{
1904 SCR_DATA_ZERO,
1905 }/*-------------------------< PM1_DATA_ADDR >--------------------*/,{
1906 SCR_DATA_ZERO,
1907 }/*-------------------------< DONE_POS >-------------------------*/,{
1908 SCR_DATA_ZERO,
1909 }/*-------------------------< STARTPOS >-------------------------*/,{
1910 SCR_DATA_ZERO,
1911 }/*-------------------------< TARGTBL >--------------------------*/,{
1912 SCR_DATA_ZERO,
1913 }/*-------------------------<>-----------------------------------*/
1914 };
1915
1916 static struct SYM_FWZ_SCR SYM_FWZ_SCR = {
1917 /*-------------------------< SNOOPTEST >------------------------*/{
1918 /*
1919 * Read the variable from memory.
1920 */
1921 SCR_LOAD_REL (scratcha, 4),
1922 offsetof(struct sym_hcb, scratch),
1923 /*
1924 * Write the variable to memory.
1925 */
1926 SCR_STORE_REL (temp, 4),
1927 offsetof(struct sym_hcb, scratch),
1928 /*
1929 * Read back the variable from memory.
1930 */
1931 SCR_LOAD_REL (temp, 4),
1932 offsetof(struct sym_hcb, scratch),
1933 }/*-------------------------< SNOOPEND >-------------------------*/,{
1934 /*
1935 * And stop.
1936 */
1937 SCR_INT,
1938 99,
1939 }/*-------------------------<>-----------------------------------*/
1940 };
MOXA 2.6.9 from sdlinux-moxaart.tgz