include/asm-arm/arch-moxacpu/ahb_dma.h

   1 /* ahb_dma.h */
   2 #ifndef _AHB_DMA_H_
   3 #define _AHB_DMA_H_
   4
   5 /* register definition */
   6 #define AHBDMA_INT_TC_0x04     0x04
   7 #define AHBDMA_ISR_0x8          0x8
   8 #define AHBDMA_INT_ERR_0x0C     0x0C
   9 #define AHBDMA_ENABLE_0x24      0x24
  10
  11 #define AHBDMA_CHANNEL_CSR_0x0          0x0
  12 #define AHBDMA_CHANNEL_CFG_0x4          0x4
  13 #define AHBDMA_CHANNEL_SRC_0x8          0x8
  14 #define AHBDMA_CHANNEL_DST_0xC          0xc
  15 #define AHBDMA_CHANNEL_LLP_0x10         0x10
  16 #define AHBDMA_CHANNEL_TXSZ_0x14        0x14
  17
  18 #define AHBDMA_WIDTH_8BIT       0x0
  19 #define AHBDMA_WIDTH_16BIT      0x1
  20 #define AHBDMA_WIDTH_32BIT      0x2
  21 #define AHBDMA_CTL_INC          0x0
  22 #define AHBDMA_CTL_DEC          0x1
  23 #define AHBDMA_CTL_FIX          0x2
  24
  25 #define AHBDMA_MASTER_0         0x0
  26 #define AHBDMA_MASTER_1         0x1
  27
  28 #define AHBDMA_NO_TRIGGER_IRQ   0x0
  29 #define AHBDMA_TRIGGER_IRQ      0x1    //john
  30
  31 //john add for interrupt status, error
  32 #define INT_TRIGGER 0x01
  33 #define INT_ERROR   0x02
  34
  35 typedef struct
  36 {
  37         unsigned int source;
  38         unsigned int dest;
  39         unsigned int llp;
  40         unsigned int control;
  41 } ahb_lld_t;
  42
  43 typedef struct
  44 {
  45     /* add dma parameter */
  46     unsigned int    src;        //source address for dma
  47     unsigned int    dest;       //dest address for dma
  48     unsigned int    sw;         //source width (0/1/2=>8/16/32)
  49     unsigned int    dw;         //dest width (0/1/2=>8/16/32)
  50     unsigned int    sctl;       //source control (0/1/2/3=>inc/dec/fix/x)
  51     unsigned int    dctl;       // dest coontrol (0/1/2/3=>inc/dec/fix/x)
  52     unsigned int    size;       // dma count
  53     unsigned int    irq;        // (0/1)==>(disable/enable)
  54 } ahb_dma_parm_t;
  55
  56 typedef struct
  57 {
  58     /* init parameter */
  59     unsigned int    base;
  60     unsigned int    channel_base;
  61     unsigned int    llp_master; //0,1
  62     unsigned int    src_data_master;//0,1
  63     unsigned int    dest_data_master;//0,1
  64     unsigned int    llp_count;
  65     unsigned int    channel;
  66     unsigned int    hw_handshake;
  67     unsigned int    llp_last_idx;   //0(register),1(first llp),2(second llp),3...
  68     unsigned int    llp_free_idx;   //0(register),1(first llp),2(second llp),3...
  69     ahb_lld_t       *ahb_dma_lld;
  70     ahb_lld_t       *ahb_last_lld;
  71     ahb_lld_t       *ahb_dma_lld_phys;
  72 } ahb_dma_data_t;
  73
  74
  75 ahb_dma_data_t *ahb_dma_alloc(void);
  76 void ahb_dma_free(ahb_dma_data_t *priv);
  77 int ahb_dma_init(ahb_dma_data_t *priv);
  78 void ahb_dma_add(ahb_dma_data_t *priv,ahb_dma_parm_t *parm);
  79 void ahb_dma_reset(ahb_dma_data_t *priv);
  80
  81 inline void ahb_dma_start(ahb_dma_data_t *priv);
  82 inline void ahbdma_clear_int(ahb_dma_data_t *priv);
  83 inline u32 ahbdma_get_dest_addr(ahb_dma_data_t *priv);
  84
  85 u32 ahbdma_get_status(ahb_dma_data_t *priv);
  86
  87 #endif