include/asm-arm/arch-omap/hardware.h

   1 /*
   2  * linux/include/asm-arm/arch-omap/hardware.h
   3  *
   4  * Hardware definitions for TI OMAP processors and boards
   5  *
   6  * NOTE: Please put device driver specific defines into a separate header
   7  *       file for each driver.
   8  *
   9  * Copyright (C) 2001 RidgeRun, Inc.
  10  * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
  11  *
  12  * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
  13  *                          and Dirk Behme <dirk.behme@de.bosch.com>
  14  *
  15  * This program is free software; you can redistribute it and/or modify it
  16  * under the terms of the GNU General Public License as published by the
  17  * Free Software Foundation; either version 2 of the License, or (at your
  18  * option) any later version.
  19  *
  20  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  21  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  22  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  23  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  26  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  27  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  30  *
  31  * You should have received a copy of the GNU General Public License along
  32  * with this program; if not, write to the Free Software Foundation, Inc.,
  33  * 675 Mass Ave, Cambridge, MA 02139, USA.
  34  */
  35
  36 #ifndef __ASM_ARCH_OMAP_HARDWARE_H
  37 #define __ASM_ARCH_OMAP_HARDWARE_H
  38
  39 #include <asm/sizes.h>
  40 #include <linux/config.h>
  41 #ifndef __ASSEMBLER__
  42 #include <asm/types.h>
  43 #endif
  44 #include <asm/arch/io.h>
  45
  46 /*
  47  * ---------------------------------------------------------------------------
  48  * Common definitions for all OMAP processors
  49  * NOTE: Put all processor or board specific parts to the special header
  50  *       files.
  51  * ---------------------------------------------------------------------------
  52  */
  53
  54 /*
  55  * ----------------------------------------------------------------------------
  56  * Clocks
  57  * ----------------------------------------------------------------------------
  58  */
  59 #define CLKGEN_REG_BASE         (0xfffece00)
  60 #define ARM_CKCTL               (CLKGEN_REG_BASE + 0x0)
  61 #define ARM_IDLECT1             (CLKGEN_REG_BASE + 0x4)
  62 #define ARM_IDLECT2             (CLKGEN_REG_BASE + 0x8)
  63 #define ARM_EWUPCT              (CLKGEN_REG_BASE + 0xC)
  64 #define ARM_RSTCT1              (CLKGEN_REG_BASE + 0x10)
  65 #define ARM_RSTCT2              (CLKGEN_REG_BASE + 0x14)
  66 #define ARM_SYSST               (CLKGEN_REG_BASE + 0x18)
  67
  68 #define CK_RATEF                1
  69 #define CK_IDLEF                2
  70 #define CK_ENABLEF              4
  71 #define CK_SELECTF              8
  72 #define SETARM_IDLE_SHIFT
  73
  74 /* DPLL control registers */
  75 #define DPLL_CTL                (0xfffecf00)
  76
  77 /* DSP clock control */
  78 #define DSP_CONFIG_REG_BASE     (0xe1008000)
  79 #define DSP_IDLECT1             (DSP_CONFIG_REG_BASE + 0x4)
  80 #define DSP_IDLECT2             (DSP_CONFIG_REG_BASE + 0x8)
  81
  82 /*
  83  * ---------------------------------------------------------------------------
  84  * UPLD
  85  * ---------------------------------------------------------------------------
  86  */
  87 #define ULPD_REG_BASE           (0xfffe0800)
  88 #define ULPD_IT_STATUS          (ULPD_REG_BASE + 0x14)
  89 #define ULPD_CLOCK_CTRL         (ULPD_REG_BASE + 0x30)
  90 #define ULPD_SOFT_REQ           (ULPD_REG_BASE + 0x34)
  91 #define ULPD_DPLL_CTRL          (ULPD_REG_BASE + 0x3c)
  92 #define ULPD_STATUS_REQ         (ULPD_REG_BASE + 0x40)
  93 #define ULPD_APLL_CTRL          (ULPD_REG_BASE + 0x4c)
  94 #define ULPD_POWER_CTRL         (ULPD_REG_BASE + 0x50)
  95 #define ULPD_CAM_CLK_CTRL       (ULPD_REG_BASE + 0x7c)
  96
  97 /*
  98  * ---------------------------------------------------------------------------
  99  * Timers
 100  * ---------------------------------------------------------------------------
 101  */
 102 #define OMAP_32kHz_TIMER_BASE 0xfffb9000
 103
 104 /* 32k Timer Registers */
 105 #define TIMER32k_CR             0x08
 106 #define TIMER32k_TVR            0x00
 107 #define TIMER32k_TCR            0x04
 108
 109 /* 32k Timer Control Register definition */
 110 #define TIMER32k_TSS            (1<<0)
 111 #define TIMER32k_TRB            (1<<1)
 112 #define TIMER32k_INT            (1<<2)
 113 #define TIMER32k_ARL            (1<<3)
 114
 115 /* MPU Timer base addresses */
 116 #define OMAP_TIMER1_BASE        (0xfffec500)
 117 #define OMAP_TIMER2_BASE        (0xfffec600)
 118 #define OMAP_TIMER3_BASE        (0xfffec700)
 119 #define OMAP_MPUTIMER_BASE      OMAP_TIMER1_BASE
 120 #define OMAP_MPUTIMER_OFFSET    0x100
 121
 122 /* MPU Timer Registers */
 123 #define OMAP_TIMER1_CNTL        (OMAP_TIMER_BASE1 + 0x0)
 124 #define OMAP_TIMER1_LOAD_TIM    (OMAP_TIMER_BASE1 + 0x4)
 125 #define OMAP_TIMER1_READ_TIM    (OMAP_TIMER_BASE1 + 0x8)
 126
 127 #define OMAP_TIMER2_CNTL        (OMAP_TIMER_BASE2 + 0x0)
 128 #define OMAP_TIMER2_LOAD_TIM    (OMAP_TIMER_BASE2 + 0x4)
 129 #define OMAP_TIMER2_READ_TIM    (OMAP_TIMER_BASE2 + 0x8)
 130
 131 #define OMAP_TIMER3_CNTL        (OMAP_TIMER_BASE3 + 0x0)
 132 #define OMAP_TIMER3_LOAD_TIM    (OMAP_TIMER_BASE3 + 0x4)
 133 #define OMAP_TIMER3_READ_TIM    (OMAP_TIMER_BASE3 + 0x8)
 134
 135 /* CNTL_TIMER register bits */
 136 #define MPUTIM_FREE             (1<<6)
 137 #define MPUTIM_CLOCK_ENABLE     (1<<5)
 138 #define MPUTIM_PTV_MASK         (0x7<<PTV_BIT)
 139 #define MPUTIM_PTV_BIT          2
 140 #define MPUTIM_AR               (1<<1)
 141 #define MPUTIM_ST               (1<<0)
 142
 143 /* Watchdog */
 144 #define OMAP_WATCHDOG_BASE      (0xfffec800)
 145 #define OMAP_WDT_TIMER          (OMAP_WATCHDOG_BASE + 0x0)
 146 #define OMAP_WDT_LOAD_TIM       (OMAP_WATCHDOG_BASE + 0x4)
 147 #define OMAP_WDT_READ_TIM       (OMAP_WATCHDOG_BASE + 0x4)
 148 #define OMAP_WDT_TIMER_MODE     (OMAP_WATCHDOG_BASE + 0x8)
 149
 150 /*
 151  * ---------------------------------------------------------------------------
 152  * Interrupts
 153  * ---------------------------------------------------------------------------
 154  */
 155 #define OMAP_IH1_BASE           0xfffecb00
 156 #define OMAP_IH2_BASE           0xfffe0000
 157
 158 #define OMAP_IH1_ITR            (OMAP_IH1_BASE + 0x00)
 159 #define OMAP_IH1_MIR            (OMAP_IH1_BASE + 0x04)
 160 #define OMAP_IH1_SIR_IRQ        (OMAP_IH1_BASE + 0x10)
 161 #define OMAP_IH1_SIR_FIQ        (OMAP_IH1_BASE + 0x14)
 162 #define OMAP_IH1_CONTROL        (OMAP_IH1_BASE + 0x18)
 163 #define OMAP_IH1_ILR0           (OMAP_IH1_BASE + 0x1c)
 164 #define OMAP_IH1_ISR            (OMAP_IH1_BASE + 0x9c)
 165
 166 #define OMAP_IH2_ITR            (OMAP_IH2_BASE + 0x00)
 167 #define OMAP_IH2_MIR            (OMAP_IH2_BASE + 0x04)
 168 #define OMAP_IH2_SIR_IRQ        (OMAP_IH2_BASE + 0x10)
 169 #define OMAP_IH2_SIR_FIQ        (OMAP_IH2_BASE + 0x14)
 170 #define OMAP_IH2_CONTROL        (OMAP_IH2_BASE + 0x18)
 171 #define OMAP_IH2_ILR0           (OMAP_IH2_BASE + 0x1c)
 172 #define OMAP_IH2_ISR            (OMAP_IH2_BASE + 0x9c)
 173
 174 #define IRQ_ITR_REG_OFFSET      0x00
 175 #define IRQ_MIR_REG_OFFSET      0x04
 176 #define IRQ_SIR_IRQ_REG_OFFSET  0x10
 177 #define IRQ_SIR_FIQ_REG_OFFSET  0x14
 178 #define IRQ_CONTROL_REG_OFFSET  0x18
 179 #define IRQ_ISR_REG_OFFSET      0x9c
 180 #define IRQ_ILR0_REG_OFFSET     0x1c
 181 #define IRQ_GMR_REG_OFFSET      0xa0
 182
 183 /*
 184  * ---------------------------------------------------------------------------
 185  * Traffic controller memory interface
 186  * ---------------------------------------------------------------------------
 187  */
 188 #define TCMIF_BASE              0xfffecc00
 189 #define IMIF_PRIO_REG           __REG32(TCMIF_BASE + 0x00)
 190 #define EMIFS_PRIO_REG          __REG32(TCMIF_BASE + 0x04)
 191 #define EMIFF_PRIO_REG          __REG32(TCMIF_BASE + 0x08)
 192 #define EMIFS_CONFIG_REG        __REG32(TCMIF_BASE + 0x0c)
 193 #define EMIFS_CS0_CONFIG_REG    __REG32(TCMIF_BASE + 0x10)
 194 #define EMIFS_CS1_CONFIG_REG    __REG32(TCMIF_BASE + 0x14)
 195 #define EMIFS_CS2_CONFIG_REG    __REG32(TCMIF_BASE + 0x18)
 196 #define EMIFS_CS3_CONFIG_REG    __REG32(TCMIF_BASE + 0x1c)
 197 #define EMIFF_SDRAM_CONFIG_REG  __REG32(TCMIF_BASE + 0x20)
 198 #define EMIFF_MRS_REG           __REG32(TCMIF_BASE + 0x24)
 199 #define TC_TIMEOUT1_REG         __REG32(TCMIF_BASE + 0x28)
 200 #define TC_TIMEOUT2_REG         __REG32(TCMIF_BASE + 0x2c)
 201 #define TC_TIMEOUT3_REG         __REG32(TCMIF_BASE + 0x30)
 202 #define TC_ENDIANISM_REG        __REG32(TCMIF_BASE + 0x34)
 203 #define EMIFF_SDRAM_CONFIG_2_REG __REG32(TCMIF_BASE + 0x3c)
 204 #define EMIF_CFG_DYNAMIC_WS_REG __REG32(TCMIF_BASE + 0x40)
 205
 206 /*
 207  * ----------------------------------------------------------------------------
 208  * System control registers
 209  * ----------------------------------------------------------------------------
 210  */
 211 #define MOD_CONF_CTRL_0         0xfffe1080
 212 #define MOD_CONF_CTRL_1         0xfffe1110
 213
 214 /*
 215  * ----------------------------------------------------------------------------
 216  * Pin multiplexing registers
 217  * ----------------------------------------------------------------------------
 218  */
 219 #define FUNC_MUX_CTRL_0         0xfffe1000
 220 #define FUNC_MUX_CTRL_1         0xfffe1004
 221 #define FUNC_MUX_CTRL_2         0xfffe1008
 222 #define COMP_MODE_CTRL_0        0xfffe100c
 223 #define FUNC_MUX_CTRL_3         0xfffe1010
 224 #define FUNC_MUX_CTRL_4         0xfffe1014
 225 #define FUNC_MUX_CTRL_5         0xfffe1018
 226 #define FUNC_MUX_CTRL_6         0xfffe101C
 227 #define FUNC_MUX_CTRL_7         0xfffe1020
 228 #define FUNC_MUX_CTRL_8         0xfffe1024
 229 #define FUNC_MUX_CTRL_9         0xfffe1028
 230 #define FUNC_MUX_CTRL_A         0xfffe102C
 231 #define FUNC_MUX_CTRL_B         0xfffe1030
 232 #define FUNC_MUX_CTRL_C         0xfffe1034
 233 #define FUNC_MUX_CTRL_D         0xfffe1038
 234 #define PULL_DWN_CTRL_0         0xfffe1040
 235 #define PULL_DWN_CTRL_1         0xfffe1044
 236 #define PULL_DWN_CTRL_2         0xfffe1048
 237 #define PULL_DWN_CTRL_3         0xfffe104c
 238
 239 /* OMAP-1610 specific multiplexing registers */
 240 #define FUNC_MUX_CTRL_E         0xfffe1090
 241 #define FUNC_MUX_CTRL_F         0xfffe1094
 242 #define FUNC_MUX_CTRL_10        0xfffe1098
 243 #define FUNC_MUX_CTRL_11        0xfffe109c
 244 #define FUNC_MUX_CTRL_12        0xfffe10a0
 245 #define PU_PD_SEL_0             0xfffe10b4
 246 #define PU_PD_SEL_1             0xfffe10b8
 247 #define PU_PD_SEL_2             0xfffe10bc
 248 #define PU_PD_SEL_3             0xfffe10c0
 249 #define PU_PD_SEL_4             0xfffe10c4
 250
 251 /*
 252  * ---------------------------------------------------------------------------
 253  * TIPB bus interface
 254  * ---------------------------------------------------------------------------
 255  */
 256 #define TIPB_PUBLIC_CNTL_BASE           0xfffed300
 257 #define MPU_PUBLIC_TIPB_CNTL            (TIPB_PUBLIC_CNTL_BASE + 0x8)
 258 #define TIPB_PRIVATE_CNTL_BASE          0xfffeca00
 259 #define MPU_PRIVATE_TIPB_CNTL           (TIPB_PRIVATE_CNTL_BASE + 0x8)
 260
 261 /*
 262  * ----------------------------------------------------------------------------
 263  * MPUI interface
 264  * ----------------------------------------------------------------------------
 265  */
 266 #define MPUI_BASE                       (0xfffec900)
 267 #define MPUI_CTRL                       (MPUI_BASE + 0x0)
 268 #define MPUI_DEBUG_ADDR                 (MPUI_BASE + 0x4)
 269 #define MPUI_DEBUG_DATA                 (MPUI_BASE + 0x8)
 270 #define MPUI_DEBUG_FLAG                 (MPUI_BASE + 0xc)
 271 #define MPUI_STATUS_REG                 (MPUI_BASE + 0x10)
 272 #define MPUI_DSP_STATUS                 (MPUI_BASE + 0x14)
 273 #define MPUI_DSP_BOOT_CONFIG            (MPUI_BASE + 0x18)
 274 #define MPUI_DSP_API_CONFIG             (MPUI_BASE + 0x1c)
 275
 276 #ifndef __ASSEMBLER__
 277
 278 /*
 279  * ---------------------------------------------------------------------------
 280  * Processor differentiation
 281  * ---------------------------------------------------------------------------
 282  */
 283 #define OMAP_ID_BASE            (0xfffed400)
 284 #define OMAP_ID_REG             __REG32(OMAP_ID_BASE +  0x04)
 285
 286 #define ID_SHIFT                12
 287 #define ID_MASK                 0x7fff
 288
 289 /* See also uncompress.h */
 290 #define OMAP_ID_730             0x355F
 291 #define OMAP_ID_1510            0x3470
 292 #define OMAP_ID_1610            0x3576
 293 #define OMAP_ID_1710            0x35F7
 294 #define OMAP_ID_5912            0x358C
 295 #define OMAP_ID_1611            0x358C
 296
 297 #ifdef CONFIG_ARCH_OMAP730
 298 #include "omap730.h"
 299 #define cpu_is_omap730()        (((OMAP_ID_REG >> ID_SHIFT) & ID_MASK) == OMAP_ID_730)
 300 #else
 301 #define cpu_is_omap730()        0
 302 #endif
 303
 304 #ifdef CONFIG_ARCH_OMAP1510
 305 #include "omap1510.h"
 306 #define cpu_is_omap1510()       (((OMAP_ID_REG >> ID_SHIFT) & ID_MASK) == OMAP_ID_1510)
 307 #else
 308 #define cpu_is_omap1510()       0
 309 #endif
 310
 311 #ifdef CONFIG_ARCH_OMAP1610
 312 #include "omap1610.h"
 313 #define cpu_is_omap1610()       (((OMAP_ID_REG >> ID_SHIFT) & ID_MASK) == OMAP_ID_1610) || \
 314                                 (((OMAP_ID_REG >> ID_SHIFT) & ID_MASK) == OMAP_ID_1611)
 315 #else
 316 #define cpu_is_omap1610()       0
 317 #endif
 318
 319 #ifdef CONFIG_ARCH_OMAP1710
 320 #include "omap1610.h"
 321 #define cpu_is_omap1710()       (((OMAP_ID_REG >> ID_SHIFT) & ID_MASK) == OMAP_ID_1710)
 322 #else
 323 #define cpu_is_omap1710()       0
 324 #endif
 325
 326 #ifdef CONFIG_ARCH_OMAP5912
 327 #include "omap5912.h"
 328 #define cpu_is_omap5912()       (((OMAP_ID_REG >> ID_SHIFT) & ID_MASK) == OMAP_ID_5912)
 329 #else
 330 #define cpu_is_omap5912()       0
 331 #endif
 332
 333 /*
 334  * ---------------------------------------------------------------------------
 335  * Board differentiation
 336  * ---------------------------------------------------------------------------
 337  */
 338
 339 #ifdef CONFIG_MACH_OMAP_INNOVATOR
 340 #include "board-innovator.h"
 341 #endif
 342
 343 #ifdef CONFIG_MACH_OMAP_H2
 344 #include "board-h2.h"
 345 #endif
 346
 347 #ifdef CONFIG_MACH_OMAP_PERSEUS2
 348 #include "board-perseus2.h"
 349 #endif
 350
 351 #ifdef CONFIG_MACH_OMAP_H3
 352 #include "board-h3.h"
 353 #endif
 354
 355 #ifdef CONFIG_MACH_OMAP_H4
 356 #include "board-h4.h"
 357 #error "Support for H4 board not yet implemented."
 358 #endif
 359
 360 #ifdef CONFIG_MACH_OMAP_OSK
 361 #include "board-osk.h"
 362 #endif
 363
 364 #endif /* !__ASSEMBLER__ */
 365
 366 #endif  /* __ASM_ARCH_OMAP_HARDWARE_H */