?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
MOXA linux-2.6.x / linux-2.6.9-uc0 from sdlinux-moxaart.tgz
[linux-2.6.9-moxart.git] / include / asm-arm / arch-omap / mux.h
blobd0fdf9833ac4a7e6ffda4b547e87d71465951f2b
1 /*
2 * linux/include/asm-arm/arch-omap/mux.h
3 *
4 * Table of the Omap register configurations for the FUNC_MUX and
5 * PULL_DWN combinations.
6 *
7 * Copyright (C) 2003 Nokia Corporation
8 *
9 * Written by Tony Lindgren <tony.lindgren@nokia.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 * NOTE: Please use the following naming style for new pin entries.
26 * For example, W8_1610_MMC2_DAT0, where:
27 * - W8 = ball
28 * - 1610 = 1510 or 1610, none if common for both 1510 and 1610
29 * - MMC2_DAT0 = function
30 *
31 * Change log:
32 * Added entry for the I2C interface. (02Feb 2004)
33 * Copyright (C) 2004 Texas Instruments
34 *
35 * Added entry for the keypad and uwire CS1. (09Mar 2004)
36 * Copyright (C) 2004 Texas Instruments
37 *
38 */
39
40 #ifndef __ASM_ARCH_MUX_H
41 #define __ASM_ARCH_MUX_H
42
43 #define PU_PD_SEL_NA 0 /* No pu_pd reg available */
44 #define PULL_DWN_CTRL_NA 0 /* No pull-down control needed */
45
46 #define DEBUG_MUX
47
48 #ifdef DEBUG_MUX
49 #define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
50 .mux_reg = FUNC_MUX_CTRL_##reg, \
51 .mask_offset = mode_offset, \
52 .mask = mode,
53
54 #define PULL_REG(reg, bit, status) .pull_name = "PULL_DWN_CTRL_"#reg, \
55 .pull_reg = PULL_DWN_CTRL_##reg, \
56 .pull_bit = bit, \
57 .pull_val = status,
58
59 #define PU_PD_REG(reg, status) .pu_pd_name = "PU_PD_SEL_"#reg, \
60 .pu_pd_reg = PU_PD_SEL_##reg, \
61 .pu_pd_val = status,
62
63 #else
64
65 #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
66 .mask_offset = mode_offset, \
67 .mask = mode,
68
69 #define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg, \
70 .pull_bit = bit, \
71 .pull_val = status,
72
73 #define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \
74 .pu_pd_val = status,
75
76 #endif // DEBUG_MUX
77
78 #define MUX_CFG(desc, mux_reg, mode_offset, mode, \
79 pull_reg, pull_bit, pull_status, \
80 pu_pd_reg, pu_pd_status, debug_status) \
81 { \
82 .name = desc, \
83 .debug = debug_status, \
84 MUX_REG(mux_reg, mode_offset, mode) \
85 PULL_REG(pull_reg, pull_bit, pull_status) \
86 PU_PD_REG(pu_pd_reg, pu_pd_status) \
87 },
88
89 #define PULL_DISABLED 0
90 #define PULL_ENABLED 1
91
92 #define PULL_DOWN 0
93 #define PULL_UP 1
94
95 typedef struct {
96 char *name;
97 unsigned char busy;
98 unsigned char debug;
99
100 const char *mux_reg_name;
101 const unsigned int mux_reg;
102 const unsigned char mask_offset;
103 const unsigned char mask;
104
105 const char *pull_name;
106 const unsigned int pull_reg;
107 const unsigned char pull_val;
108 const unsigned char pull_bit;
109
110 const char *pu_pd_name;
111 const unsigned int pu_pd_reg;
112 const unsigned char pu_pd_val;
113 } reg_cfg_set;
114
115 /*
116 * Lookup table for FUNC_MUX and PULL_DWN register combinations for each
117 * device. See also reg_cfg_table below for the register values.
118 */
119 typedef enum {
120 /* UART1 (BT_UART_GATING)*/
121 UART1_TX = 0,
122 UART1_RTS,
123
124 /* UART2 (COM_UART_GATING)*/
125 UART2_TX,
126 UART2_RX,
127 UART2_CTS,
128 UART2_RTS,
129
130 /* UART3 (GIGA_UART_GATING) */
131 UART3_TX,
132 UART3_RX,
133 UART3_CTS,
134 UART3_RTS,
135 UART3_CLKREQ,
136 UART3_BCLK, /* 12MHz clock out */
137
138 /* PWT & PWL */
139 PWT,
140 PWL,
141
142 /* USB master generic */
143 R18_USB_VBUS,
144 R18_1510_USB_GPIO0,
145 W4_USB_PUEN,
146 W4_USB_CLKO,
147 W4_USB_HIGHZ,
148 W4_GPIO58,
149
150 /* USB1 master */
151 USB1_SUSP,
152 USB1_SEO,
153 W13_1610_USB1_SE0,
154 USB1_TXEN,
155 USB1_TXD,
156 USB1_VP,
157 USB1_VM,
158 USB1_RCV,
159 USB1_SPEED,
160 R13_1610_USB1_SPEED,
161 R13_1710_USB1_SE0,
162
163 /* USB2 master */
164 USB2_SUSP,
165 USB2_VP,
166 USB2_TXEN,
167 USB2_VM,
168 USB2_RCV,
169 USB2_SEO,
170 USB2_TXD,
171
172 /* OMAP-1510 GPIO */
173 R18_1510_GPIO0,
174 R19_1510_GPIO1,
175 M14_1510_GPIO2,
176
177 /* OMAP-1710 GPIO */
178 R18_1710_GPIO0,
179 W15_1710_GPIO40,
180
181 /* MPUIO */
182 MPUIO2,
183 MPUIO4,
184 MPUIO5,
185 T20_1610_MPUIO5,
186 W11_1610_MPUIO6,
187 V10_1610_MPUIO7,
188 W11_1610_MPUIO9,
189 V10_1610_MPUIO10,
190 W10_1610_MPUIO11,
191 E20_1610_MPUIO13,
192 U20_1610_MPUIO14,
193 E19_1610_MPUIO15,
194
195 /* MCBSP2 */
196 MCBSP2_CLKR,
197 MCBSP2_CLKX,
198 MCBSP2_DR,
199 MCBSP2_DX,
200 MCBSP2_FSR,
201 MCBSP2_FSX,
202
203 /* MCBSP3 */
204 MCBSP3_CLKX,
205
206 /* Misc ballouts */
207 BALLOUT_V8_ARMIO3,
208
209 /* OMAP-1610 MMC2 */
210 W8_1610_MMC2_DAT0,
211 V8_1610_MMC2_DAT1,
212 W15_1610_MMC2_DAT2,
213 R10_1610_MMC2_DAT3,
214 Y10_1610_MMC2_CLK,
215 Y8_1610_MMC2_CMD,
216 V9_1610_MMC2_CMDDIR,
217 V5_1610_MMC2_DATDIR0,
218 W19_1610_MMC2_DATDIR1,
219 R18_1610_MMC2_CLKIN,
220
221 /* OMAP-1610 External Trace Interface */
222 M19_1610_ETM_PSTAT0,
223 L15_1610_ETM_PSTAT1,
224 L18_1610_ETM_PSTAT2,
225 L19_1610_ETM_D0,
226 J19_1610_ETM_D6,
227 J18_1610_ETM_D7,
228
229 /* OMAP-1610 GPIO */
230 P20_1610_GPIO4,
231 V9_1610_GPIO7,
232 W8_1610_GPIO9,
233 N19_1610_GPIO13,
234 P10_1610_GPIO22,
235 V5_1610_GPIO24,
236 AA20_1610_GPIO_41,
237 W19_1610_GPIO48,
238
239 /* OMAP-1610 uWire */
240 V19_1610_UWIRE_SCLK,
241 U18_1610_UWIRE_SDI,
242 W21_1610_UWIRE_SDO,
243 N14_1610_UWIRE_CS0,
244 P15_1610_UWIRE_CS0,
245 N15_1610_UWIRE_CS1,
246
247 /* First MMC */
248 MMC_CMD,
249 MMC_DAT1,
250 MMC_DAT2,
251 MMC_DAT0,
252 MMC_CLK,
253 MMC_DAT3,
254
255 /* OMAP-1710 MMC CMDDIR and DATDIR0 */
256 M15_1710_MMC_CLKI,
257 P19_1710_MMC_CMDDIR,
258 P20_1710_MMC_DATDIR0,
259
260 /* OMAP-1610 USB0 alternate pin configuration */
261 W9_USB0_TXEN,
262 AA9_USB0_VP,
263 Y5_USB0_RCV,
264 R9_USB0_VM,
265 V6_USB0_TXD,
266 W5_USB0_SE0,
267 V9_USB0_SPEED,
268 V9_USB0_SUSP,
269
270 /* USB2 */
271 W9_USB2_TXEN,
272 AA9_USB2_VP,
273 Y5_USB2_RCV,
274 R9_USB2_VM,
275 V6_USB2_TXD,
276 W5_USB2_SE0,
277
278 /* UART1 1610 */
279
280 R13_1610_UART1_TX,
281 V14_1610_UART1_RX,
282 R14_1610_UART1_CTS,
283 AA15_1610_UART1_RTS,
284
285 /* I2C OMAP-1610 */
286 I2C_SCL,
287 I2C_SDA,
288
289 /* Keypad */
290 F18_1610_KBC0,
291 D20_1610_KBC1,
292 D19_1610_KBC2,
293 E18_1610_KBC3,
294 C21_1610_KBC4,
295 G18_1610_KBR0,
296 F19_1610_KBR1,
297 H14_1610_KBR2,
298 E20_1610_KBR3,
299 E19_1610_KBR4,
300 N19_1610_KBR5,
301
302 /* Power management */
303 T20_1610_LOW_PWR,
304
305 } reg_cfg_t;
306
307 #if defined(__MUX_C__) && defined(CONFIG_OMAP_MUX)
308
309 /*
310 * Table of various FUNC_MUX and PULL_DWN combinations for each device.
311 * See also reg_cfg_t above for the lookup table.
312 */
313 static reg_cfg_set reg_cfg_table[] = {
314 /*
315 * description mux mode mux pull pull pull pu_pd pu dbg
316 * reg offset mode reg bit ena reg
317 */
318 MUX_CFG("UART1_TX", 9, 21, 1, 2, 3, 0, NA, 0, 0)
319 MUX_CFG("UART1_RTS", 9, 12, 1, 2, 0, 0, NA, 0, 0)
320
321 /* UART2 (COM_UART_GATING), conflicts with USB2 */
322 MUX_CFG("UART2_TX", C, 27, 1, 3, 3, 0, NA, 0, 0)
323 MUX_CFG("UART2_RX", C, 18, 0, 3, 1, 1, NA, 0, 0)
324 MUX_CFG("UART2_CTS", C, 21, 0, 3, 1, 1, NA, 0, 0)
325 MUX_CFG("UART2_RTS", C, 24, 1, 3, 2, 0, NA, 0, 0)
326
327 /* UART3 (GIGA_UART_GATING) */
328 MUX_CFG("UART3_TX", 6, 0, 1, 0, 30, 0, NA, 0, 0)
329 MUX_CFG("UART3_RX", 6, 3, 0, 0, 31, 1, NA, 0, 0)
330 MUX_CFG("UART3_CTS", 5, 12, 2, 0, 24, 0, NA, 0, 0)
331 MUX_CFG("UART3_RTS", 5, 15, 2, 0, 25, 0, NA, 0, 0)
332 MUX_CFG("UART3_CLKREQ", 9, 27, 0, 2, 5, 0, NA, 0, 0)
333 MUX_CFG("UART3_BCLK", A, 0, 0, 2, 6, 0, NA, 0, 0)
334
335 /* PWT & PWL, conflicts with UART3 */
336 MUX_CFG("PWT", 6, 0, 2, 0, 30, 0, NA, 0, 0)
337 MUX_CFG("PWL", 6, 3, 1, 0, 31, 1, NA, 0, 0)
338
339 /* USB internal master generic */
340 MUX_CFG("R18_USB_VBUS", 7, 9, 2, 1, 11, 0, NA, 0, 1)
341 MUX_CFG("R18_1510_USB_GPIO0", 7, 9, 0, 1, 11, 1, NA, 0, 1)
342 MUX_CFG("W4_USB_PUEN", D, 3, 0, 3, 5, 1, NA, 0, 1)
343 MUX_CFG("W4_USB_CLKO", D, 3, 1, 3, 5, 0, NA, 0, 1)
344 MUX_CFG("W4_USB_HIGHZ", D, 3, 4, 3, 5, 0, 3, 0, 1)
345 MUX_CFG("W4_GPIO58", D, 3, 7, 3, 5, 0, 3, 0, 1)
346
347 /* USB1 master */
348 MUX_CFG("USB1_SUSP", 8, 27, 2, 1, 27, 0, NA, 0, 1)
349 MUX_CFG("USB1_SE0", 9, 0, 2, 1, 28, 0, NA, 0, 1)
350 MUX_CFG("W13_1610_USB1_SE0", 9, 0, 4, 1, 28, 0, NA, 0, 1)
351 MUX_CFG("USB1_TXEN", 9, 3, 2, 1, 29, 0, NA, 0, 1)
352 MUX_CFG("USB1_TXD", 9, 24, 1, 2, 4, 0, NA, 0, 1)
353 MUX_CFG("USB1_VP", A, 3, 1, 2, 7, 0, NA, 0, 1)
354 MUX_CFG("USB1_VM", A, 6, 1, 2, 8, 0, NA, 0, 1)
355 MUX_CFG("USB1_RCV", A, 9, 1, 2, 9, 0, NA, 0, 1)
356 MUX_CFG("USB1_SPEED", A, 12, 2, 2, 10, 0, NA, 0, 1)
357 MUX_CFG("R13_1610_USB1_SPEED", A, 12, 5, 2, 10, 0, NA, 0, 1)
358 MUX_CFG("R13_1710_USB1_SEO", A, 12, 5, 2, 10, 0, NA, 0, 1)
359
360 /* USB2 master */
361 MUX_CFG("USB2_SUSP", B, 3, 1, 2, 17, 0, NA, 0, 1)
362 MUX_CFG("USB2_VP", B, 6, 1, 2, 18, 0, NA, 0, 1)
363 MUX_CFG("USB2_TXEN", B, 9, 1, 2, 19, 0, NA, 0, 1)
364 MUX_CFG("USB2_VM", C, 18, 1, 3, 0, 0, NA, 0, 1)
365 MUX_CFG("USB2_RCV", C, 21, 1, 3, 1, 0, NA, 0, 1)
366 MUX_CFG("USB2_SE0", C, 24, 2, 3, 2, 0, NA, 0, 1)
367 MUX_CFG("USB2_TXD", C, 27, 2, 3, 3, 0, NA, 0, 1)
368
369 /* OMAP-1510 GPIO */
370 MUX_CFG("R18_1510_GPIO0", 7, 9, 0, 1, 11, 1, 0, 0, 1)
371 MUX_CFG("R19_1510_GPIO1", 7, 6, 0, 1, 10, 1, 0, 0, 1)
372 MUX_CFG("M14_1510_GPIO2", 7, 3, 0, 1, 9, 1, 0, 0, 1)
373
374 /* OMAP-1710 GPIO */
375 MUX_CFG("R18_1710_GPIO0", 7, 9, 0, 1, 11, 1, 1, 1, 1)
376 MUX_CFG("W15_1710_GPIO40", 9, 27, 7, 2, 5, 1, 2, 1, 1)
377
378 /* MPUIO */
379 MUX_CFG("MPUIO2", 7, 18, 0, 1, 1, 1, NA, 0, 1)
380 MUX_CFG("MPUIO4", 7, 15, 0, 1, 13, 1, NA, 0, 1)
381 MUX_CFG("MPUIO5", 7, 12, 0, 1, 12, 1, NA, 0, 1)
382
383 MUX_CFG("T20_1610_MPUIO5", 7, 12, 0, 1, 12, 0, 3, 0, 1)
384 MUX_CFG("W11_1610_MPUIO6", 10, 15, 2, 3, 8, 0, 3, 0, 1)
385 MUX_CFG("V10_1610_MPUIO7", A, 24, 2, 2, 14, 0, 2, 0, 1)
386 MUX_CFG("W11_1610_MPUIO9", 10, 15, 1, 3, 8, 0, 3, 0, 1)
387 MUX_CFG("V10_1610_MPUIO10", A, 24, 1, 2, 14, 0, 2, 0, 1)
388 MUX_CFG("W10_1610_MPUIO11", A, 18, 2, 2, 11, 0, 2, 0, 1)
389 MUX_CFG("E20_1610_MPUIO13", 3, 21, 1, 0, 7, 0, 0, 0, 1)
390 MUX_CFG("U20_1610_MPUIO14", 9, 6, 6, 0, 30, 0, 0, 0, 1)
391 MUX_CFG("E19_1610_MPUIO15", 3, 18, 1, 0, 6, 0, 0, 0, 1)
392
393 /* MCBSP2 */
394 MUX_CFG("MCBSP2_CLKR", C, 6, 0, 2, 27, 1, NA, 0, 1)
395 MUX_CFG("MCBSP2_CLKX", C, 9, 0, 2, 29, 1, NA, 0, 1)
396 MUX_CFG("MCBSP2_DR", C, 0, 0, 2, 26, 1, NA, 0, 1)
397 MUX_CFG("MCBSP2_DX", C, 15, 0, 2, 31, 1, NA, 0, 1)
398 MUX_CFG("MCBSP2_FSR", C, 12, 0, 2, 30, 1, NA, 0, 1)
399 MUX_CFG("MCBSP2_FSX", C, 3, 0, 2, 27, 1, NA, 0, 1)
400
401 /* MCBSP3 NOTE: Mode must 1 for clock */
402 MUX_CFG("MCBSP3_CLKX", 9, 3, 1, 1, 29, 0, NA, 0, 1)
403
404 /* Misc ballouts */
405 MUX_CFG("BALLOUT_V8_ARMIO3", B, 18, 0, 2, 25, 1, NA, 0, 1)
406
407 /* OMAP-1610 MMC2 */
408 MUX_CFG("W8_1610_MMC2_DAT0", B, 21, 6, 2, 23, 1, 2, 1, 1)
409 MUX_CFG("V8_1610_MMC2_DAT1", B, 27, 6, 2, 25, 1, 2, 1, 1)
410 MUX_CFG("W15_1610_MMC2_DAT2", 9, 12, 6, 2, 5, 1, 2, 1, 1)
411 MUX_CFG("R10_1610_MMC2_DAT3", B, 18, 6, 2, 22, 1, 2, 1, 1)
412 MUX_CFG("Y10_1610_MMC2_CLK", B, 3, 6, 2, 17, 0, 2, 0, 1)
413 MUX_CFG("Y8_1610_MMC2_CMD", B, 24, 6, 2, 24, 1, 2, 1, 1)
414 MUX_CFG("V9_1610_MMC2_CMDDIR", B, 12, 6, 2, 20, 0, 2, 1, 1)
415 MUX_CFG("V5_1610_MMC2_DATDIR0", B, 15, 6, 2, 21, 0, 2, 1, 1)
416 MUX_CFG("W19_1610_MMC2_DATDIR1", 8, 15, 6, 1, 23, 0, 1, 1, 1)
417 MUX_CFG("R18_1610_MMC2_CLKIN", 7, 9, 6, 1, 11, 0, 1, 11, 1)
418
419 /* OMAP-1610 External Trace Interface */
420 MUX_CFG("M19_1610_ETM_PSTAT0", 5, 27, 1, 0, 29, 0, 0, 0, 1)
421 MUX_CFG("L15_1610_ETM_PSTAT1", 5, 24, 1, 0, 28, 0, 0, 0, 1)
422 MUX_CFG("L18_1610_ETM_PSTAT2", 5, 21, 1, 0, 27, 0, 0, 0, 1)
423 MUX_CFG("L19_1610_ETM_D0", 5, 18, 1, 0, 26, 0, 0, 0, 1)
424 MUX_CFG("J19_1610_ETM_D6", 5, 0, 1, 0, 20, 0, 0, 0, 1)
425 MUX_CFG("J18_1610_ETM_D7", 5, 27, 1, 0, 19, 0, 0, 0, 1)
426
427 /* OMAP-1610 GPIO */
428 MUX_CFG("P20_1610_GPIO4", 6, 27, 0, 1, 7, 0, 1, 1, 1)
429 MUX_CFG("V9_1610_GPIO7", B, 12, 1, 2, 20, 0, 2, 1, 1)
430 MUX_CFG("W8_1610_GPIO9", B, 21, 0, 2, 23, 0, 2, 1, 1)
431 MUX_CFG("N19_1610_GPIO13", 6, 12, 0, 1, 2, 0, 1, 1, 1)
432 MUX_CFG("P10_1610_GPIO22", C, 0, 7, 2, 26, 0, 2, 1, 1)
433 MUX_CFG("V5_1610_GPIO24", B, 15, 7, 2, 21, 0, 2, 1, 1)
434 MUX_CFG("AA20_1610_GPIO_41", 9, 9, 7, 1, 31, 0, 1, 1, 1)
435 MUX_CFG("W19_1610_GPIO48", 8, 15, 7, 1, 23, 1, 1, 0, 1)
436
437 /* OMAP-1610 uWire */
438 MUX_CFG("V19_1610_UWIRE_SCLK", 8, 6, 0, 1, 20, 0, 1, 1, 1)
439 MUX_CFG("U18_1610_UWIRE_SDI", 8, 0, 0, 1, 18, 0, 1, 1, 1)
440 MUX_CFG("W21_1610_UWIRE_SDO", 8, 3, 0, 1, 19, 0, 1, 1, 1)
441 MUX_CFG("N14_1610_UWIRE_CS0", 8, 9, 1, 1, 21, 0, 1, 1, 1)
442 MUX_CFG("P15_1610_UWIRE_CS3", 8, 12, 1, 1, 22, 0, 1, 1, 1)
443 MUX_CFG("N15_1610_UWIRE_CS1", 7, 18, 2, 1, 14, 0, NA, 0, 1)
444
445 /* First MMC interface, same on 1510, 1610 and 1710 */
446 MUX_CFG("MMC_CMD", A, 27, 0, 2, 15, 1, 2, 1, 1)
447 MUX_CFG("MMC_DAT1", A, 24, 0, 2, 14, 1, 2, 1, 1)
448 MUX_CFG("MMC_DAT2", A, 18, 0, 2, 12, 1, 2, 1, 1)
449 MUX_CFG("MMC_DAT0", B, 0, 0, 2, 16, 1, 2, 1, 1)
450 MUX_CFG("MMC_CLK", A, 21, 0, NA, 0, 0, NA, 0, 1)
451 MUX_CFG("MMC_DAT3", 10, 15, 0, 3, 8, 1, 3, 1, 1)
452 MUX_CFG("M15_1710_MMC_CLKI", 6, 21, 2, 0, 0, 0, NA, 0, 1)
453 MUX_CFG("P19_1710_MMC_CMDDIR", 6, 24, 6, 0, 0, 0, NA, 0, 1)
454 MUX_CFG("P20_1710_MMC_DATDIR0", 6, 27, 5, 0, 0, 0, NA, 0, 1)
455
456 /* OMAP-1610 USB0 alternate configuration */
457 MUX_CFG("W9_USB0_TXEN", B, 9, 5, 2, 19, 0, 2, 0, 1)
458 MUX_CFG("AA9_USB0_VP", B, 6, 5, 2, 18, 0, 2, 0, 1)
459 MUX_CFG("Y5_USB0_RCV", C, 21, 5, 3, 1, 0, 1, 0, 1)
460 MUX_CFG("R9_USB0_VM", C, 18, 5, 3, 0, 0, 3, 0, 1)
461 MUX_CFG("V6_USB0_TXD", C, 27, 5, 3, 3, 0, 3, 0, 1)
462 MUX_CFG("W5_USB0_SE0", C, 24, 5, 3, 2, 0, 3, 0, 1)
463 MUX_CFG("V9_USB0_SPEED", B, 12, 5, 2, 20, 0, 2, 0, 1)
464 MUX_CFG("Y10_USB0_SUSP", B, 3, 5, 2, 17, 0, 2, 0, 1)
465
466 /* USB2 interface */
467 MUX_CFG("W9_USB2_TXEN", B, 9, 1, NA, 0, 0, NA, 0, 1)
468 MUX_CFG("AA9_USB2_VP", B, 6, 1, NA, 0, 0, NA, 0, 1)
469 MUX_CFG("Y5_USB2_RCV", C, 21, 1, NA, 0, 0, NA, 0, 1)
470 MUX_CFG("R8_USB2_VM", C, 18, 1, NA, 0, 0, NA, 0, 1)
471 MUX_CFG("V6_USB2_TXD", C, 27, 2, NA, 0, 0, NA, 0, 1)
472 MUX_CFG("W5_USB2_SE0", C, 24, 2, NA, 0, 0, NA, 0, 1)
473
474
475 /* UART1 */
476 MUX_CFG("R13_1610_UART1_TX", A, 12, 6, 2, 10, 0, 2, 10, 1)
477 MUX_CFG("V14_1610_UART1_RX", 9, 18, 0, 2, 2, 0, 2, 2, 1)
478 MUX_CFG("R14_1610_UART1_CTS", 9, 15, 0, 2, 1, 0, 2, 1, 1)
479 MUX_CFG("AA15_1610_UART1_RTS", 9, 12, 1, 2, 0, 0, 2, 0, 1)
480
481 /* I2C interface */
482 MUX_CFG("I2C_SCL", 7, 24, 0, NA, 0, 0, NA, 0, 0)
483 MUX_CFG("I2C_SDA", 7, 27, 0, NA, 0, 0, NA, 0, 0)
484
485 /* Keypad */
486 MUX_CFG("F18_1610_KBC0", 3, 15, 0, 0, 5, 1, 0, 0, 0)
487 MUX_CFG("D20_1610_KBC1", 3, 12, 0, 0, 4, 1, 0, 0, 0)
488 MUX_CFG("D19_1610_KBC2", 3, 9, 0, 0, 3, 1, 0, 0, 0)
489 MUX_CFG("E18_1610_KBC3", 3, 6, 0, 0, 2, 1, 0, 0, 0)
490 MUX_CFG("C21_1610_KBC4", 3, 3, 0, 0, 1, 1, 0, 0, 0)
491 MUX_CFG("G18_1610_KBR0", 4, 0, 0, 0, 10, 1, 0, 1, 0)
492 MUX_CFG("F19_1610_KBR1", 3, 27, 0, 0, 9, 1, 0, 1, 0)
493 MUX_CFG("H14_1610_KBR2", 3, 24, 0, 0, 8, 1, 0, 1, 0)
494 MUX_CFG("E20_1610_KBR3", 3, 21, 0, 0, 7, 1, 0, 1, 0)
495 MUX_CFG("E19_1610_KBR4", 3, 18, 0, 0, 6, 1, 0, 1, 0)
496 MUX_CFG("N19_1610_KBR5", 6, 12, 1, 1, 2, 1, 1, 1, 0)
497
498 /* Power management */
499 MUX_CFG("T20_1610_LOW_PWR", 7, 12, 1, NA, 0, 0, NA, 0, 0)
500 };
501
502 #endif /* __MUX_C__ */
503
504 extern int omap_cfg_reg(reg_cfg_t reg_cfg);
505
506 #endif
MOXA 2.6.9 from sdlinux-moxaart.tgz