include/asm-arm/arch-omap/pm.h

   1 /*
   2  * FILE NAME include/asm/arch-omap/pm.h
   3  *
   4  * BRIEF MODULE DESCRIPTION
   5  *
   6  * Author: MontaVista Software, Inc.
   7  *         support@mvista.com
   8  *
   9  * Copyright 2002 MontaVista Software Inc.
  10  *
  11  * This program is free software; you can redistribute it and/or modify it
  12  * under the terms of the GNU General Public License as published by the
  13  * Free Software Foundation; either version 2 of the License, or (at your
  14  * option) any later version.
  15  *
  16  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  17  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  18  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  19  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  21  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  22  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  23  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  25  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  *
  27  * You should have received a copy of the GNU General Public License along
  28  * with this program; if not, write to the Free Software Foundation, Inc.,
  29  * 675 Mass Ave, Cambridge, MA 02139, USA.
  30  */
  31
  32 /*
  33  * List of global OMAP registers to preserve.  All registers are 16 bits
  34  * and must be accessed with 16 read/writes.
  35  * More ones like CP and general purpose register values are preserved
  36  * with the stack pointer in sleep.S.
  37  */
  38 #ifndef __ASM_ARCH_OMAP_PM_H
  39 #define __ASM_ARCH_OMAP_PM_H
  40
  41 #define ARM_REG_BASE            (0xfffece00)
  42 #define ARM_ASM_IDLECT1         (ARM_REG_BASE + 0x4)
  43 #define ARM_ASM_IDLECT2         (ARM_REG_BASE + 0x8)
  44 #define ARM_ASM_RSTCT1          (ARM_REG_BASE + 0x10)
  45 #define ARM_ASM_RSTCT2          (ARM_REG_BASE + 0x14)
  46 #define ARM_ASM_SYSST           (ARM_REG_BASE + 0x18)
  47 /*
  48  * Traffic Controller Memory Interface Registers
  49  */
  50 #define TCMIF_BASE              0xfffecc00
  51 #define EMIFS_ASM_CONFIG_REG    (TCMIF_BASE + 0x0c)
  52 #define EMIFF_ASM_SDRAM_CONFIG  (TCMIF_BASE + 0x20)
  53 #define IRQ_MIR1                (OMAP_IH1_BASE + IRQ_MIR)
  54
  55 #ifdef CONFIG_ARCH_OMAP1510
  56 #define IRQ_MIR2                (OMAP_IH2_BASE + IRQ_MIR)
  57 #else /* CONFIG_ARCH_OMAP1610 */
  58 #define IRQ_MIR2_0              (OMAP_IH2_0_BASE + IRQ_MIR)
  59 #define IRQ_MIR2_1              (OMAP_IH2_1_BASE + IRQ_MIR)
  60 #define IRQ_MIR2_2              (OMAP_IH2_2_BASE + IRQ_MIR)
  61 #define IRQ_MIR2_3              (OMAP_IH2_3_BASE + IRQ_MIR)
  62 #endif
  63
  64 #define IDLE_WAIT_CYCLES                0x00000fff
  65 #define PERIPHERAL_ENABLE               0x2
  66
  67 #ifdef CONFIG_ARCH_OMAP1510
  68 #define DEEP_SLEEP_REQUEST              0x0ec7
  69 #define BIG_SLEEP_REQUEST               0x0cc5
  70 #define IDLE_LOOP_REQUEST               0x0c00
  71 #define IDLE_CLOCK_DOMAINS              0x2
  72 #else /* CONFIG_ARCH_OMAP1610 */
  73 #define DEEP_SLEEP_REQUEST              0x17c7
  74 #define BIG_SLEEP_REQUEST               TBD
  75 #define IDLE_LOOP_REQUEST               0x0400
  76 #define IDLE_CLOCK_DOMAINS              0x09c7
  77 #endif
  78
  79 #define SELF_REFRESH_MODE               0x0c000001
  80 #define IDLE_EMIFS_REQUEST              0xc
  81 #define MODEM_32K_EN                    0x1
  82
  83 #ifndef __ASSEMBLER__
  84 extern void omap_pm_idle(void);
  85 extern void omap_pm_suspend(void);
  86 extern int omap_cpu_suspend(unsigned short, unsigned short);
  87 extern int omap_idle_loop_suspend(void);
  88
  89 #ifdef CONFIG_ARCH_OMAP1510
  90 #define OMAP_SRAM_IDLE_SUSPEND  0xd002F000
  91 #define OMAP_SRAM_API_SUSPEND   0xd002F200
  92 #else /* CONFIG_ARCH_OMAP1610 */
  93 #define OMAP_SRAM_IDLE_SUSPEND  0xd0000400
  94 #define OMAP_SRAM_API_SUSPEND   0xd0000600
  95 #endif
  96
  97 #define CPU_SUSPEND_SIZE        200
  98 #define ARM_REG_BASE            (0xfffece00)
  99 #define ARM_ASM_IDLECT1         (ARM_REG_BASE + 0x4)
 100 #define ARM_ASM_IDLECT2         (ARM_REG_BASE + 0x8)
 101 #define ARM_ASM_RSTCT1          (ARM_REG_BASE + 0x10)
 102 #define ARM_ASM_RSTCT2          (ARM_REG_BASE + 0x14)
 103 #define ARM_ASM_SYSST           (ARM_REG_BASE + 0x18)
 104
 105 #define TCMIF_BASE              0xfffecc00
 106 #define PM_EMIFS_CONFIG_REG     (TCMIF_BASE + 0x0c)
 107 #define PM_EMIFF_SDRAM_CONFIG   (TCMIF_BASE + 0x20)
 108 #define FUNC_MUX_CTRL_LOW_PWR   (0xfffe1020)
 109
 110 #ifdef CONFIG_ARCH_OMAP1510
 111 #define ULPD_LOW_POWER_REQ             0x0001
 112 #else /* CONFIG_ARCH_OMAP1610 */
 113 #define ULPD_LOW_POWER_REQ             0x3
 114 #endif
 115 #define ULPD_LOW_PWR                   0x1000
 116 #define ULPD_LOW_POWER_EN              0x0001
 117
 118 #define DSP_IDLE_DELAY                  10
 119 #define DSP_IDLE                        0x0040
 120 #define DSP_ENABLE                      0x0002
 121 #define SUFFICIENT_DSP_RESET_TIME       1000
 122 #define DEFAULT_MPUI_CONFIG             0x05cf
 123 #define ENABLE_XORCLK                   0x2
 124 #define DSP_RESET                       0x2000
 125 #define TC_IDLE_REQUEST                 (0x0000000c)
 126 #define EMIFF_CONFIG_REG                EMIFF_SDRAM_CONFIG
 127
 128
 129 #define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = omap_readw(x)
 130 #define ARM_RESTORE(x) omap_writew((unsigned short)arm_sleep_save[ARM_SLEEP_SAVE_##x], x)
 131 #define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x]
 132
 133 #define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = omap_readw(x)
 134 #define ULPD_RESTORE(x) omap_writew((unsigned short)ulpd_sleep_save[ULPD_SLEEP_SAVE_##x], x)
 135 #define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]
 136
 137 #define MPUI_SAVE(x) mpui_sleep_save[MPUI_SLEEP_SAVE_##x] = omap_readl(x)
 138 #define MPUI_RESTORE(x) omap_writel((unsigned int)mpui_sleep_save[MPUI_SLEEP_SAVE_##x], x)
 139 #define MPUI_SHOW(x) (unsigned int)mpui_sleep_save[MPUI_SLEEP_SAVE_##x]
 140
 141 enum arm_save_state {
 142         ARM_SLEEP_SAVE_START = 0,
 143         /*
 144          * 9 MPU control registers, all 16 bits
 145          */
 146         ARM_SLEEP_SAVE_ARM_CKCTL, ARM_SLEEP_SAVE_ARM_IDLECT1,
 147         ARM_SLEEP_SAVE_ARM_IDLECT2, ARM_SLEEP_SAVE_ARM_EWUPCT,
 148         ARM_SLEEP_SAVE_ARM_RSTCT1, ARM_SLEEP_SAVE_ARM_RSTCT2,
 149         ARM_SLEEP_SAVE_ARM_SYSST,
 150
 151         ARM_SLEEP_SAVE_SIZE
 152 };
 153
 154 enum ulpd_save_state {
 155         ULPD_SLEEP_SAVE_START = 0,
 156         ULPD_SLEEP_SAVE_ULPD_IT_STATUS_REG, ULPD_SLEEP_SAVE_ULPD_CLOCK_CTRL_REG,
 157         ULPD_SLEEP_SAVE_ULPD_SOFT_REQ_REG, ULPD_SLEEP_SAVE_ULPD_STATUS_REQ_REG,
 158         ULPD_SLEEP_SAVE_ULPD_DPLL_CTRL_REG, ULPD_SLEEP_SAVE_ULPD_POWER_CTRL_REG,
 159         ULPD_SLEEP_SAVE_SIZE
 160 };
 161
 162 enum mpui_save_state {
 163         /*
 164          * MPUI registers 32 bits
 165          */
 166         MPUI_SLEEP_SAVE_MPUI_CTRL_REG, MPUI_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
 167         MPUI_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
 168         MPUI_SLEEP_SAVE_MPUI_DSP_STATUS_REG,
 169         MPUI_SLEEP_SAVE_PM_EMIFF_SDRAM_CONFIG,
 170         MPUI_SLEEP_SAVE_PM_EMIFS_CONFIG_REG,
 171         MPUI_SLEEP_SAVE_IRQ_MIR1,
 172 #ifdef CONFIG_ARCH_OMAP1510
 173         MPUI_SLEEP_SAVE_IRQ_MIR2,
 174 #else /* CONFIG_ARCH_OMAP1610 */
 175         MPUI_SLEEP_SAVE_IRQ_MIR2_0,
 176         MPUI_SLEEP_SAVE_IRQ_MIR2_1,
 177         MPUI_SLEEP_SAVE_IRQ_MIR2_2,
 178         MPUI_SLEEP_SAVE_IRQ_MIR2_3,
 179 #endif
 180
 181         MPUI_SLEEP_SAVE_SIZE
 182 };
 183
 184
 185 #endif  /* ASSEMBLER */
 186 #endif