include/asm-ia64/sn/xtalk/xbow.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All Rights Reserved.
   7  */
   8 #ifndef _ASM_IA64_SN_XTALK_XBOW_H
   9 #define _ASM_IA64_SN_XTALK_XBOW_H
  10
  11 /*
  12  * xbow.h - header file for crossbow chip and xbow section of xbridge
  13  */
  14
  15 #include <asm/types.h>
  16 #include <asm/sn/xtalk/xtalk.h>
  17 #include <asm/sn/xtalk/xwidget.h>
  18 #include <asm/sn/xtalk/xswitch.h>
  19 #ifndef __ASSEMBLY__
  20 #include <asm/sn/xtalk/xbow_info.h>
  21 #endif
  22
  23
  24 #define XBOW_DRV_PREFIX "xbow_"
  25
  26 /* The crossbow chip supports 8 8/16 bits I/O ports, numbered 0x8 through 0xf.
  27  * It also implements the widget 0 address space and register set.
  28  */
  29 #define XBOW_PORT_0     0x0
  30 #define XBOW_PORT_8     0x8
  31 #define XBOW_PORT_9     0x9
  32 #define XBOW_PORT_A     0xa
  33 #define XBOW_PORT_B     0xb
  34 #define XBOW_PORT_C     0xc
  35 #define XBOW_PORT_D     0xd
  36 #define XBOW_PORT_E     0xe
  37 #define XBOW_PORT_F     0xf
  38
  39 #define MAX_XBOW_PORTS  8       /* number of ports on xbow chip */
  40 #define BASE_XBOW_PORT  XBOW_PORT_8     /* Lowest external port */
  41 #define MAX_PORT_NUM    0x10    /* maximum port number + 1 */
  42 #define XBOW_WIDGET_ID  0       /* xbow is itself widget 0 */
  43
  44 #define XBOW_HUBLINK_LOW  0xa
  45 #define XBOW_HUBLINK_HIGH 0xb
  46
  47 #define XBOW_PEER_LINK(link) (link == XBOW_HUBLINK_LOW) ? \
  48                                 XBOW_HUBLINK_HIGH : XBOW_HUBLINK_LOW
  49
  50
  51 #define XBOW_CREDIT     4
  52
  53 #define MAX_XBOW_NAME   16
  54
  55 #ifndef __ASSEMBLY__
  56 typedef uint32_t      xbowreg_t;
  57
  58 /* Register set for each xbow link */
  59 typedef volatile struct xb_linkregs_s {
  60 /*
  61  * we access these through synergy unswizzled space, so the address
  62  * gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.)
  63  * That's why we put the register first and filler second.
  64  */
  65     xbowreg_t               link_ibf;
  66     xbowreg_t               filler0;    /* filler for proper alignment */
  67     xbowreg_t               link_control;
  68     xbowreg_t               filler1;
  69     xbowreg_t               link_status;
  70     xbowreg_t               filler2;
  71     xbowreg_t               link_arb_upper;
  72     xbowreg_t               filler3;
  73     xbowreg_t               link_arb_lower;
  74     xbowreg_t               filler4;
  75     xbowreg_t               link_status_clr;
  76     xbowreg_t               filler5;
  77     xbowreg_t               link_reset;
  78     xbowreg_t               filler6;
  79     xbowreg_t               link_aux_status;
  80     xbowreg_t               filler7;
  81 } xb_linkregs_t;
  82
  83 typedef volatile struct xbow_s {
  84     /* standard widget configuration                       0x000000-0x000057 */
  85     widget_cfg_t            xb_widget;  /* 0x000000 */
  86
  87     /* helper fieldnames for accessing bridge widget */
  88
  89 #define xb_wid_id                       xb_widget.w_id
  90 #define xb_wid_stat                     xb_widget.w_status
  91 #define xb_wid_err_upper                xb_widget.w_err_upper_addr
  92 #define xb_wid_err_lower                xb_widget.w_err_lower_addr
  93 #define xb_wid_control                  xb_widget.w_control
  94 #define xb_wid_req_timeout              xb_widget.w_req_timeout
  95 #define xb_wid_int_upper                xb_widget.w_intdest_upper_addr
  96 #define xb_wid_int_lower                xb_widget.w_intdest_lower_addr
  97 #define xb_wid_err_cmdword              xb_widget.w_err_cmd_word
  98 #define xb_wid_llp                      xb_widget.w_llp_cfg
  99 #define xb_wid_stat_clr                 xb_widget.w_tflush
 100
 101 /*
 102  * we access these through synergy unswizzled space, so the address
 103  * gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.)
 104  * That's why we put the register first and filler second.
 105  */
 106     /* xbow-specific widget configuration                  0x000058-0x0000FF */
 107     xbowreg_t               xb_wid_arb_reload;  /* 0x00005C */
 108     xbowreg_t               _pad_000058;
 109     xbowreg_t               xb_perf_ctr_a;      /* 0x000064 */
 110     xbowreg_t               _pad_000060;
 111     xbowreg_t               xb_perf_ctr_b;      /* 0x00006c */
 112     xbowreg_t               _pad_000068;
 113     xbowreg_t               xb_nic;     /* 0x000074 */
 114     xbowreg_t               _pad_000070;
 115
 116     /* Xbridge only */
 117     xbowreg_t               xb_w0_rst_fnc;      /* 0x00007C */
 118     xbowreg_t               _pad_000078;
 119     xbowreg_t               xb_l8_rst_fnc;      /* 0x000084 */
 120     xbowreg_t               _pad_000080;
 121     xbowreg_t               xb_l9_rst_fnc;      /* 0x00008c */
 122     xbowreg_t               _pad_000088;
 123     xbowreg_t               xb_la_rst_fnc;      /* 0x000094 */
 124     xbowreg_t               _pad_000090;
 125     xbowreg_t               xb_lb_rst_fnc;      /* 0x00009c */
 126     xbowreg_t               _pad_000098;
 127     xbowreg_t               xb_lc_rst_fnc;      /* 0x0000a4 */
 128     xbowreg_t               _pad_0000a0;
 129     xbowreg_t               xb_ld_rst_fnc;      /* 0x0000ac */
 130     xbowreg_t               _pad_0000a8;
 131     xbowreg_t               xb_le_rst_fnc;      /* 0x0000b4 */
 132     xbowreg_t               _pad_0000b0;
 133     xbowreg_t               xb_lf_rst_fnc;      /* 0x0000bc */
 134     xbowreg_t               _pad_0000b8;
 135     xbowreg_t               xb_lock;            /* 0x0000c4 */
 136     xbowreg_t               _pad_0000c0;
 137     xbowreg_t               xb_lock_clr;        /* 0x0000cc */
 138     xbowreg_t               _pad_0000c8;
 139     /* end of Xbridge only */
 140     xbowreg_t               _pad_0000d0[12];
 141
 142     /* Link Specific Registers, port 8..15                 0x000100-0x000300 */
 143     xb_linkregs_t           xb_link_raw[MAX_XBOW_PORTS];
 144 #define xb_link(p)      xb_link_raw[(p) & (MAX_XBOW_PORTS - 1)]
 145
 146 } xbow_t;
 147
 148 /* Configuration structure which describes each xbow link */
 149 typedef struct xbow_cfg_s {
 150     int                     xb_port;    /* port number (0-15) */
 151     int                     xb_flags;   /* port software flags */
 152     short                   xb_shift;   /* shift for arb reg (mask is 0xff) */
 153     short                   xb_ul;      /* upper or lower arb reg */
 154     int                     xb_pad;     /* use this later (pad to ptr align) */
 155     xb_linkregs_t          *xb_linkregs;        /* pointer to link registers */
 156     widget_cfg_t           *xb_widget;  /* pointer to widget registers */
 157     char                    xb_name[MAX_XBOW_NAME];     /* port name */
 158     xbowreg_t               xb_sh_arb_upper;    /* shadow upper arb register */
 159     xbowreg_t               xb_sh_arb_lower;    /* shadow lower arb register */
 160 } xbow_cfg_t;
 161
 162 #define XB_FLAGS_EXISTS         0x1     /* device exists */
 163 #define XB_FLAGS_MASTER         0x2
 164 #define XB_FLAGS_SLAVE          0x0
 165 #define XB_FLAGS_GBR            0x4
 166 #define XB_FLAGS_16BIT          0x8
 167 #define XB_FLAGS_8BIT           0x0
 168
 169 /* get xbow config information for port p */
 170 #define XB_CONFIG(p)    xbow_cfg[xb_ports[p]]
 171
 172 /* is widget port number valid?  (based on version 7.0 of xbow spec) */
 173 #define XBOW_WIDGET_IS_VALID(wid) ((wid) >= XBOW_PORT_8 && (wid) <= XBOW_PORT_F)
 174
 175 /* whether to use upper or lower arbitration register, given source widget id */
 176 #define XBOW_ARB_IS_UPPER(wid)  ((wid) >= XBOW_PORT_8 && (wid) <= XBOW_PORT_B)
 177 #define XBOW_ARB_IS_LOWER(wid)  ((wid) >= XBOW_PORT_C && (wid) <= XBOW_PORT_F)
 178
 179 /* offset of arbitration register, given source widget id */
 180 #define XBOW_ARB_OFF(wid)       (XBOW_ARB_IS_UPPER(wid) ? 0x1c : 0x24)
 181
 182 #endif                          /* __ASSEMBLY__ */
 183
 184 #define XBOW_WID_ID             WIDGET_ID
 185 #define XBOW_WID_STAT           WIDGET_STATUS
 186 #define XBOW_WID_ERR_UPPER      WIDGET_ERR_UPPER_ADDR
 187 #define XBOW_WID_ERR_LOWER      WIDGET_ERR_LOWER_ADDR
 188 #define XBOW_WID_CONTROL        WIDGET_CONTROL
 189 #define XBOW_WID_REQ_TO         WIDGET_REQ_TIMEOUT
 190 #define XBOW_WID_INT_UPPER      WIDGET_INTDEST_UPPER_ADDR
 191 #define XBOW_WID_INT_LOWER      WIDGET_INTDEST_LOWER_ADDR
 192 #define XBOW_WID_ERR_CMDWORD    WIDGET_ERR_CMD_WORD
 193 #define XBOW_WID_LLP            WIDGET_LLP_CFG
 194 #define XBOW_WID_STAT_CLR       WIDGET_TFLUSH
 195 #define XBOW_WID_ARB_RELOAD     0x5c
 196 #define XBOW_WID_PERF_CTR_A     0x64
 197 #define XBOW_WID_PERF_CTR_B     0x6c
 198 #define XBOW_WID_NIC            0x74
 199
 200 /* Xbridge only */
 201 #define XBOW_W0_RST_FNC         0x00007C
 202 #define XBOW_L8_RST_FNC         0x000084
 203 #define XBOW_L9_RST_FNC         0x00008c
 204 #define XBOW_LA_RST_FNC         0x000094
 205 #define XBOW_LB_RST_FNC         0x00009c
 206 #define XBOW_LC_RST_FNC         0x0000a4
 207 #define XBOW_LD_RST_FNC         0x0000ac
 208 #define XBOW_LE_RST_FNC         0x0000b4
 209 #define XBOW_LF_RST_FNC         0x0000bc
 210 #define XBOW_RESET_FENCE(x) ((x) > 7 && (x) < 16) ? \
 211                                 (XBOW_W0_RST_FNC + ((x) - 7) * 8) : \
 212                                 ((x) == 0) ? XBOW_W0_RST_FNC : 0
 213 #define XBOW_LOCK               0x0000c4
 214 #define XBOW_LOCK_CLR           0x0000cc
 215 /* End of Xbridge only */
 216
 217 /* used only in ide, but defined here within the reserved portion */
 218 /*              of the widget0 address space (before 0xf4) */
 219 #define XBOW_WID_UNDEF          0xe4
 220
 221 /* xbow link register set base, legal value for x is 0x8..0xf */
 222 #define XB_LINK_BASE            0x100
 223 #define XB_LINK_OFFSET          0x40
 224 #define XB_LINK_REG_BASE(x)     (XB_LINK_BASE + ((x) & (MAX_XBOW_PORTS - 1)) * XB_LINK_OFFSET)
 225
 226 #define XB_LINK_IBUF_FLUSH(x)   (XB_LINK_REG_BASE(x) + 0x4)
 227 #define XB_LINK_CTRL(x)         (XB_LINK_REG_BASE(x) + 0xc)
 228 #define XB_LINK_STATUS(x)       (XB_LINK_REG_BASE(x) + 0x14)
 229 #define XB_LINK_ARB_UPPER(x)    (XB_LINK_REG_BASE(x) + 0x1c)
 230 #define XB_LINK_ARB_LOWER(x)    (XB_LINK_REG_BASE(x) + 0x24)
 231 #define XB_LINK_STATUS_CLR(x)   (XB_LINK_REG_BASE(x) + 0x2c)
 232 #define XB_LINK_RESET(x)        (XB_LINK_REG_BASE(x) + 0x34)
 233 #define XB_LINK_AUX_STATUS(x)   (XB_LINK_REG_BASE(x) + 0x3c)
 234
 235 /* link_control(x) */
 236 #define XB_CTRL_LINKALIVE_IE            0x80000000      /* link comes alive */
 237      /* reserved:                       0x40000000 */
 238 #define XB_CTRL_PERF_CTR_MODE_MSK       0x30000000      /* perf counter mode */
 239 #define XB_CTRL_IBUF_LEVEL_MSK          0x0e000000      /* input packet buffer level */
 240 #define XB_CTRL_8BIT_MODE               0x01000000      /* force link into 8 bit mode */
 241 #define XB_CTRL_BAD_LLP_PKT             0x00800000      /* force bad LLP packet */
 242 #define XB_CTRL_WIDGET_CR_MSK           0x007c0000      /* LLP widget credit mask */
 243 #define XB_CTRL_WIDGET_CR_SHFT  18                      /* LLP widget credit shift */
 244 #define XB_CTRL_ILLEGAL_DST_IE          0x00020000      /* illegal destination */
 245 #define XB_CTRL_OALLOC_IBUF_IE          0x00010000      /* overallocated input buffer */
 246      /* reserved:                       0x0000fe00 */
 247 #define XB_CTRL_BNDWDTH_ALLOC_IE        0x00000100      /* bandwidth alloc */
 248 #define XB_CTRL_RCV_CNT_OFLOW_IE        0x00000080      /* rcv retry overflow */
 249 #define XB_CTRL_XMT_CNT_OFLOW_IE        0x00000040      /* xmt retry overflow */
 250 #define XB_CTRL_XMT_MAX_RTRY_IE         0x00000020      /* max transmit retry */
 251 #define XB_CTRL_RCV_IE                  0x00000010      /* receive */
 252 #define XB_CTRL_XMT_RTRY_IE             0x00000008      /* transmit retry */
 253      /* reserved:                       0x00000004 */
 254 #define XB_CTRL_MAXREQ_TOUT_IE          0x00000002      /* maximum request timeout */
 255 #define XB_CTRL_SRC_TOUT_IE             0x00000001      /* source timeout */
 256
 257 /* link_status(x) */
 258 #define XB_STAT_LINKALIVE               XB_CTRL_LINKALIVE_IE
 259      /* reserved:                       0x7ff80000 */
 260 #define XB_STAT_MULTI_ERR               0x00040000      /* multi error */
 261 #define XB_STAT_ILLEGAL_DST_ERR         XB_CTRL_ILLEGAL_DST_IE
 262 #define XB_STAT_OALLOC_IBUF_ERR         XB_CTRL_OALLOC_IBUF_IE
 263 #define XB_STAT_BNDWDTH_ALLOC_ID_MSK    0x0000ff00      /* port bitmask */
 264 #define XB_STAT_RCV_CNT_OFLOW_ERR       XB_CTRL_RCV_CNT_OFLOW_IE
 265 #define XB_STAT_XMT_CNT_OFLOW_ERR       XB_CTRL_XMT_CNT_OFLOW_IE
 266 #define XB_STAT_XMT_MAX_RTRY_ERR        XB_CTRL_XMT_MAX_RTRY_IE
 267 #define XB_STAT_RCV_ERR                 XB_CTRL_RCV_IE
 268 #define XB_STAT_XMT_RTRY_ERR            XB_CTRL_XMT_RTRY_IE
 269      /* reserved:                       0x00000004 */
 270 #define XB_STAT_MAXREQ_TOUT_ERR         XB_CTRL_MAXREQ_TOUT_IE
 271 #define XB_STAT_SRC_TOUT_ERR            XB_CTRL_SRC_TOUT_IE
 272
 273 /* link_aux_status(x) */
 274 #define XB_AUX_STAT_RCV_CNT     0xff000000
 275 #define XB_AUX_STAT_XMT_CNT     0x00ff0000
 276 #define XB_AUX_STAT_TOUT_DST    0x0000ff00
 277 #define XB_AUX_LINKFAIL_RST_BAD 0x00000040
 278 #define XB_AUX_STAT_PRESENT     0x00000020
 279 #define XB_AUX_STAT_PORT_WIDTH  0x00000010
 280      /* reserved:               0x0000000f */
 281
 282 /*
 283  * link_arb_upper/link_arb_lower(x), (reg) should be the link_arb_upper
 284  * register if (x) is 0x8..0xb, link_arb_lower if (x) is 0xc..0xf
 285  */
 286 #define XB_ARB_GBR_MSK          0x1f
 287 #define XB_ARB_RR_MSK           0x7
 288 #define XB_ARB_GBR_SHFT(x)      (((x) & 0x3) * 8)
 289 #define XB_ARB_RR_SHFT(x)       (((x) & 0x3) * 8 + 5)
 290 #define XB_ARB_GBR_CNT(reg,x)   ((reg) >> XB_ARB_GBR_SHFT(x) & XB_ARB_GBR_MSK)
 291 #define XB_ARB_RR_CNT(reg,x)    ((reg) >> XB_ARB_RR_SHFT(x) & XB_ARB_RR_MSK)
 292
 293 /* XBOW_WID_STAT */
 294 #define XB_WID_STAT_LINK_INTR_SHFT      (24)
 295 #define XB_WID_STAT_LINK_INTR_MASK      (0xFF << XB_WID_STAT_LINK_INTR_SHFT)
 296 #define XB_WID_STAT_LINK_INTR(x)        (0x1 << (((x)&7) + XB_WID_STAT_LINK_INTR_SHFT))
 297 #define XB_WID_STAT_WIDGET0_INTR        0x00800000
 298 #define XB_WID_STAT_SRCID_MASK          0x000003c0      /* Xbridge only */
 299 #define XB_WID_STAT_REG_ACC_ERR         0x00000020
 300 #define XB_WID_STAT_RECV_TOUT           0x00000010      /* Xbridge only */
 301 #define XB_WID_STAT_ARB_TOUT            0x00000008      /* Xbridge only */
 302 #define XB_WID_STAT_XTALK_ERR           0x00000004
 303 #define XB_WID_STAT_DST_TOUT            0x00000002      /* Xbridge only */
 304 #define XB_WID_STAT_MULTI_ERR           0x00000001
 305
 306 #define XB_WID_STAT_SRCID_SHFT          6
 307
 308 /* XBOW_WID_CONTROL */
 309 #define XB_WID_CTRL_REG_ACC_IE          XB_WID_STAT_REG_ACC_ERR
 310 #define XB_WID_CTRL_RECV_TOUT           XB_WID_STAT_RECV_TOUT
 311 #define XB_WID_CTRL_ARB_TOUT            XB_WID_STAT_ARB_TOUT
 312 #define XB_WID_CTRL_XTALK_IE            XB_WID_STAT_XTALK_ERR
 313
 314 /* XBOW_WID_INT_UPPER */
 315 /* defined in xwidget.h for WIDGET_INTDEST_UPPER_ADDR */
 316
 317 /* XBOW WIDGET part number, in the ID register */
 318 #define XBOW_WIDGET_PART_NUM    0x0             /* crossbow */
 319 #define XXBOW_WIDGET_PART_NUM   0xd000          /* Xbridge */
 320 #define XBOW_WIDGET_MFGR_NUM    0x0
 321 #define XXBOW_WIDGET_MFGR_NUM   0x0
 322 #define PXBOW_WIDGET_PART_NUM   0xd100          /* PIC */
 323
 324 #define XBOW_REV_1_0            0x1     /* xbow rev 1.0 is "1" */
 325 #define XBOW_REV_1_1            0x2     /* xbow rev 1.1 is "2" */
 326 #define XBOW_REV_1_2            0x3     /* xbow rev 1.2 is "3" */
 327 #define XBOW_REV_1_3            0x4     /* xbow rev 1.3 is "4" */
 328 #define XBOW_REV_2_0            0x5     /* xbow rev 2.0 is "5" */
 329
 330 #define XXBOW_PART_REV_1_0              (XXBOW_WIDGET_PART_NUM << 4 | 0x1 )
 331 #define XXBOW_PART_REV_2_0              (XXBOW_WIDGET_PART_NUM << 4 | 0x2 )
 332
 333 /* XBOW_WID_ARB_RELOAD */
 334 #define XBOW_WID_ARB_RELOAD_INT 0x3f    /* GBR reload interval */
 335
 336 #define IS_XBRIDGE_XBOW(wid) \
 337         (XWIDGET_PART_NUM(wid) == XXBOW_WIDGET_PART_NUM && \
 338                         XWIDGET_MFG_NUM(wid) == XXBOW_WIDGET_MFGR_NUM)
 339
 340 #define IS_PIC_XBOW(wid) \
 341         (XWIDGET_PART_NUM(wid) == PXBOW_WIDGET_PART_NUM && \
 342                         XWIDGET_MFG_NUM(wid) == XXBOW_WIDGET_MFGR_NUM)
 343
 344 #define XBOW_WAR_ENABLED(pv, widid) ((1 << XWIDGET_REV_NUM(widid)) & pv)
 345
 346 #ifndef __ASSEMBLY__
 347 /*
 348  * XBOW Widget 0 Register formats.
 349  * Format for many of these registers are similar to the standard
 350  * widget register format described as part of xtalk specification
 351  * Standard widget register field format description is available in
 352  * xwidget.h
 353  * Following structures define the format for xbow widget 0 registers
 354  */
 355 /*
 356  * Xbow Widget 0 Command error word
 357  */
 358 typedef union xbw0_cmdword_u {
 359     xbowreg_t               cmdword;
 360     struct {
 361         uint32_t              rsvd:8,           /* Reserved */
 362                                 barr:1,         /* Barrier operation */
 363                                 error:1,        /* Error Occured */
 364                                 vbpm:1,         /* Virtual Backplane message */
 365                                 gbr:1,  /* GBR enable ?                 */
 366                                 ds:2,   /* Data size                    */
 367                                 ct:1,   /* Is it a coherent transaction */
 368                                 tnum:5,         /* Transaction Number */
 369                                 pactyp:4,       /* Packet type: */
 370                                 srcid:4,        /* Source ID number */
 371                                 destid:4;       /* Desination ID number */
 372
 373     } xbw0_cmdfield;
 374 } xbw0_cmdword_t;
 375
 376 #define xbcmd_destid    xbw0_cmdfield.destid
 377 #define xbcmd_srcid     xbw0_cmdfield.srcid
 378 #define xbcmd_pactyp    xbw0_cmdfield.pactyp
 379 #define xbcmd_tnum      xbw0_cmdfield.tnum
 380 #define xbcmd_ct        xbw0_cmdfield.ct
 381 #define xbcmd_ds        xbw0_cmdfield.ds
 382 #define xbcmd_gbr       xbw0_cmdfield.gbr
 383 #define xbcmd_vbpm      xbw0_cmdfield.vbpm
 384 #define xbcmd_error     xbw0_cmdfield.error
 385 #define xbcmd_barr      xbw0_cmdfield.barr
 386
 387 /*
 388  * Values for field PACTYP in xbow error command word
 389  */
 390 #define XBCMDTYP_READREQ        0       /* Read Request   packet  */
 391 #define XBCMDTYP_READRESP       1       /* Read Response packet   */
 392 #define XBCMDTYP_WRREQ_RESP     2       /* Write Request with response    */
 393 #define XBCMDTYP_WRRESP         3       /* Write Response */
 394 #define XBCMDTYP_WRREQ_NORESP   4       /* Write request with  No Response */
 395 #define XBCMDTYP_FETCHOP        6       /* Fetch & Op packet      */
 396 #define XBCMDTYP_STOREOP        8       /* Store & Op packet      */
 397 #define XBCMDTYP_SPLPKT_REQ     0xE     /* Special packet request */
 398 #define XBCMDTYP_SPLPKT_RESP    0xF     /* Special packet response        */
 399
 400 /*
 401  * Values for field ds (datasize) in xbow error command word
 402  */
 403 #define XBCMDSZ_DOUBLEWORD      0
 404 #define XBCMDSZ_QUARTRCACHE     1
 405 #define XBCMDSZ_FULLCACHE       2
 406
 407 /*
 408  * Xbow widget 0 Status register format.
 409  */
 410
 411 typedef union xbw0_status_u {
 412     xbowreg_t               statusword;
 413     struct {
 414        uint32_t         mult_err:1,     /* Multiple error occurred */
 415                                 connect_tout:1, /* Connection timeout   */
 416                                 xtalk_err:1,    /* Xtalk pkt with error bit */
 417                                 /* End of Xbridge only */
 418                                 w0_arb_tout,    /* arbiter timeout err */
 419                                 w0_recv_tout,   /* receive timeout err */
 420                                 /* Xbridge only */
 421                                 regacc_err:1,   /* Reg Access error     */
 422                                 src_id:4,       /* source id. Xbridge only */
 423                                 resvd1:13,
 424                                 wid0intr:1;     /* Widget 0 err intr */
 425     } xbw0_stfield;
 426 } xbw0_status_t;
 427
 428 #define xbst_linkXintr          xbw0_stfield.linkXintr
 429 #define xbst_w0intr             xbw0_stfield.wid0intr
 430 #define xbst_regacc_err         xbw0_stfield.regacc_err
 431 #define xbst_xtalk_err          xbw0_stfield.xtalk_err
 432 #define xbst_connect_tout       xbw0_stfield.connect_tout
 433 #define xbst_mult_err           xbw0_stfield.mult_err
 434 #define xbst_src_id             xbw0_stfield.src_id         /* Xbridge only */
 435 #define xbst_w0_recv_tout       xbw0_stfield.w0_recv_tout   /* Xbridge only */
 436 #define xbst_w0_arb_tout        xbw0_stfield.w0_arb_tout    /* Xbridge only */
 437
 438 /*
 439  * Xbow widget 0 Control register format
 440  */
 441
 442 typedef union xbw0_ctrl_u {
 443     xbowreg_t               ctrlword;
 444     struct {
 445         uint32_t
 446                                 resvd3:1,
 447                                 conntout_intr:1,
 448                                 xtalkerr_intr:1,
 449                                 w0_arg_tout_intr:1,     /* Xbridge only */
 450                                 w0_recv_tout_intr:1,    /* Xbridge only */
 451                                 accerr_intr:1,
 452                                 enable_w0_tout_cntr:1,  /* Xbridge only */
 453                                 enable_watchdog:1,      /* Xbridge only */
 454                                 resvd1:24;
 455     } xbw0_ctrlfield;
 456 } xbw0_ctrl_t;
 457
 458 typedef union xbow_linkctrl_u {
 459     xbowreg_t               xbl_ctrlword;
 460     struct {
 461         uint32_t                srcto_intr:1,
 462                                 maxto_intr:1,
 463                                 rsvd3:1,
 464                                 trx_retry_intr:1,
 465                                 rcv_err_intr:1,
 466                                 trx_max_retry_intr:1,
 467                                 trxov_intr:1,
 468                                 rcvov_intr:1,
 469                                 bwalloc_intr:1,
 470                                 rsvd2:7,
 471                                 obuf_intr:1,
 472                                 idest_intr:1,
 473                                 llp_credit:5,
 474                                 force_badllp:1,
 475                                 send_bm8:1,
 476                                 inbuf_level:3,
 477                                 perf_mode:2,
 478                                 rsvd1:1,
 479                                 alive_intr:1;
 480
 481     } xb_linkcontrol;
 482 } xbow_linkctrl_t;
 483
 484 #define xbctl_accerr_intr       (xbw0_ctrlfield.accerr_intr)
 485 #define xbctl_xtalkerr_intr     (xbw0_ctrlfield.xtalkerr_intr)
 486 #define xbctl_cnntout_intr      (xbw0_ctrlfield.conntout_intr)
 487
 488 #define XBW0_CTRL_ACCERR_INTR   (1 << 5)
 489 #define XBW0_CTRL_XTERR_INTR    (1 << 2)
 490 #define XBW0_CTRL_CONNTOUT_INTR (1 << 1)
 491
 492 /*
 493  * Xbow Link specific Registers structure definitions.
 494  */
 495
 496 typedef union xbow_linkX_status_u {
 497     xbowreg_t               linkstatus;
 498     struct {
 499         uint32_t               pkt_toutsrc:1,
 500                                 pkt_toutconn:1, /* max_req_tout in Xbridge */
 501                                 pkt_toutdest:1, /* reserved in Xbridge */
 502                                 llp_xmitretry:1,
 503                                 llp_rcverror:1,
 504                                 llp_maxtxretry:1,
 505                                 llp_txovflow:1,
 506                                 llp_rxovflow:1,
 507                                 bw_errport:8,   /* BW allocation error port   */
 508                                 ioe:1,          /* Input overallocation error */
 509                                 illdest:1,
 510                                 merror:1,
 511                                 resvd1:12,
 512                                 alive:1;
 513     } xb_linkstatus;
 514 } xbwX_stat_t;
 515
 516 #define link_alive              xb_linkstatus.alive
 517 #define link_multierror         xb_linkstatus.merror
 518 #define link_illegal_dest       xb_linkstatus.illdest
 519 #define link_ioe                xb_linkstatus.ioe
 520 #define link_max_req_tout       xb_linkstatus.pkt_toutconn  /* Xbridge */
 521 #define link_pkt_toutconn       xb_linkstatus.pkt_toutconn  /* Xbow */
 522 #define link_pkt_toutdest       xb_linkstatus.pkt_toutdest
 523 #define link_pkt_toutsrc        xb_linkstatus.pkt_toutsrc
 524
 525 typedef union xbow_aux_linkX_status_u {
 526     xbowreg_t               aux_linkstatus;
 527     struct {
 528         uint32_t                rsvd2:4,
 529                                 bit_mode_8:1,
 530                                 wid_present:1,
 531                                 fail_mode:1,
 532                                 rsvd1:1,
 533                                 to_src_loc:8,
 534                                 tx_retry_cnt:8,
 535                                 rx_err_cnt:8;
 536     } xb_aux_linkstatus;
 537 } xbow_aux_link_status_t;
 538
 539 typedef union xbow_perf_count_u {
 540     xbowreg_t               xb_counter_val;
 541     struct {
 542         uint32_t                count:20,
 543                                 link_select:3,
 544                                 rsvd:9;
 545     } xb_perf;
 546 } xbow_perfcount_t;
 547
 548 #define XBOW_COUNTER_MASK       0xFFFFF
 549
 550 extern int              xbow_widget_present(xbow_t * xbow, int port);
 551
 552 extern xwidget_intr_preset_f xbow_intr_preset;
 553 extern xswitch_reset_link_f xbow_reset_link;
 554 void                    xbow_mlreset(xbow_t *);
 555
 556 /* ========================================================================
 557  */
 558
 559 #ifdef  MACROFIELD_LINE
 560 /*
 561  * This table forms a relation between the byte offset macros normally
 562  * used for ASM coding and the calculated byte offsets of the fields
 563  * in the C structure.
 564  *
 565  * See xbow_check.c xbow_html.c for further details.
 566  */
 567 #ifndef MACROFIELD_LINE_BITFIELD
 568 #define MACROFIELD_LINE_BITFIELD(m)     /* ignored */
 569 #endif
 570
 571 struct macrofield_s     xbow_macrofield[] =
 572 {
 573
 574     MACROFIELD_LINE(XBOW_WID_ID, xb_wid_id)
 575     MACROFIELD_LINE(XBOW_WID_STAT, xb_wid_stat)
 576     MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0xF))
 577     MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0xE))
 578     MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0xD))
 579     MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0xC))
 580     MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0xB))
 581     MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0xA))
 582     MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0x9))
 583     MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0x8))
 584     MACROFIELD_LINE_BITFIELD(XB_WID_STAT_WIDGET0_INTR)
 585     MACROFIELD_LINE_BITFIELD(XB_WID_STAT_REG_ACC_ERR)
 586     MACROFIELD_LINE_BITFIELD(XB_WID_STAT_XTALK_ERR)
 587     MACROFIELD_LINE_BITFIELD(XB_WID_STAT_MULTI_ERR)
 588     MACROFIELD_LINE(XBOW_WID_ERR_UPPER, xb_wid_err_upper)
 589     MACROFIELD_LINE(XBOW_WID_ERR_LOWER, xb_wid_err_lower)
 590     MACROFIELD_LINE(XBOW_WID_CONTROL, xb_wid_control)
 591     MACROFIELD_LINE_BITFIELD(XB_WID_CTRL_REG_ACC_IE)
 592     MACROFIELD_LINE_BITFIELD(XB_WID_CTRL_XTALK_IE)
 593     MACROFIELD_LINE(XBOW_WID_REQ_TO, xb_wid_req_timeout)
 594     MACROFIELD_LINE(XBOW_WID_INT_UPPER, xb_wid_int_upper)
 595     MACROFIELD_LINE(XBOW_WID_INT_LOWER, xb_wid_int_lower)
 596     MACROFIELD_LINE(XBOW_WID_ERR_CMDWORD, xb_wid_err_cmdword)
 597     MACROFIELD_LINE(XBOW_WID_LLP, xb_wid_llp)
 598     MACROFIELD_LINE(XBOW_WID_STAT_CLR, xb_wid_stat_clr)
 599     MACROFIELD_LINE(XBOW_WID_ARB_RELOAD, xb_wid_arb_reload)
 600     MACROFIELD_LINE(XBOW_WID_PERF_CTR_A, xb_perf_ctr_a)
 601     MACROFIELD_LINE(XBOW_WID_PERF_CTR_B, xb_perf_ctr_b)
 602     MACROFIELD_LINE(XBOW_WID_NIC, xb_nic)
 603     MACROFIELD_LINE(XB_LINK_REG_BASE(8), xb_link(8))
 604     MACROFIELD_LINE(XB_LINK_IBUF_FLUSH(8), xb_link(8).link_ibf)
 605     MACROFIELD_LINE(XB_LINK_CTRL(8), xb_link(8).link_control)
 606     MACROFIELD_LINE_BITFIELD(XB_CTRL_LINKALIVE_IE)
 607     MACROFIELD_LINE_BITFIELD(XB_CTRL_PERF_CTR_MODE_MSK)
 608     MACROFIELD_LINE_BITFIELD(XB_CTRL_IBUF_LEVEL_MSK)
 609     MACROFIELD_LINE_BITFIELD(XB_CTRL_8BIT_MODE)
 610     MACROFIELD_LINE_BITFIELD(XB_CTRL_BAD_LLP_PKT)
 611     MACROFIELD_LINE_BITFIELD(XB_CTRL_WIDGET_CR_MSK)
 612     MACROFIELD_LINE_BITFIELD(XB_CTRL_ILLEGAL_DST_IE)
 613     MACROFIELD_LINE_BITFIELD(XB_CTRL_OALLOC_IBUF_IE)
 614     MACROFIELD_LINE_BITFIELD(XB_CTRL_BNDWDTH_ALLOC_IE)
 615     MACROFIELD_LINE_BITFIELD(XB_CTRL_RCV_CNT_OFLOW_IE)
 616     MACROFIELD_LINE_BITFIELD(XB_CTRL_XMT_CNT_OFLOW_IE)
 617     MACROFIELD_LINE_BITFIELD(XB_CTRL_XMT_MAX_RTRY_IE)
 618     MACROFIELD_LINE_BITFIELD(XB_CTRL_RCV_IE)
 619     MACROFIELD_LINE_BITFIELD(XB_CTRL_XMT_RTRY_IE)
 620     MACROFIELD_LINE_BITFIELD(XB_CTRL_MAXREQ_TOUT_IE)
 621     MACROFIELD_LINE_BITFIELD(XB_CTRL_SRC_TOUT_IE)
 622     MACROFIELD_LINE(XB_LINK_STATUS(8), xb_link(8).link_status)
 623     MACROFIELD_LINE_BITFIELD(XB_STAT_LINKALIVE)
 624     MACROFIELD_LINE_BITFIELD(XB_STAT_MULTI_ERR)
 625     MACROFIELD_LINE_BITFIELD(XB_STAT_ILLEGAL_DST_ERR)
 626     MACROFIELD_LINE_BITFIELD(XB_STAT_OALLOC_IBUF_ERR)
 627     MACROFIELD_LINE_BITFIELD(XB_STAT_BNDWDTH_ALLOC_ID_MSK)
 628     MACROFIELD_LINE_BITFIELD(XB_STAT_RCV_CNT_OFLOW_ERR)
 629     MACROFIELD_LINE_BITFIELD(XB_STAT_XMT_CNT_OFLOW_ERR)
 630     MACROFIELD_LINE_BITFIELD(XB_STAT_XMT_MAX_RTRY_ERR)
 631     MACROFIELD_LINE_BITFIELD(XB_STAT_RCV_ERR)
 632     MACROFIELD_LINE_BITFIELD(XB_STAT_XMT_RTRY_ERR)
 633     MACROFIELD_LINE_BITFIELD(XB_STAT_MAXREQ_TOUT_ERR)
 634     MACROFIELD_LINE_BITFIELD(XB_STAT_SRC_TOUT_ERR)
 635     MACROFIELD_LINE(XB_LINK_ARB_UPPER(8), xb_link(8).link_arb_upper)
 636     MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0xb))
 637     MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0xb))
 638     MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0xa))
 639     MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0xa))
 640     MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0x9))
 641     MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0x9))
 642     MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0x8))
 643     MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0x8))
 644     MACROFIELD_LINE(XB_LINK_ARB_LOWER(8), xb_link(8).link_arb_lower)
 645     MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0xf))
 646     MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0xf))
 647     MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0xe))
 648     MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0xe))
 649     MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0xd))
 650     MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0xd))
 651     MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0xc))
 652     MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0xc))
 653     MACROFIELD_LINE(XB_LINK_STATUS_CLR(8), xb_link(8).link_status_clr)
 654     MACROFIELD_LINE(XB_LINK_RESET(8), xb_link(8).link_reset)
 655     MACROFIELD_LINE(XB_LINK_AUX_STATUS(8), xb_link(8).link_aux_status)
 656     MACROFIELD_LINE_BITFIELD(XB_AUX_STAT_RCV_CNT)
 657     MACROFIELD_LINE_BITFIELD(XB_AUX_STAT_XMT_CNT)
 658     MACROFIELD_LINE_BITFIELD(XB_AUX_LINKFAIL_RST_BAD)
 659     MACROFIELD_LINE_BITFIELD(XB_AUX_STAT_PRESENT)
 660     MACROFIELD_LINE_BITFIELD(XB_AUX_STAT_PORT_WIDTH)
 661     MACROFIELD_LINE_BITFIELD(XB_AUX_STAT_TOUT_DST)
 662     MACROFIELD_LINE(XB_LINK_REG_BASE(0x8), xb_link(0x8))
 663     MACROFIELD_LINE(XB_LINK_REG_BASE(0x9), xb_link(0x9))
 664     MACROFIELD_LINE(XB_LINK_REG_BASE(0xA), xb_link(0xA))
 665     MACROFIELD_LINE(XB_LINK_REG_BASE(0xB), xb_link(0xB))
 666     MACROFIELD_LINE(XB_LINK_REG_BASE(0xC), xb_link(0xC))
 667     MACROFIELD_LINE(XB_LINK_REG_BASE(0xD), xb_link(0xD))
 668     MACROFIELD_LINE(XB_LINK_REG_BASE(0xE), xb_link(0xE))
 669     MACROFIELD_LINE(XB_LINK_REG_BASE(0xF), xb_link(0xF))
 670 };                              /* xbow_macrofield[] */
 671
 672 #endif                          /* MACROFIELD_LINE */
 673
 674 #endif                          /* __ASSEMBLY__ */
 675 #endif                          /* _ASM_IA64_SN_XTALK_XBOW_H */