| blob | 330c0a2ff5e1f32c315436769ac0e1e794286a6f |
1 /*
2 * linux/arch/arm/mm/proc-xscale.S
3 *
4 * Author: Nicolas Pitre
5 * Created: November 2000
6 * Copyright: (C) 2000, 2001 MontaVista Software Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * MMU functions for the Intel XScale CPUs
13 *
14 * 2001 Aug 21:
15 * some contributions by Brett Gaines <brett.w.gaines@intel.com>
16 * Copyright 2001 by Intel Corp.
17 *
18 * 2001 Sep 08:
19 * Completely revisited, many important fixes
20 * Nicolas Pitre <nico@cam.org>
21 */
23 #include <linux/linkage.h>
24 #include <linux/init.h>
25 #include <asm/assembler.h>
26 #include <asm/procinfo.h>
27 #include <asm/hardware.h>
28 #include <asm/pgtable.h>
29 #include <asm/page.h>
30 #include <asm/ptrace.h>
31 #include "proc-macros.S"
33 /*
34 * This is the maximum size of an area which will be flushed. If the area
35 * is larger than this, then we flush the whole cache
36 */
37 #define MAX_AREA_SIZE 32768
39 /*
40 * the cache line size of the I and D cache
41 */
42 #define CACHELINESIZE 32
44 /*
45 * the size of the data cache
46 */
47 #define CACHESIZE 32768
49 /*
50 * Virtual address used to allocate the cache when flushed
51 *
52 * This must be an address range which is _never_ used. It should
53 * apparently have a mapping in the corresponding page table for
54 * compatibility with future CPUs that _could_ require it. For instance we
55 * don't care.
56 *
57 * This must be aligned on a 2*CACHESIZE boundary. The code selects one of
58 * the 2 areas in alternance each time the clean_d_cache macro is used.
59 * Without this the XScale core exhibits cache eviction problems and no one
60 * knows why.
61 *
62 * Reminder: the vector table is located at 0xffff0000-0xffff0fff.
63 */
64 #define CLEAN_ADDR 0xfffe0000
66 /*
67 * This macro is used to wait for a CP15 write and is needed
68 * when we have to ensure that the last operation to the co-pro
69 * was completed before continuing with operation.
70 */
71 .macro cpwait, rd
72 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
73 mov \rd, \rd @ wait for completion
74 sub pc, pc, #4 @ flush instruction pipeline
75 .endm
77 .macro cpwait_ret, lr, rd
78 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
79 sub pc, \lr, \rd, LSR #32 @ wait for completion and
80 @ flush instruction pipeline
81 .endm
83 /*
84 * This macro cleans the entire dcache using line allocate.
85 * The main loop has been unrolled to reduce loop overhead.
86 * rd and rs are two scratch registers.
87 */
88 .macro clean_d_cache, rd, rs
89 ldr \rs, =clean_addr
90 ldr \rd, [\rs]
91 eor \rd, \rd, #CACHESIZE
92 str \rd, [\rs]
93 add \rs, \rd, #CACHESIZE
94 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
95 add \rd, \rd, #CACHELINESIZE
96 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
97 add \rd, \rd, #CACHELINESIZE
98 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
99 add \rd, \rd, #CACHELINESIZE
100 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
101 add \rd, \rd, #CACHELINESIZE
102 teq \rd, \rs
103 bne 1b
104 .endm
106 .data
107 clean_addr: .word CLEAN_ADDR
109 .text
111 /*
112 * cpu_xscale_proc_init()
113 *
114 * Nothing too exciting at the moment
115 */
116 ENTRY(cpu_xscale_proc_init)
117 mov pc, lr
119 /*
120 * cpu_xscale_proc_fin()
121 */
122 ENTRY(cpu_xscale_proc_fin)
123 str lr, [sp, #-4]!
124 mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
125 msr cpsr_c, r0
126 bl xscale_flush_kern_cache_all @ clean caches
127 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
128 bic r0, r0, #0x1800 @ ...IZ...........
129 bic r0, r0, #0x0006 @ .............CA.
130 mcr p15, 0, r0, c1, c0, 0 @ disable caches
131 ldr pc, [sp], #4
133 /*
134 * cpu_xscale_reset(loc)
135 *
136 * Perform a soft reset of the system. Put the CPU into the
137 * same state as it would be if it had been reset, and branch
138 * to what would be the reset vector.
139 *
140 * loc: location to jump to for soft reset
141 */
142 .align 5
143 ENTRY(cpu_xscale_reset)
144 mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
145 msr cpsr_c, r1 @ reset CPSR
146 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
147 bic r1, r1, #0x0086 @ ........B....CA.
148 bic r1, r1, #0x3900 @ ..VIZ..S........
149 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
150 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
151 bic r1, r1, #0x0001 @ ...............M
152 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
153 @ CAUTION: MMU turned off from this point. We count on the pipeline
154 @ already containing those two last instructions to survive.
155 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
156 mov pc, r0
158 /*
159 * cpu_xscale_do_idle()
160 *
161 * Cause the processor to idle
162 *
163 * For now we do nothing but go to idle mode for every case
164 *
165 * XScale supports clock switching, but using idle mode support
166 * allows external hardware to react to system state changes.
167 */
168 .align 5
170 ENTRY(cpu_xscale_do_idle)
171 mov r0, #1
172 mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE
173 mov pc, lr
175 /* ================================= CACHE ================================ */
177 /*
178 * flush_user_cache_all()
179 *
180 * Invalidate all cache entries in a particular address
181 * space.
182 */
183 ENTRY(xscale_flush_user_cache_all)
184 /* FALLTHROUGH */
186 /*
187 * flush_kern_cache_all()
188 *
189 * Clean and invalidate the entire cache.
190 */
191 ENTRY(xscale_flush_kern_cache_all)
192 mov r2, #VM_EXEC
193 mov ip, #0
194 __flush_whole_cache:
195 clean_d_cache r0, r1
196 tst r2, #VM_EXEC
197 mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
198 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
199 mov pc, lr
201 /*
202 * flush_user_cache_range(start, end, vm_flags)
203 *
204 * Invalidate a range of cache entries in the specified
205 * address space.
206 *
207 * - start - start address (may not be aligned)
208 * - end - end address (exclusive, may not be aligned)
209 * - vma - vma_area_struct describing address space
210 */
211 .align 5
212 ENTRY(xscale_flush_user_cache_range)
213 mov ip, #0
214 sub r3, r1, r0 @ calculate total size
215 cmp r3, #MAX_AREA_SIZE
216 bhs __flush_whole_cache
218 1: tst r2, #VM_EXEC
219 mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line
220 mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
221 mcr p15, 0, r0, c7, c6, 1 @ Invalidate D cache line
222 add r0, r0, #CACHELINESIZE
223 cmp r0, r1
224 blo 1b
225 tst r2, #VM_EXEC
226 mcrne p15, 0, ip, c7, c5, 6 @ Invalidate BTB
227 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
228 mov pc, lr
230 /*
231 * coherent_kern_range(start, end)
232 *
233 * Ensure coherency between the Icache and the Dcache in the
234 * region described by start. If you have non-snooping
235 * Harvard caches, you need to implement this function.
236 *
237 * - start - virtual start address
238 * - end - virtual end address
239 *
240 * Note: single I-cache line invalidation isn't used here since
241 * it also trashes the mini I-cache used by JTAG debuggers.
242 */
243 ENTRY(xscale_coherent_kern_range)
244 /* FALLTHROUGH */
246 /*
247 * coherent_user_range(start, end)
248 *
249 * Ensure coherency between the Icache and the Dcache in the
250 * region described by start. If you have non-snooping
251 * Harvard caches, you need to implement this function.
252 *
253 * - start - virtual start address
254 * - end - virtual end address
255 *
256 * Note: single I-cache line invalidation isn't used here since
257 * it also trashes the mini I-cache used by JTAG debuggers.
258 */
259 ENTRY(xscale_coherent_user_range)
260 bic r0, r0, #CACHELINESIZE - 1
261 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
262 add r0, r0, #CACHELINESIZE
263 cmp r0, r1
264 blo 1b
265 mov r0, #0
266 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
267 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
268 mov pc, lr
270 /*
271 * flush_kern_dcache_page(void *page)
272 *
273 * Ensure no D cache aliasing occurs, either with itself or
274 * the I cache
275 *
276 * - addr - page aligned address
277 */
278 ENTRY(xscale_flush_kern_dcache_page)
279 add r1, r0, #PAGE_SZ
280 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
281 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
282 add r0, r0, #CACHELINESIZE
283 cmp r0, r1
284 blo 1b
285 mov r0, #0
286 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
287 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
288 mov pc, lr
290 /*
291 * dma_inv_range(start, end)
292 *
293 * Invalidate (discard) the specified virtual address range.
294 * May not write back any entries. If 'start' or 'end'
295 * are not cache line aligned, those lines must be written
296 * back.
297 *
298 * - start - virtual start address
299 * - end - virtual end address
300 */
301 ENTRY(xscale_dma_inv_range)
302 mrc p15, 0, r2, c0, c0, 0 @ read ID
303 eor r2, r2, #0x69000000
304 eor r2, r2, #0x00052000
305 bics r2, r2, #1
306 beq xscale_dma_flush_range
308 tst r0, #CACHELINESIZE - 1
309 bic r0, r0, #CACHELINESIZE - 1
310 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
311 tst r1, #CACHELINESIZE - 1
312 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
313 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
314 add r0, r0, #CACHELINESIZE
315 cmp r0, r1
316 blo 1b
317 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
318 mov pc, lr
320 /*
321 * dma_clean_range(start, end)
322 *
323 * Clean the specified virtual address range.
324 *
325 * - start - virtual start address
326 * - end - virtual end address
327 */
328 ENTRY(xscale_dma_clean_range)
329 bic r0, r0, #CACHELINESIZE - 1
330 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
331 add r0, r0, #CACHELINESIZE
332 cmp r0, r1
333 blo 1b
334 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
335 mov pc, lr
337 /*
338 * dma_flush_range(start, end)
339 *
340 * Clean and invalidate the specified virtual address range.
341 *
342 * - start - virtual start address
343 * - end - virtual end address
344 */
345 ENTRY(xscale_dma_flush_range)
346 bic r0, r0, #CACHELINESIZE - 1
347 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
348 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
349 add r0, r0, #CACHELINESIZE
350 cmp r0, r1
351 blo 1b
352 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
353 mov pc, lr
355 ENTRY(xscale_cache_fns)
356 .long xscale_flush_kern_cache_all
357 .long xscale_flush_user_cache_all
358 .long xscale_flush_user_cache_range
359 .long xscale_coherent_kern_range
360 .long xscale_coherent_user_range
361 .long xscale_flush_kern_dcache_page
362 .long xscale_dma_inv_range
363 .long xscale_dma_clean_range
364 .long xscale_dma_flush_range
366 ENTRY(cpu_xscale_dcache_clean_area)
367 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
368 add r0, r0, #CACHELINESIZE
369 subs r1, r1, #CACHELINESIZE
370 bhi 1b
371 mov pc, lr
373 /* ================================ CACHE LOCKING============================
374 *
375 * The XScale MicroArchitecture implements support for locking entries into
376 * the data and instruction cache. The following functions implement the core
377 * low level instructions needed to accomplish the locking. The developer's
378 * manual states that the code that performs the locking must be in non-cached
379 * memory. To accomplish this, the code in xscale-cache-lock.c copies the
380 * following functions from the cache into a non-cached memory region that
381 * is allocated through consistent_alloc().
382 *
383 */
384 .align 5
385 /*
386 * xscale_icache_lock
387 *
388 * r0: starting address to lock
389 * r1: end address to lock
390 */
391 ENTRY(xscale_icache_lock)
393 iLockLoop:
394 bic r0, r0, #CACHELINESIZE - 1
395 mcr p15, 0, r0, c9, c1, 0 @ lock into cache
396 cmp r0, r1 @ are we done?
397 add r0, r0, #CACHELINESIZE @ advance to next cache line
398 bls iLockLoop
399 mov pc, lr
401 /*
402 * xscale_icache_unlock
403 */
404 ENTRY(xscale_icache_unlock)
405 mcr p15, 0, r0, c9, c1, 1 @ Unlock icache
406 mov pc, lr
408 /*
409 * xscale_dcache_lock
410 *
411 * r0: starting address to lock
412 * r1: end address to lock
413 */
414 ENTRY(xscale_dcache_lock)
415 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
416 mov r2, #1
417 mcr p15, 0, r2, c9, c2, 0 @ Put dcache in lock mode
418 cpwait ip @ Wait for completion
420 mrs r2, cpsr
421 orr r3, r2, #PSR_F_BIT | PSR_I_BIT
422 dLockLoop:
423 msr cpsr_c, r3
424 mcr p15, 0, r0, c7, c10, 1 @ Write back line if it is dirty
425 mcr p15, 0, r0, c7, c6, 1 @ Flush/invalidate line
426 msr cpsr_c, r2
427 ldr ip, [r0], #CACHELINESIZE @ Preload 32 bytes into cache from
428 @ location [r0]. Post-increment
429 @ r3 to next cache line
430 cmp r0, r1 @ Are we done?
431 bls dLockLoop
433 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
434 mov r2, #0
435 mcr p15, 0, r2, c9, c2, 0 @ Get out of lock mode
436 cpwait_ret lr, ip
438 /*
439 * xscale_dcache_unlock
440 */
441 ENTRY(xscale_dcache_unlock)
442 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
443 mcr p15, 0, ip, c9, c2, 1 @ Unlock cache
444 mov pc, lr
446 /*
447 * Needed to determine the length of the code that needs to be copied.
448 */
449 .align 5
450 ENTRY(xscale_cache_dummy)
451 mov pc, lr
453 /* ================================ TLB LOCKING==============================
454 *
455 * The XScale MicroArchitecture implements support for locking entries into
456 * the Instruction and Data TLBs. The following functions provide the
457 * low level support for supporting these under Linux. xscale-lock.c
458 * implements some higher level management code. Most of the following
459 * is taken straight out of the Developer's Manual.
460 */
462 /*
463 * Lock I-TLB entry
464 *
465 * r0: Virtual address to translate and lock
466 */
467 .align 5
468 ENTRY(xscale_itlb_lock)
469 mrs r2, cpsr
470 orr r3, r2, #PSR_F_BIT | PSR_I_BIT
471 msr cpsr_c, r3 @ Disable interrupts
472 mcr p15, 0, r0, c8, c5, 1 @ Invalidate I-TLB entry
473 mcr p15, 0, r0, c10, c4, 0 @ Translate and lock
474 msr cpsr_c, r2 @ Restore interrupts
475 cpwait_ret lr, ip
477 /*
478 * Lock D-TLB entry
479 *
480 * r0: Virtual address to translate and lock
481 */
482 .align 5
483 ENTRY(xscale_dtlb_lock)
484 mrs r2, cpsr
485 orr r3, r2, #PSR_F_BIT | PSR_I_BIT
486 msr cpsr_c, r3 @ Disable interrupts
487 mcr p15, 0, r0, c8, c6, 1 @ Invalidate D-TLB entry
488 mcr p15, 0, r0, c10, c8, 0 @ Translate and lock
489 msr cpsr_c, r2 @ Restore interrupts
490 cpwait_ret lr, ip
492 /*
493 * Unlock all I-TLB entries
494 */
495 .align 5
496 ENTRY(xscale_itlb_unlock)
497 mcr p15, 0, ip, c10, c4, 1 @ Unlock I-TLB
498 mcr p15, 0, ip, c8, c5, 0 @ Invalidate I-TLB
499 cpwait_ret lr, ip
501 /*
502 * Unlock all D-TLB entries
503 */
504 ENTRY(xscale_dtlb_unlock)
505 mcr p15, 0, ip, c10, c8, 1 @ Unlock D-TBL
506 mcr p15, 0, ip, c8, c6, 0 @ Invalidate D-TLB
507 cpwait_ret lr, ip
509 /* =============================== PageTable ============================== */
511 #define PTE_CACHE_WRITE_ALLOCATE 0
513 /*
514 * cpu_xscale_switch_mm(pgd)
515 *
516 * Set the translation base pointer to be as described by pgd.
517 *
518 * pgd: new page tables
519 */
520 .align 5
521 ENTRY(cpu_xscale_switch_mm)
522 clean_d_cache r1, r2
523 mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
524 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
525 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
526 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
527 cpwait_ret lr, ip
529 /*
530 * cpu_xscale_set_pte(ptep, pte)
531 *
532 * Set a PTE and flush it out
533 *
534 * Errata 40: must set memory to write-through for user read-only pages.
535 */
536 .align 5
537 ENTRY(cpu_xscale_set_pte)
538 str r1, [r0], #-2048 @ linux version
540 bic r2, r1, #0xff0
541 orr r2, r2, #PTE_TYPE_EXT @ extended page
543 eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
545 tst r3, #L_PTE_USER @ User?
546 orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w
548 tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
549 orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w
550 @ combined with user -> user r/w
552 @
553 @ Handle the X bit. We want to set this bit for the minicache
554 @ (U = E = B = W = 0, C = 1) or when write allocate is enabled,
555 @ and we have a writeable, cacheable region. If we ignore the
556 @ U and E bits, we can allow user space to use the minicache as
557 @ well.
558 @
559 @ X = (C & ~W & ~B) | (C & W & B & write_allocate)
560 @
561 eor ip, r1, #L_PTE_CACHEABLE
562 tst ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
563 #if PTE_CACHE_WRITE_ALLOCATE
564 eorne ip, r1, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
565 tstne ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
566 #endif
567 orreq r2, r2, #PTE_EXT_TEX(1)
569 @
570 @ Erratum 40: The B bit must be cleared for a user read-only
571 @ cacheable page.
572 @
573 @ B = B & ~(U & C & ~W)
574 @
575 and ip, r1, #L_PTE_USER | L_PTE_WRITE | L_PTE_CACHEABLE
576 teq ip, #L_PTE_USER | L_PTE_CACHEABLE
577 biceq r2, r2, #PTE_BUFFERABLE
579 tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
580 movne r2, #0 @ no -> fault
582 str r2, [r0] @ hardware version
583 mov ip, #0
584 mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
585 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
586 mov pc, lr
589 .ltorg
591 .align
593 __INIT
595 .type __xscale_setup, #function
596 __xscale_setup:
597 mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
598 msr cpsr_c, r0
599 mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB
600 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
601 mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs
602 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
603 mov r0, #0x1f @ Domains 0, 1 = client
604 mcr p15, 0, r0, c3, c0, 0 @ load domain access register
605 #ifdef CONFIG_IWMMXT
606 mov r0, #0 @ initially disallow access to CP0/CP1
607 #else
608 mov r0, #1 @ Allow access to CP0
609 #endif
610 orr r0, r0, #1 << 6 @ cp6 for IOP3xx and Bulverde
611 orr r0, r0, #1 << 13 @ Its undefined whether this
612 mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes
613 mrc p15, 0, r0, c1, c0, 0 @ get control register
614 bic r0, r0, #0x0200 @ .... ..R. .... ....
615 bic r0, r0, #0x0002 @ .... .... .... ..A.
616 orr r0, r0, #0x0005 @ .... .... .... .C.M
617 orr r0, r0, #0x3900 @ ..VI Z..S .... ....
618 mov pc, lr
619 .size __xscale_setup, . - __xscale_setup
621 __INITDATA
623 /*
624 * Purpose : Function pointers used to access above functions - all calls
625 * come through these
626 */
628 .type xscale_processor_functions, #object
629 ENTRY(xscale_processor_functions)
630 .word v5t_early_abort
631 .word cpu_xscale_proc_init
632 .word cpu_xscale_proc_fin
633 .word cpu_xscale_reset
634 .word cpu_xscale_do_idle
635 .word cpu_xscale_dcache_clean_area
636 .word cpu_xscale_switch_mm
637 .word cpu_xscale_set_pte
638 .size xscale_processor_functions, . - xscale_processor_functions
640 .section ".rodata"
642 .type cpu_arch_name, #object
643 cpu_arch_name:
644 .asciz "armv5te"
645 .size cpu_arch_name, . - cpu_arch_name
647 .type cpu_elf_name, #object
648 cpu_elf_name:
649 .asciz "v5"
650 .size cpu_elf_name, . - cpu_elf_name
652 .type cpu_80200_name, #object
653 cpu_80200_name:
654 .asciz "XScale-80200"
655 .size cpu_80200_name, . - cpu_80200_name
657 .type cpu_8032x_name, #object
658 cpu_8032x_name:
659 .asciz "XScale-IOP8032x Family"
660 .size cpu_8032x_name, . - cpu_8032x_name
662 .type cpu_8033x_name, #object
663 cpu_8033x_name:
664 .asciz "XScale-IOP8033x Family"
665 .size cpu_8033x_name, . - cpu_8033x_name
667 .type cpu_pxa250_name, #object
668 cpu_pxa250_name:
669 .asciz "XScale-PXA250"
670 .size cpu_pxa250_name, . - cpu_pxa250_name
672 .type cpu_pxa210_name, #object
673 cpu_pxa210_name:
674 .asciz "XScale-PXA210"
675 .size cpu_pxa210_name, . - cpu_pxa210_name
677 .type cpu_ixp4xx_name, #object
678 cpu_ixp4xx_name:
679 .asciz "XScale-IXP4xx"
680 .size cpu_ixp4xx_name, . - cpu_ixp4xx_name
682 .type cpu_ixp2400_name, #object
683 cpu_ixp2400_name:
684 .asciz "XScale-IXP2400"
685 .size cpu_ixp2400_name, . - cpu_ixp2400_name
687 .type cpu_ixp2800_name, #object
688 cpu_ixp2800_name:
689 .asciz "XScale-IXP2800"
690 .size cpu_ixp2800_name, . - cpu_ixp2800_name
692 .type cpu_pxa255_name, #object
693 cpu_pxa255_name:
694 .asciz "XScale-PXA255"
695 .size cpu_pxa255_name, . - cpu_pxa255_name
697 .type cpu_pxa270_name, #object
698 cpu_pxa270_name:
699 .asciz "XScale-PXA270"
700 .size cpu_pxa270_name, . - cpu_pxa270_name
702 .align
704 .section ".proc.info", #alloc, #execinstr
706 .type __80200_proc_info,#object
707 __80200_proc_info:
708 .long 0x69052000
709 .long 0xfffffff0
710 .long 0x00000c0e
711 b __xscale_setup
712 .long cpu_arch_name
713 .long cpu_elf_name
714 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
715 .long cpu_80200_name
716 .long xscale_processor_functions
717 .long v4wbi_tlb_fns
718 .long xscale_mc_user_fns
719 .long xscale_cache_fns
720 .size __80200_proc_info, . - __80200_proc_info
722 .type __8032x_proc_info,#object
723 __8032x_proc_info:
724 .long 0x69052420
725 .long 0xfffff5e0 @ mask should accomodate IOP80219 also
726 .long 0x00000c0e
727 b __xscale_setup
728 .long cpu_arch_name
729 .long cpu_elf_name
730 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
731 .long cpu_8032x_name
732 .long xscale_processor_functions
733 .long v4wbi_tlb_fns
734 .long xscale_mc_user_fns
735 .long xscale_cache_fns
736 .size __8032x_proc_info, . - __8032x_proc_info
738 .type __8033x_proc_info,#object
739 __8033x_proc_info:
740 .long 0x69054090
741 .long 0xffffffb0
742 .long 0x00000c0e
743 b __xscale_setup
744 .long cpu_arch_name
745 .long cpu_elf_name
746 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
747 .long cpu_8033x_name
748 .long xscale_processor_functions
749 .long v4wbi_tlb_fns
750 .long xscale_mc_user_fns
751 .long xscale_cache_fns
752 .size __8033x_proc_info, . - __8033x_proc_info
754 .type __pxa250_proc_info,#object
755 __pxa250_proc_info:
756 .long 0x69052100
757 .long 0xfffff7f0
758 .long 0x00000c0e
759 b __xscale_setup
760 .long cpu_arch_name
761 .long cpu_elf_name
762 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
763 .long cpu_pxa250_name
764 .long xscale_processor_functions
765 .long v4wbi_tlb_fns
766 .long xscale_mc_user_fns
767 .long xscale_cache_fns
768 .size __pxa250_proc_info, . - __pxa250_proc_info
770 .type __pxa210_proc_info,#object
771 __pxa210_proc_info:
772 .long 0x69052120
773 .long 0xfffff3f0
774 .long 0x00000c0e
775 b __xscale_setup
776 .long cpu_arch_name
777 .long cpu_elf_name
778 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
779 .long cpu_pxa210_name
780 .long xscale_processor_functions
781 .long v4wbi_tlb_fns
782 .long xscale_mc_user_fns
783 .long xscale_cache_fns
784 .size __pxa210_proc_info, . - __pxa210_proc_info
786 .type __ixp2400_proc_info, #object
787 __ixp2400_proc_info:
788 .long 0x69054190
789 .long 0xfffffff0
790 .long 0x00000c0e
791 b __xscale_setup
792 .long cpu_arch_name
793 .long cpu_elf_name
794 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
795 .long cpu_ixp2400_name
796 .long xscale_processor_functions
797 .long v4wbi_tlb_fns
798 .long xscale_mc_user_fns
799 .long xscale_cache_fns
800 .size __ixp2400_proc_info, . - __ixp2400_proc_info
802 .type __ixp2800_proc_info, #object
803 __ixp2800_proc_info:
804 .long 0x690541a0
805 .long 0xfffffff0
806 .long 0x00000c0e
807 b __xscale_setup
808 .long cpu_arch_name
809 .long cpu_elf_name
810 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
811 .long cpu_ixp2800_name
812 .long xscale_processor_functions
813 .long v4wbi_tlb_fns
814 .long xscale_mc_user_fns
815 .long xscale_cache_fns
816 .size __ixp2800_proc_info, . - __ixp2800_proc_info
818 .type __ixp42x_proc_info, #object
819 __ixp42x_proc_info:
820 .long 0x690541c0
821 .long 0xffffffc0
822 .long 0x00000c0e
823 b __xscale_setup
824 .long cpu_arch_name
825 .long cpu_elf_name
826 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
827 .long cpu_ixp4xx_name
828 .long xscale_processor_functions
829 .long v4wbi_tlb_fns
830 .long xscale_mc_user_fns
831 .long xscale_cache_fns
832 .size __ixp4xx_proc_info, . - __ixp4xx_proc_info
834 .type __pxa255_proc_info,#object
835 __pxa255_proc_info:
836 .long 0x69052d00
837 .long 0xfffffff0
838 .long 0x00000c0e
839 b __xscale_setup
840 .long cpu_arch_name
841 .long cpu_elf_name
842 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
843 .long cpu_pxa255_name
844 .long xscale_processor_functions
845 .long v4wbi_tlb_fns
846 .long xscale_mc_user_fns
847 .long xscale_cache_fns
848 .size __pxa255_proc_info, . - __pxa255_proc_info
850 .type __pxa270_proc_info,#object
851 __pxa270_proc_info:
852 .long 0x69054110
853 .long 0xfffffff0
854 .long 0x00000c0e
855 b __xscale_setup
856 .long cpu_arch_name
857 .long cpu_elf_name
858 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
859 .long cpu_pxa270_name
860 .long xscale_processor_functions
861 .long v4wbi_tlb_fns
862 .long xscale_mc_user_fns
863 .long xscale_cache_fns
864 .size __pxa270_proc_info, . - __pxa270_proc_info