arch/m68knommu/platform/5282/pit.c

   1 /***************************************************************************/
   2
   3 /*
   4  *      pit.c -- Motorola ColdFire PIT timer. Currently this type of
   5  *               hardware timer only exists in the Motorola ColdFire
   6  *               5282 CPU.
   7  *
   8  *      Copyright (C) 1999-2003, Greg Ungerer (gerg@snapgear.com)
   9  *      Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
  10  *
  11  */
  12
  13 /***************************************************************************/
  14
  15 #include <linux/config.h>
  16 #include <linux/kernel.h>
  17 #include <linux/sched.h>
  18 #include <linux/param.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <asm/irq.h>
  22 #include <asm/coldfire.h>
  23 #include <asm/mcfpit.h>
  24 #include <asm/mcfsim.h>
  25
  26 /***************************************************************************/
  27
  28 void coldfire_pit_tick(void)
  29 {
  30         volatile struct mcfpit *tp;
  31
  32         /* Reset the ColdFire timer */
  33         tp = (volatile struct mcfpit *) (MCF_IPSBAR + MCFPIT_BASE1);
  34         tp->pcsr |= MCFPIT_PCSR_PIF;
  35 }
  36
  37 /***************************************************************************/
  38
  39 void coldfire_pit_init(irqreturn_t (*handler)(int, void *, struct pt_regs *))
  40 {
  41         volatile unsigned char *icrp;
  42         volatile unsigned long *imrp;
  43         volatile struct mcfpit *tp;
  44
  45         request_irq(64+55, handler, SA_INTERRUPT, "ColdFire Timer", NULL);
  46
  47         icrp = (volatile unsigned char *) (MCF_IPSBAR + MCFICM_INTC0 +
  48                 MCFINTC_ICR0 + MCFINT_PIT1);
  49         *icrp = 0x2b; /* PIT1 with level 5, priority 3 */
  50
  51         imrp = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH);
  52         *imrp &= ~(1 << (55 - 32));
  53
  54         /* Set up PIT timer 1 as poll clock */
  55         tp = (volatile struct mcfpit *) (MCF_IPSBAR + MCFPIT_BASE1);
  56         tp->pcsr = MCFPIT_PCSR_DISABLE;
  57
  58         tp->pmr = ((MCF_CLK / 2) / 64) / HZ;
  59         tp->pcsr = MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE | MCFPIT_PCSR_OVW |
  60                 MCFPIT_PCSR_RLD | MCFPIT_PCSR_CLK64;
  61 }
  62
  63 /***************************************************************************/
  64
  65 unsigned long coldfire_pit_offset(void)
  66 {
  67         volatile struct mcfpit *tp;
  68         volatile unsigned long *ipr;
  69         unsigned long pmr, pcntr, offset;
  70
  71         tp = (volatile struct mcfpit *) (MCF_IPSBAR + MCFPIT_BASE1);
  72         ipr = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IPRH);
  73
  74         pmr = tp->pmr;
  75         pcntr = tp->pcntr;
  76
  77         /*
  78          * If we are still in the first half of the upcount and a
  79          * timer interupt is pending, then add on a ticks worth of time.
  80          */
  81         offset = ((pcntr * (1000000 / HZ)) / pmr);
  82         if ((offset < (1000000 / HZ / 2)) && (*ipr & (1 << (55 - 32))))
  83                 offset += 1000000 / HZ;
  84         return offset;
  85 }
  86
  87 /***************************************************************************/