drivers/mtd/maps/nettel.c

   1 /****************************************************************************/
   2
   3 /*
   4  *      nettel.c -- mappings for NETtel/SecureEdge/SnapGear (x86) boards.
   5  *
   6  *      (C) Copyright 2000-2001, Greg Ungerer (gerg@snapgear.com)
   7  *      (C) Copyright 2001-2002, SnapGear (www.snapgear.com)
   8  *
   9  *      $Id: nettel.c,v 1.5 2004/07/12 21:59:44 dwmw2 Exp $
  10  */
  11
  12 /****************************************************************************/
  13
  14 #include <linux/module.h>
  15 #include <linux/init.h>
  16 #include <linux/types.h>
  17 #include <linux/kernel.h>
  18 #include <linux/major.h>
  19 #include <linux/fs.h>
  20 #include <linux/root_dev.h>
  21 #include <linux/mtd/mtd.h>
  22 #include <linux/mtd/map.h>
  23 #include <linux/mtd/partitions.h>
  24 #include <linux/mtd/cfi.h>
  25 #include <linux/reboot.h>
  26 #include <asm/io.h>
  27
  28 /****************************************************************************/
  29
  30 #define INTEL_BUSWIDTH          1
  31 #define AMD_WINDOW_MAXSIZE      0x00200000
  32 #define AMD_BUSWIDTH            1
  33
  34 /*
  35  *      PAR masks and shifts, assuming 64K pages.
  36  */
  37 #define SC520_PAR_ADDR_MASK     0x00003fff
  38 #define SC520_PAR_ADDR_SHIFT    16
  39 #define SC520_PAR_TO_ADDR(par) \
  40         (((par)&SC520_PAR_ADDR_MASK) << SC520_PAR_ADDR_SHIFT)
  41
  42 #define SC520_PAR_SIZE_MASK     0x01ffc000
  43 #define SC520_PAR_SIZE_SHIFT    2
  44 #define SC520_PAR_TO_SIZE(par) \
  45         ((((par)&SC520_PAR_SIZE_MASK) << SC520_PAR_SIZE_SHIFT) + (64*1024))
  46
  47 #define SC520_PAR(cs, addr, size) \
  48         ((cs) | \
  49         ((((size)-(64*1024)) >> SC520_PAR_SIZE_SHIFT) & SC520_PAR_SIZE_MASK) | \
  50         (((addr) >> SC520_PAR_ADDR_SHIFT) & SC520_PAR_ADDR_MASK))
  51
  52 #define SC520_PAR_BOOTCS        0x8a000000
  53 #define SC520_PAR_ROMCS1        0xaa000000
  54 #define SC520_PAR_ROMCS2        0xca000000      /* Cache disabled, 64K page */
  55
  56 static void *nettel_mmcrp = NULL;
  57
  58 #ifdef CONFIG_MTD_CFI_INTELEXT
  59 static struct mtd_info *intel_mtd;
  60 #endif
  61 static struct mtd_info *amd_mtd;
  62
  63 /****************************************************************************/
  64
  65 /****************************************************************************/
  66
  67 #ifdef CONFIG_MTD_CFI_INTELEXT
  68 static struct map_info nettel_intel_map = {
  69         .name = "SnapGear Intel",
  70         .size = 0,
  71         .bankwidth = INTEL_BUSWIDTH,
  72 };
  73
  74 static struct mtd_partition nettel_intel_partitions[] = {
  75         {
  76                 .name = "SnapGear kernel",
  77                 .offset = 0,
  78                 .size = 0x000e0000
  79         },
  80         {
  81                 .name = "SnapGear filesystem",
  82                 .offset = 0x00100000,
  83         },
  84         {
  85                 .name = "SnapGear config",
  86                 .offset = 0x000e0000,
  87                 .size = 0x00020000
  88         },
  89         {
  90                 .name = "SnapGear Intel",
  91                 .offset = 0
  92         },
  93         {
  94                 .name = "SnapGear BIOS Config",
  95                 .offset = 0x007e0000,
  96                 .size = 0x00020000
  97         },
  98         {
  99                 .name = "SnapGear BIOS",
 100                 .offset = 0x007e0000,
 101                 .size = 0x00020000
 102         },
 103 };
 104 #endif
 105
 106 static struct map_info nettel_amd_map = {
 107         .name = "SnapGear AMD",
 108         .size = AMD_WINDOW_MAXSIZE,
 109         .bankwidth = AMD_BUSWIDTH,
 110 };
 111
 112 static struct mtd_partition nettel_amd_partitions[] = {
 113         {
 114                 .name = "SnapGear BIOS config",
 115                 .offset = 0x000e0000,
 116                 .size = 0x00010000
 117         },
 118         {
 119                 .name = "SnapGear BIOS",
 120                 .offset = 0x000f0000,
 121                 .size = 0x00010000
 122         },
 123         {
 124                 .name = "SnapGear AMD",
 125                 .offset = 0
 126         },
 127         {
 128                 .name = "SnapGear high BIOS",
 129                 .offset = 0x001f0000,
 130                 .size = 0x00010000
 131         }
 132 };
 133
 134 #define NUM_AMD_PARTITIONS \
 135         (sizeof(nettel_amd_partitions)/sizeof(nettel_amd_partitions[0]))
 136
 137 /****************************************************************************/
 138
 139 #ifdef CONFIG_MTD_CFI_INTELEXT
 140
 141 /*
 142  *      Set the Intel flash back to read mode since some old boot
 143  *      loaders don't.
 144  */
 145 static int nettel_reboot_notifier(struct notifier_block *nb, unsigned long val, void *v)
 146 {
 147         struct cfi_private *cfi = nettel_intel_map.fldrv_priv;
 148         unsigned long b;
 149
 150         /* Make sure all FLASH chips are put back into read mode */
 151         for (b = 0; (b < nettel_intel_partitions[3].size); b += 0x100000) {
 152                 cfi_send_gen_cmd(0xff, 0x55, b, &nettel_intel_map, cfi,
 153                         cfi->device_type, NULL);
 154         }
 155         return(NOTIFY_OK);
 156 }
 157
 158 static struct notifier_block nettel_notifier_block = {
 159         nettel_reboot_notifier, NULL, 0
 160 };
 161
 162 /*
 163  *      Erase the configuration file system.
 164  *      Used to support the software reset button.
 165  */
 166 static void nettel_erasecallback(struct erase_info *done)
 167 {
 168         wait_queue_head_t *wait_q = (wait_queue_head_t *)done->priv;
 169         wake_up(wait_q);
 170 }
 171
 172 static struct erase_info nettel_erase;
 173
 174 int nettel_eraseconfig(void)
 175 {
 176         struct mtd_info *mtd;
 177         DECLARE_WAITQUEUE(wait, current);
 178         wait_queue_head_t wait_q;
 179         int ret;
 180
 181         init_waitqueue_head(&wait_q);
 182         mtd = get_mtd_device(NULL, 2);
 183         if (mtd) {
 184                 nettel_erase.mtd = mtd;
 185                 nettel_erase.callback = nettel_erasecallback;
 186                 nettel_erase.callback = NULL;
 187                 nettel_erase.addr = 0;
 188                 nettel_erase.len = mtd->size;
 189                 nettel_erase.priv = (u_long) &wait_q;
 190                 nettel_erase.priv = 0;
 191
 192                 set_current_state(TASK_INTERRUPTIBLE);
 193                 add_wait_queue(&wait_q, &wait);
 194
 195                 ret = MTD_ERASE(mtd, &nettel_erase);
 196                 if (ret) {
 197                         set_current_state(TASK_RUNNING);
 198                         remove_wait_queue(&wait_q, &wait);
 199                         put_mtd_device(mtd);
 200                         return(ret);
 201                 }
 202
 203                 schedule();  /* Wait for erase to finish. */
 204                 remove_wait_queue(&wait_q, &wait);
 205
 206                 put_mtd_device(mtd);
 207         }
 208
 209         return(0);
 210 }
 211
 212 #else
 213
 214 int nettel_eraseconfig(void)
 215 {
 216         return(0);
 217 }
 218
 219 #endif
 220
 221 /****************************************************************************/
 222
 223 int __init nettel_init(void)
 224 {
 225         volatile unsigned long *amdpar;
 226         unsigned long amdaddr, maxsize;
 227         int num_amd_partitions=0;
 228 #ifdef CONFIG_MTD_CFI_INTELEXT
 229         volatile unsigned long *intel0par, *intel1par;
 230         unsigned long orig_bootcspar, orig_romcs1par;
 231         unsigned long intel0addr, intel0size;
 232         unsigned long intel1addr, intel1size;
 233         int intelboot, intel0cs, intel1cs;
 234         int num_intel_partitions;
 235 #endif
 236         int rc = 0;
 237
 238         nettel_mmcrp = (void *) ioremap_nocache(0xfffef000, 4096);
 239         if (nettel_mmcrp == NULL) {
 240                 printk("SNAPGEAR: failed to disable MMCR cache??\n");
 241                 return(-EIO);
 242         }
 243
 244         /* Set CPU clock to be 33.000MHz */
 245         *((unsigned char *) (nettel_mmcrp + 0xc64)) = 0x01;
 246
 247         amdpar = (volatile unsigned long *) (nettel_mmcrp + 0xc4);
 248
 249 #ifdef CONFIG_MTD_CFI_INTELEXT
 250         intelboot = 0;
 251         intel0cs = SC520_PAR_ROMCS1;
 252         intel0par = (volatile unsigned long *) (nettel_mmcrp + 0xc0);
 253         intel1cs = SC520_PAR_ROMCS2;
 254         intel1par = (volatile unsigned long *) (nettel_mmcrp + 0xbc);
 255
 256         /*
 257          *      Save the CS settings then ensure ROMCS1 and ROMCS2 are off,
 258          *      otherwise they might clash with where we try to map BOOTCS.
 259          */
 260         orig_bootcspar = *amdpar;
 261         orig_romcs1par = *intel0par;
 262         *intel0par = 0;
 263         *intel1par = 0;
 264 #endif
 265
 266         /*
 267          *      The first thing to do is determine if we have a separate
 268          *      boot FLASH device. Typically this is a small (1 to 2MB)
 269          *      AMD FLASH part. It seems that device size is about the
 270          *      only way to tell if this is the case...
 271          */
 272         amdaddr = 0x20000000;
 273         maxsize = AMD_WINDOW_MAXSIZE;
 274
 275         *amdpar = SC520_PAR(SC520_PAR_BOOTCS, amdaddr, maxsize);
 276         __asm__ ("wbinvd");
 277
 278         nettel_amd_map.phys = amdaddr;
 279         nettel_amd_map.virt = (unsigned long)
 280                 ioremap_nocache(amdaddr, maxsize);
 281         if (!nettel_amd_map.virt) {
 282                 printk("SNAPGEAR: failed to ioremap() BOOTCS\n");
 283                 return(-EIO);
 284         }
 285         simple_map_init(&nettel_amd_map);
 286
 287         if ((amd_mtd = do_map_probe("jedec_probe", &nettel_amd_map))) {
 288                 printk(KERN_NOTICE "SNAPGEAR: AMD flash device size = %dK\n",
 289                         amd_mtd->size>>10);
 290
 291                 amd_mtd->owner = THIS_MODULE;
 292
 293                 /* The high BIOS partition is only present for 2MB units */
 294                 num_amd_partitions = NUM_AMD_PARTITIONS;
 295                 if (amd_mtd->size < AMD_WINDOW_MAXSIZE)
 296                         num_amd_partitions--;
 297                 /* Don't add the partition until after the primary INTEL's */
 298
 299 #ifdef CONFIG_MTD_CFI_INTELEXT
 300                 /*
 301                  *      Map the Intel flash into memory after the AMD
 302                  *      It has to start on a multiple of maxsize.
 303                  */
 304                 maxsize = SC520_PAR_TO_SIZE(orig_romcs1par);
 305                 if (maxsize < (32 * 1024 * 1024))
 306                         maxsize = (32 * 1024 * 1024);
 307                 intel0addr = amdaddr + maxsize;
 308 #endif
 309         } else {
 310 #ifdef CONFIG_MTD_CFI_INTELEXT
 311                 /* INTEL boot FLASH */
 312                 intelboot++;
 313
 314                 if (!orig_romcs1par) {
 315                         intel0cs = SC520_PAR_BOOTCS;
 316                         intel0par = (volatile unsigned long *)
 317                                 (nettel_mmcrp + 0xc4);
 318                         intel1cs = SC520_PAR_ROMCS1;
 319                         intel1par = (volatile unsigned long *)
 320                                 (nettel_mmcrp + 0xc0);
 321
 322                         intel0addr = SC520_PAR_TO_ADDR(orig_bootcspar);
 323                         maxsize = SC520_PAR_TO_SIZE(orig_bootcspar);
 324                 } else {
 325                         /* Kernel base is on ROMCS1, not BOOTCS */
 326                         intel0cs = SC520_PAR_ROMCS1;
 327                         intel0par = (volatile unsigned long *)
 328                                 (nettel_mmcrp + 0xc0);
 329                         intel1cs = SC520_PAR_BOOTCS;
 330                         intel1par = (volatile unsigned long *)
 331                                 (nettel_mmcrp + 0xc4);
 332
 333                         intel0addr = SC520_PAR_TO_ADDR(orig_romcs1par);
 334                         maxsize = SC520_PAR_TO_SIZE(orig_romcs1par);
 335                 }
 336
 337                 /* Destroy useless AMD MTD mapping */
 338                 amd_mtd = NULL;
 339                 iounmap((void *) nettel_amd_map.virt);
 340                 nettel_amd_map.virt = (unsigned long) NULL;
 341 #else
 342                 /* Only AMD flash supported */
 343                 return(-ENXIO);
 344 #endif
 345         }
 346
 347 #ifdef CONFIG_MTD_CFI_INTELEXT
 348         /*
 349          *      We have determined the INTEL FLASH configuration, so lets
 350          *      go ahead and probe for them now.
 351          */
 352
 353         /* Set PAR to the maximum size */
 354         if (maxsize < (32 * 1024 * 1024))
 355                 maxsize = (32 * 1024 * 1024);
 356         *intel0par = SC520_PAR(intel0cs, intel0addr, maxsize);
 357
 358         /* Turn other PAR off so the first probe doesn't find it */
 359         *intel1par = 0;
 360
 361         /* Probe for the the size of the first Intel flash */
 362         nettel_intel_map.size = maxsize;
 363         nettel_intel_map.phys = intel0addr;
 364         nettel_intel_map.virt = (unsigned long)
 365                 ioremap_nocache(intel0addr, maxsize);
 366         if (!nettel_intel_map.virt) {
 367                 printk("SNAPGEAR: failed to ioremap() ROMCS1\n");
 368                 return(-EIO);
 369         }
 370         simple_map_init(&nettel_intel_map);
 371
 372         intel_mtd = do_map_probe("cfi_probe", &nettel_intel_map);
 373         if (! intel_mtd) {
 374                 iounmap((void *) nettel_intel_map.virt);
 375                 return(-ENXIO);
 376         }
 377
 378         /* Set PAR to the detected size */
 379         intel0size = intel_mtd->size;
 380         *intel0par = SC520_PAR(intel0cs, intel0addr, intel0size);
 381
 382         /*
 383          *      Map second Intel FLASH right after first. Set its size to the
 384          *      same maxsize used for the first Intel FLASH.
 385          */
 386         intel1addr = intel0addr + intel0size;
 387         *intel1par = SC520_PAR(intel1cs, intel1addr, maxsize);
 388         __asm__ ("wbinvd");
 389
 390         maxsize += intel0size;
 391
 392         /* Delete the old map and probe again to do both chips */
 393         map_destroy(intel_mtd);
 394         intel_mtd = NULL;
 395         iounmap((void *) nettel_intel_map.virt);
 396
 397         nettel_intel_map.size = maxsize;
 398         nettel_intel_map.virt = (unsigned long)
 399                 ioremap_nocache(intel0addr, maxsize);
 400         if (!nettel_intel_map.virt) {
 401                 printk("SNAPGEAR: failed to ioremap() ROMCS1/2\n");
 402                 return(-EIO);
 403         }
 404
 405         intel_mtd = do_map_probe("cfi_probe", &nettel_intel_map);
 406         if (! intel_mtd) {
 407                 iounmap((void *) nettel_intel_map.virt);
 408                 return(-ENXIO);
 409         }
 410
 411         intel1size = intel_mtd->size - intel0size;
 412         if (intel1size > 0) {
 413                 *intel1par = SC520_PAR(intel1cs, intel1addr, intel1size);
 414                 __asm__ ("wbinvd");
 415         } else {
 416                 *intel1par = 0;
 417         }
 418
 419         printk(KERN_NOTICE "SNAPGEAR: Intel flash device size = %dK\n",
 420                 (intel_mtd->size >> 10));
 421
 422         intel_mtd->owner = THIS_MODULE;
 423
 424 #ifndef CONFIG_BLK_DEV_INITRD
 425         ROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, 1);
 426 #endif
 427
 428         num_intel_partitions = sizeof(nettel_intel_partitions) /
 429                 sizeof(nettel_intel_partitions[0]);
 430
 431         if (intelboot) {
 432                 /*
 433                  *      Adjust offset and size of last boot partition.
 434                  *      Must allow for BIOS region at end of FLASH.
 435                  */
 436                 nettel_intel_partitions[1].size = (intel0size + intel1size) -
 437                         (1024*1024 + intel_mtd->erasesize);
 438                 nettel_intel_partitions[3].size = intel0size + intel1size;
 439                 nettel_intel_partitions[4].offset =
 440                         (intel0size + intel1size) - intel_mtd->erasesize;
 441                 nettel_intel_partitions[4].size = intel_mtd->erasesize;
 442                 nettel_intel_partitions[5].offset =
 443                         nettel_intel_partitions[4].offset;
 444                 nettel_intel_partitions[5].size =
 445                         nettel_intel_partitions[4].size;
 446         } else {
 447                 /* No BIOS regions when AMD boot */
 448                 num_intel_partitions -= 2;
 449         }
 450         rc = add_mtd_partitions(intel_mtd, nettel_intel_partitions,
 451                 num_intel_partitions);
 452 #endif
 453
 454         if (amd_mtd) {
 455                 rc = add_mtd_partitions(amd_mtd, nettel_amd_partitions,
 456                         num_amd_partitions);
 457         }
 458
 459 #ifdef CONFIG_MTD_CFI_INTELEXT
 460         register_reboot_notifier(&nettel_notifier_block);
 461 #endif
 462
 463         return(rc);
 464 }
 465
 466 /****************************************************************************/
 467
 468 void __exit nettel_cleanup(void)
 469 {
 470 #ifdef CONFIG_MTD_CFI_INTELEXT
 471         unregister_reboot_notifier(&nettel_notifier_block);
 472 #endif
 473         if (amd_mtd) {
 474                 del_mtd_partitions(amd_mtd);
 475                 map_destroy(amd_mtd);
 476         }
 477         if (nettel_amd_map.virt) {
 478                 iounmap((void *)nettel_amd_map.virt);
 479                 nettel_amd_map.virt = 0;
 480         }
 481 #ifdef CONFIG_MTD_CFI_INTELEXT
 482         if (intel_mtd) {
 483                 del_mtd_partitions(intel_mtd);
 484                 map_destroy(intel_mtd);
 485         }
 486         if (nettel_intel_map.virt) {
 487                 iounmap((void *)nettel_intel_map.virt);
 488                 nettel_intel_map.virt = 0;
 489         }
 490 #endif
 491 }
 492
 493 /****************************************************************************/
 494
 495 module_init(nettel_init);
 496 module_exit(nettel_cleanup);
 497
 498 MODULE_LICENSE("GPL");
 499 MODULE_AUTHOR("Greg Ungerer <gerg@snapgear.com>");
 500 MODULE_DESCRIPTION("SnapGear/SecureEdge FLASH support");
 501
 502 /****************************************************************************/