?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
MOXA linux-2.6.x / linux-2.6.9-uc0 from sdlinux-moxaart.tgz
[linux-2.6.9-moxart.git] / drivers / parport / parport_pc.c
blob5b550ab81ad60e638dbf1db522f1ec0fd252f832
1 /* Low-level parallel-port routines for 8255-based PC-style hardware.
2 *
3 * Authors: Phil Blundell <Philip.Blundell@pobox.com>
4 * Tim Waugh <tim@cyberelk.demon.co.uk>
5 * Jose Renau <renau@acm.org>
6 * David Campbell <campbell@torque.net>
7 * Andrea Arcangeli
8 *
9 * based on work by Grant Guenther <grant@torque.net> and Phil Blundell.
10 *
11 * Cleaned up include files - Russell King <linux@arm.uk.linux.org>
12 * DMA support - Bert De Jonghe <bert@sophis.be>
13 * Many ECP bugs fixed. Fred Barnes & Jamie Lokier, 1999
14 * More PCI support now conditional on CONFIG_PCI, 03/2001, Paul G.
15 * Various hacks, Fred Barnes, 04/2001
16 * Updated probing logic - Adam Belay <ambx1@neo.rr.com>
17 */
18
19 /* This driver should work with any hardware that is broadly compatible
20 * with that in the IBM PC. This applies to the majority of integrated
21 * I/O chipsets that are commonly available. The expected register
22 * layout is:
23 *
24 * base+0 data
25 * base+1 status
26 * base+2 control
27 *
28 * In addition, there are some optional registers:
29 *
30 * base+3 EPP address
31 * base+4 EPP data
32 * base+0x400 ECP config A
33 * base+0x401 ECP config B
34 * base+0x402 ECP control
35 *
36 * All registers are 8 bits wide and read/write. If your hardware differs
37 * only in register addresses (eg because your registers are on 32-bit
38 * word boundaries) then you can alter the constants in parport_pc.h to
39 * accommodate this.
40 *
41 * Note that the ECP registers may not start at offset 0x400 for PCI cards,
42 * but rather will start at port->base_hi.
43 */
44
45 #include <linux/config.h>
46 #include <linux/module.h>
47 #include <linux/init.h>
48 #include <linux/sched.h>
49 #include <linux/delay.h>
50 #include <linux/errno.h>
51 #include <linux/interrupt.h>
52 #include <linux/ioport.h>
53 #include <linux/kernel.h>
54 #include <linux/slab.h>
55 #include <linux/pci.h>
56 #include <linux/pnp.h>
57 #include <linux/sysctl.h>
58
59 #include <asm/io.h>
60 #include <asm/dma.h>
61 #include <asm/uaccess.h>
62
63 #include <linux/parport.h>
64 #include <linux/parport_pc.h>
65 #include <asm/parport.h>
66
67 #define PARPORT_PC_MAX_PORTS PARPORT_MAX
68
69 /* ECR modes */
70 #define ECR_SPP 00
71 #define ECR_PS2 01
72 #define ECR_PPF 02
73 #define ECR_ECP 03
74 #define ECR_EPP 04
75 #define ECR_VND 05
76 #define ECR_TST 06
77 #define ECR_CNF 07
78 #define ECR_MODE_MASK 0xe0
79 #define ECR_WRITE(p,v) frob_econtrol((p),0xff,(v))
80
81 #undef DEBUG
82
83 #ifdef DEBUG
84 #define DPRINTK printk
85 #else
86 #define DPRINTK(stuff...)
87 #endif
88
89
90 #define NR_SUPERIOS 3
91 static struct superio_struct { /* For Super-IO chips autodetection */
92 int io;
93 int irq;
94 int dma;
95 } superios[NR_SUPERIOS] __devinitdata = { {0,},};
96
97 static int user_specified;
98 #if defined(CONFIG_PARPORT_PC_SUPERIO) || \
99 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
100 static int verbose_probing;
101 #endif
102 static int pci_registered_parport;
103 static int pnp_registered_parport;
104
105 /* frob_control, but for ECR */
106 static void frob_econtrol (struct parport *pb, unsigned char m,
107 unsigned char v)
108 {
109 unsigned char ectr = 0;
110
111 if (m != 0xff)
112 ectr = inb (ECONTROL (pb));
113
114 DPRINTK (KERN_DEBUG "frob_econtrol(%02x,%02x): %02x -> %02x\n",
115 m, v, ectr, (ectr & ~m) ^ v);
116
117 outb ((ectr & ~m) ^ v, ECONTROL (pb));
118 }
119
120 static __inline__ void frob_set_mode (struct parport *p, int mode)
121 {
122 frob_econtrol (p, ECR_MODE_MASK, mode << 5);
123 }
124
125 #ifdef CONFIG_PARPORT_PC_FIFO
126 /* Safely change the mode bits in the ECR
127 Returns:
128 0 : Success
129 -EBUSY: Could not drain FIFO in some finite amount of time,
130 mode not changed!
131 */
132 static int change_mode(struct parport *p, int m)
133 {
134 const struct parport_pc_private *priv = p->physport->private_data;
135 unsigned char oecr;
136 int mode;
137
138 DPRINTK(KERN_INFO "parport change_mode ECP-ISA to mode 0x%02x\n",m);
139
140 if (!priv->ecr) {
141 printk (KERN_DEBUG "change_mode: but there's no ECR!\n");
142 return 0;
143 }
144
145 /* Bits <7:5> contain the mode. */
146 oecr = inb (ECONTROL (p));
147 mode = (oecr >> 5) & 0x7;
148 if (mode == m) return 0;
149
150 if (mode >= 2 && !(priv->ctr & 0x20)) {
151 /* This mode resets the FIFO, so we may
152 * have to wait for it to drain first. */
153 unsigned long expire = jiffies + p->physport->cad->timeout;
154 int counter;
155 switch (mode) {
156 case ECR_PPF: /* Parallel Port FIFO mode */
157 case ECR_ECP: /* ECP Parallel Port mode */
158 /* Busy wait for 200us */
159 for (counter = 0; counter < 40; counter++) {
160 if (inb (ECONTROL (p)) & 0x01)
161 break;
162 if (signal_pending (current)) break;
163 udelay (5);
164 }
165
166 /* Poll slowly. */
167 while (!(inb (ECONTROL (p)) & 0x01)) {
168 if (time_after_eq (jiffies, expire))
169 /* The FIFO is stuck. */
170 return -EBUSY;
171 __set_current_state (TASK_INTERRUPTIBLE);
172 schedule_timeout ((HZ + 99) / 100);
173 if (signal_pending (current))
174 break;
175 }
176 }
177 }
178
179 if (mode >= 2 && m >= 2) {
180 /* We have to go through mode 001 */
181 oecr &= ~(7 << 5);
182 oecr |= ECR_PS2 << 5;
183 ECR_WRITE (p, oecr);
184 }
185
186 /* Set the mode. */
187 oecr &= ~(7 << 5);
188 oecr |= m << 5;
189 ECR_WRITE (p, oecr);
190 return 0;
191 }
192
193 #ifdef CONFIG_PARPORT_1284
194 /* Find FIFO lossage; FIFO is reset */
195 static int get_fifo_residue (struct parport *p)
196 {
197 int residue;
198 int cnfga;
199 const struct parport_pc_private *priv = p->physport->private_data;
200
201 /* Adjust for the contents of the FIFO. */
202 for (residue = priv->fifo_depth; ; residue--) {
203 if (inb (ECONTROL (p)) & 0x2)
204 /* Full up. */
205 break;
206
207 outb (0, FIFO (p));
208 }
209
210 printk (KERN_DEBUG "%s: %d PWords were left in FIFO\n", p->name,
211 residue);
212
213 /* Reset the FIFO. */
214 frob_set_mode (p, ECR_PS2);
215
216 /* Now change to config mode and clean up. FIXME */
217 frob_set_mode (p, ECR_CNF);
218 cnfga = inb (CONFIGA (p));
219 printk (KERN_DEBUG "%s: cnfgA contains 0x%02x\n", p->name, cnfga);
220
221 if (!(cnfga & (1<<2))) {
222 printk (KERN_DEBUG "%s: Accounting for extra byte\n", p->name);
223 residue++;
224 }
225
226 /* Don't care about partial PWords until support is added for
227 * PWord != 1 byte. */
228
229 /* Back to PS2 mode. */
230 frob_set_mode (p, ECR_PS2);
231
232 DPRINTK (KERN_DEBUG "*** get_fifo_residue: done residue collecting (ecr = 0x%2.2x)\n", inb (ECONTROL (p)));
233 return residue;
234 }
235 #endif /* IEEE 1284 support */
236 #endif /* FIFO support */
237
238 /*
239 * Clear TIMEOUT BIT in EPP MODE
240 *
241 * This is also used in SPP detection.
242 */
243 static int clear_epp_timeout(struct parport *pb)
244 {
245 unsigned char r;
246
247 if (!(parport_pc_read_status(pb) & 0x01))
248 return 1;
249
250 /* To clear timeout some chips require double read */
251 parport_pc_read_status(pb);
252 r = parport_pc_read_status(pb);
253 outb (r | 0x01, STATUS (pb)); /* Some reset by writing 1 */
254 outb (r & 0xfe, STATUS (pb)); /* Others by writing 0 */
255 r = parport_pc_read_status(pb);
256
257 return !(r & 0x01);
258 }
259
260 /*
261 * Access functions.
262 *
263 * Most of these aren't static because they may be used by the
264 * parport_xxx_yyy macros. extern __inline__ versions of several
265 * of these are in parport_pc.h.
266 */
267
268 static irqreturn_t parport_pc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
269 {
270 parport_generic_irq(irq, (struct parport *) dev_id, regs);
271 /* FIXME! Was it really ours? */
272 return IRQ_HANDLED;
273 }
274
275 void parport_pc_init_state(struct pardevice *dev, struct parport_state *s)
276 {
277 s->u.pc.ctr = 0xc;
278 if (dev->irq_func &&
279 dev->port->irq != PARPORT_IRQ_NONE)
280 /* Set ackIntEn */
281 s->u.pc.ctr |= 0x10;
282
283 s->u.pc.ecr = 0x34; /* NetMos chip can cause problems 0x24;
284 * D.Gruszka VScom */
285 }
286
287 void parport_pc_save_state(struct parport *p, struct parport_state *s)
288 {
289 const struct parport_pc_private *priv = p->physport->private_data;
290 s->u.pc.ctr = priv->ctr;
291 if (priv->ecr)
292 s->u.pc.ecr = inb (ECONTROL (p));
293 }
294
295 void parport_pc_restore_state(struct parport *p, struct parport_state *s)
296 {
297 struct parport_pc_private *priv = p->physport->private_data;
298 register unsigned char c = s->u.pc.ctr & priv->ctr_writable;
299 outb (c, CONTROL (p));
300 priv->ctr = c;
301 if (priv->ecr)
302 ECR_WRITE (p, s->u.pc.ecr);
303 }
304
305 #ifdef CONFIG_PARPORT_1284
306 static size_t parport_pc_epp_read_data (struct parport *port, void *buf,
307 size_t length, int flags)
308 {
309 size_t got = 0;
310
311 if (flags & PARPORT_W91284PIC) {
312 unsigned char status;
313 size_t left = length;
314
315 /* use knowledge about data lines..:
316 * nFault is 0 if there is at least 1 byte in the Warp's FIFO
317 * pError is 1 if there are 16 bytes in the Warp's FIFO
318 */
319 status = inb (STATUS (port));
320
321 while (!(status & 0x08) && (got < length)) {
322 if ((left >= 16) && (status & 0x20) && !(status & 0x08)) {
323 /* can grab 16 bytes from warp fifo */
324 if (!((long)buf & 0x03)) {
325 insl (EPPDATA (port), buf, 4);
326 } else {
327 insb (EPPDATA (port), buf, 16);
328 }
329 buf += 16;
330 got += 16;
331 left -= 16;
332 } else {
333 /* grab single byte from the warp fifo */
334 *((char *)buf) = inb (EPPDATA (port));
335 buf++;
336 got++;
337 left--;
338 }
339 status = inb (STATUS (port));
340 if (status & 0x01) {
341 /* EPP timeout should never occur... */
342 printk (KERN_DEBUG "%s: EPP timeout occurred while talking to "
343 "w91284pic (should not have done)\n", port->name);
344 clear_epp_timeout (port);
345 }
346 }
347 return got;
348 }
349 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
350 if (!(((long)buf | length) & 0x03)) {
351 insl (EPPDATA (port), buf, (length >> 2));
352 } else {
353 insb (EPPDATA (port), buf, length);
354 }
355 if (inb (STATUS (port)) & 0x01) {
356 clear_epp_timeout (port);
357 return -EIO;
358 }
359 return length;
360 }
361 for (; got < length; got++) {
362 *((char*)buf) = inb (EPPDATA(port));
363 buf++;
364 if (inb (STATUS (port)) & 0x01) {
365 /* EPP timeout */
366 clear_epp_timeout (port);
367 break;
368 }
369 }
370
371 return got;
372 }
373
374 static size_t parport_pc_epp_write_data (struct parport *port, const void *buf,
375 size_t length, int flags)
376 {
377 size_t written = 0;
378
379 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
380 if (!(((long)buf | length) & 0x03)) {
381 outsl (EPPDATA (port), buf, (length >> 2));
382 } else {
383 outsb (EPPDATA (port), buf, length);
384 }
385 if (inb (STATUS (port)) & 0x01) {
386 clear_epp_timeout (port);
387 return -EIO;
388 }
389 return length;
390 }
391 for (; written < length; written++) {
392 outb (*((char*)buf), EPPDATA(port));
393 buf++;
394 if (inb (STATUS(port)) & 0x01) {
395 clear_epp_timeout (port);
396 break;
397 }
398 }
399
400 return written;
401 }
402
403 static size_t parport_pc_epp_read_addr (struct parport *port, void *buf,
404 size_t length, int flags)
405 {
406 size_t got = 0;
407
408 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
409 insb (EPPADDR (port), buf, length);
410 if (inb (STATUS (port)) & 0x01) {
411 clear_epp_timeout (port);
412 return -EIO;
413 }
414 return length;
415 }
416 for (; got < length; got++) {
417 *((char*)buf) = inb (EPPADDR (port));
418 buf++;
419 if (inb (STATUS (port)) & 0x01) {
420 clear_epp_timeout (port);
421 break;
422 }
423 }
424
425 return got;
426 }
427
428 static size_t parport_pc_epp_write_addr (struct parport *port,
429 const void *buf, size_t length,
430 int flags)
431 {
432 size_t written = 0;
433
434 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
435 outsb (EPPADDR (port), buf, length);
436 if (inb (STATUS (port)) & 0x01) {
437 clear_epp_timeout (port);
438 return -EIO;
439 }
440 return length;
441 }
442 for (; written < length; written++) {
443 outb (*((char*)buf), EPPADDR (port));
444 buf++;
445 if (inb (STATUS (port)) & 0x01) {
446 clear_epp_timeout (port);
447 break;
448 }
449 }
450
451 return written;
452 }
453
454 static size_t parport_pc_ecpepp_read_data (struct parport *port, void *buf,
455 size_t length, int flags)
456 {
457 size_t got;
458
459 frob_set_mode (port, ECR_EPP);
460 parport_pc_data_reverse (port);
461 parport_pc_write_control (port, 0x4);
462 got = parport_pc_epp_read_data (port, buf, length, flags);
463 frob_set_mode (port, ECR_PS2);
464
465 return got;
466 }
467
468 static size_t parport_pc_ecpepp_write_data (struct parport *port,
469 const void *buf, size_t length,
470 int flags)
471 {
472 size_t written;
473
474 frob_set_mode (port, ECR_EPP);
475 parport_pc_write_control (port, 0x4);
476 parport_pc_data_forward (port);
477 written = parport_pc_epp_write_data (port, buf, length, flags);
478 frob_set_mode (port, ECR_PS2);
479
480 return written;
481 }
482
483 static size_t parport_pc_ecpepp_read_addr (struct parport *port, void *buf,
484 size_t length, int flags)
485 {
486 size_t got;
487
488 frob_set_mode (port, ECR_EPP);
489 parport_pc_data_reverse (port);
490 parport_pc_write_control (port, 0x4);
491 got = parport_pc_epp_read_addr (port, buf, length, flags);
492 frob_set_mode (port, ECR_PS2);
493
494 return got;
495 }
496
497 static size_t parport_pc_ecpepp_write_addr (struct parport *port,
498 const void *buf, size_t length,
499 int flags)
500 {
501 size_t written;
502
503 frob_set_mode (port, ECR_EPP);
504 parport_pc_write_control (port, 0x4);
505 parport_pc_data_forward (port);
506 written = parport_pc_epp_write_addr (port, buf, length, flags);
507 frob_set_mode (port, ECR_PS2);
508
509 return written;
510 }
511 #endif /* IEEE 1284 support */
512
513 #ifdef CONFIG_PARPORT_PC_FIFO
514 static size_t parport_pc_fifo_write_block_pio (struct parport *port,
515 const void *buf, size_t length)
516 {
517 int ret = 0;
518 const unsigned char *bufp = buf;
519 size_t left = length;
520 unsigned long expire = jiffies + port->physport->cad->timeout;
521 const int fifo = FIFO (port);
522 int poll_for = 8; /* 80 usecs */
523 const struct parport_pc_private *priv = port->physport->private_data;
524 const int fifo_depth = priv->fifo_depth;
525
526 port = port->physport;
527
528 /* We don't want to be interrupted every character. */
529 parport_pc_disable_irq (port);
530 /* set nErrIntrEn and serviceIntr */
531 frob_econtrol (port, (1<<4) | (1<<2), (1<<4) | (1<<2));
532
533 /* Forward mode. */
534 parport_pc_data_forward (port); /* Must be in PS2 mode */
535
536 while (left) {
537 unsigned char byte;
538 unsigned char ecrval = inb (ECONTROL (port));
539 int i = 0;
540
541 if (need_resched() && time_before (jiffies, expire))
542 /* Can't yield the port. */
543 schedule ();
544
545 /* Anyone else waiting for the port? */
546 if (port->waithead) {
547 printk (KERN_DEBUG "Somebody wants the port\n");
548 break;
549 }
550
551 if (ecrval & 0x02) {
552 /* FIFO is full. Wait for interrupt. */
553
554 /* Clear serviceIntr */
555 ECR_WRITE (port, ecrval & ~(1<<2));
556 false_alarm:
557 ret = parport_wait_event (port, HZ);
558 if (ret < 0) break;
559 ret = 0;
560 if (!time_before (jiffies, expire)) {
561 /* Timed out. */
562 printk (KERN_DEBUG "FIFO write timed out\n");
563 break;
564 }
565 ecrval = inb (ECONTROL (port));
566 if (!(ecrval & (1<<2))) {
567 if (need_resched() &&
568 time_before (jiffies, expire))
569 schedule ();
570
571 goto false_alarm;
572 }
573
574 continue;
575 }
576
577 /* Can't fail now. */
578 expire = jiffies + port->cad->timeout;
579
580 poll:
581 if (signal_pending (current))
582 break;
583
584 if (ecrval & 0x01) {
585 /* FIFO is empty. Blast it full. */
586 const int n = left < fifo_depth ? left : fifo_depth;
587 outsb (fifo, bufp, n);
588 bufp += n;
589 left -= n;
590
591 /* Adjust the poll time. */
592 if (i < (poll_for - 2)) poll_for--;
593 continue;
594 } else if (i++ < poll_for) {
595 udelay (10);
596 ecrval = inb (ECONTROL (port));
597 goto poll;
598 }
599
600 /* Half-full (call me an optimist) */
601 byte = *bufp++;
602 outb (byte, fifo);
603 left--;
604 }
605
606 dump_parport_state ("leave fifo_write_block_pio", port);
607 return length - left;
608 }
609
610 static size_t parport_pc_fifo_write_block_dma (struct parport *port,
611 const void *buf, size_t length)
612 {
613 int ret = 0;
614 unsigned long dmaflag;
615 size_t left = length;
616 const struct parport_pc_private *priv = port->physport->private_data;
617 dma_addr_t dma_addr, dma_handle;
618 size_t maxlen = 0x10000; /* max 64k per DMA transfer */
619 unsigned long start = (unsigned long) buf;
620 unsigned long end = (unsigned long) buf + length - 1;
621
622 dump_parport_state ("enter fifo_write_block_dma", port);
623 if (end < MAX_DMA_ADDRESS) {
624 /* If it would cross a 64k boundary, cap it at the end. */
625 if ((start ^ end) & ~0xffffUL)
626 maxlen = 0x10000 - (start & 0xffff);
627
628 dma_addr = dma_handle = pci_map_single(priv->dev, (void *)buf, length,
629 PCI_DMA_TODEVICE);
630 } else {
631 /* above 16 MB we use a bounce buffer as ISA-DMA is not possible */
632 maxlen = PAGE_SIZE; /* sizeof(priv->dma_buf) */
633 dma_addr = priv->dma_handle;
634 dma_handle = 0;
635 }
636
637 port = port->physport;
638
639 /* We don't want to be interrupted every character. */
640 parport_pc_disable_irq (port);
641 /* set nErrIntrEn and serviceIntr */
642 frob_econtrol (port, (1<<4) | (1<<2), (1<<4) | (1<<2));
643
644 /* Forward mode. */
645 parport_pc_data_forward (port); /* Must be in PS2 mode */
646
647 while (left) {
648 unsigned long expire = jiffies + port->physport->cad->timeout;
649
650 size_t count = left;
651
652 if (count > maxlen)
653 count = maxlen;
654
655 if (!dma_handle) /* bounce buffer ! */
656 memcpy(priv->dma_buf, buf, count);
657
658 dmaflag = claim_dma_lock();
659 disable_dma(port->dma);
660 clear_dma_ff(port->dma);
661 set_dma_mode(port->dma, DMA_MODE_WRITE);
662 set_dma_addr(port->dma, dma_addr);
663 set_dma_count(port->dma, count);
664
665 /* Set DMA mode */
666 frob_econtrol (port, 1<<3, 1<<3);
667
668 /* Clear serviceIntr */
669 frob_econtrol (port, 1<<2, 0);
670
671 enable_dma(port->dma);
672 release_dma_lock(dmaflag);
673
674 /* assume DMA will be successful */
675 left -= count;
676 buf += count;
677 if (dma_handle) dma_addr += count;
678
679 /* Wait for interrupt. */
680 false_alarm:
681 ret = parport_wait_event (port, HZ);
682 if (ret < 0) break;
683 ret = 0;
684 if (!time_before (jiffies, expire)) {
685 /* Timed out. */
686 printk (KERN_DEBUG "DMA write timed out\n");
687 break;
688 }
689 /* Is serviceIntr set? */
690 if (!(inb (ECONTROL (port)) & (1<<2))) {
691 cond_resched();
692
693 goto false_alarm;
694 }
695
696 dmaflag = claim_dma_lock();
697 disable_dma(port->dma);
698 clear_dma_ff(port->dma);
699 count = get_dma_residue(port->dma);
700 release_dma_lock(dmaflag);
701
702 cond_resched(); /* Can't yield the port. */
703
704 /* Anyone else waiting for the port? */
705 if (port->waithead) {
706 printk (KERN_DEBUG "Somebody wants the port\n");
707 break;
708 }
709
710 /* update for possible DMA residue ! */
711 buf -= count;
712 left += count;
713 if (dma_handle) dma_addr -= count;
714 }
715
716 /* Maybe got here through break, so adjust for DMA residue! */
717 dmaflag = claim_dma_lock();
718 disable_dma(port->dma);
719 clear_dma_ff(port->dma);
720 left += get_dma_residue(port->dma);
721 release_dma_lock(dmaflag);
722
723 /* Turn off DMA mode */
724 frob_econtrol (port, 1<<3, 0);
725
726 if (dma_handle)
727 pci_unmap_single(priv->dev, dma_handle, length, PCI_DMA_TODEVICE);
728
729 dump_parport_state ("leave fifo_write_block_dma", port);
730 return length - left;
731 }
732
733 /* Parallel Port FIFO mode (ECP chipsets) */
734 size_t parport_pc_compat_write_block_pio (struct parport *port,
735 const void *buf, size_t length,
736 int flags)
737 {
738 size_t written;
739 int r;
740 unsigned long expire;
741 const struct parport_pc_private *priv = port->physport->private_data;
742
743 /* Special case: a timeout of zero means we cannot call schedule().
744 * Also if O_NONBLOCK is set then use the default implementation. */
745 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
746 return parport_ieee1284_write_compat (port, buf,
747 length, flags);
748
749 /* Set up parallel port FIFO mode.*/
750 parport_pc_data_forward (port); /* Must be in PS2 mode */
751 parport_pc_frob_control (port, PARPORT_CONTROL_STROBE, 0);
752 r = change_mode (port, ECR_PPF); /* Parallel port FIFO */
753 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_PPF failed\n", port->name);
754
755 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
756
757 /* Write the data to the FIFO. */
758 if (port->dma != PARPORT_DMA_NONE)
759 written = parport_pc_fifo_write_block_dma (port, buf, length);
760 else
761 written = parport_pc_fifo_write_block_pio (port, buf, length);
762
763 /* Finish up. */
764 /* For some hardware we don't want to touch the mode until
765 * the FIFO is empty, so allow 4 seconds for each position
766 * in the fifo.
767 */
768 expire = jiffies + (priv->fifo_depth * HZ * 4);
769 do {
770 /* Wait for the FIFO to empty */
771 r = change_mode (port, ECR_PS2);
772 if (r != -EBUSY) {
773 break;
774 }
775 } while (time_before (jiffies, expire));
776 if (r == -EBUSY) {
777
778 printk (KERN_DEBUG "%s: FIFO is stuck\n", port->name);
779
780 /* Prevent further data transfer. */
781 frob_set_mode (port, ECR_TST);
782
783 /* Adjust for the contents of the FIFO. */
784 for (written -= priv->fifo_depth; ; written++) {
785 if (inb (ECONTROL (port)) & 0x2) {
786 /* Full up. */
787 break;
788 }
789 outb (0, FIFO (port));
790 }
791
792 /* Reset the FIFO and return to PS2 mode. */
793 frob_set_mode (port, ECR_PS2);
794 }
795
796 r = parport_wait_peripheral (port,
797 PARPORT_STATUS_BUSY,
798 PARPORT_STATUS_BUSY);
799 if (r)
800 printk (KERN_DEBUG
801 "%s: BUSY timeout (%d) in compat_write_block_pio\n",
802 port->name, r);
803
804 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
805
806 return written;
807 }
808
809 /* ECP */
810 #ifdef CONFIG_PARPORT_1284
811 size_t parport_pc_ecp_write_block_pio (struct parport *port,
812 const void *buf, size_t length,
813 int flags)
814 {
815 size_t written;
816 int r;
817 unsigned long expire;
818 const struct parport_pc_private *priv = port->physport->private_data;
819
820 /* Special case: a timeout of zero means we cannot call schedule().
821 * Also if O_NONBLOCK is set then use the default implementation. */
822 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
823 return parport_ieee1284_ecp_write_data (port, buf,
824 length, flags);
825
826 /* Switch to forward mode if necessary. */
827 if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) {
828 /* Event 47: Set nInit high. */
829 parport_frob_control (port,
830 PARPORT_CONTROL_INIT
831 | PARPORT_CONTROL_AUTOFD,
832 PARPORT_CONTROL_INIT
833 | PARPORT_CONTROL_AUTOFD);
834
835 /* Event 49: PError goes high. */
836 r = parport_wait_peripheral (port,
837 PARPORT_STATUS_PAPEROUT,
838 PARPORT_STATUS_PAPEROUT);
839 if (r) {
840 printk (KERN_DEBUG "%s: PError timeout (%d) "
841 "in ecp_write_block_pio\n", port->name, r);
842 }
843 }
844
845 /* Set up ECP parallel port mode.*/
846 parport_pc_data_forward (port); /* Must be in PS2 mode */
847 parport_pc_frob_control (port,
848 PARPORT_CONTROL_STROBE |
849 PARPORT_CONTROL_AUTOFD,
850 0);
851 r = change_mode (port, ECR_ECP); /* ECP FIFO */
852 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", port->name);
853 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
854
855 /* Write the data to the FIFO. */
856 if (port->dma != PARPORT_DMA_NONE)
857 written = parport_pc_fifo_write_block_dma (port, buf, length);
858 else
859 written = parport_pc_fifo_write_block_pio (port, buf, length);
860
861 /* Finish up. */
862 /* For some hardware we don't want to touch the mode until
863 * the FIFO is empty, so allow 4 seconds for each position
864 * in the fifo.
865 */
866 expire = jiffies + (priv->fifo_depth * (HZ * 4));
867 do {
868 /* Wait for the FIFO to empty */
869 r = change_mode (port, ECR_PS2);
870 if (r != -EBUSY) {
871 break;
872 }
873 } while (time_before (jiffies, expire));
874 if (r == -EBUSY) {
875
876 printk (KERN_DEBUG "%s: FIFO is stuck\n", port->name);
877
878 /* Prevent further data transfer. */
879 frob_set_mode (port, ECR_TST);
880
881 /* Adjust for the contents of the FIFO. */
882 for (written -= priv->fifo_depth; ; written++) {
883 if (inb (ECONTROL (port)) & 0x2) {
884 /* Full up. */
885 break;
886 }
887 outb (0, FIFO (port));
888 }
889
890 /* Reset the FIFO and return to PS2 mode. */
891 frob_set_mode (port, ECR_PS2);
892
893 /* Host transfer recovery. */
894 parport_pc_data_reverse (port); /* Must be in PS2 mode */
895 udelay (5);
896 parport_frob_control (port, PARPORT_CONTROL_INIT, 0);
897 r = parport_wait_peripheral (port, PARPORT_STATUS_PAPEROUT, 0);
898 if (r)
899 printk (KERN_DEBUG "%s: PE,1 timeout (%d) "
900 "in ecp_write_block_pio\n", port->name, r);
901
902 parport_frob_control (port,
903 PARPORT_CONTROL_INIT,
904 PARPORT_CONTROL_INIT);
905 r = parport_wait_peripheral (port,
906 PARPORT_STATUS_PAPEROUT,
907 PARPORT_STATUS_PAPEROUT);
908 if (r)
909 printk (KERN_DEBUG "%s: PE,2 timeout (%d) "
910 "in ecp_write_block_pio\n", port->name, r);
911 }
912
913 r = parport_wait_peripheral (port,
914 PARPORT_STATUS_BUSY,
915 PARPORT_STATUS_BUSY);
916 if(r)
917 printk (KERN_DEBUG
918 "%s: BUSY timeout (%d) in ecp_write_block_pio\n",
919 port->name, r);
920
921 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
922
923 return written;
924 }
925
926 size_t parport_pc_ecp_read_block_pio (struct parport *port,
927 void *buf, size_t length, int flags)
928 {
929 size_t left = length;
930 size_t fifofull;
931 int r;
932 const int fifo = FIFO(port);
933 const struct parport_pc_private *priv = port->physport->private_data;
934 const int fifo_depth = priv->fifo_depth;
935 char *bufp = buf;
936
937 port = port->physport;
938 DPRINTK (KERN_DEBUG "parport_pc: parport_pc_ecp_read_block_pio\n");
939 dump_parport_state ("enter fcn", port);
940
941 /* Special case: a timeout of zero means we cannot call schedule().
942 * Also if O_NONBLOCK is set then use the default implementation. */
943 if (port->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
944 return parport_ieee1284_ecp_read_data (port, buf,
945 length, flags);
946
947 if (port->ieee1284.mode == IEEE1284_MODE_ECPRLE) {
948 /* If the peripheral is allowed to send RLE compressed
949 * data, it is possible for a byte to expand to 128
950 * bytes in the FIFO. */
951 fifofull = 128;
952 } else {
953 fifofull = fifo_depth;
954 }
955
956 /* If the caller wants less than a full FIFO's worth of data,
957 * go through software emulation. Otherwise we may have to throw
958 * away data. */
959 if (length < fifofull)
960 return parport_ieee1284_ecp_read_data (port, buf,
961 length, flags);
962
963 if (port->ieee1284.phase != IEEE1284_PH_REV_IDLE) {
964 /* change to reverse-idle phase (must be in forward-idle) */
965
966 /* Event 38: Set nAutoFd low (also make sure nStrobe is high) */
967 parport_frob_control (port,
968 PARPORT_CONTROL_AUTOFD
969 | PARPORT_CONTROL_STROBE,
970 PARPORT_CONTROL_AUTOFD);
971 parport_pc_data_reverse (port); /* Must be in PS2 mode */
972 udelay (5);
973 /* Event 39: Set nInit low to initiate bus reversal */
974 parport_frob_control (port,
975 PARPORT_CONTROL_INIT,
976 0);
977 /* Event 40: Wait for nAckReverse (PError) to go low */
978 r = parport_wait_peripheral (port, PARPORT_STATUS_PAPEROUT, 0);
979 if (r) {
980 printk (KERN_DEBUG "%s: PE timeout Event 40 (%d) "
981 "in ecp_read_block_pio\n", port->name, r);
982 return 0;
983 }
984 }
985
986 /* Set up ECP FIFO mode.*/
987 /* parport_pc_frob_control (port,
988 PARPORT_CONTROL_STROBE |
989 PARPORT_CONTROL_AUTOFD,
990 PARPORT_CONTROL_AUTOFD); */
991 r = change_mode (port, ECR_ECP); /* ECP FIFO */
992 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", port->name);
993
994 port->ieee1284.phase = IEEE1284_PH_REV_DATA;
995
996 /* the first byte must be collected manually */
997 dump_parport_state ("pre 43", port);
998 /* Event 43: Wait for nAck to go low */
999 r = parport_wait_peripheral (port, PARPORT_STATUS_ACK, 0);
1000 if (r) {
1001 /* timed out while reading -- no data */
1002 printk (KERN_DEBUG "PIO read timed out (initial byte)\n");
1003 goto out_no_data;
1004 }
1005 /* read byte */
1006 *bufp++ = inb (DATA (port));
1007 left--;
1008 dump_parport_state ("43-44", port);
1009 /* Event 44: nAutoFd (HostAck) goes high to acknowledge */
1010 parport_pc_frob_control (port,
1011 PARPORT_CONTROL_AUTOFD,
1012 0);
1013 dump_parport_state ("pre 45", port);
1014 /* Event 45: Wait for nAck to go high */
1015 /* r = parport_wait_peripheral (port, PARPORT_STATUS_ACK, PARPORT_STATUS_ACK); */
1016 dump_parport_state ("post 45", port);
1017 r = 0;
1018 if (r) {
1019 /* timed out while waiting for peripheral to respond to ack */
1020 printk (KERN_DEBUG "ECP PIO read timed out (waiting for nAck)\n");
1021
1022 /* keep hold of the byte we've got already */
1023 goto out_no_data;
1024 }
1025 /* Event 46: nAutoFd (HostAck) goes low to accept more data */
1026 parport_pc_frob_control (port,
1027 PARPORT_CONTROL_AUTOFD,
1028 PARPORT_CONTROL_AUTOFD);
1029
1030
1031 dump_parport_state ("rev idle", port);
1032 /* Do the transfer. */
1033 while (left > fifofull) {
1034 int ret;
1035 unsigned long expire = jiffies + port->cad->timeout;
1036 unsigned char ecrval = inb (ECONTROL (port));
1037
1038 if (need_resched() && time_before (jiffies, expire))
1039 /* Can't yield the port. */
1040 schedule ();
1041
1042 /* At this point, the FIFO may already be full. In
1043 * that case ECP is already holding back the
1044 * peripheral (assuming proper design) with a delayed
1045 * handshake. Work fast to avoid a peripheral
1046 * timeout. */
1047
1048 if (ecrval & 0x01) {
1049 /* FIFO is empty. Wait for interrupt. */
1050 dump_parport_state ("FIFO empty", port);
1051
1052 /* Anyone else waiting for the port? */
1053 if (port->waithead) {
1054 printk (KERN_DEBUG "Somebody wants the port\n");
1055 break;
1056 }
1057
1058 /* Clear serviceIntr */
1059 ECR_WRITE (port, ecrval & ~(1<<2));
1060 false_alarm:
1061 dump_parport_state ("waiting", port);
1062 ret = parport_wait_event (port, HZ);
1063 DPRINTK (KERN_DEBUG "parport_wait_event returned %d\n", ret);
1064 if (ret < 0)
1065 break;
1066 ret = 0;
1067 if (!time_before (jiffies, expire)) {
1068 /* Timed out. */
1069 dump_parport_state ("timeout", port);
1070 printk (KERN_DEBUG "PIO read timed out\n");
1071 break;
1072 }
1073 ecrval = inb (ECONTROL (port));
1074 if (!(ecrval & (1<<2))) {
1075 if (need_resched() &&
1076 time_before (jiffies, expire)) {
1077 schedule ();
1078 }
1079 goto false_alarm;
1080 }
1081
1082 /* Depending on how the FIFO threshold was
1083 * set, how long interrupt service took, and
1084 * how fast the peripheral is, we might be
1085 * lucky and have a just filled FIFO. */
1086 continue;
1087 }
1088
1089 if (ecrval & 0x02) {
1090 /* FIFO is full. */
1091 dump_parport_state ("FIFO full", port);
1092 insb (fifo, bufp, fifo_depth);
1093 bufp += fifo_depth;
1094 left -= fifo_depth;
1095 continue;
1096 }
1097
1098 DPRINTK (KERN_DEBUG "*** ecp_read_block_pio: reading one byte from the FIFO\n");
1099
1100 /* FIFO not filled. We will cycle this loop for a while
1101 * and either the peripheral will fill it faster,
1102 * tripping a fast empty with insb, or we empty it. */
1103 *bufp++ = inb (fifo);
1104 left--;
1105 }
1106
1107 /* scoop up anything left in the FIFO */
1108 while (left && !(inb (ECONTROL (port) & 0x01))) {
1109 *bufp++ = inb (fifo);
1110 left--;
1111 }
1112
1113 port->ieee1284.phase = IEEE1284_PH_REV_IDLE;
1114 dump_parport_state ("rev idle2", port);
1115
1116 out_no_data:
1117
1118 /* Go to forward idle mode to shut the peripheral up (event 47). */
1119 parport_frob_control (port, PARPORT_CONTROL_INIT, PARPORT_CONTROL_INIT);
1120
1121 /* event 49: PError goes high */
1122 r = parport_wait_peripheral (port,
1123 PARPORT_STATUS_PAPEROUT,
1124 PARPORT_STATUS_PAPEROUT);
1125 if (r) {
1126 printk (KERN_DEBUG
1127 "%s: PE timeout FWDIDLE (%d) in ecp_read_block_pio\n",
1128 port->name, r);
1129 }
1130
1131 port->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
1132
1133 /* Finish up. */
1134 {
1135 int lost = get_fifo_residue (port);
1136 if (lost)
1137 /* Shouldn't happen with compliant peripherals. */
1138 printk (KERN_DEBUG "%s: DATA LOSS (%d bytes)!\n",
1139 port->name, lost);
1140 }
1141
1142 dump_parport_state ("fwd idle", port);
1143 return length - left;
1144 }
1145
1146 #endif /* IEEE 1284 support */
1147 #endif /* Allowed to use FIFO/DMA */
1148
1149
1150 /*
1151 * ******************************************
1152 * INITIALISATION AND MODULE STUFF BELOW HERE
1153 * ******************************************
1154 */
1155
1156 /* GCC is not inlining extern inline function later overwriten to non-inline,
1157 so we use outlined_ variants here. */
1158 struct parport_operations parport_pc_ops =
1159 {
1160 .write_data = parport_pc_write_data,
1161 .read_data = parport_pc_read_data,
1162
1163 .write_control = parport_pc_write_control,
1164 .read_control = parport_pc_read_control,
1165 .frob_control = parport_pc_frob_control,
1166
1167 .read_status = parport_pc_read_status,
1168
1169 .enable_irq = parport_pc_enable_irq,
1170 .disable_irq = parport_pc_disable_irq,
1171
1172 .data_forward = parport_pc_data_forward,
1173 .data_reverse = parport_pc_data_reverse,
1174
1175 .init_state = parport_pc_init_state,
1176 .save_state = parport_pc_save_state,
1177 .restore_state = parport_pc_restore_state,
1178
1179 .epp_write_data = parport_ieee1284_epp_write_data,
1180 .epp_read_data = parport_ieee1284_epp_read_data,
1181 .epp_write_addr = parport_ieee1284_epp_write_addr,
1182 .epp_read_addr = parport_ieee1284_epp_read_addr,
1183
1184 .ecp_write_data = parport_ieee1284_ecp_write_data,
1185 .ecp_read_data = parport_ieee1284_ecp_read_data,
1186 .ecp_write_addr = parport_ieee1284_ecp_write_addr,
1187
1188 .compat_write_data = parport_ieee1284_write_compat,
1189 .nibble_read_data = parport_ieee1284_read_nibble,
1190 .byte_read_data = parport_ieee1284_read_byte,
1191
1192 .owner = THIS_MODULE,
1193 };
1194
1195 #ifdef CONFIG_PARPORT_PC_SUPERIO
1196 /* Super-IO chipset detection, Winbond, SMSC */
1197 static int __devinit show_parconfig_smsc37c669(int io, int key)
1198 {
1199 int cr1,cr4,cra,cr23,cr26,cr27,i=0;
1200 static const char *modes[]={ "SPP and Bidirectional (PS/2)",
1201 "EPP and SPP",
1202 "ECP",
1203 "ECP and EPP" };
1204
1205 outb(key,io);
1206 outb(key,io);
1207 outb(1,io);
1208 cr1=inb(io+1);
1209 outb(4,io);
1210 cr4=inb(io+1);
1211 outb(0x0a,io);
1212 cra=inb(io+1);
1213 outb(0x23,io);
1214 cr23=inb(io+1);
1215 outb(0x26,io);
1216 cr26=inb(io+1);
1217 outb(0x27,io);
1218 cr27=inb(io+1);
1219 outb(0xaa,io);
1220
1221 if (verbose_probing) {
1222 printk (KERN_INFO "SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, "
1223 "A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n",
1224 cr1,cr4,cra,cr23,cr26,cr27);
1225
1226 /* The documentation calls DMA and IRQ-Lines by letters, so
1227 the board maker can/will wire them
1228 appropriately/randomly... G=reserved H=IDE-irq, */
1229 printk (KERN_INFO "SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, "
1230 "fifo threshold=%d\n", cr23*4,
1231 (cr27 &0x0f) ? 'A'-1+(cr27 &0x0f): '-',
1232 (cr26 &0x0f) ? 'A'-1+(cr26 &0x0f): '-', cra & 0x0f);
1233 printk(KERN_INFO "SMSC LPT Config: enabled=%s power=%s\n",
1234 (cr23*4 >=0x100) ?"yes":"no", (cr1 & 4) ? "yes" : "no");
1235 printk(KERN_INFO "SMSC LPT Config: Port mode=%s, EPP version =%s\n",
1236 (cr1 & 0x08 ) ? "Standard mode only (SPP)" : modes[cr4 & 0x03],
1237 (cr4 & 0x40) ? "1.7" : "1.9");
1238 }
1239
1240 /* Heuristics ! BIOS setup for this mainboard device limits
1241 the choices to standard settings, i.e. io-address and IRQ
1242 are related, however DMA can be 1 or 3, assume DMA_A=DMA1,
1243 DMA_C=DMA3 (this is true e.g. for TYAN 1564D Tomcat IV) */
1244 if(cr23*4 >=0x100) { /* if active */
1245 while((superios[i].io!= 0) && (i<NR_SUPERIOS))
1246 i++;
1247 if(i==NR_SUPERIOS)
1248 printk(KERN_INFO "Super-IO: too many chips!\n");
1249 else {
1250 int d;
1251 switch (cr23*4) {
1252 case 0x3bc:
1253 superios[i].io = 0x3bc;
1254 superios[i].irq = 7;
1255 break;
1256 case 0x378:
1257 superios[i].io = 0x378;
1258 superios[i].irq = 7;
1259 break;
1260 case 0x278:
1261 superios[i].io = 0x278;
1262 superios[i].irq = 5;
1263 }
1264 if (io != superios[i].io) {
1265 /* how many bytes? */
1266 if (!request_region(superios[i].io, 3, "smsc parport")) {
1267 superios[i].io = 0;
1268 return 0;
1269 }
1270 }
1271 d=(cr26 &0x0f);
1272 if((d==1) || (d==3))
1273 superios[i].dma= d;
1274 else
1275 superios[i].dma= PARPORT_DMA_NONE;
1276 return 1;
1277 }
1278 }
1279 return 0;
1280 }
1281
1282
1283 static int __devinit show_parconfig_winbond(int io, int key)
1284 {
1285 int cr30,cr60,cr61,cr70,cr74,crf0,i=0;
1286 static const char *modes[] = {
1287 "Standard (SPP) and Bidirectional(PS/2)", /* 0 */
1288 "EPP-1.9 and SPP",
1289 "ECP",
1290 "ECP and EPP-1.9",
1291 "Standard (SPP)",
1292 "EPP-1.7 and SPP", /* 5 */
1293 "undefined!",
1294 "ECP and EPP-1.7" };
1295 static char *irqtypes[] = { "pulsed low, high-Z", "follows nACK" };
1296
1297 /* The registers are called compatible-PnP because the
1298 register layout is modelled after ISA-PnP, the access
1299 method is just another ... */
1300 outb(key,io);
1301 outb(key,io);
1302 outb(0x07,io); /* Register 7: Select Logical Device */
1303 outb(0x01,io+1); /* LD1 is Parallel Port */
1304 outb(0x30,io);
1305 cr30=inb(io+1);
1306 outb(0x60,io);
1307 cr60=inb(io+1);
1308 outb(0x61,io);
1309 cr61=inb(io+1);
1310 outb(0x70,io);
1311 cr70=inb(io+1);
1312 outb(0x74,io);
1313 cr74=inb(io+1);
1314 outb(0xf0,io);
1315 crf0=inb(io+1);
1316 outb(0xaa,io);
1317
1318 if (verbose_probing) {
1319 printk(KERN_INFO "Winbond LPT Config: cr_30=%02x 60,61=%02x%02x "
1320 "70=%02x 74=%02x, f0=%02x\n", cr30,cr60,cr61,cr70,cr74,crf0);
1321 printk(KERN_INFO "Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ",
1322 (cr30 & 0x01) ? "yes":"no", cr60,cr61,cr70&0x0f );
1323 if ((cr74 & 0x07) > 3)
1324 printk("dma=none\n");
1325 else
1326 printk("dma=%d\n",cr74 & 0x07);
1327 printk(KERN_INFO "Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n",
1328 irqtypes[crf0>>7], (crf0>>3)&0x0f);
1329 printk(KERN_INFO "Winbond LPT Config: Port mode=%s\n", modes[crf0 & 0x07]);
1330 }
1331
1332 if(cr30 & 0x01) { /* the settings can be interrogated later ... */
1333 while((superios[i].io!= 0) && (i<NR_SUPERIOS))
1334 i++;
1335 if(i==NR_SUPERIOS)
1336 printk(KERN_INFO "Super-IO: too many chips!\n");
1337 else {
1338 superios[i].io = (cr60<<8)|cr61;
1339 if (io != superios[i].io) {
1340 /* how many bytes? */
1341 if (!request_region(superios[i].io, 3, "winbond parport")) {
1342 superios[i].io = 0;
1343 return 0;
1344 }
1345 }
1346 superios[i].irq = cr70&0x0f;
1347 superios[i].dma = (((cr74 & 0x07) > 3) ?
1348 PARPORT_DMA_NONE : (cr74 & 0x07));
1349 return 1;
1350 }
1351 }
1352 return 0;
1353 }
1354
1355 static int __devinit decode_winbond(int efer, int key, int devid, int devrev, int oldid)
1356 {
1357 const char *type = "unknown";
1358 int id,progif=2;
1359
1360 if (devid == devrev)
1361 /* simple heuristics, we happened to read some
1362 non-winbond register */
1363 return 0;
1364
1365 id=(devid<<8) | devrev;
1366
1367 /* Values are from public data sheets pdf files, I can just
1368 confirm 83977TF is correct :-) */
1369 if (id == 0x9771) type="83977F/AF";
1370 else if (id == 0x9773) type="83977TF / SMSC 97w33x/97w34x";
1371 else if (id == 0x9774) type="83977ATF";
1372 else if ((id & ~0x0f) == 0x5270) type="83977CTF / SMSC 97w36x";
1373 else if ((id & ~0x0f) == 0x52f0) type="83977EF / SMSC 97w35x";
1374 else if ((id & ~0x0f) == 0x5210) type="83627";
1375 else if ((id & ~0x0f) == 0x6010) type="83697HF";
1376 else if ((oldid &0x0f ) == 0x0a) { type="83877F"; progif=1;}
1377 else if ((oldid &0x0f ) == 0x0b) { type="83877AF"; progif=1;}
1378 else if ((oldid &0x0f ) == 0x0c) { type="83877TF"; progif=1;}
1379 else if ((oldid &0x0f ) == 0x0d) { type="83877ATF"; progif=1;}
1380 else progif=0;
1381
1382 if (verbose_probing)
1383 printk(KERN_INFO "Winbond chip at EFER=0x%x key=0x%02x "
1384 "devid=%02x devrev=%02x oldid=%02x type=%s\n",
1385 efer, key, devid, devrev, oldid, type);
1386
1387 if (progif == 2)
1388 return show_parconfig_winbond(efer,key);
1389 return 0;
1390 }
1391
1392 static int __devinit decode_smsc(int efer, int key, int devid, int devrev)
1393 {
1394 const char *type = "unknown";
1395 int (*func)(int io, int key);
1396 int id;
1397
1398 if (devid == devrev)
1399 /* simple heuristics, we happened to read some
1400 non-smsc register */
1401 return 0;
1402
1403 func=NULL;
1404 id=(devid<<8) | devrev;
1405
1406 if (id==0x0302) {type="37c669"; func=show_parconfig_smsc37c669;}
1407 else if (id==0x6582) type="37c665IR";
1408 else if (devid==0x65) type="37c665GT";
1409 else if (devid==0x66) type="37c666GT";
1410
1411 if (verbose_probing)
1412 printk(KERN_INFO "SMSC chip at EFER=0x%x "
1413 "key=0x%02x devid=%02x devrev=%02x type=%s\n",
1414 efer, key, devid, devrev, type);
1415
1416 if (func)
1417 return func(efer,key);
1418 return 0;
1419 }
1420
1421
1422 static void __devinit winbond_check(int io, int key)
1423 {
1424 int devid,devrev,oldid,x_devid,x_devrev,x_oldid;
1425
1426 if (!request_region(io, 3, __FUNCTION__))
1427 return;
1428
1429 /* First probe without key */
1430 outb(0x20,io);
1431 x_devid=inb(io+1);
1432 outb(0x21,io);
1433 x_devrev=inb(io+1);
1434 outb(0x09,io);
1435 x_oldid=inb(io+1);
1436
1437 outb(key,io);
1438 outb(key,io); /* Write Magic Sequence to EFER, extended
1439 funtion enable register */
1440 outb(0x20,io); /* Write EFIR, extended function index register */
1441 devid=inb(io+1); /* Read EFDR, extended function data register */
1442 outb(0x21,io);
1443 devrev=inb(io+1);
1444 outb(0x09,io);
1445 oldid=inb(io+1);
1446 outb(0xaa,io); /* Magic Seal */
1447
1448 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid))
1449 goto out; /* protection against false positives */
1450
1451 if (decode_winbond(io,key,devid,devrev,oldid));
1452 return;
1453 out:
1454 release_region(io, 3);
1455 }
1456
1457 static void __devinit winbond_check2(int io,int key)
1458 {
1459 int devid,devrev,oldid,x_devid,x_devrev,x_oldid;
1460
1461 if (!request_region(io, 3, __FUNCTION__))
1462 return;
1463
1464 /* First probe without the key */
1465 outb(0x20,io+2);
1466 x_devid=inb(io+2);
1467 outb(0x21,io+1);
1468 x_devrev=inb(io+2);
1469 outb(0x09,io+1);
1470 x_oldid=inb(io+2);
1471
1472 outb(key,io); /* Write Magic Byte to EFER, extended
1473 funtion enable register */
1474 outb(0x20,io+2); /* Write EFIR, extended function index register */
1475 devid=inb(io+2); /* Read EFDR, extended function data register */
1476 outb(0x21,io+1);
1477 devrev=inb(io+2);
1478 outb(0x09,io+1);
1479 oldid=inb(io+2);
1480 outb(0xaa,io); /* Magic Seal */
1481
1482 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid))
1483 goto out; /* protection against false positives */
1484
1485 if (decode_winbond(io,key,devid,devrev,oldid))
1486 return;
1487 out:
1488 release_region(io, 3);
1489 }
1490
1491 static void __devinit smsc_check(int io, int key)
1492 {
1493 int id,rev,oldid,oldrev,x_id,x_rev,x_oldid,x_oldrev;
1494
1495 if (!request_region(io, 3, __FUNCTION__))
1496 return;
1497
1498 /* First probe without the key */
1499 outb(0x0d,io);
1500 x_oldid=inb(io+1);
1501 outb(0x0e,io);
1502 x_oldrev=inb(io+1);
1503 outb(0x20,io);
1504 x_id=inb(io+1);
1505 outb(0x21,io);
1506 x_rev=inb(io+1);
1507
1508 outb(key,io);
1509 outb(key,io); /* Write Magic Sequence to EFER, extended
1510 funtion enable register */
1511 outb(0x0d,io); /* Write EFIR, extended function index register */
1512 oldid=inb(io+1); /* Read EFDR, extended function data register */
1513 outb(0x0e,io);
1514 oldrev=inb(io+1);
1515 outb(0x20,io);
1516 id=inb(io+1);
1517 outb(0x21,io);
1518 rev=inb(io+1);
1519 outb(0xaa,io); /* Magic Seal */
1520
1521 if ((x_id == id) && (x_oldrev == oldrev) &&
1522 (x_oldid == oldid) && (x_rev == rev))
1523 goto out; /* protection against false positives */
1524
1525 if (decode_smsc(io,key,oldid,oldrev))
1526 return;
1527 out:
1528 release_region(io, 3);
1529 }
1530
1531
1532 static void __devinit detect_and_report_winbond (void)
1533 {
1534 if (verbose_probing)
1535 printk(KERN_DEBUG "Winbond Super-IO detection, now testing ports 3F0,370,250,4E,2E ...\n");
1536 winbond_check(0x3f0,0x87);
1537 winbond_check(0x370,0x87);
1538 winbond_check(0x2e ,0x87);
1539 winbond_check(0x4e ,0x87);
1540 winbond_check(0x3f0,0x86);
1541 winbond_check2(0x250,0x88);
1542 winbond_check2(0x250,0x89);
1543 }
1544
1545 static void __devinit detect_and_report_smsc (void)
1546 {
1547 if (verbose_probing)
1548 printk(KERN_DEBUG "SMSC Super-IO detection, now testing Ports 2F0, 370 ...\n");
1549 smsc_check(0x3f0,0x55);
1550 smsc_check(0x370,0x55);
1551 smsc_check(0x3f0,0x44);
1552 smsc_check(0x370,0x44);
1553 }
1554 #endif /* CONFIG_PARPORT_PC_SUPERIO */
1555
1556 static int __devinit get_superio_dma (struct parport *p)
1557 {
1558 int i=0;
1559 while( (superios[i].io != p->base) && (i<NR_SUPERIOS))
1560 i++;
1561 if (i!=NR_SUPERIOS)
1562 return superios[i].dma;
1563 return PARPORT_DMA_NONE;
1564 }
1565
1566 static int __devinit get_superio_irq (struct parport *p)
1567 {
1568 int i=0;
1569 while( (superios[i].io != p->base) && (i<NR_SUPERIOS))
1570 i++;
1571 if (i!=NR_SUPERIOS)
1572 return superios[i].irq;
1573 return PARPORT_IRQ_NONE;
1574 }
1575
1576
1577 /* --- Mode detection ------------------------------------- */
1578
1579 /*
1580 * Checks for port existence, all ports support SPP MODE
1581 * Returns:
1582 * 0 : No parallel port at this address
1583 * PARPORT_MODE_PCSPP : SPP port detected
1584 * (if the user specified an ioport himself,
1585 * this shall always be the case!)
1586 *
1587 */
1588 static int __devinit parport_SPP_supported(struct parport *pb)
1589 {
1590 unsigned char r, w;
1591
1592 /*
1593 * first clear an eventually pending EPP timeout
1594 * I (sailer@ife.ee.ethz.ch) have an SMSC chipset
1595 * that does not even respond to SPP cycles if an EPP
1596 * timeout is pending
1597 */
1598 clear_epp_timeout(pb);
1599
1600 /* Do a simple read-write test to make sure the port exists. */
1601 w = 0xc;
1602 outb (w, CONTROL (pb));
1603
1604 /* Is there a control register that we can read from? Some
1605 * ports don't allow reads, so read_control just returns a
1606 * software copy. Some ports _do_ allow reads, so bypass the
1607 * software copy here. In addition, some bits aren't
1608 * writable. */
1609 r = inb (CONTROL (pb));
1610 if ((r & 0xf) == w) {
1611 w = 0xe;
1612 outb (w, CONTROL (pb));
1613 r = inb (CONTROL (pb));
1614 outb (0xc, CONTROL (pb));
1615 if ((r & 0xf) == w)
1616 return PARPORT_MODE_PCSPP;
1617 }
1618
1619 if (user_specified)
1620 /* That didn't work, but the user thinks there's a
1621 * port here. */
1622 printk (KERN_INFO "parport 0x%lx (WARNING): CTR: "
1623 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
1624
1625 /* Try the data register. The data lines aren't tri-stated at
1626 * this stage, so we expect back what we wrote. */
1627 w = 0xaa;
1628 parport_pc_write_data (pb, w);
1629 r = parport_pc_read_data (pb);
1630 if (r == w) {
1631 w = 0x55;
1632 parport_pc_write_data (pb, w);
1633 r = parport_pc_read_data (pb);
1634 if (r == w)
1635 return PARPORT_MODE_PCSPP;
1636 }
1637
1638 if (user_specified) {
1639 /* Didn't work, but the user is convinced this is the
1640 * place. */
1641 printk (KERN_INFO "parport 0x%lx (WARNING): DATA: "
1642 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
1643 printk (KERN_INFO "parport 0x%lx: You gave this address, "
1644 "but there is probably no parallel port there!\n",
1645 pb->base);
1646 }
1647
1648 /* It's possible that we can't read the control register or
1649 * the data register. In that case just believe the user. */
1650 if (user_specified)
1651 return PARPORT_MODE_PCSPP;
1652
1653 return 0;
1654 }
1655
1656 /* Check for ECR
1657 *
1658 * Old style XT ports alias io ports every 0x400, hence accessing ECR
1659 * on these cards actually accesses the CTR.
1660 *
1661 * Modern cards don't do this but reading from ECR will return 0xff
1662 * regardless of what is written here if the card does NOT support
1663 * ECP.
1664 *
1665 * We first check to see if ECR is the same as CTR. If not, the low
1666 * two bits of ECR aren't writable, so we check by writing ECR and
1667 * reading it back to see if it's what we expect.
1668 */
1669 static int __devinit parport_ECR_present(struct parport *pb)
1670 {
1671 struct parport_pc_private *priv = pb->private_data;
1672 unsigned char r = 0xc;
1673
1674 outb (r, CONTROL (pb));
1675 if ((inb (ECONTROL (pb)) & 0x3) == (r & 0x3)) {
1676 outb (r ^ 0x2, CONTROL (pb)); /* Toggle bit 1 */
1677
1678 r = inb (CONTROL (pb));
1679 if ((inb (ECONTROL (pb)) & 0x2) == (r & 0x2))
1680 goto no_reg; /* Sure that no ECR register exists */
1681 }
1682
1683 if ((inb (ECONTROL (pb)) & 0x3 ) != 0x1)
1684 goto no_reg;
1685
1686 ECR_WRITE (pb, 0x34);
1687 if (inb (ECONTROL (pb)) != 0x35)
1688 goto no_reg;
1689
1690 priv->ecr = 1;
1691 outb (0xc, CONTROL (pb));
1692
1693 /* Go to mode 000 */
1694 frob_set_mode (pb, ECR_SPP);
1695
1696 return 1;
1697
1698 no_reg:
1699 outb (0xc, CONTROL (pb));
1700 return 0;
1701 }
1702
1703 #ifdef CONFIG_PARPORT_1284
1704 /* Detect PS/2 support.
1705 *
1706 * Bit 5 (0x20) sets the PS/2 data direction; setting this high
1707 * allows us to read data from the data lines. In theory we would get back
1708 * 0xff but any peripheral attached to the port may drag some or all of the
1709 * lines down to zero. So if we get back anything that isn't the contents
1710 * of the data register we deem PS/2 support to be present.
1711 *
1712 * Some SPP ports have "half PS/2" ability - you can't turn off the line
1713 * drivers, but an external peripheral with sufficiently beefy drivers of
1714 * its own can overpower them and assert its own levels onto the bus, from
1715 * where they can then be read back as normal. Ports with this property
1716 * and the right type of device attached are likely to fail the SPP test,
1717 * (as they will appear to have stuck bits) and so the fact that they might
1718 * be misdetected here is rather academic.
1719 */
1720
1721 static int __devinit parport_PS2_supported(struct parport *pb)
1722 {
1723 int ok = 0;
1724
1725 clear_epp_timeout(pb);
1726
1727 /* try to tri-state the buffer */
1728 parport_pc_data_reverse (pb);
1729
1730 parport_pc_write_data(pb, 0x55);
1731 if (parport_pc_read_data(pb) != 0x55) ok++;
1732
1733 parport_pc_write_data(pb, 0xaa);
1734 if (parport_pc_read_data(pb) != 0xaa) ok++;
1735
1736 /* cancel input mode */
1737 parport_pc_data_forward (pb);
1738
1739 if (ok) {
1740 pb->modes |= PARPORT_MODE_TRISTATE;
1741 } else {
1742 struct parport_pc_private *priv = pb->private_data;
1743 priv->ctr_writable &= ~0x20;
1744 }
1745
1746 return ok;
1747 }
1748
1749 #ifdef CONFIG_PARPORT_PC_FIFO
1750 static int __devinit parport_ECP_supported(struct parport *pb)
1751 {
1752 int i;
1753 int config, configb;
1754 int pword;
1755 struct parport_pc_private *priv = pb->private_data;
1756 /* Translate ECP intrLine to ISA irq value */
1757 static const int intrline[]= { 0, 7, 9, 10, 11, 14, 15, 5 };
1758
1759 /* If there is no ECR, we have no hope of supporting ECP. */
1760 if (!priv->ecr)
1761 return 0;
1762
1763 /* Find out FIFO depth */
1764 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */
1765 ECR_WRITE (pb, ECR_TST << 5); /* TEST FIFO */
1766 for (i=0; i < 1024 && !(inb (ECONTROL (pb)) & 0x02); i++)
1767 outb (0xaa, FIFO (pb));
1768
1769 /*
1770 * Using LGS chipset it uses ECR register, but
1771 * it doesn't support ECP or FIFO MODE
1772 */
1773 if (i == 1024) {
1774 ECR_WRITE (pb, ECR_SPP << 5);
1775 return 0;
1776 }
1777
1778 priv->fifo_depth = i;
1779 if (verbose_probing)
1780 printk (KERN_DEBUG "0x%lx: FIFO is %d bytes\n", pb->base, i);
1781
1782 /* Find out writeIntrThreshold */
1783 frob_econtrol (pb, 1<<2, 1<<2);
1784 frob_econtrol (pb, 1<<2, 0);
1785 for (i = 1; i <= priv->fifo_depth; i++) {
1786 inb (FIFO (pb));
1787 udelay (50);
1788 if (inb (ECONTROL (pb)) & (1<<2))
1789 break;
1790 }
1791
1792 if (i <= priv->fifo_depth) {
1793 if (verbose_probing)
1794 printk (KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n",
1795 pb->base, i);
1796 } else
1797 /* Number of bytes we know we can write if we get an
1798 interrupt. */
1799 i = 0;
1800
1801 priv->writeIntrThreshold = i;
1802
1803 /* Find out readIntrThreshold */
1804 frob_set_mode (pb, ECR_PS2); /* Reset FIFO and enable PS2 */
1805 parport_pc_data_reverse (pb); /* Must be in PS2 mode */
1806 frob_set_mode (pb, ECR_TST); /* Test FIFO */
1807 frob_econtrol (pb, 1<<2, 1<<2);
1808 frob_econtrol (pb, 1<<2, 0);
1809 for (i = 1; i <= priv->fifo_depth; i++) {
1810 outb (0xaa, FIFO (pb));
1811 if (inb (ECONTROL (pb)) & (1<<2))
1812 break;
1813 }
1814
1815 if (i <= priv->fifo_depth) {
1816 if (verbose_probing)
1817 printk (KERN_INFO "0x%lx: readIntrThreshold is %d\n",
1818 pb->base, i);
1819 } else
1820 /* Number of bytes we can read if we get an interrupt. */
1821 i = 0;
1822
1823 priv->readIntrThreshold = i;
1824
1825 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */
1826 ECR_WRITE (pb, 0xf4); /* Configuration mode */
1827 config = inb (CONFIGA (pb));
1828 pword = (config >> 4) & 0x7;
1829 switch (pword) {
1830 case 0:
1831 pword = 2;
1832 printk (KERN_WARNING "0x%lx: Unsupported pword size!\n",
1833 pb->base);
1834 break;
1835 case 2:
1836 pword = 4;
1837 printk (KERN_WARNING "0x%lx: Unsupported pword size!\n",
1838 pb->base);
1839 break;
1840 default:
1841 printk (KERN_WARNING "0x%lx: Unknown implementation ID\n",
1842 pb->base);
1843 /* Assume 1 */
1844 case 1:
1845 pword = 1;
1846 }
1847 priv->pword = pword;
1848
1849 if (verbose_probing) {
1850 printk (KERN_DEBUG "0x%lx: PWord is %d bits\n", pb->base, 8 * pword);
1851
1852 printk (KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n", pb->base,
1853 config & 0x80 ? "Level" : "Pulses");
1854
1855 configb = inb (CONFIGB (pb));
1856 printk (KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n",
1857 pb->base, config, configb);
1858 printk (KERN_DEBUG "0x%lx: ECP settings irq=", pb->base);
1859 if ((configb >>3) & 0x07)
1860 printk("%d",intrline[(configb >>3) & 0x07]);
1861 else
1862 printk("<none or set by other means>");
1863 printk (" dma=");
1864 if( (configb & 0x03 ) == 0x00)
1865 printk("<none or set by other means>\n");
1866 else
1867 printk("%d\n",configb & 0x07);
1868 }
1869
1870 /* Go back to mode 000 */
1871 frob_set_mode (pb, ECR_SPP);
1872
1873 return 1;
1874 }
1875 #endif
1876
1877 static int __devinit parport_ECPPS2_supported(struct parport *pb)
1878 {
1879 const struct parport_pc_private *priv = pb->private_data;
1880 int result;
1881 unsigned char oecr;
1882
1883 if (!priv->ecr)
1884 return 0;
1885
1886 oecr = inb (ECONTROL (pb));
1887 ECR_WRITE (pb, ECR_PS2 << 5);
1888 result = parport_PS2_supported(pb);
1889 ECR_WRITE (pb, oecr);
1890 return result;
1891 }
1892
1893 /* EPP mode detection */
1894
1895 static int __devinit parport_EPP_supported(struct parport *pb)
1896 {
1897 const struct parport_pc_private *priv = pb->private_data;
1898
1899 /*
1900 * Theory:
1901 * Bit 0 of STR is the EPP timeout bit, this bit is 0
1902 * when EPP is possible and is set high when an EPP timeout
1903 * occurs (EPP uses the HALT line to stop the CPU while it does
1904 * the byte transfer, an EPP timeout occurs if the attached
1905 * device fails to respond after 10 micro seconds).
1906 *
1907 * This bit is cleared by either reading it (National Semi)
1908 * or writing a 1 to the bit (SMC, UMC, WinBond), others ???
1909 * This bit is always high in non EPP modes.
1910 */
1911
1912 /* If EPP timeout bit clear then EPP available */
1913 if (!clear_epp_timeout(pb)) {
1914 return 0; /* No way to clear timeout */
1915 }
1916
1917 /* Check for Intel bug. */
1918 if (priv->ecr) {
1919 unsigned char i;
1920 for (i = 0x00; i < 0x80; i += 0x20) {
1921 ECR_WRITE (pb, i);
1922 if (clear_epp_timeout (pb)) {
1923 /* Phony EPP in ECP. */
1924 return 0;
1925 }
1926 }
1927 }
1928
1929 pb->modes |= PARPORT_MODE_EPP;
1930
1931 /* Set up access functions to use EPP hardware. */
1932 pb->ops->epp_read_data = parport_pc_epp_read_data;
1933 pb->ops->epp_write_data = parport_pc_epp_write_data;
1934 pb->ops->epp_read_addr = parport_pc_epp_read_addr;
1935 pb->ops->epp_write_addr = parport_pc_epp_write_addr;
1936
1937 return 1;
1938 }
1939
1940 static int __devinit parport_ECPEPP_supported(struct parport *pb)
1941 {
1942 struct parport_pc_private *priv = pb->private_data;
1943 int result;
1944 unsigned char oecr;
1945
1946 if (!priv->ecr) {
1947 return 0;
1948 }
1949
1950 oecr = inb (ECONTROL (pb));
1951 /* Search for SMC style EPP+ECP mode */
1952 ECR_WRITE (pb, 0x80);
1953 outb (0x04, CONTROL (pb));
1954 result = parport_EPP_supported(pb);
1955
1956 ECR_WRITE (pb, oecr);
1957
1958 if (result) {
1959 /* Set up access functions to use ECP+EPP hardware. */
1960 pb->ops->epp_read_data = parport_pc_ecpepp_read_data;
1961 pb->ops->epp_write_data = parport_pc_ecpepp_write_data;
1962 pb->ops->epp_read_addr = parport_pc_ecpepp_read_addr;
1963 pb->ops->epp_write_addr = parport_pc_ecpepp_write_addr;
1964 }
1965
1966 return result;
1967 }
1968
1969 #else /* No IEEE 1284 support */
1970
1971 /* Don't bother probing for modes we know we won't use. */
1972 static int __devinit parport_PS2_supported(struct parport *pb) { return 0; }
1973 #ifdef CONFIG_PARPORT_PC_FIFO
1974 static int __devinit parport_ECP_supported(struct parport *pb) { return 0; }
1975 #endif
1976 static int __devinit parport_EPP_supported(struct parport *pb) { return 0; }
1977 static int __devinit parport_ECPEPP_supported(struct parport *pb){return 0;}
1978 static int __devinit parport_ECPPS2_supported(struct parport *pb){return 0;}
1979
1980 #endif /* No IEEE 1284 support */
1981
1982 /* --- IRQ detection -------------------------------------- */
1983
1984 /* Only if supports ECP mode */
1985 static int __devinit programmable_irq_support(struct parport *pb)
1986 {
1987 int irq, intrLine;
1988 unsigned char oecr = inb (ECONTROL (pb));
1989 static const int lookup[8] = {
1990 PARPORT_IRQ_NONE, 7, 9, 10, 11, 14, 15, 5
1991 };
1992
1993 ECR_WRITE (pb, ECR_CNF << 5); /* Configuration MODE */
1994
1995 intrLine = (inb (CONFIGB (pb)) >> 3) & 0x07;
1996 irq = lookup[intrLine];
1997
1998 ECR_WRITE (pb, oecr);
1999 return irq;
2000 }
2001
2002 static int __devinit irq_probe_ECP(struct parport *pb)
2003 {
2004 int i;
2005 unsigned long irqs;
2006
2007 irqs = probe_irq_on();
2008
2009 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */
2010 ECR_WRITE (pb, (ECR_TST << 5) | 0x04);
2011 ECR_WRITE (pb, ECR_TST << 5);
2012
2013 /* If Full FIFO sure that writeIntrThreshold is generated */
2014 for (i=0; i < 1024 && !(inb (ECONTROL (pb)) & 0x02) ; i++)
2015 outb (0xaa, FIFO (pb));
2016
2017 pb->irq = probe_irq_off(irqs);
2018 ECR_WRITE (pb, ECR_SPP << 5);
2019
2020 if (pb->irq <= 0)
2021 pb->irq = PARPORT_IRQ_NONE;
2022
2023 return pb->irq;
2024 }
2025
2026 /*
2027 * This detection seems that only works in National Semiconductors
2028 * This doesn't work in SMC, LGS, and Winbond
2029 */
2030 static int __devinit irq_probe_EPP(struct parport *pb)
2031 {
2032 #ifndef ADVANCED_DETECT
2033 return PARPORT_IRQ_NONE;
2034 #else
2035 int irqs;
2036 unsigned char oecr;
2037
2038 if (pb->modes & PARPORT_MODE_PCECR)
2039 oecr = inb (ECONTROL (pb));
2040
2041 irqs = probe_irq_on();
2042
2043 if (pb->modes & PARPORT_MODE_PCECR)
2044 frob_econtrol (pb, 0x10, 0x10);
2045
2046 clear_epp_timeout(pb);
2047 parport_pc_frob_control (pb, 0x20, 0x20);
2048 parport_pc_frob_control (pb, 0x10, 0x10);
2049 clear_epp_timeout(pb);
2050
2051 /* Device isn't expecting an EPP read
2052 * and generates an IRQ.
2053 */
2054 parport_pc_read_epp(pb);
2055 udelay(20);
2056
2057 pb->irq = probe_irq_off (irqs);
2058 if (pb->modes & PARPORT_MODE_PCECR)
2059 ECR_WRITE (pb, oecr);
2060 parport_pc_write_control(pb, 0xc);
2061
2062 if (pb->irq <= 0)
2063 pb->irq = PARPORT_IRQ_NONE;
2064
2065 return pb->irq;
2066 #endif /* Advanced detection */
2067 }
2068
2069 static int __devinit irq_probe_SPP(struct parport *pb)
2070 {
2071 /* Don't even try to do this. */
2072 return PARPORT_IRQ_NONE;
2073 }
2074
2075 /* We will attempt to share interrupt requests since other devices
2076 * such as sound cards and network cards seem to like using the
2077 * printer IRQs.
2078 *
2079 * When ECP is available we can autoprobe for IRQs.
2080 * NOTE: If we can autoprobe it, we can register the IRQ.
2081 */
2082 static int __devinit parport_irq_probe(struct parport *pb)
2083 {
2084 struct parport_pc_private *priv = pb->private_data;
2085
2086 if (priv->ecr) {
2087 pb->irq = programmable_irq_support(pb);
2088
2089 if (pb->irq == PARPORT_IRQ_NONE)
2090 pb->irq = irq_probe_ECP(pb);
2091 }
2092
2093 if ((pb->irq == PARPORT_IRQ_NONE) && priv->ecr &&
2094 (pb->modes & PARPORT_MODE_EPP))
2095 pb->irq = irq_probe_EPP(pb);
2096
2097 clear_epp_timeout(pb);
2098
2099 if (pb->irq == PARPORT_IRQ_NONE && (pb->modes & PARPORT_MODE_EPP))
2100 pb->irq = irq_probe_EPP(pb);
2101
2102 clear_epp_timeout(pb);
2103
2104 if (pb->irq == PARPORT_IRQ_NONE)
2105 pb->irq = irq_probe_SPP(pb);
2106
2107 if (pb->irq == PARPORT_IRQ_NONE)
2108 pb->irq = get_superio_irq(pb);
2109
2110 return pb->irq;
2111 }
2112
2113 /* --- DMA detection -------------------------------------- */
2114
2115 /* Only if chipset conforms to ECP ISA Interface Standard */
2116 static int __devinit programmable_dma_support (struct parport *p)
2117 {
2118 unsigned char oecr = inb (ECONTROL (p));
2119 int dma;
2120
2121 frob_set_mode (p, ECR_CNF);
2122
2123 dma = inb (CONFIGB(p)) & 0x07;
2124 /* 000: Indicates jumpered 8-bit DMA if read-only.
2125 100: Indicates jumpered 16-bit DMA if read-only. */
2126 if ((dma & 0x03) == 0)
2127 dma = PARPORT_DMA_NONE;
2128
2129 ECR_WRITE (p, oecr);
2130 return dma;
2131 }
2132
2133 static int __devinit parport_dma_probe (struct parport *p)
2134 {
2135 const struct parport_pc_private *priv = p->private_data;
2136 if (priv->ecr)
2137 p->dma = programmable_dma_support(p); /* ask ECP chipset first */
2138 if (p->dma == PARPORT_DMA_NONE) {
2139 /* ask known Super-IO chips proper, although these
2140 claim ECP compatible, some don't report their DMA
2141 conforming to ECP standards */
2142 p->dma = get_superio_dma(p);
2143 }
2144
2145 return p->dma;
2146 }
2147
2148 /* --- Initialisation code -------------------------------- */
2149
2150 static LIST_HEAD(ports_list);
2151 static spinlock_t ports_lock = SPIN_LOCK_UNLOCKED;
2152
2153 struct parport *parport_pc_probe_port (unsigned long int base,
2154 unsigned long int base_hi,
2155 int irq, int dma,
2156 struct pci_dev *dev)
2157 {
2158 struct parport_pc_private *priv;
2159 struct parport_operations *ops;
2160 struct parport *p;
2161 int probedirq = PARPORT_IRQ_NONE;
2162 struct resource *base_res;
2163 struct resource *ECR_res = NULL;
2164 struct resource *EPP_res = NULL;
2165
2166 ops = kmalloc(sizeof (struct parport_operations), GFP_KERNEL);
2167 if (!ops)
2168 goto out1;
2169
2170 priv = kmalloc (sizeof (struct parport_pc_private), GFP_KERNEL);
2171 if (!priv)
2172 goto out2;
2173
2174 /* a misnomer, actually - it's allocate and reserve parport number */
2175 p = parport_register_port(base, irq, dma, ops);
2176 if (!p)
2177 goto out3;
2178
2179 base_res = request_region(base, 3, p->name);
2180 if (!base_res)
2181 goto out4;
2182
2183 memcpy(ops, &parport_pc_ops, sizeof (struct parport_operations));
2184 priv->ctr = 0xc;
2185 priv->ctr_writable = ~0x10;
2186 priv->ecr = 0;
2187 priv->fifo_depth = 0;
2188 priv->dma_buf = NULL;
2189 priv->dma_handle = 0;
2190 priv->dev = dev;
2191 INIT_LIST_HEAD(&priv->list);
2192 priv->port = p;
2193 p->base_hi = base_hi;
2194 p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
2195 p->private_data = priv;
2196
2197 if (base_hi) {
2198 ECR_res = request_region(base_hi, 3, p->name);
2199 if (ECR_res)
2200 parport_ECR_present(p);
2201 }
2202
2203 if (base != 0x3bc) {
2204 EPP_res = request_region(base+0x3, 5, p->name);
2205 if (EPP_res)
2206 if (!parport_EPP_supported(p))
2207 parport_ECPEPP_supported(p);
2208 }
2209 if (!parport_SPP_supported (p))
2210 /* No port. */
2211 goto out5;
2212 if (priv->ecr)
2213 parport_ECPPS2_supported(p);
2214 else
2215 parport_PS2_supported(p);
2216
2217 p->size = (p->modes & PARPORT_MODE_EPP)?8:3;
2218
2219 printk(KERN_INFO "%s: PC-style at 0x%lx", p->name, p->base);
2220 if (p->base_hi && priv->ecr)
2221 printk(" (0x%lx)", p->base_hi);
2222 if (p->irq == PARPORT_IRQ_AUTO) {
2223 p->irq = PARPORT_IRQ_NONE;
2224 parport_irq_probe(p);
2225 } else if (p->irq == PARPORT_IRQ_PROBEONLY) {
2226 p->irq = PARPORT_IRQ_NONE;
2227 parport_irq_probe(p);
2228 probedirq = p->irq;
2229 p->irq = PARPORT_IRQ_NONE;
2230 }
2231 if (p->irq != PARPORT_IRQ_NONE) {
2232 printk(", irq %d", p->irq);
2233 priv->ctr_writable |= 0x10;
2234
2235 if (p->dma == PARPORT_DMA_AUTO) {
2236 p->dma = PARPORT_DMA_NONE;
2237 parport_dma_probe(p);
2238 }
2239 }
2240 if (p->dma == PARPORT_DMA_AUTO) /* To use DMA, giving the irq
2241 is mandatory (see above) */
2242 p->dma = PARPORT_DMA_NONE;
2243
2244 #ifdef CONFIG_PARPORT_PC_FIFO
2245 if (parport_ECP_supported(p) &&
2246 p->dma != PARPORT_DMA_NOFIFO &&
2247 priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) {
2248 p->modes |= PARPORT_MODE_ECP | PARPORT_MODE_COMPAT;
2249 p->ops->compat_write_data = parport_pc_compat_write_block_pio;
2250 #ifdef CONFIG_PARPORT_1284
2251 p->ops->ecp_write_data = parport_pc_ecp_write_block_pio;
2252 /* currently broken, but working on it.. (FB) */
2253 /* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */
2254 #endif /* IEEE 1284 support */
2255 if (p->dma != PARPORT_DMA_NONE) {
2256 printk(", dma %d", p->dma);
2257 p->modes |= PARPORT_MODE_DMA;
2258 }
2259 else printk(", using FIFO");
2260 }
2261 else
2262 /* We can't use the DMA channel after all. */
2263 p->dma = PARPORT_DMA_NONE;
2264 #endif /* Allowed to use FIFO/DMA */
2265
2266 printk(" [");
2267 #define printmode(x) {if(p->modes&PARPORT_MODE_##x){printk("%s%s",f?",":"",#x);f++;}}
2268 {
2269 int f = 0;
2270 printmode(PCSPP);
2271 printmode(TRISTATE);
2272 printmode(COMPAT)
2273 printmode(EPP);
2274 printmode(ECP);
2275 printmode(DMA);
2276 }
2277 #undef printmode
2278 #ifndef CONFIG_PARPORT_1284
2279 printk ("(,...)");
2280 #endif /* CONFIG_PARPORT_1284 */
2281 printk("]\n");
2282 if (probedirq != PARPORT_IRQ_NONE)
2283 printk(KERN_INFO "%s: irq %d detected\n", p->name, probedirq);
2284
2285 /* If No ECP release the ports grabbed above. */
2286 if (ECR_res && (p->modes & PARPORT_MODE_ECP) == 0) {
2287 release_region(base_hi, 3);
2288 ECR_res = NULL;
2289 }
2290 /* Likewise for EEP ports */
2291 if (EPP_res && (p->modes & PARPORT_MODE_EPP) == 0) {
2292 release_region(base+3, 5);
2293 EPP_res = NULL;
2294 }
2295 if (p->irq != PARPORT_IRQ_NONE) {
2296 if (request_irq (p->irq, parport_pc_interrupt,
2297 0, p->name, p)) {
2298 printk (KERN_WARNING "%s: irq %d in use, "
2299 "resorting to polled operation\n",
2300 p->name, p->irq);
2301 p->irq = PARPORT_IRQ_NONE;
2302 p->dma = PARPORT_DMA_NONE;
2303 }
2304
2305 #ifdef CONFIG_PARPORT_PC_FIFO
2306 if (p->dma != PARPORT_DMA_NONE) {
2307 if (request_dma (p->dma, p->name)) {
2308 printk (KERN_WARNING "%s: dma %d in use, "
2309 "resorting to PIO operation\n",
2310 p->name, p->dma);
2311 p->dma = PARPORT_DMA_NONE;
2312 } else {
2313 priv->dma_buf =
2314 pci_alloc_consistent(priv->dev,
2315 PAGE_SIZE,
2316 &priv->dma_handle);
2317 if (! priv->dma_buf) {
2318 printk (KERN_WARNING "%s: "
2319 "cannot get buffer for DMA, "
2320 "resorting to PIO operation\n",
2321 p->name);
2322 free_dma(p->dma);
2323 p->dma = PARPORT_DMA_NONE;
2324 }
2325 }
2326 }
2327 #endif /* CONFIG_PARPORT_PC_FIFO */
2328 }
2329
2330 /* Done probing. Now put the port into a sensible start-up state. */
2331 if (priv->ecr)
2332 /*
2333 * Put the ECP detected port in PS2 mode.
2334 * Do this also for ports that have ECR but don't do ECP.
2335 */
2336 ECR_WRITE (p, 0x34);
2337
2338 parport_pc_write_data(p, 0);
2339 parport_pc_data_forward (p);
2340
2341 /* Now that we've told the sharing engine about the port, and
2342 found out its characteristics, let the high-level drivers
2343 know about it. */
2344 spin_lock(&ports_lock);
2345 list_add(&priv->list, &ports_list);
2346 spin_unlock(&ports_lock);
2347 parport_announce_port (p);
2348
2349 return p;
2350
2351 out5:
2352 if (ECR_res)
2353 release_region(base_hi, 3);
2354 if (EPP_res)
2355 release_region(base+0x3, 5);
2356 release_region(base, 3);
2357 out4:
2358 parport_put_port(p);
2359 out3:
2360 kfree (priv);
2361 out2:
2362 kfree (ops);
2363 out1:
2364 return NULL;
2365 }
2366
2367 EXPORT_SYMBOL (parport_pc_probe_port);
2368
2369 void parport_pc_unregister_port (struct parport *p)
2370 {
2371 struct parport_pc_private *priv = p->private_data;
2372 struct parport_operations *ops = p->ops;
2373
2374 parport_remove_port(p);
2375 spin_lock(&ports_lock);
2376 list_del_init(&priv->list);
2377 spin_unlock(&ports_lock);
2378 if (p->dma != PARPORT_DMA_NONE)
2379 free_dma(p->dma);
2380 if (p->irq != PARPORT_IRQ_NONE)
2381 free_irq(p->irq, p);
2382 release_region(p->base, 3);
2383 if (p->size > 3)
2384 release_region(p->base + 3, p->size - 3);
2385 if (p->modes & PARPORT_MODE_ECP)
2386 release_region(p->base_hi, 3);
2387 #ifdef CONFIG_PARPORT_PC_FIFO
2388 if (priv->dma_buf)
2389 pci_free_consistent(priv->dev, PAGE_SIZE,
2390 priv->dma_buf,
2391 priv->dma_handle);
2392 #endif /* CONFIG_PARPORT_PC_FIFO */
2393 kfree (p->private_data);
2394 parport_put_port(p);
2395 kfree (ops); /* hope no-one cached it */
2396 }
2397
2398 EXPORT_SYMBOL (parport_pc_unregister_port);
2399
2400 #ifdef CONFIG_PCI
2401
2402 /* ITE support maintained by Rich Liu <richliu@poorman.org> */
2403 static int __devinit sio_ite_8872_probe (struct pci_dev *pdev, int autoirq,
2404 int autodma)
2405 {
2406 short inta_addr[6] = { 0x2A0, 0x2C0, 0x220, 0x240, 0x1E0 };
2407 struct resource *base_res;
2408 u32 ite8872set;
2409 u32 ite8872_lpt, ite8872_lpthi;
2410 u8 ite8872_irq, type;
2411 char *fake_name = "parport probe";
2412 int irq;
2413 int i;
2414
2415 DPRINTK (KERN_DEBUG "sio_ite_8872_probe()\n");
2416
2417 // make sure which one chip
2418 for(i = 0; i < 5; i++) {
2419 base_res = request_region(inta_addr[i], 0x8, fake_name);
2420 if (base_res) {
2421 int test;
2422 pci_write_config_dword (pdev, 0x60,
2423 0xe7000000 | inta_addr[i]);
2424 pci_write_config_dword (pdev, 0x78,
2425 0x00000000 | inta_addr[i]);
2426 test = inb (inta_addr[i]);
2427 if (test != 0xff) break;
2428 release_region(inta_addr[i], 0x8);
2429 }
2430 }
2431 if(i >= 5) {
2432 printk (KERN_INFO "parport_pc: cannot find ITE8872 INTA\n");
2433 return 0;
2434 }
2435
2436 type = inb (inta_addr[i] + 0x18);
2437 type &= 0x0f;
2438
2439 switch (type) {
2440 case 0x2:
2441 printk (KERN_INFO "parport_pc: ITE8871 found (1P)\n");
2442 ite8872set = 0x64200000;
2443 break;
2444 case 0xa:
2445 printk (KERN_INFO "parport_pc: ITE8875 found (1P)\n");
2446 ite8872set = 0x64200000;
2447 break;
2448 case 0xe:
2449 printk (KERN_INFO "parport_pc: ITE8872 found (2S1P)\n");
2450 ite8872set = 0x64e00000;
2451 break;
2452 case 0x6:
2453 printk (KERN_INFO "parport_pc: ITE8873 found (1S)\n");
2454 return 0;
2455 case 0x8:
2456 DPRINTK (KERN_DEBUG "parport_pc: ITE8874 found (2S)\n");
2457 return 0;
2458 default:
2459 printk (KERN_INFO "parport_pc: unknown ITE887x\n");
2460 printk (KERN_INFO "parport_pc: please mail 'lspci -nvv' "
2461 "output to Rich.Liu@ite.com.tw\n");
2462 return 0;
2463 }
2464
2465 pci_read_config_byte (pdev, 0x3c, &ite8872_irq);
2466 pci_read_config_dword (pdev, 0x1c, &ite8872_lpt);
2467 ite8872_lpt &= 0x0000ff00;
2468 pci_read_config_dword (pdev, 0x20, &ite8872_lpthi);
2469 ite8872_lpthi &= 0x0000ff00;
2470 pci_write_config_dword (pdev, 0x6c, 0xe3000000 | ite8872_lpt);
2471 pci_write_config_dword (pdev, 0x70, 0xe3000000 | ite8872_lpthi);
2472 pci_write_config_dword (pdev, 0x80, (ite8872_lpthi<<16) | ite8872_lpt);
2473 // SET SPP&EPP , Parallel Port NO DMA , Enable All Function
2474 // SET Parallel IRQ
2475 pci_write_config_dword (pdev, 0x9c,
2476 ite8872set | (ite8872_irq * 0x11111));
2477
2478 DPRINTK (KERN_DEBUG "ITE887x: The IRQ is %d.\n", ite8872_irq);
2479 DPRINTK (KERN_DEBUG "ITE887x: The PARALLEL I/O port is 0x%x.\n",
2480 ite8872_lpt);
2481 DPRINTK (KERN_DEBUG "ITE887x: The PARALLEL I/O porthi is 0x%x.\n",
2482 ite8872_lpthi);
2483
2484 /* Let the user (or defaults) steer us away from interrupts */
2485 irq = ite8872_irq;
2486 if (autoirq != PARPORT_IRQ_AUTO)
2487 irq = PARPORT_IRQ_NONE;
2488
2489 /*
2490 * Release the resource so that parport_pc_probe_port can get it.
2491 */
2492 release_resource(base_res);
2493 if (parport_pc_probe_port (ite8872_lpt, ite8872_lpthi,
2494 irq, PARPORT_DMA_NONE, NULL)) {
2495 printk (KERN_INFO
2496 "parport_pc: ITE 8872 parallel port: io=0x%X",
2497 ite8872_lpt);
2498 if (irq != PARPORT_IRQ_NONE)
2499 printk (", irq=%d", irq);
2500 printk ("\n");
2501 return 1;
2502 }
2503
2504 return 0;
2505 }
2506
2507 /* Via support maintained by Jeff Garzik <jgarzik@pobox.com> */
2508 static int __devinit sio_via_686a_probe (struct pci_dev *pdev, int autoirq,
2509 int autodma)
2510 {
2511 u8 tmp;
2512 int dma, irq;
2513 unsigned port1, port2, have_eppecp;
2514
2515 /*
2516 * unlock super i/o configuration, set 0x85_1
2517 */
2518 pci_read_config_byte (pdev, 0x85, &tmp);
2519 tmp |= (1 << 1);
2520 pci_write_config_byte (pdev, 0x85, tmp);
2521
2522 /*
2523 * Super I/O configuration, index port == 3f0h, data port == 3f1h
2524 */
2525
2526 /* 0xE2_1-0: Parallel Port Mode / Enable */
2527 outb (0xE2, 0x3F0);
2528 tmp = inb (0x3F1);
2529
2530 if ((tmp & 0x03) == 0x03) {
2531 printk (KERN_INFO "parport_pc: Via 686A parallel port disabled in BIOS\n");
2532 return 0;
2533 }
2534
2535 /* 0xE6: Parallel Port I/O Base Address, bits 9-2 */
2536 outb (0xE6, 0x3F0);
2537 port1 = inb (0x3F1) << 2;
2538
2539 switch (port1) {
2540 case 0x3bc: port2 = 0x7bc; break;
2541 case 0x378: port2 = 0x778; break;
2542 case 0x278: port2 = 0x678; break;
2543 default:
2544 printk (KERN_INFO "parport_pc: Weird Via 686A parport base 0x%X, ignoring\n",
2545 port1);
2546 return 0;
2547 }
2548
2549 /* 0xF0_5: EPP+ECP enable */
2550 outb (0xF0, 0x3F0);
2551 have_eppecp = (inb (0x3F1) & (1 << 5));
2552
2553 /*
2554 * lock super i/o configuration, clear 0x85_1
2555 */
2556 pci_read_config_byte (pdev, 0x85, &tmp);
2557 tmp &= ~(1 << 1);
2558 pci_write_config_byte (pdev, 0x85, tmp);
2559
2560 /*
2561 * Get DMA and IRQ from PCI->ISA bridge PCI config registers
2562 */
2563
2564 /* 0x50_3-2: PnP Routing for Parallel Port DRQ */
2565 pci_read_config_byte (pdev, 0x50, &tmp);
2566 dma = ((tmp >> 2) & 0x03);
2567
2568 /* 0x51_7-4: PnP Routing for Parallel Port IRQ */
2569 pci_read_config_byte (pdev, 0x51, &tmp);
2570 irq = ((tmp >> 4) & 0x0F);
2571
2572 /* filter bogus IRQs */
2573 switch (irq) {
2574 case 0:
2575 case 2:
2576 case 8:
2577 case 13:
2578 irq = PARPORT_IRQ_NONE;
2579 break;
2580
2581 default: /* do nothing */
2582 break;
2583 }
2584
2585 /* if ECP not enabled, DMA is not enabled, assumed bogus 'dma' value */
2586 if (!have_eppecp)
2587 dma = PARPORT_DMA_NONE;
2588
2589 /* Let the user (or defaults) steer us away from interrupts and DMA */
2590 if (autoirq != PARPORT_IRQ_AUTO) {
2591 irq = PARPORT_IRQ_NONE;
2592 dma = PARPORT_DMA_NONE;
2593 }
2594 if (autodma != PARPORT_DMA_AUTO)
2595 dma = PARPORT_DMA_NONE;
2596
2597 /* finally, do the probe with values obtained */
2598 if (parport_pc_probe_port (port1, port2, irq, dma, NULL)) {
2599 printk (KERN_INFO
2600 "parport_pc: Via 686A parallel port: io=0x%X", port1);
2601 if (irq != PARPORT_IRQ_NONE)
2602 printk (", irq=%d", irq);
2603 if (dma != PARPORT_DMA_NONE)
2604 printk (", dma=%d", dma);
2605 printk ("\n");
2606 return 1;
2607 }
2608
2609 printk (KERN_WARNING "parport_pc: Strange, can't probe Via 686A parallel port: io=0x%X, irq=%d, dma=%d\n",
2610 port1, irq, dma);
2611 return 0;
2612 }
2613
2614
2615 enum parport_pc_sio_types {
2616 sio_via_686a = 0, /* Via VT82C686A motherboard Super I/O */
2617 sio_ite_8872,
2618 last_sio
2619 };
2620
2621 /* each element directly indexed from enum list, above */
2622 static struct parport_pc_superio {
2623 int (*probe) (struct pci_dev *pdev, int autoirq, int autodma);
2624 } parport_pc_superio_info[] __devinitdata = {
2625 { sio_via_686a_probe, },
2626 { sio_ite_8872_probe, },
2627 };
2628
2629
2630 enum parport_pc_pci_cards {
2631 siig_1p_10x = last_sio,
2632 siig_2p_10x,
2633 siig_1p_20x,
2634 siig_2p_20x,
2635 lava_parallel,
2636 lava_parallel_dual_a,
2637 lava_parallel_dual_b,
2638 boca_ioppar,
2639 plx_9050,
2640 timedia_4078a,
2641 timedia_4079h,
2642 timedia_4085h,
2643 timedia_4088a,
2644 timedia_4089a,
2645 timedia_4095a,
2646 timedia_4096a,
2647 timedia_4078u,
2648 timedia_4079a,
2649 timedia_4085u,
2650 timedia_4079r,
2651 timedia_4079s,
2652 timedia_4079d,
2653 timedia_4079e,
2654 timedia_4079f,
2655 timedia_9079a,
2656 timedia_9079b,
2657 timedia_9079c,
2658 timedia_4006a,
2659 timedia_4014,
2660 timedia_4008a,
2661 timedia_4018,
2662 timedia_9018a,
2663 syba_2p_epp,
2664 syba_1p_ecp,
2665 titan_010l,
2666 titan_1284p2,
2667 avlab_1p,
2668 avlab_2p,
2669 oxsemi_954,
2670 oxsemi_840,
2671 aks_0100,
2672 mobility_pp,
2673 netmos_9705,
2674 netmos_9805,
2675 netmos_9815,
2676 netmos_9855,
2677 netmos_9735,
2678 netmos_9835,
2679 netmos_9755,
2680 netmos_9715
2681 };
2682
2683
2684 /* each element directly indexed from enum list, above
2685 * (but offset by last_sio) */
2686 static struct parport_pc_pci {
2687 int numports;
2688 struct { /* BAR (base address registers) numbers in the config
2689 space header */
2690 int lo;
2691 int hi; /* -1 if not there, >6 for offset-method (max
2692 BAR is 6) */
2693 } addr[4];
2694
2695 /* If set, this is called immediately after pci_enable_device.
2696 * If it returns non-zero, no probing will take place and the
2697 * ports will not be used. */
2698 int (*preinit_hook) (struct pci_dev *pdev, int autoirq, int autodma);
2699
2700 /* If set, this is called after probing for ports. If 'failed'
2701 * is non-zero we couldn't use any of the ports. */
2702 void (*postinit_hook) (struct pci_dev *pdev, int failed);
2703 } cards[] __devinitdata = {
2704 /* siig_1p_10x */ { 1, { { 2, 3 }, } },
2705 /* siig_2p_10x */ { 2, { { 2, 3 }, { 4, 5 }, } },
2706 /* siig_1p_20x */ { 1, { { 0, 1 }, } },
2707 /* siig_2p_20x */ { 2, { { 0, 1 }, { 2, 3 }, } },
2708 /* lava_parallel */ { 1, { { 0, -1 }, } },
2709 /* lava_parallel_dual_a */ { 1, { { 0, -1 }, } },
2710 /* lava_parallel_dual_b */ { 1, { { 0, -1 }, } },
2711 /* boca_ioppar */ { 1, { { 0, -1 }, } },
2712 /* plx_9050 */ { 2, { { 4, -1 }, { 5, -1 }, } },
2713 /* timedia_4078a */ { 1, { { 2, -1 }, } },
2714 /* timedia_4079h */ { 1, { { 2, 3 }, } },
2715 /* timedia_4085h */ { 2, { { 2, -1 }, { 4, -1 }, } },
2716 /* timedia_4088a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2717 /* timedia_4089a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2718 /* timedia_4095a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2719 /* timedia_4096a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2720 /* timedia_4078u */ { 1, { { 2, -1 }, } },
2721 /* timedia_4079a */ { 1, { { 2, 3 }, } },
2722 /* timedia_4085u */ { 2, { { 2, -1 }, { 4, -1 }, } },
2723 /* timedia_4079r */ { 1, { { 2, 3 }, } },
2724 /* timedia_4079s */ { 1, { { 2, 3 }, } },
2725 /* timedia_4079d */ { 1, { { 2, 3 }, } },
2726 /* timedia_4079e */ { 1, { { 2, 3 }, } },
2727 /* timedia_4079f */ { 1, { { 2, 3 }, } },
2728 /* timedia_9079a */ { 1, { { 2, 3 }, } },
2729 /* timedia_9079b */ { 1, { { 2, 3 }, } },
2730 /* timedia_9079c */ { 1, { { 2, 3 }, } },
2731 /* timedia_4006a */ { 1, { { 0, -1 }, } },
2732 /* timedia_4014 */ { 2, { { 0, -1 }, { 2, -1 }, } },
2733 /* timedia_4008a */ { 1, { { 0, 1 }, } },
2734 /* timedia_4018 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2735 /* timedia_9018a */ { 2, { { 0, 1 }, { 2, 3 }, } },
2736 /* SYBA uses fixed offsets in
2737 a 1K io window */
2738 /* syba_2p_epp AP138B */ { 2, { { 0, 0x078 }, { 0, 0x178 }, } },
2739 /* syba_1p_ecp W83787 */ { 1, { { 0, 0x078 }, } },
2740 /* titan_010l */ { 1, { { 3, -1 }, } },
2741 /* titan_1284p2 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2742 /* avlab_1p */ { 1, { { 0, 1}, } },
2743 /* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} },
2744 /* The Oxford Semi cards are unusual: 954 doesn't support ECP,
2745 * and 840 locks up if you write 1 to bit 2! */
2746 /* oxsemi_954 */ { 1, { { 0, -1 }, } },
2747 /* oxsemi_840 */ { 1, { { 0, -1 }, } },
2748 /* aks_0100 */ { 1, { { 0, -1 }, } },
2749 /* mobility_pp */ { 1, { { 0, 1 }, } },
2750 /* netmos_9705 */ { 1, { { 0, -1 }, } }, /* untested */
2751 /* netmos_9805 */ { 1, { { 0, -1 }, } }, /* untested */
2752 /* netmos_9815 */ { 2, { { 0, -1 }, { 2, -1 }, } }, /* untested */
2753 /* netmos_9855 */ { 2, { { 0, -1 }, { 2, -1 }, } }, /* untested */
2754 /* netmos_9735 */ { 1, { { 2, 3 }, } }, /* untested */
2755 /* netmos_9835 */ { 1, { { 2, 3 }, } }, /* untested */
2756 /* netmos_9755 */ { 2, { { 0, 1 }, { 2, 3 },} }, /* untested */
2757 /* netmos_9715 */ { 2, { { 0, 1 }, { 2, 3 },} }, /* untested */
2758 };
2759
2760 static struct pci_device_id parport_pc_pci_tbl[] = {
2761 /* Super-IO onboard chips */
2762 { 0x1106, 0x0686, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_686a },
2763 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
2764 PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_ite_8872 },
2765
2766 /* PCI cards */
2767 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_10x,
2768 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_10x },
2769 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_10x,
2770 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_10x },
2771 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_20x,
2772 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_20x },
2773 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_20x,
2774 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_20x },
2775 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PARALLEL,
2776 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel },
2777 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_A,
2778 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_a },
2779 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_B,
2780 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_b },
2781 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_BOCA_IOPPAR,
2782 PCI_ANY_ID, PCI_ANY_ID, 0, 0, boca_ioppar },
2783 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2784 PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4014, 0,0, plx_9050 },
2785 /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/
2786 { 0x1409, 0x7168, 0x1409, 0x4078, 0, 0, timedia_4078a },
2787 { 0x1409, 0x7168, 0x1409, 0x4079, 0, 0, timedia_4079h },
2788 { 0x1409, 0x7168, 0x1409, 0x4085, 0, 0, timedia_4085h },
2789 { 0x1409, 0x7168, 0x1409, 0x4088, 0, 0, timedia_4088a },
2790 { 0x1409, 0x7168, 0x1409, 0x4089, 0, 0, timedia_4089a },
2791 { 0x1409, 0x7168, 0x1409, 0x4095, 0, 0, timedia_4095a },
2792 { 0x1409, 0x7168, 0x1409, 0x4096, 0, 0, timedia_4096a },
2793 { 0x1409, 0x7168, 0x1409, 0x5078, 0, 0, timedia_4078u },
2794 { 0x1409, 0x7168, 0x1409, 0x5079, 0, 0, timedia_4079a },
2795 { 0x1409, 0x7168, 0x1409, 0x5085, 0, 0, timedia_4085u },
2796 { 0x1409, 0x7168, 0x1409, 0x6079, 0, 0, timedia_4079r },
2797 { 0x1409, 0x7168, 0x1409, 0x7079, 0, 0, timedia_4079s },
2798 { 0x1409, 0x7168, 0x1409, 0x8079, 0, 0, timedia_4079d },
2799 { 0x1409, 0x7168, 0x1409, 0x9079, 0, 0, timedia_4079e },
2800 { 0x1409, 0x7168, 0x1409, 0xa079, 0, 0, timedia_4079f },
2801 { 0x1409, 0x7168, 0x1409, 0xb079, 0, 0, timedia_9079a },
2802 { 0x1409, 0x7168, 0x1409, 0xc079, 0, 0, timedia_9079b },
2803 { 0x1409, 0x7168, 0x1409, 0xd079, 0, 0, timedia_9079c },
2804 { 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a },
2805 { 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014 },
2806 { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a },
2807 { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 },
2808 { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a },
2809 { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp },
2810 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP,
2811 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp },
2812 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP,
2813 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp },
2814 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_010L,
2815 PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l },
2816 { 0x9710, 0x9815, 0x1000, 0x0020, 0, 0, titan_1284p2 },
2817 /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/
2818 { 0x14db, 0x2120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1p}, /* AFAVLAB_TK9902 */
2819 { 0x14db, 0x2121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2p},
2820 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954PP,
2821 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 },
2822 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_12PCI840,
2823 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 },
2824 { PCI_VENDOR_ID_AKS, PCI_DEVICE_ID_AKS_ALADDINCARD,
2825 PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 },
2826 /* NetMos communication controllers */
2827 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9705,
2828 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9705 },
2829 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9805,
2830 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9805 },
2831 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9815,
2832 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9815 },
2833 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9855,
2834 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9855 },
2835 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9735,
2836 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9735 },
2837 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
2838 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9835 },
2839 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9755,
2840 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9755 },
2841 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9715,
2842 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9715 },
2843 { 0, } /* terminate list */
2844 };
2845 MODULE_DEVICE_TABLE(pci,parport_pc_pci_tbl);
2846
2847 static int parport_pc_pci_probe (struct pci_dev *dev,
2848 const struct pci_device_id *id)
2849 {
2850 int err, count, n, i = id->driver_data;
2851
2852 if (i < last_sio)
2853 /* This is an onboard Super-IO and has already been probed */
2854 return 0;
2855
2856 /* This is a PCI card */
2857 i -= last_sio;
2858 count = 0;
2859 if ((err = pci_enable_device (dev)) != 0)
2860 return err;
2861
2862 if (cards[i].preinit_hook &&
2863 cards[i].preinit_hook (dev, PARPORT_IRQ_NONE, PARPORT_DMA_NONE))
2864 return -ENODEV;
2865
2866 for (n = 0; n < cards[i].numports; n++) {
2867 int lo = cards[i].addr[n].lo;
2868 int hi = cards[i].addr[n].hi;
2869 unsigned long io_lo, io_hi;
2870 io_lo = pci_resource_start (dev, lo);
2871 io_hi = 0;
2872 if ((hi >= 0) && (hi <= 6))
2873 io_hi = pci_resource_start (dev, hi);
2874 else if (hi > 6)
2875 io_lo += hi; /* Reinterpret the meaning of
2876 "hi" as an offset (see SYBA
2877 def.) */
2878 /* TODO: test if sharing interrupts works */
2879 printk (KERN_DEBUG "PCI parallel port detected: %04x:%04x, "
2880 "I/O at %#lx(%#lx)\n",
2881 parport_pc_pci_tbl[i + last_sio].vendor,
2882 parport_pc_pci_tbl[i + last_sio].device, io_lo, io_hi);
2883 if (parport_pc_probe_port (io_lo, io_hi, PARPORT_IRQ_NONE,
2884 PARPORT_DMA_NONE, dev))
2885 count++;
2886 }
2887
2888 if (cards[i].postinit_hook)
2889 cards[i].postinit_hook (dev, count == 0);
2890
2891 return count == 0 ? -ENODEV : 0;
2892 }
2893
2894 static struct pci_driver parport_pc_pci_driver = {
2895 .name = "parport_pc",
2896 .id_table = parport_pc_pci_tbl,
2897 .probe = parport_pc_pci_probe,
2898 };
2899
2900 static int __init parport_pc_init_superio (int autoirq, int autodma)
2901 {
2902 const struct pci_device_id *id;
2903 struct pci_dev *pdev = NULL;
2904 int ret = 0;
2905
2906 while ((pdev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pdev)) != NULL) {
2907 id = pci_match_device (parport_pc_pci_tbl, pdev);
2908 if (id == NULL || id->driver_data >= last_sio)
2909 continue;
2910
2911 if (parport_pc_superio_info[id->driver_data].probe
2912 (pdev, autoirq, autodma)) {
2913 ret++;
2914 }
2915 }
2916
2917 return ret; /* number of devices found */
2918 }
2919 #else
2920 static struct pci_driver parport_pc_pci_driver;
2921 static int __init parport_pc_init_superio(int autoirq, int autodma) {return 0;}
2922 #endif /* CONFIG_PCI */
2923
2924
2925 static const struct pnp_device_id parport_pc_pnp_tbl[] = {
2926 /* Standard LPT Printer Port */
2927 {.id = "PNP0400", .driver_data = 0},
2928 /* ECP Printer Port */
2929 {.id = "PNP0401", .driver_data = 0},
2930 { }
2931 };
2932
2933 MODULE_DEVICE_TABLE(pnp,parport_pc_pnp_tbl);
2934
2935 static int parport_pc_pnp_probe(struct pnp_dev *dev, const struct pnp_device_id *id)
2936 {
2937 struct parport *pdata;
2938 unsigned long io_lo, io_hi;
2939 int dma, irq;
2940
2941 if (pnp_port_valid(dev,0) &&
2942 !(pnp_port_flags(dev,0) & IORESOURCE_DISABLED)) {
2943 io_lo = pnp_port_start(dev,0);
2944 } else
2945 return -EINVAL;
2946
2947 if (pnp_port_valid(dev,1) &&
2948 !(pnp_port_flags(dev,1) & IORESOURCE_DISABLED)) {
2949 io_hi = pnp_port_start(dev,1);
2950 } else
2951 io_hi = 0;
2952
2953 if (pnp_irq_valid(dev,0) &&
2954 !(pnp_irq_flags(dev,0) & IORESOURCE_DISABLED)) {
2955 irq = pnp_irq(dev,0);
2956 } else
2957 irq = PARPORT_IRQ_NONE;
2958
2959 if (pnp_dma_valid(dev,0) &&
2960 !(pnp_dma_flags(dev,0) & IORESOURCE_DISABLED)) {
2961 dma = pnp_dma(dev,0);
2962 } else
2963 dma = PARPORT_DMA_NONE;
2964
2965 printk(KERN_INFO "parport: PnPBIOS parport detected.\n");
2966 if (!(pdata = parport_pc_probe_port (io_lo, io_hi, irq, dma, NULL)))
2967 return -ENODEV;
2968
2969 pnp_set_drvdata(dev,pdata);
2970 return 0;
2971 }
2972
2973 static void parport_pc_pnp_remove(struct pnp_dev *dev)
2974 {
2975 struct parport *pdata = (struct parport *)pnp_get_drvdata(dev);
2976 if (!pdata)
2977 return;
2978
2979 parport_pc_unregister_port(pdata);
2980 }
2981
2982 /* we only need the pnp layer to activate the device, at least for now */
2983 static struct pnp_driver parport_pc_pnp_driver = {
2984 .name = "parport_pc",
2985 .id_table = parport_pc_pnp_tbl,
2986 .probe = parport_pc_pnp_probe,
2987 .remove = parport_pc_pnp_remove,
2988 };
2989
2990
2991 /* This is called by parport_pc_find_nonpci_ports (in asm/parport.h) */
2992 static int __init __attribute__((unused))
2993 parport_pc_find_isa_ports (int autoirq, int autodma)
2994 {
2995 int count = 0;
2996
2997 if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL))
2998 count++;
2999 if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL))
3000 count++;
3001 if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL))
3002 count++;
3003
3004 return count;
3005 }
3006
3007 /* This function is called by parport_pc_init if the user didn't
3008 * specify any ports to probe. Its job is to find some ports. Order
3009 * is important here -- we want ISA ports to be registered first,
3010 * followed by PCI cards (for least surprise), but before that we want
3011 * to do chipset-specific tests for some onboard ports that we know
3012 * about.
3013 *
3014 * autoirq is PARPORT_IRQ_NONE, PARPORT_IRQ_AUTO, or PARPORT_IRQ_PROBEONLY
3015 * autodma is PARPORT_DMA_NONE or PARPORT_DMA_AUTO
3016 */
3017 static int __init parport_pc_find_ports (int autoirq, int autodma)
3018 {
3019 int count = 0, r;
3020
3021 #ifdef CONFIG_PARPORT_PC_SUPERIO
3022 detect_and_report_winbond ();
3023 detect_and_report_smsc ();
3024 #endif
3025
3026 /* Onboard SuperIO chipsets that show themselves on the PCI bus. */
3027 count += parport_pc_init_superio (autoirq, autodma);
3028
3029 /* PnP ports, skip detection if SuperIO already found them */
3030 if (!count) {
3031 r = pnp_register_driver (&parport_pc_pnp_driver);
3032 if (r >= 0) {
3033 pnp_registered_parport = 1;
3034 count += r;
3035 }
3036 }
3037
3038 /* ISA ports and whatever (see asm/parport.h). */
3039 count += parport_pc_find_nonpci_ports (autoirq, autodma);
3040
3041 r = pci_register_driver (&parport_pc_pci_driver);
3042 if (r >= 0) {
3043 pci_registered_parport = 1;
3044 count += r;
3045 }
3046
3047 return count;
3048 }
3049
3050 /*
3051 * Piles of crap below pretend to be a parser for module and kernel
3052 * parameters. Say "thank you" to whoever had come up with that
3053 * syntax and keep in mind that code below is a cleaned up version.
3054 */
3055
3056 static int __initdata io[PARPORT_PC_MAX_PORTS+1] = { [0 ... PARPORT_PC_MAX_PORTS] = 0 };
3057 static int __initdata io_hi[PARPORT_PC_MAX_PORTS+1] =
3058 { [0 ... PARPORT_PC_MAX_PORTS] = PARPORT_IOHI_AUTO };
3059 static int __initdata dmaval[PARPORT_PC_MAX_PORTS] = { [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_DMA_NONE };
3060 static int __initdata irqval[PARPORT_PC_MAX_PORTS] = { [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_IRQ_PROBEONLY };
3061
3062 static int __init parport_parse_param(const char *s, int *val,
3063 int automatic, int none, int nofifo)
3064 {
3065 if (!s)
3066 return 0;
3067 if (!strncmp(s, "auto", 4))
3068 *val = automatic;
3069 else if (!strncmp(s, "none", 4))
3070 *val = none;
3071 else if (nofifo && !strncmp(s, "nofifo", 4))
3072 *val = nofifo;
3073 else {
3074 char *ep;
3075 unsigned long r = simple_strtoul(s, &ep, 0);
3076 if (ep != s)
3077 *val = r;
3078 else {
3079 printk(KERN_ERR "parport: bad specifier `%s'\n", s);
3080 return -1;
3081 }
3082 }
3083 return 0;
3084 }
3085
3086 static int __init parport_parse_irq(const char *irqstr, int *val)
3087 {
3088 return parport_parse_param(irqstr, val, PARPORT_IRQ_AUTO,
3089 PARPORT_IRQ_NONE, 0);
3090 }
3091
3092 static int __init parport_parse_dma(const char *dmastr, int *val)
3093 {
3094 return parport_parse_param(dmastr, val, PARPORT_DMA_AUTO,
3095 PARPORT_DMA_NONE, PARPORT_DMA_NOFIFO);
3096 }
3097
3098 #ifdef MODULE
3099 static const char *irq[PARPORT_PC_MAX_PORTS];
3100 static const char *dma[PARPORT_PC_MAX_PORTS];
3101
3102 MODULE_PARM_DESC(io, "Base I/O address (SPP regs)");
3103 MODULE_PARM(io, "1-" __MODULE_STRING(PARPORT_PC_MAX_PORTS) "i");
3104 MODULE_PARM_DESC(io_hi, "Base I/O address (ECR)");
3105 MODULE_PARM(io_hi, "1-" __MODULE_STRING(PARPORT_PC_MAX_PORTS) "i");
3106 MODULE_PARM_DESC(irq, "IRQ line");
3107 MODULE_PARM(irq, "1-" __MODULE_STRING(PARPORT_PC_MAX_PORTS) "s");
3108 MODULE_PARM_DESC(dma, "DMA channel");
3109 MODULE_PARM(dma, "1-" __MODULE_STRING(PARPORT_PC_MAX_PORTS) "s");
3110 #if defined(CONFIG_PARPORT_PC_SUPERIO) || \
3111 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
3112 MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialisation");
3113 MODULE_PARM(verbose_probing, "i");
3114 #endif
3115
3116 static int __init parse_parport_params(void)
3117 {
3118 unsigned int i;
3119 int val;
3120
3121 for (i = 0; i < PARPORT_PC_MAX_PORTS && io[i]; i++) {
3122 if (parport_parse_irq(irq[i], &val))
3123 return 1;
3124 irqval[i] = val;
3125 if (parport_parse_dma(dma[i], &val))
3126 return 1;
3127 dmaval[i] = val;
3128 }
3129 if (!io[0]) {
3130 /* The user can make us use any IRQs or DMAs we find. */
3131 if (irq[0] && !parport_parse_irq(irq[0], &val))
3132 switch (val) {
3133 case PARPORT_IRQ_NONE:
3134 case PARPORT_IRQ_AUTO:
3135 irqval[0] = val;
3136 break;
3137 default:
3138 printk (KERN_WARNING
3139 "parport_pc: irq specified "
3140 "without base address. Use 'io=' "
3141 "to specify one\n");
3142 }
3143
3144 if (dma[0] && !parport_parse_dma(dma[0], &val))
3145 switch (val) {
3146 case PARPORT_DMA_NONE:
3147 case PARPORT_DMA_AUTO:
3148 dmaval[0] = val;
3149 break;
3150 default:
3151 printk (KERN_WARNING
3152 "parport_pc: dma specified "
3153 "without base address. Use 'io=' "
3154 "to specify one\n");
3155 }
3156 }
3157 return 0;
3158 }
3159
3160 #else
3161
3162 static int parport_setup_ptr __initdata = 0;
3163
3164 /*
3165 * Acceptable parameters:
3166 *
3167 * parport=0
3168 * parport=auto
3169 * parport=0xBASE[,IRQ[,DMA]]
3170 *
3171 * IRQ/DMA may be numeric or 'auto' or 'none'
3172 */
3173 static int __init parport_setup (char *str)
3174 {
3175 char *endptr;
3176 char *sep;
3177 int val;
3178
3179 if (!str || !*str || (*str == '0' && !*(str+1))) {
3180 /* Disable parport if "parport=0" in cmdline */
3181 io[0] = PARPORT_DISABLE;
3182 return 1;
3183 }
3184
3185 if (!strncmp (str, "auto", 4)) {
3186 irqval[0] = PARPORT_IRQ_AUTO;
3187 dmaval[0] = PARPORT_DMA_AUTO;
3188 return 1;
3189 }
3190
3191 val = simple_strtoul (str, &endptr, 0);
3192 if (endptr == str) {
3193 printk (KERN_WARNING "parport=%s not understood\n", str);
3194 return 1;
3195 }
3196
3197 if (parport_setup_ptr == PARPORT_PC_MAX_PORTS) {
3198 printk(KERN_ERR "parport=%s ignored, too many ports\n", str);
3199 return 1;
3200 }
3201
3202 io[parport_setup_ptr] = val;
3203 irqval[parport_setup_ptr] = PARPORT_IRQ_NONE;
3204 dmaval[parport_setup_ptr] = PARPORT_DMA_NONE;
3205
3206 sep = strchr(str, ',');
3207 if (sep++) {
3208 if (parport_parse_irq(sep, &val))
3209 return 1;
3210 irqval[parport_setup_ptr] = val;
3211 sep = strchr(sep, ',');
3212 if (sep++) {
3213 if (parport_parse_dma(sep, &val))
3214 return 1;
3215 dmaval[parport_setup_ptr] = val;
3216 }
3217 }
3218 parport_setup_ptr++;
3219 return 1;
3220 }
3221
3222 static int __init parse_parport_params(void)
3223 {
3224 return io[0] == PARPORT_DISABLE;
3225 }
3226
3227 __setup ("parport=", parport_setup);
3228 #endif
3229
3230 /* "Parser" ends here */
3231
3232 static int __init parport_pc_init(void)
3233 {
3234 int count = 0;
3235
3236 if (parse_parport_params())
3237 return -EINVAL;
3238
3239 if (io[0]) {
3240 int i;
3241 /* Only probe the ports we were given. */
3242 user_specified = 1;
3243 for (i = 0; i < PARPORT_PC_MAX_PORTS; i++) {
3244 if (!io[i])
3245 break;
3246 if ((io_hi[i]) == PARPORT_IOHI_AUTO)
3247 io_hi[i] = 0x400 + io[i];
3248 if (parport_pc_probe_port(io[i], io_hi[i],
3249 irqval[i], dmaval[i], NULL))
3250 count++;
3251 }
3252 } else
3253 count += parport_pc_find_ports (irqval[0], dmaval[0]);
3254
3255 return 0;
3256 }
3257
3258 static void __exit parport_pc_exit(void)
3259 {
3260 if (pci_registered_parport)
3261 pci_unregister_driver (&parport_pc_pci_driver);
3262 if (pnp_registered_parport)
3263 pnp_unregister_driver (&parport_pc_pnp_driver);
3264
3265 spin_lock(&ports_lock);
3266 while (!list_empty(&ports_list)) {
3267 struct parport_pc_private *priv;
3268 struct parport *port;
3269 priv = list_entry(ports_list.next,
3270 struct parport_pc_private, list);
3271 port = priv->port;
3272 spin_unlock(&ports_lock);
3273 parport_pc_unregister_port(port);
3274 spin_lock(&ports_lock);
3275 }
3276 spin_unlock(&ports_lock);
3277 }
3278
3279 MODULE_AUTHOR("Phil Blundell, Tim Waugh, others");
3280 MODULE_DESCRIPTION("PC-style parallel port driver");
3281 MODULE_LICENSE("GPL");
3282 module_init(parport_pc_init)
3283 module_exit(parport_pc_exit)
MOXA 2.6.9 from sdlinux-moxaart.tgz