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MOXA linux-2.6.x / linux-2.6.9-uc0 from sdlinux-moxaart.tgz
[linux-2.6.9-moxart.git] / drivers / serial / 8250_pci.c
blob55c8aa908616428f1a2c6f4c752f7470411e9c35
1 /*
2 * linux/drivers/char/8250_pci.c
3 *
4 * Probe module for 8250/16550-type PCI serial ports.
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
15 */
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/pci.h>
19 #include <linux/sched.h>
20 #include <linux/string.h>
21 #include <linux/kernel.h>
22 #include <linux/slab.h>
23 #include <linux/delay.h>
24 #include <linux/tty.h>
25 #include <linux/serial.h>
26 #include <linux/serial_core.h>
27 #include <linux/8250_pci.h>
28
29 #include <asm/bitops.h>
30 #include <asm/byteorder.h>
31 #include <asm/io.h>
32
33 #include "8250.h"
34
35 /*
36 * Definitions for PCI support.
37 */
38 #define FL_BASE_MASK 0x0007
39 #define FL_BASE0 0x0000
40 #define FL_BASE1 0x0001
41 #define FL_BASE2 0x0002
42 #define FL_BASE3 0x0003
43 #define FL_BASE4 0x0004
44 #define FL_GET_BASE(x) (x & FL_BASE_MASK)
45
46 /* Use successive BARs (PCI base address registers),
47 else use offset into some specified BAR */
48 #define FL_BASE_BARS 0x0008
49
50 /* do not assign an irq */
51 #define FL_NOIRQ 0x0080
52
53 /* Use the Base address register size to cap number of ports */
54 #define FL_REGION_SZ_CAP 0x0100
55
56 struct pci_board {
57 unsigned int flags;
58 unsigned int num_ports;
59 unsigned int base_baud;
60 unsigned int uart_offset;
61 unsigned int reg_shift;
62 unsigned int first_offset;
63 };
64
65 /*
66 * init function returns:
67 * > 0 - number of ports
68 * = 0 - use board->num_ports
69 * < 0 - error
70 */
71 struct pci_serial_quirk {
72 u32 vendor;
73 u32 device;
74 u32 subvendor;
75 u32 subdevice;
76 int (*init)(struct pci_dev *dev);
77 int (*setup)(struct pci_dev *dev, struct pci_board *board,
78 struct serial_struct *req, int idx);
79 void (*exit)(struct pci_dev *dev);
80 };
81
82 #define PCI_NUM_BAR_RESOURCES 6
83
84 struct serial_private {
85 unsigned int nr;
86 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
87 struct pci_serial_quirk *quirk;
88 int line[0];
89 };
90
91 static void moan_device(const char *str, struct pci_dev *dev)
92 {
93 printk(KERN_WARNING "%s: %s\n"
94 KERN_WARNING "Please send the output of lspci -vv, this\n"
95 KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
96 KERN_WARNING "manufacturer and name of serial board or\n"
97 KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
98 pci_name(dev), str, dev->vendor, dev->device,
99 dev->subsystem_vendor, dev->subsystem_device);
100 }
101
102 static int
103 setup_port(struct pci_dev *dev, struct serial_struct *req,
104 int bar, int offset, int regshift)
105 {
106 struct serial_private *priv = pci_get_drvdata(dev);
107 unsigned long port, len;
108
109 if (bar >= PCI_NUM_BAR_RESOURCES)
110 return -EINVAL;
111
112 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
113 port = pci_resource_start(dev, bar);
114 len = pci_resource_len(dev, bar);
115
116 if (!priv->remapped_bar[bar])
117 priv->remapped_bar[bar] = ioremap(port, len);
118 if (!priv->remapped_bar[bar])
119 return -ENOMEM;
120
121 req->io_type = UPIO_MEM;
122 req->iomap_base = port + offset;
123 req->iomem_base = priv->remapped_bar[bar] + offset;
124 req->iomem_reg_shift = regshift;
125 } else {
126 port = pci_resource_start(dev, bar) + offset;
127 req->io_type = UPIO_PORT;
128 req->port = port;
129 if (HIGH_BITS_OFFSET)
130 req->port_high = port >> HIGH_BITS_OFFSET;
131 }
132 return 0;
133 }
134
135 /*
136 * AFAVLAB uses a different mixture of BARs and offsets
137 * Not that ugly ;) -- HW
138 */
139 static int
140 afavlab_setup(struct pci_dev *dev, struct pci_board *board,
141 struct serial_struct *req, int idx)
142 {
143 unsigned int bar, offset = board->first_offset;
144
145 bar = FL_GET_BASE(board->flags);
146 if (idx < 4)
147 bar += idx;
148 else {
149 bar = 4;
150 offset += (idx - 4) * board->uart_offset;
151 }
152
153 return setup_port(dev, req, bar, offset, board->reg_shift);
154 }
155
156 /*
157 * HP's Remote Management Console. The Diva chip came in several
158 * different versions. N-class, L2000 and A500 have two Diva chips, each
159 * with 3 UARTs (the third UART on the second chip is unused). Superdome
160 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
161 * one Diva chip, but it has been expanded to 5 UARTs.
162 */
163 static int __devinit pci_hp_diva_init(struct pci_dev *dev)
164 {
165 int rc = 0;
166
167 switch (dev->subsystem_device) {
168 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
169 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
170 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
171 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
172 rc = 3;
173 break;
174 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
175 rc = 2;
176 break;
177 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
178 rc = 4;
179 break;
180 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
181 rc = 1;
182 break;
183 }
184
185 return rc;
186 }
187
188 /*
189 * HP's Diva chip puts the 4th/5th serial port further out, and
190 * some serial ports are supposed to be hidden on certain models.
191 */
192 static int
193 pci_hp_diva_setup(struct pci_dev *dev, struct pci_board *board,
194 struct serial_struct *req, int idx)
195 {
196 unsigned int offset = board->first_offset;
197 unsigned int bar = FL_GET_BASE(board->flags);
198
199 switch (dev->subsystem_device) {
200 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
201 if (idx == 3)
202 idx++;
203 break;
204 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
205 if (idx > 0)
206 idx++;
207 if (idx > 2)
208 idx++;
209 break;
210 }
211 if (idx > 2)
212 offset = 0x18;
213
214 offset += idx * board->uart_offset;
215
216 return setup_port(dev, req, bar, offset, board->reg_shift);
217 }
218
219 /*
220 * Added for EKF Intel i960 serial boards
221 */
222 static int __devinit pci_inteli960ni_init(struct pci_dev *dev)
223 {
224 unsigned long oldval;
225
226 if (!(dev->subsystem_device & 0x1000))
227 return -ENODEV;
228
229 /* is firmware started? */
230 pci_read_config_dword(dev, 0x44, (void*) &oldval);
231 if (oldval == 0x00001000L) { /* RESET value */
232 printk(KERN_DEBUG "Local i960 firmware missing");
233 return -ENODEV;
234 }
235 return 0;
236 }
237
238 /*
239 * Some PCI serial cards using the PLX 9050 PCI interface chip require
240 * that the card interrupt be explicitly enabled or disabled. This
241 * seems to be mainly needed on card using the PLX which also use I/O
242 * mapped memory.
243 */
244 static int __devinit pci_plx9050_init(struct pci_dev *dev)
245 {
246 u8 irq_config;
247 void __iomem *p;
248
249 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
250 moan_device("no memory in bar 0", dev);
251 return 0;
252 }
253
254 irq_config = 0x41;
255 if (dev->vendor == PCI_VENDOR_ID_PANACOM)
256 irq_config = 0x43;
257 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
258 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
259 /*
260 * As the megawolf cards have the int pins active
261 * high, and have 2 UART chips, both ints must be
262 * enabled on the 9050. Also, the UARTS are set in
263 * 16450 mode by default, so we have to enable the
264 * 16C950 'enhanced' mode so that we can use the
265 * deep FIFOs
266 */
267 irq_config = 0x5b;
268 }
269
270 /*
271 * enable/disable interrupts
272 */
273 p = ioremap(pci_resource_start(dev, 0), 0x80);
274 if (p == NULL)
275 return -ENOMEM;
276 writel(irq_config, p + 0x4c);
277
278 /*
279 * Read the register back to ensure that it took effect.
280 */
281 readl(p + 0x4c);
282 iounmap(p);
283
284 return 0;
285 }
286
287 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
288 {
289 u8 *p;
290
291 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
292 return;
293
294 /*
295 * disable interrupts
296 */
297 p = ioremap(pci_resource_start(dev, 0), 0x80);
298 if (p != NULL) {
299 writel(0, p + 0x4c);
300
301 /*
302 * Read the register back to ensure that it took effect.
303 */
304 readl(p + 0x4c);
305 iounmap(p);
306 }
307 }
308
309 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
310 static int
311 sbs_setup(struct pci_dev *dev, struct pci_board *board,
312 struct serial_struct *req, int idx)
313 {
314 unsigned int bar, offset = board->first_offset;
315
316 bar = 0;
317
318 if (idx < 4) {
319 /* first four channels map to 0, 0x100, 0x200, 0x300 */
320 offset += idx * board->uart_offset;
321 } else if (idx < 8) {
322 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
323 offset += idx * board->uart_offset + 0xC00;
324 } else /* we have only 8 ports on PMC-OCTALPRO */
325 return 1;
326
327 return setup_port(dev, req, bar, offset, board->reg_shift);
328 }
329
330 /*
331 * This does initialization for PMC OCTALPRO cards:
332 * maps the device memory, resets the UARTs (needed, bc
333 * if the module is removed and inserted again, the card
334 * is in the sleep mode) and enables global interrupt.
335 */
336
337 /* global control register offset for SBS PMC-OctalPro */
338 #define OCT_REG_CR_OFF 0x500
339
340 static int __devinit sbs_init(struct pci_dev *dev)
341 {
342 u8 * p;
343
344 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
345
346 if (p == NULL)
347 return -ENOMEM;
348 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
349 writeb(0x10,p + OCT_REG_CR_OFF);
350 udelay(50);
351 writeb(0x0,p + OCT_REG_CR_OFF);
352
353 /* Set bit-2 (INTENABLE) of Control Register */
354 writeb(0x4, p + OCT_REG_CR_OFF);
355 iounmap(p);
356
357 return 0;
358 }
359
360 /*
361 * Disables the global interrupt of PMC-OctalPro
362 */
363
364 static void __devexit sbs_exit(struct pci_dev *dev)
365 {
366 u8 * p;
367
368 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
369 if (p != NULL) {
370 writeb(0, p + OCT_REG_CR_OFF);
371 }
372 iounmap(p);
373 }
374
375 /*
376 * SIIG serial cards have an PCI interface chip which also controls
377 * the UART clocking frequency. Each UART can be clocked independently
378 * (except cards equiped with 4 UARTs) and initial clocking settings
379 * are stored in the EEPROM chip. It can cause problems because this
380 * version of serial driver doesn't support differently clocked UART's
381 * on single PCI card. To prevent this, initialization functions set
382 * high frequency clocking for all UART's on given card. It is safe (I
383 * hope) because it doesn't touch EEPROM settings to prevent conflicts
384 * with other OSes (like M$ DOS).
385 *
386 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
387 *
388 * There is two family of SIIG serial cards with different PCI
389 * interface chip and different configuration methods:
390 * - 10x cards have control registers in IO and/or memory space;
391 * - 20x cards have control registers in standard PCI configuration space.
392 *
393 * Note: some SIIG cards are probed by the parport_serial object.
394 */
395
396 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
397 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
398
399 static int pci_siig10x_init(struct pci_dev *dev)
400 {
401 u16 data;
402 void __iomem *p;
403
404 switch (dev->device & 0xfff8) {
405 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
406 data = 0xffdf;
407 break;
408 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
409 data = 0xf7ff;
410 break;
411 default: /* 1S1P, 4S */
412 data = 0xfffb;
413 break;
414 }
415
416 p = ioremap(pci_resource_start(dev, 0), 0x80);
417 if (p == NULL)
418 return -ENOMEM;
419
420 writew(readw(p + 0x28) & data, p + 0x28);
421 readw(p + 0x28);
422 iounmap(p);
423 return 0;
424 }
425
426 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
427 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
428
429 static int pci_siig20x_init(struct pci_dev *dev)
430 {
431 u8 data;
432
433 /* Change clock frequency for the first UART. */
434 pci_read_config_byte(dev, 0x6f, &data);
435 pci_write_config_byte(dev, 0x6f, data & 0xef);
436
437 /* If this card has 2 UART, we have to do the same with second UART. */
438 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
439 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
440 pci_read_config_byte(dev, 0x73, &data);
441 pci_write_config_byte(dev, 0x73, data & 0xef);
442 }
443 return 0;
444 }
445
446 int pci_siig10x_fn(struct pci_dev *dev, int enable)
447 {
448 int ret = 0;
449 if (enable)
450 ret = pci_siig10x_init(dev);
451 return ret;
452 }
453
454 int pci_siig20x_fn(struct pci_dev *dev, int enable)
455 {
456 int ret = 0;
457 if (enable)
458 ret = pci_siig20x_init(dev);
459 return ret;
460 }
461
462 EXPORT_SYMBOL(pci_siig10x_fn);
463 EXPORT_SYMBOL(pci_siig20x_fn);
464
465 /*
466 * Timedia has an explosion of boards, and to avoid the PCI table from
467 * growing *huge*, we use this function to collapse some 70 entries
468 * in the PCI table into one, for sanity's and compactness's sake.
469 */
470 static unsigned short timedia_single_port[] = {
471 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
472 };
473
474 static unsigned short timedia_dual_port[] = {
475 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
476 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
477 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
478 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
479 0xD079, 0
480 };
481
482 static unsigned short timedia_quad_port[] = {
483 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
484 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
485 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
486 0xB157, 0
487 };
488
489 static unsigned short timedia_eight_port[] = {
490 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
491 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
492 };
493
494 static struct timedia_struct {
495 int num;
496 unsigned short *ids;
497 } timedia_data[] = {
498 { 1, timedia_single_port },
499 { 2, timedia_dual_port },
500 { 4, timedia_quad_port },
501 { 8, timedia_eight_port },
502 { 0, NULL }
503 };
504
505 static int __devinit pci_timedia_init(struct pci_dev *dev)
506 {
507 unsigned short *ids;
508 int i, j;
509
510 for (i = 0; timedia_data[i].num; i++) {
511 ids = timedia_data[i].ids;
512 for (j = 0; ids[j]; j++)
513 if (dev->subsystem_device == ids[j])
514 return timedia_data[i].num;
515 }
516 return 0;
517 }
518
519 /*
520 * Timedia/SUNIX uses a mixture of BARs and offsets
521 * Ugh, this is ugly as all hell --- TYT
522 */
523 static int
524 pci_timedia_setup(struct pci_dev *dev, struct pci_board *board,
525 struct serial_struct *req, int idx)
526 {
527 unsigned int bar = 0, offset = board->first_offset;
528
529 switch (idx) {
530 case 0:
531 bar = 0;
532 break;
533 case 1:
534 offset = board->uart_offset;
535 bar = 0;
536 break;
537 case 2:
538 bar = 1;
539 break;
540 case 3:
541 offset = board->uart_offset;
542 bar = 1;
543 case 4: /* BAR 2 */
544 case 5: /* BAR 3 */
545 case 6: /* BAR 4 */
546 case 7: /* BAR 5 */
547 bar = idx - 2;
548 }
549
550 return setup_port(dev, req, bar, offset, board->reg_shift);
551 }
552
553 /*
554 * Some Titan cards are also a little weird
555 */
556 static int
557 titan_400l_800l_setup(struct pci_dev *dev, struct pci_board *board,
558 struct serial_struct *req, int idx)
559 {
560 unsigned int bar, offset = board->first_offset;
561
562 switch (idx) {
563 case 0:
564 bar = 1;
565 break;
566 case 1:
567 bar = 2;
568 break;
569 default:
570 bar = 4;
571 offset = (idx - 2) * board->uart_offset;
572 }
573
574 return setup_port(dev, req, bar, offset, board->reg_shift);
575 }
576
577 static int __devinit pci_xircom_init(struct pci_dev *dev)
578 {
579 msleep(100);
580 return 0;
581 }
582
583 static int
584 pci_default_setup(struct pci_dev *dev, struct pci_board *board,
585 struct serial_struct *req, int idx)
586 {
587 unsigned int bar, offset = board->first_offset, maxnr;
588
589 bar = FL_GET_BASE(board->flags);
590 if (board->flags & FL_BASE_BARS)
591 bar += idx;
592 else
593 offset += idx * board->uart_offset;
594
595 maxnr = (pci_resource_len(dev, bar) - board->first_offset) /
596 (8 << board->reg_shift);
597
598 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
599 return 1;
600
601 return setup_port(dev, req, bar, offset, board->reg_shift);
602 }
603
604 /* This should be in linux/pci_ids.h */
605 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
606 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
607 #define PCI_DEVICE_ID_OCTPRO 0x0001
608 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
609 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
610 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
611 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
612
613 /*
614 * Master list of serial port init/setup/exit quirks.
615 * This does not describe the general nature of the port.
616 * (ie, baud base, number and location of ports, etc)
617 *
618 * This list is ordered alphabetically by vendor then device.
619 * Specific entries must come before more generic entries.
620 */
621 static struct pci_serial_quirk pci_serial_quirks[] = {
622 /*
623 * AFAVLAB cards.
624 * It is not clear whether this applies to all products.
625 */
626 {
627 .vendor = PCI_VENDOR_ID_AFAVLAB,
628 .device = PCI_ANY_ID,
629 .subvendor = PCI_ANY_ID,
630 .subdevice = PCI_ANY_ID,
631 .setup = afavlab_setup,
632 },
633 /*
634 * HP Diva
635 */
636 {
637 .vendor = PCI_VENDOR_ID_HP,
638 .device = PCI_DEVICE_ID_HP_DIVA,
639 .subvendor = PCI_ANY_ID,
640 .subdevice = PCI_ANY_ID,
641 .init = pci_hp_diva_init,
642 .setup = pci_hp_diva_setup,
643 },
644 /*
645 * Intel
646 */
647 {
648 .vendor = PCI_VENDOR_ID_INTEL,
649 .device = PCI_DEVICE_ID_INTEL_80960_RP,
650 .subvendor = 0xe4bf,
651 .subdevice = PCI_ANY_ID,
652 .init = pci_inteli960ni_init,
653 .setup = pci_default_setup,
654 },
655 /*
656 * Panacom
657 */
658 {
659 .vendor = PCI_VENDOR_ID_PANACOM,
660 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
661 .subvendor = PCI_ANY_ID,
662 .subdevice = PCI_ANY_ID,
663 .init = pci_plx9050_init,
664 .setup = pci_default_setup,
665 .exit = __devexit_p(pci_plx9050_exit),
666 },
667 {
668 .vendor = PCI_VENDOR_ID_PANACOM,
669 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
670 .subvendor = PCI_ANY_ID,
671 .subdevice = PCI_ANY_ID,
672 .init = pci_plx9050_init,
673 .setup = pci_default_setup,
674 .exit = __devexit_p(pci_plx9050_exit),
675 },
676 /*
677 * PLX
678 */
679 {
680 .vendor = PCI_VENDOR_ID_PLX,
681 .device = PCI_DEVICE_ID_PLX_9050,
682 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
683 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
684 .init = pci_plx9050_init,
685 .setup = pci_default_setup,
686 .exit = __devexit_p(pci_plx9050_exit),
687 },
688 {
689 .vendor = PCI_VENDOR_ID_PLX,
690 .device = PCI_DEVICE_ID_PLX_ROMULUS,
691 .subvendor = PCI_VENDOR_ID_PLX,
692 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
693 .init = pci_plx9050_init,
694 .setup = pci_default_setup,
695 .exit = __devexit_p(pci_plx9050_exit),
696 },
697 /*
698 * SBS Technologies, Inc., PMC-OCTALPRO 232
699 */
700 {
701 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
702 .device = PCI_DEVICE_ID_OCTPRO,
703 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
704 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
705 .init = sbs_init,
706 .setup = sbs_setup,
707 .exit = __devexit_p(sbs_exit),
708 },
709 /*
710 * SBS Technologies, Inc., PMC-OCTALPRO 422
711 */
712 {
713 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
714 .device = PCI_DEVICE_ID_OCTPRO,
715 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
716 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
717 .init = sbs_init,
718 .setup = sbs_setup,
719 .exit = __devexit_p(sbs_exit),
720 },
721 /*
722 * SBS Technologies, Inc., P-Octal 232
723 */
724 {
725 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
726 .device = PCI_DEVICE_ID_OCTPRO,
727 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
728 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
729 .init = sbs_init,
730 .setup = sbs_setup,
731 .exit = __devexit_p(sbs_exit),
732 },
733 /*
734 * SBS Technologies, Inc., P-Octal 422
735 */
736 {
737 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
738 .device = PCI_DEVICE_ID_OCTPRO,
739 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
740 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
741 .init = sbs_init,
742 .setup = sbs_setup,
743 .exit = __devexit_p(sbs_exit),
744 },
745
746 /*
747 * SIIG cards.
748 * It is not clear whether these could be collapsed.
749 */
750 {
751 .vendor = PCI_VENDOR_ID_SIIG,
752 .device = PCI_DEVICE_ID_SIIG_1S_10x_550,
753 .subvendor = PCI_ANY_ID,
754 .subdevice = PCI_ANY_ID,
755 .init = pci_siig10x_init,
756 .setup = pci_default_setup,
757 },
758 {
759 .vendor = PCI_VENDOR_ID_SIIG,
760 .device = PCI_DEVICE_ID_SIIG_1S_10x_650,
761 .subvendor = PCI_ANY_ID,
762 .subdevice = PCI_ANY_ID,
763 .init = pci_siig10x_init,
764 .setup = pci_default_setup,
765 },
766 {
767 .vendor = PCI_VENDOR_ID_SIIG,
768 .device = PCI_DEVICE_ID_SIIG_1S_10x_850,
769 .subvendor = PCI_ANY_ID,
770 .subdevice = PCI_ANY_ID,
771 .init = pci_siig10x_init,
772 .setup = pci_default_setup,
773 },
774 {
775 .vendor = PCI_VENDOR_ID_SIIG,
776 .device = PCI_DEVICE_ID_SIIG_2S_10x_550,
777 .subvendor = PCI_ANY_ID,
778 .subdevice = PCI_ANY_ID,
779 .init = pci_siig10x_init,
780 .setup = pci_default_setup,
781 },
782 {
783 .vendor = PCI_VENDOR_ID_SIIG,
784 .device = PCI_DEVICE_ID_SIIG_2S_10x_650,
785 .subvendor = PCI_ANY_ID,
786 .subdevice = PCI_ANY_ID,
787 .init = pci_siig10x_init,
788 .setup = pci_default_setup,
789 },
790 {
791 .vendor = PCI_VENDOR_ID_SIIG,
792 .device = PCI_DEVICE_ID_SIIG_2S_10x_850,
793 .subvendor = PCI_ANY_ID,
794 .subdevice = PCI_ANY_ID,
795 .init = pci_siig10x_init,
796 .setup = pci_default_setup,
797 },
798 {
799 .vendor = PCI_VENDOR_ID_SIIG,
800 .device = PCI_DEVICE_ID_SIIG_4S_10x_550,
801 .subvendor = PCI_ANY_ID,
802 .subdevice = PCI_ANY_ID,
803 .init = pci_siig10x_init,
804 .setup = pci_default_setup,
805 },
806 {
807 .vendor = PCI_VENDOR_ID_SIIG,
808 .device = PCI_DEVICE_ID_SIIG_4S_10x_650,
809 .subvendor = PCI_ANY_ID,
810 .subdevice = PCI_ANY_ID,
811 .init = pci_siig10x_init,
812 .setup = pci_default_setup,
813 },
814 {
815 .vendor = PCI_VENDOR_ID_SIIG,
816 .device = PCI_DEVICE_ID_SIIG_4S_10x_850,
817 .subvendor = PCI_ANY_ID,
818 .subdevice = PCI_ANY_ID,
819 .init = pci_siig10x_init,
820 .setup = pci_default_setup,
821 },
822 {
823 .vendor = PCI_VENDOR_ID_SIIG,
824 .device = PCI_DEVICE_ID_SIIG_1S_20x_550,
825 .subvendor = PCI_ANY_ID,
826 .subdevice = PCI_ANY_ID,
827 .init = pci_siig20x_init,
828 .setup = pci_default_setup,
829 },
830 {
831 .vendor = PCI_VENDOR_ID_SIIG,
832 .device = PCI_DEVICE_ID_SIIG_1S_20x_650,
833 .subvendor = PCI_ANY_ID,
834 .subdevice = PCI_ANY_ID,
835 .init = pci_siig20x_init,
836 .setup = pci_default_setup,
837 },
838 {
839 .vendor = PCI_VENDOR_ID_SIIG,
840 .device = PCI_DEVICE_ID_SIIG_1S_20x_850,
841 .subvendor = PCI_ANY_ID,
842 .subdevice = PCI_ANY_ID,
843 .init = pci_siig20x_init,
844 .setup = pci_default_setup,
845 },
846 {
847 .vendor = PCI_VENDOR_ID_SIIG,
848 .device = PCI_DEVICE_ID_SIIG_2S_20x_550,
849 .subvendor = PCI_ANY_ID,
850 .subdevice = PCI_ANY_ID,
851 .init = pci_siig20x_init,
852 .setup = pci_default_setup,
853 },
854 { .vendor = PCI_VENDOR_ID_SIIG,
855 .device = PCI_DEVICE_ID_SIIG_2S_20x_650,
856 .subvendor = PCI_ANY_ID,
857 .subdevice = PCI_ANY_ID,
858 .init = pci_siig20x_init,
859 .setup = pci_default_setup,
860 },
861 {
862 .vendor = PCI_VENDOR_ID_SIIG,
863 .device = PCI_DEVICE_ID_SIIG_2S_20x_850,
864 .subvendor = PCI_ANY_ID,
865 .subdevice = PCI_ANY_ID,
866 .init = pci_siig20x_init,
867 .setup = pci_default_setup,
868 },
869 {
870 .vendor = PCI_VENDOR_ID_SIIG,
871 .device = PCI_DEVICE_ID_SIIG_4S_20x_550,
872 .subvendor = PCI_ANY_ID,
873 .subdevice = PCI_ANY_ID,
874 .init = pci_siig20x_init,
875 .setup = pci_default_setup,
876 },
877 {
878 .vendor = PCI_VENDOR_ID_SIIG,
879 .device = PCI_DEVICE_ID_SIIG_4S_20x_650,
880 .subvendor = PCI_ANY_ID,
881 .subdevice = PCI_ANY_ID,
882 .init = pci_siig20x_init,
883 .setup = pci_default_setup,
884 },
885 {
886 .vendor = PCI_VENDOR_ID_SIIG,
887 .device = PCI_DEVICE_ID_SIIG_4S_20x_850,
888 .subvendor = PCI_ANY_ID,
889 .subdevice = PCI_ANY_ID,
890 .init = pci_siig20x_init,
891 .setup = pci_default_setup,
892 },
893 /*
894 * Titan cards
895 */
896 {
897 .vendor = PCI_VENDOR_ID_TITAN,
898 .device = PCI_DEVICE_ID_TITAN_400L,
899 .subvendor = PCI_ANY_ID,
900 .subdevice = PCI_ANY_ID,
901 .setup = titan_400l_800l_setup,
902 },
903 {
904 .vendor = PCI_VENDOR_ID_TITAN,
905 .device = PCI_DEVICE_ID_TITAN_800L,
906 .subvendor = PCI_ANY_ID,
907 .subdevice = PCI_ANY_ID,
908 .setup = titan_400l_800l_setup,
909 },
910 /*
911 * Timedia cards
912 */
913 {
914 .vendor = PCI_VENDOR_ID_TIMEDIA,
915 .device = PCI_DEVICE_ID_TIMEDIA_1889,
916 .subvendor = PCI_VENDOR_ID_TIMEDIA,
917 .subdevice = PCI_ANY_ID,
918 .init = pci_timedia_init,
919 .setup = pci_timedia_setup,
920 },
921 {
922 .vendor = PCI_VENDOR_ID_TIMEDIA,
923 .device = PCI_ANY_ID,
924 .subvendor = PCI_ANY_ID,
925 .subdevice = PCI_ANY_ID,
926 .setup = pci_timedia_setup,
927 },
928 /*
929 * Xircom cards
930 */
931 {
932 .vendor = PCI_VENDOR_ID_XIRCOM,
933 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
934 .subvendor = PCI_ANY_ID,
935 .subdevice = PCI_ANY_ID,
936 .init = pci_xircom_init,
937 .setup = pci_default_setup,
938 },
939 /*
940 * Default "match everything" terminator entry
941 */
942 {
943 .vendor = PCI_ANY_ID,
944 .device = PCI_ANY_ID,
945 .subvendor = PCI_ANY_ID,
946 .subdevice = PCI_ANY_ID,
947 .setup = pci_default_setup,
948 }
949 };
950
951 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
952 {
953 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
954 }
955
956 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
957 {
958 struct pci_serial_quirk *quirk;
959
960 for (quirk = pci_serial_quirks; ; quirk++)
961 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
962 quirk_id_matches(quirk->device, dev->device) &&
963 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
964 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
965 break;
966 return quirk;
967 }
968
969 static _INLINE_ int
970 get_pci_irq(struct pci_dev *dev, struct pci_board *board, int idx)
971 {
972 if (board->flags & FL_NOIRQ)
973 return 0;
974 else
975 return dev->irq;
976 }
977
978 /*
979 * This is the configuration table for all of the PCI serial boards
980 * which we support. It is directly indexed by the pci_board_num_t enum
981 * value, which is encoded in the pci_device_id PCI probe table's
982 * driver_data member.
983 *
984 * The makeup of these names are:
985 * pbn_bn{_bt}_n_baud
986 *
987 * bn = PCI BAR number
988 * bt = Index using PCI BARs
989 * n = number of serial ports
990 * baud = baud rate
991 *
992 * Please note: in theory if n = 1, _bt infix should make no difference.
993 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
994 */
995 enum pci_board_num_t {
996 pbn_default = 0,
997
998 pbn_b0_1_115200,
999 pbn_b0_2_115200,
1000 pbn_b0_4_115200,
1001 pbn_b0_5_115200,
1002
1003 pbn_b0_1_921600,
1004 pbn_b0_2_921600,
1005 pbn_b0_4_921600,
1006
1007 pbn_b0_bt_1_115200,
1008 pbn_b0_bt_2_115200,
1009 pbn_b0_bt_8_115200,
1010
1011 pbn_b0_bt_1_460800,
1012 pbn_b0_bt_2_460800,
1013 pbn_b0_bt_4_460800,
1014
1015 pbn_b0_bt_1_921600,
1016 pbn_b0_bt_2_921600,
1017 pbn_b0_bt_4_921600,
1018 pbn_b0_bt_8_921600,
1019
1020 pbn_b1_1_115200,
1021 pbn_b1_2_115200,
1022 pbn_b1_4_115200,
1023 pbn_b1_8_115200,
1024
1025 pbn_b1_1_921600,
1026 pbn_b1_2_921600,
1027 pbn_b1_4_921600,
1028 pbn_b1_8_921600,
1029
1030 pbn_b1_bt_2_921600,
1031
1032 pbn_b1_2_1382400,
1033 pbn_b1_4_1382400,
1034 pbn_b1_8_1382400,
1035
1036 pbn_b2_1_115200,
1037 pbn_b2_8_115200,
1038
1039 pbn_b2_1_460800,
1040 pbn_b2_4_460800,
1041 pbn_b2_8_460800,
1042 pbn_b2_16_460800,
1043
1044 pbn_b2_1_921600,
1045 pbn_b2_4_921600,
1046 pbn_b2_8_921600,
1047
1048 pbn_b2_bt_1_115200,
1049 pbn_b2_bt_2_115200,
1050 pbn_b2_bt_4_115200,
1051
1052 pbn_b2_bt_2_921600,
1053 pbn_b2_bt_4_921600,
1054
1055 pbn_b3_4_115200,
1056 pbn_b3_8_115200,
1057
1058 /*
1059 * Board-specific versions.
1060 */
1061 pbn_panacom,
1062 pbn_panacom2,
1063 pbn_panacom4,
1064 pbn_plx_romulus,
1065 pbn_oxsemi,
1066 pbn_intel_i960,
1067 pbn_sgi_ioc3,
1068 pbn_nec_nile4,
1069 pbn_computone_4,
1070 pbn_computone_6,
1071 pbn_computone_8,
1072 pbn_sbsxrsio,
1073 pbn_exar_XR17C152,
1074 pbn_exar_XR17C154,
1075 pbn_exar_XR17C158,
1076 };
1077
1078 /*
1079 * uart_offset - the space between channels
1080 * reg_shift - describes how the UART registers are mapped
1081 * to PCI memory by the card.
1082 * For example IER register on SBS, Inc. PMC-OctPro is located at
1083 * offset 0x10 from the UART base, while UART_IER is defined as 1
1084 * in include/linux/serial_reg.h,
1085 * see first lines of serial_in() and serial_out() in 8250.c
1086 */
1087
1088 static struct pci_board pci_boards[] __devinitdata = {
1089 [pbn_default] = {
1090 .flags = FL_BASE0,
1091 .num_ports = 1,
1092 .base_baud = 115200,
1093 .uart_offset = 8,
1094 },
1095 [pbn_b0_1_115200] = {
1096 .flags = FL_BASE0,
1097 .num_ports = 1,
1098 .base_baud = 115200,
1099 .uart_offset = 8,
1100 },
1101 [pbn_b0_2_115200] = {
1102 .flags = FL_BASE0,
1103 .num_ports = 2,
1104 .base_baud = 115200,
1105 .uart_offset = 8,
1106 },
1107 [pbn_b0_4_115200] = {
1108 .flags = FL_BASE0,
1109 .num_ports = 4,
1110 .base_baud = 115200,
1111 .uart_offset = 8,
1112 },
1113 [pbn_b0_5_115200] = {
1114 .flags = FL_BASE0,
1115 .num_ports = 5,
1116 .base_baud = 115200,
1117 .uart_offset = 8,
1118 },
1119
1120 [pbn_b0_1_921600] = {
1121 .flags = FL_BASE0,
1122 .num_ports = 1,
1123 .base_baud = 921600,
1124 .uart_offset = 8,
1125 },
1126 [pbn_b0_2_921600] = {
1127 .flags = FL_BASE0,
1128 .num_ports = 2,
1129 .base_baud = 921600,
1130 .uart_offset = 8,
1131 },
1132 [pbn_b0_4_921600] = {
1133 .flags = FL_BASE0,
1134 .num_ports = 4,
1135 .base_baud = 921600,
1136 .uart_offset = 8,
1137 },
1138
1139 [pbn_b0_bt_1_115200] = {
1140 .flags = FL_BASE0|FL_BASE_BARS,
1141 .num_ports = 1,
1142 .base_baud = 115200,
1143 .uart_offset = 8,
1144 },
1145 [pbn_b0_bt_2_115200] = {
1146 .flags = FL_BASE0|FL_BASE_BARS,
1147 .num_ports = 2,
1148 .base_baud = 115200,
1149 .uart_offset = 8,
1150 },
1151 [pbn_b0_bt_8_115200] = {
1152 .flags = FL_BASE0|FL_BASE_BARS,
1153 .num_ports = 8,
1154 .base_baud = 115200,
1155 .uart_offset = 8,
1156 },
1157
1158 [pbn_b0_bt_1_460800] = {
1159 .flags = FL_BASE0|FL_BASE_BARS,
1160 .num_ports = 1,
1161 .base_baud = 460800,
1162 .uart_offset = 8,
1163 },
1164 [pbn_b0_bt_2_460800] = {
1165 .flags = FL_BASE0|FL_BASE_BARS,
1166 .num_ports = 2,
1167 .base_baud = 460800,
1168 .uart_offset = 8,
1169 },
1170 [pbn_b0_bt_4_460800] = {
1171 .flags = FL_BASE0|FL_BASE_BARS,
1172 .num_ports = 4,
1173 .base_baud = 460800,
1174 .uart_offset = 8,
1175 },
1176
1177 [pbn_b0_bt_1_921600] = {
1178 .flags = FL_BASE0|FL_BASE_BARS,
1179 .num_ports = 1,
1180 .base_baud = 921600,
1181 .uart_offset = 8,
1182 },
1183 [pbn_b0_bt_2_921600] = {
1184 .flags = FL_BASE0|FL_BASE_BARS,
1185 .num_ports = 2,
1186 .base_baud = 921600,
1187 .uart_offset = 8,
1188 },
1189 [pbn_b0_bt_4_921600] = {
1190 .flags = FL_BASE0|FL_BASE_BARS,
1191 .num_ports = 4,
1192 .base_baud = 921600,
1193 .uart_offset = 8,
1194 },
1195 [pbn_b0_bt_8_921600] = {
1196 .flags = FL_BASE0|FL_BASE_BARS,
1197 .num_ports = 8,
1198 .base_baud = 921600,
1199 .uart_offset = 8,
1200 },
1201
1202 [pbn_b1_1_115200] = {
1203 .flags = FL_BASE1,
1204 .num_ports = 1,
1205 .base_baud = 115200,
1206 .uart_offset = 8,
1207 },
1208 [pbn_b1_2_115200] = {
1209 .flags = FL_BASE1,
1210 .num_ports = 2,
1211 .base_baud = 115200,
1212 .uart_offset = 8,
1213 },
1214 [pbn_b1_4_115200] = {
1215 .flags = FL_BASE1,
1216 .num_ports = 4,
1217 .base_baud = 115200,
1218 .uart_offset = 8,
1219 },
1220 [pbn_b1_8_115200] = {
1221 .flags = FL_BASE1,
1222 .num_ports = 8,
1223 .base_baud = 115200,
1224 .uart_offset = 8,
1225 },
1226
1227 [pbn_b1_1_921600] = {
1228 .flags = FL_BASE1,
1229 .num_ports = 1,
1230 .base_baud = 921600,
1231 .uart_offset = 8,
1232 },
1233 [pbn_b1_2_921600] = {
1234 .flags = FL_BASE1,
1235 .num_ports = 2,
1236 .base_baud = 921600,
1237 .uart_offset = 8,
1238 },
1239 [pbn_b1_4_921600] = {
1240 .flags = FL_BASE1,
1241 .num_ports = 4,
1242 .base_baud = 921600,
1243 .uart_offset = 8,
1244 },
1245 [pbn_b1_8_921600] = {
1246 .flags = FL_BASE1,
1247 .num_ports = 8,
1248 .base_baud = 921600,
1249 .uart_offset = 8,
1250 },
1251
1252 [pbn_b1_bt_2_921600] = {
1253 .flags = FL_BASE1|FL_BASE_BARS,
1254 .num_ports = 2,
1255 .base_baud = 921600,
1256 .uart_offset = 8,
1257 },
1258
1259 [pbn_b1_2_1382400] = {
1260 .flags = FL_BASE1,
1261 .num_ports = 2,
1262 .base_baud = 1382400,
1263 .uart_offset = 8,
1264 },
1265 [pbn_b1_4_1382400] = {
1266 .flags = FL_BASE1,
1267 .num_ports = 4,
1268 .base_baud = 1382400,
1269 .uart_offset = 8,
1270 },
1271 [pbn_b1_8_1382400] = {
1272 .flags = FL_BASE1,
1273 .num_ports = 8,
1274 .base_baud = 1382400,
1275 .uart_offset = 8,
1276 },
1277
1278 [pbn_b2_1_115200] = {
1279 .flags = FL_BASE2,
1280 .num_ports = 1,
1281 .base_baud = 115200,
1282 .uart_offset = 8,
1283 },
1284 [pbn_b2_8_115200] = {
1285 .flags = FL_BASE2,
1286 .num_ports = 8,
1287 .base_baud = 115200,
1288 .uart_offset = 8,
1289 },
1290
1291 [pbn_b2_1_460800] = {
1292 .flags = FL_BASE2,
1293 .num_ports = 1,
1294 .base_baud = 460800,
1295 .uart_offset = 8,
1296 },
1297 [pbn_b2_4_460800] = {
1298 .flags = FL_BASE2,
1299 .num_ports = 4,
1300 .base_baud = 460800,
1301 .uart_offset = 8,
1302 },
1303 [pbn_b2_8_460800] = {
1304 .flags = FL_BASE2,
1305 .num_ports = 8,
1306 .base_baud = 460800,
1307 .uart_offset = 8,
1308 },
1309 [pbn_b2_16_460800] = {
1310 .flags = FL_BASE2,
1311 .num_ports = 16,
1312 .base_baud = 460800,
1313 .uart_offset = 8,
1314 },
1315
1316 [pbn_b2_1_921600] = {
1317 .flags = FL_BASE2,
1318 .num_ports = 1,
1319 .base_baud = 921600,
1320 .uart_offset = 8,
1321 },
1322 [pbn_b2_4_921600] = {
1323 .flags = FL_BASE2,
1324 .num_ports = 4,
1325 .base_baud = 921600,
1326 .uart_offset = 8,
1327 },
1328 [pbn_b2_8_921600] = {
1329 .flags = FL_BASE2,
1330 .num_ports = 8,
1331 .base_baud = 921600,
1332 .uart_offset = 8,
1333 },
1334
1335 [pbn_b2_bt_1_115200] = {
1336 .flags = FL_BASE2|FL_BASE_BARS,
1337 .num_ports = 1,
1338 .base_baud = 115200,
1339 .uart_offset = 8,
1340 },
1341 [pbn_b2_bt_2_115200] = {
1342 .flags = FL_BASE2|FL_BASE_BARS,
1343 .num_ports = 2,
1344 .base_baud = 115200,
1345 .uart_offset = 8,
1346 },
1347 [pbn_b2_bt_4_115200] = {
1348 .flags = FL_BASE2|FL_BASE_BARS,
1349 .num_ports = 4,
1350 .base_baud = 115200,
1351 .uart_offset = 8,
1352 },
1353
1354 [pbn_b2_bt_2_921600] = {
1355 .flags = FL_BASE2|FL_BASE_BARS,
1356 .num_ports = 2,
1357 .base_baud = 921600,
1358 .uart_offset = 8,
1359 },
1360 [pbn_b2_bt_4_921600] = {
1361 .flags = FL_BASE2|FL_BASE_BARS,
1362 .num_ports = 4,
1363 .base_baud = 921600,
1364 .uart_offset = 8,
1365 },
1366
1367 [pbn_b3_4_115200] = {
1368 .flags = FL_BASE3,
1369 .num_ports = 4,
1370 .base_baud = 115200,
1371 .uart_offset = 8,
1372 },
1373 [pbn_b3_8_115200] = {
1374 .flags = FL_BASE3,
1375 .num_ports = 8,
1376 .base_baud = 115200,
1377 .uart_offset = 8,
1378 },
1379
1380 /*
1381 * Entries following this are board-specific.
1382 */
1383
1384 /*
1385 * Panacom - IOMEM
1386 */
1387 [pbn_panacom] = {
1388 .flags = FL_BASE2,
1389 .num_ports = 2,
1390 .base_baud = 921600,
1391 .uart_offset = 0x400,
1392 .reg_shift = 7,
1393 },
1394 [pbn_panacom2] = {
1395 .flags = FL_BASE2|FL_BASE_BARS,
1396 .num_ports = 2,
1397 .base_baud = 921600,
1398 .uart_offset = 0x400,
1399 .reg_shift = 7,
1400 },
1401 [pbn_panacom4] = {
1402 .flags = FL_BASE2|FL_BASE_BARS,
1403 .num_ports = 4,
1404 .base_baud = 921600,
1405 .uart_offset = 0x400,
1406 .reg_shift = 7,
1407 },
1408
1409 /* I think this entry is broken - the first_offset looks wrong --rmk */
1410 [pbn_plx_romulus] = {
1411 .flags = FL_BASE2,
1412 .num_ports = 4,
1413 .base_baud = 921600,
1414 .uart_offset = 8 << 2,
1415 .reg_shift = 2,
1416 .first_offset = 0x03,
1417 },
1418
1419 /*
1420 * This board uses the size of PCI Base region 0 to
1421 * signal now many ports are available
1422 */
1423 [pbn_oxsemi] = {
1424 .flags = FL_BASE0|FL_REGION_SZ_CAP,
1425 .num_ports = 32,
1426 .base_baud = 115200,
1427 .uart_offset = 8,
1428 },
1429
1430 /*
1431 * EKF addition for i960 Boards form EKF with serial port.
1432 * Max 256 ports.
1433 */
1434 [pbn_intel_i960] = {
1435 .flags = FL_BASE0,
1436 .num_ports = 32,
1437 .base_baud = 921600,
1438 .uart_offset = 8 << 2,
1439 .reg_shift = 2,
1440 .first_offset = 0x10000,
1441 },
1442 [pbn_sgi_ioc3] = {
1443 .flags = FL_BASE0|FL_NOIRQ,
1444 .num_ports = 1,
1445 .base_baud = 458333,
1446 .uart_offset = 8,
1447 .reg_shift = 0,
1448 .first_offset = 0x20178,
1449 },
1450
1451 /*
1452 * NEC Vrc-5074 (Nile 4) builtin UART.
1453 */
1454 [pbn_nec_nile4] = {
1455 .flags = FL_BASE0,
1456 .num_ports = 1,
1457 .base_baud = 520833,
1458 .uart_offset = 8 << 3,
1459 .reg_shift = 3,
1460 .first_offset = 0x300,
1461 },
1462
1463 /*
1464 * Computone - uses IOMEM.
1465 */
1466 [pbn_computone_4] = {
1467 .flags = FL_BASE0,
1468 .num_ports = 4,
1469 .base_baud = 921600,
1470 .uart_offset = 0x40,
1471 .reg_shift = 2,
1472 .first_offset = 0x200,
1473 },
1474 [pbn_computone_6] = {
1475 .flags = FL_BASE0,
1476 .num_ports = 6,
1477 .base_baud = 921600,
1478 .uart_offset = 0x40,
1479 .reg_shift = 2,
1480 .first_offset = 0x200,
1481 },
1482 [pbn_computone_8] = {
1483 .flags = FL_BASE0,
1484 .num_ports = 8,
1485 .base_baud = 921600,
1486 .uart_offset = 0x40,
1487 .reg_shift = 2,
1488 .first_offset = 0x200,
1489 },
1490 [pbn_sbsxrsio] = {
1491 .flags = FL_BASE0,
1492 .num_ports = 8,
1493 .base_baud = 460800,
1494 .uart_offset = 256,
1495 .reg_shift = 4,
1496 },
1497 /*
1498 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1499 * Only basic 16550A support.
1500 * XR17C15[24] are not tested, but they should work.
1501 */
1502 [pbn_exar_XR17C152] = {
1503 .flags = FL_BASE0,
1504 .num_ports = 2,
1505 .base_baud = 921600,
1506 .uart_offset = 0x200,
1507 },
1508 [pbn_exar_XR17C154] = {
1509 .flags = FL_BASE0,
1510 .num_ports = 4,
1511 .base_baud = 921600,
1512 .uart_offset = 0x200,
1513 },
1514 [pbn_exar_XR17C158] = {
1515 .flags = FL_BASE0,
1516 .num_ports = 8,
1517 .base_baud = 921600,
1518 .uart_offset = 0x200,
1519 },
1520 };
1521
1522 /*
1523 * Given a complete unknown PCI device, try to use some heuristics to
1524 * guess what the configuration might be, based on the pitiful PCI
1525 * serial specs. Returns 0 on success, 1 on failure.
1526 */
1527 static int __devinit
1528 serial_pci_guess_board(struct pci_dev *dev, struct pci_board *board)
1529 {
1530 int num_iomem, num_port, first_port = -1, i;
1531
1532 /*
1533 * If it is not a communications device or the programming
1534 * interface is greater than 6, give up.
1535 *
1536 * (Should we try to make guesses for multiport serial devices
1537 * later?)
1538 */
1539 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1540 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1541 (dev->class & 0xff) > 6)
1542 return -ENODEV;
1543
1544 num_iomem = num_port = 0;
1545 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1546 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1547 num_port++;
1548 if (first_port == -1)
1549 first_port = i;
1550 }
1551 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1552 num_iomem++;
1553 }
1554
1555 /*
1556 * If there is 1 or 0 iomem regions, and exactly one port,
1557 * use it. We guess the number of ports based on the IO
1558 * region size.
1559 */
1560 if (num_iomem <= 1 && num_port == 1) {
1561 board->flags = first_port;
1562 board->num_ports = pci_resource_len(dev, first_port) / 8;
1563 return 0;
1564 }
1565
1566 /*
1567 * Now guess if we've got a board which indexes by BARs.
1568 * Each IO BAR should be 8 bytes, and they should follow
1569 * consecutively.
1570 */
1571 first_port = -1;
1572 num_port = 0;
1573 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1574 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1575 pci_resource_len(dev, i) == 8 &&
1576 (first_port == -1 || (first_port + num_port) == i)) {
1577 num_port++;
1578 if (first_port == -1)
1579 first_port = i;
1580 }
1581 }
1582
1583 if (num_port > 1) {
1584 board->flags = first_port | FL_BASE_BARS;
1585 board->num_ports = num_port;
1586 return 0;
1587 }
1588
1589 return -ENODEV;
1590 }
1591
1592 static inline int
1593 serial_pci_matches(struct pci_board *board, struct pci_board *guessed)
1594 {
1595 return
1596 board->num_ports == guessed->num_ports &&
1597 board->base_baud == guessed->base_baud &&
1598 board->uart_offset == guessed->uart_offset &&
1599 board->reg_shift == guessed->reg_shift &&
1600 board->first_offset == guessed->first_offset;
1601 }
1602
1603 /*
1604 * Probe one serial board. Unfortunately, there is no rhyme nor reason
1605 * to the arrangement of serial ports on a PCI card.
1606 */
1607 static int __devinit
1608 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1609 {
1610 struct serial_private *priv;
1611 struct pci_board *board, tmp;
1612 struct pci_serial_quirk *quirk;
1613 struct serial_struct serial_req;
1614 int rc, nr_ports, i;
1615
1616 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1617 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1618 ent->driver_data);
1619 return -EINVAL;
1620 }
1621
1622 board = &pci_boards[ent->driver_data];
1623
1624 rc = pci_enable_device(dev);
1625 if (rc)
1626 return rc;
1627
1628 if (ent->driver_data == pbn_default) {
1629 /*
1630 * Use a copy of the pci_board entry for this;
1631 * avoid changing entries in the table.
1632 */
1633 memcpy(&tmp, board, sizeof(struct pci_board));
1634 board = &tmp;
1635
1636 /*
1637 * We matched one of our class entries. Try to
1638 * determine the parameters of this board.
1639 */
1640 rc = serial_pci_guess_board(dev, board);
1641 if (rc)
1642 goto disable;
1643 } else {
1644 /*
1645 * We matched an explicit entry. If we are able to
1646 * detect this boards settings with our heuristic,
1647 * then we no longer need this entry.
1648 */
1649 memcpy(&tmp, &pci_boards[pbn_default], sizeof(struct pci_board));
1650 rc = serial_pci_guess_board(dev, &tmp);
1651 if (rc == 0 && serial_pci_matches(board, &tmp))
1652 moan_device("Redundant entry in serial pci_table.",
1653 dev);
1654 }
1655
1656 nr_ports = board->num_ports;
1657
1658 /*
1659 * Find an init and setup quirks.
1660 */
1661 quirk = find_quirk(dev);
1662
1663 /*
1664 * Run the new-style initialization function.
1665 * The initialization function returns:
1666 * <0 - error
1667 * 0 - use board->num_ports
1668 * >0 - number of ports
1669 */
1670 if (quirk->init) {
1671 rc = quirk->init(dev);
1672 if (rc < 0)
1673 goto disable;
1674 if (rc)
1675 nr_ports = rc;
1676 }
1677
1678 priv = kmalloc(sizeof(struct serial_private) +
1679 sizeof(unsigned int) * nr_ports,
1680 GFP_KERNEL);
1681 if (!priv) {
1682 rc = -ENOMEM;
1683 goto deinit;
1684 }
1685
1686 memset(priv, 0, sizeof(struct serial_private) +
1687 sizeof(unsigned int) * nr_ports);
1688
1689 priv->quirk = quirk;
1690 pci_set_drvdata(dev, priv);
1691
1692 for (i = 0; i < nr_ports; i++) {
1693 memset(&serial_req, 0, sizeof(serial_req));
1694 serial_req.flags = UPF_SKIP_TEST | UPF_AUTOPROBE |
1695 UPF_SHARE_IRQ;
1696 serial_req.baud_base = board->base_baud;
1697 serial_req.irq = get_pci_irq(dev, board, i);
1698 if (quirk->setup(dev, board, &serial_req, i))
1699 break;
1700 #ifdef SERIAL_DEBUG_PCI
1701 printk("Setup PCI port: port %x, irq %d, type %d\n",
1702 serial_req.port, serial_req.irq, serial_req.io_type);
1703 #endif
1704
1705 priv->line[i] = register_serial(&serial_req);
1706 if (priv->line[i] < 0) {
1707 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1708 break;
1709 }
1710 }
1711
1712 priv->nr = i;
1713
1714 return 0;
1715
1716 deinit:
1717 if (quirk->exit)
1718 quirk->exit(dev);
1719 disable:
1720 pci_disable_device(dev);
1721 return rc;
1722 }
1723
1724 static void __devexit pciserial_remove_one(struct pci_dev *dev)
1725 {
1726 struct serial_private *priv = pci_get_drvdata(dev);
1727
1728 pci_set_drvdata(dev, NULL);
1729
1730 if (priv) {
1731 struct pci_serial_quirk *quirk;
1732 int i;
1733
1734 for (i = 0; i < priv->nr; i++)
1735 unregister_serial(priv->line[i]);
1736
1737 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1738 if (priv->remapped_bar[i])
1739 iounmap(priv->remapped_bar[i]);
1740 priv->remapped_bar[i] = NULL;
1741 }
1742
1743 /*
1744 * Find the exit quirks.
1745 */
1746 quirk = find_quirk(dev);
1747 if (quirk->exit)
1748 quirk->exit(dev);
1749
1750 pci_disable_device(dev);
1751
1752 kfree(priv);
1753 }
1754 }
1755
1756 static int pciserial_suspend_one(struct pci_dev *dev, u32 state)
1757 {
1758 struct serial_private *priv = pci_get_drvdata(dev);
1759
1760 if (priv) {
1761 int i;
1762
1763 for (i = 0; i < priv->nr; i++)
1764 serial8250_suspend_port(priv->line[i]);
1765 }
1766 return 0;
1767 }
1768
1769 static int pciserial_resume_one(struct pci_dev *dev)
1770 {
1771 struct serial_private *priv = pci_get_drvdata(dev);
1772
1773 if (priv) {
1774 int i;
1775
1776 /*
1777 * Ensure that the board is correctly configured.
1778 */
1779 if (priv->quirk->init)
1780 priv->quirk->init(dev);
1781
1782 for (i = 0; i < priv->nr; i++)
1783 serial8250_resume_port(priv->line[i]);
1784 }
1785 return 0;
1786 }
1787
1788 static struct pci_device_id serial_pci_tbl[] = {
1789 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1790 PCI_SUBVENDOR_ID_CONNECT_TECH,
1791 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1792 pbn_b1_8_1382400 },
1793 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1794 PCI_SUBVENDOR_ID_CONNECT_TECH,
1795 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1796 pbn_b1_4_1382400 },
1797 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1798 PCI_SUBVENDOR_ID_CONNECT_TECH,
1799 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1800 pbn_b1_2_1382400 },
1801 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1802 PCI_SUBVENDOR_ID_CONNECT_TECH,
1803 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1804 pbn_b1_8_1382400 },
1805 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1806 PCI_SUBVENDOR_ID_CONNECT_TECH,
1807 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1808 pbn_b1_4_1382400 },
1809 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1810 PCI_SUBVENDOR_ID_CONNECT_TECH,
1811 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1812 pbn_b1_2_1382400 },
1813 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1814 PCI_SUBVENDOR_ID_CONNECT_TECH,
1815 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
1816 pbn_b1_8_921600 },
1817 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1818 PCI_SUBVENDOR_ID_CONNECT_TECH,
1819 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
1820 pbn_b1_8_921600 },
1821 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1822 PCI_SUBVENDOR_ID_CONNECT_TECH,
1823 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
1824 pbn_b1_4_921600 },
1825 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1826 PCI_SUBVENDOR_ID_CONNECT_TECH,
1827 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
1828 pbn_b1_4_921600 },
1829 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1830 PCI_SUBVENDOR_ID_CONNECT_TECH,
1831 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
1832 pbn_b1_2_921600 },
1833 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1834 PCI_SUBVENDOR_ID_CONNECT_TECH,
1835 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
1836 pbn_b1_8_921600 },
1837 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1838 PCI_SUBVENDOR_ID_CONNECT_TECH,
1839 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
1840 pbn_b1_8_921600 },
1841 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1842 PCI_SUBVENDOR_ID_CONNECT_TECH,
1843 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
1844 pbn_b1_4_921600 },
1845
1846 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
1847 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1848 pbn_b2_bt_1_115200 },
1849 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
1850 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1851 pbn_b2_bt_2_115200 },
1852 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
1853 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1854 pbn_b2_bt_4_115200 },
1855 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
1856 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1857 pbn_b2_bt_2_115200 },
1858 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
1859 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1860 pbn_b2_bt_4_115200 },
1861 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
1862 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1863 pbn_b2_8_115200 },
1864
1865 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
1866 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1867 pbn_b2_bt_2_115200 },
1868 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
1869 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1870 pbn_b2_bt_2_921600 },
1871 /*
1872 * VScom SPCOM800, from sl@s.pl
1873 */
1874 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
1875 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1876 pbn_b2_8_921600 },
1877 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
1878 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1879 pbn_b2_4_921600 },
1880 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1881 PCI_SUBVENDOR_ID_KEYSPAN,
1882 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
1883 pbn_panacom },
1884 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
1885 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1886 pbn_panacom4 },
1887 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
1888 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1889 pbn_panacom2 },
1890 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1891 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1892 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1893 pbn_b2_4_460800 },
1894 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1895 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1896 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1897 pbn_b2_8_460800 },
1898 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1899 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1900 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1901 pbn_b2_16_460800 },
1902 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1903 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1904 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1905 pbn_b2_16_460800 },
1906 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1907 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1908 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1909 pbn_b2_4_460800 },
1910 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1911 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1912 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1913 pbn_b2_8_460800 },
1914 /*
1915 * Megawolf Romulus PCI Serial Card, from Mike Hudson
1916 * (Exoray@isys.ca)
1917 */
1918 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
1919 0x10b5, 0x106a, 0, 0,
1920 pbn_plx_romulus },
1921 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
1922 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1923 pbn_b1_4_115200 },
1924 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
1925 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1926 pbn_b1_2_115200 },
1927 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
1928 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1929 pbn_b1_8_115200 },
1930 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
1931 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1932 pbn_b1_8_115200 },
1933 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
1934 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
1935 pbn_b0_4_921600 },
1936 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1937 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1938 pbn_b0_4_115200 },
1939 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
1940 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1941 pbn_b0_bt_2_921600 },
1942
1943 /*
1944 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
1945 * from skokodyn@yahoo.com
1946 */
1947 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1948 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
1949 pbn_sbsxrsio },
1950 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1951 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
1952 pbn_sbsxrsio },
1953 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1954 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
1955 pbn_sbsxrsio },
1956 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1957 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
1958 pbn_sbsxrsio },
1959
1960 /*
1961 * Digitan DS560-558, from jimd@esoft.com
1962 */
1963 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
1964 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1965 pbn_b1_1_115200 },
1966
1967 /*
1968 * Titan Electronic cards
1969 * The 400L and 800L have a custom setup quirk.
1970 */
1971 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
1972 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1973 pbn_b0_1_921600 },
1974 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
1975 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1976 pbn_b0_2_921600 },
1977 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
1978 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1979 pbn_b0_4_921600 },
1980 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
1981 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1982 pbn_b0_4_921600 },
1983 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
1984 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1985 pbn_b1_1_921600 },
1986 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
1987 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1988 pbn_b1_bt_2_921600 },
1989 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
1990 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1991 pbn_b0_bt_4_921600 },
1992 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
1993 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1994 pbn_b0_bt_8_921600 },
1995
1996 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
1997 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1998 pbn_b2_1_460800 },
1999 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2000 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2001 pbn_b2_1_460800 },
2002 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2003 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2004 pbn_b2_1_460800 },
2005 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
2006 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2007 pbn_b2_bt_2_921600 },
2008 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
2009 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2010 pbn_b2_bt_2_921600 },
2011 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
2012 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2013 pbn_b2_bt_2_921600 },
2014 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
2015 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2016 pbn_b2_bt_4_921600 },
2017 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
2018 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2019 pbn_b2_bt_4_921600 },
2020 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2021 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2022 pbn_b2_bt_4_921600 },
2023 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2024 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2025 pbn_b0_1_921600 },
2026 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2027 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2028 pbn_b0_1_921600 },
2029 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2030 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2031 pbn_b0_1_921600 },
2032 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2033 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2034 pbn_b0_bt_2_921600 },
2035 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2036 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2037 pbn_b0_bt_2_921600 },
2038 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2039 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2040 pbn_b0_bt_2_921600 },
2041 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2042 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2043 pbn_b0_bt_4_921600 },
2044 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2045 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2046 pbn_b0_bt_4_921600 },
2047 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2048 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2049 pbn_b0_bt_4_921600 },
2050
2051 /*
2052 * Computone devices submitted by Doug McNash dmcnash@computone.com
2053 */
2054 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2055 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2056 0, 0, pbn_computone_4 },
2057 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2058 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2059 0, 0, pbn_computone_8 },
2060 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2061 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2062 0, 0, pbn_computone_6 },
2063
2064 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2065 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2066 pbn_oxsemi },
2067 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2068 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2069 pbn_b0_bt_1_921600 },
2070
2071 /*
2072 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2073 */
2074 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2075 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2076 pbn_b0_bt_8_115200 },
2077 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2078 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2079 pbn_b0_bt_8_115200 },
2080
2081 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2082 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2083 pbn_b0_bt_2_115200 },
2084 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2085 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2086 pbn_b0_bt_2_115200 },
2087 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2088 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2089 pbn_b0_bt_2_115200 },
2090 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2091 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2092 pbn_b0_bt_4_460800 },
2093 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2094 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2095 pbn_b0_bt_4_460800 },
2096 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2097 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2098 pbn_b0_bt_2_460800 },
2099 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2100 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2101 pbn_b0_bt_2_460800 },
2102 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2103 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2104 pbn_b0_bt_2_460800 },
2105 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2106 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2107 pbn_b0_bt_1_115200 },
2108 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2109 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2110 pbn_b0_bt_1_460800 },
2111
2112 /*
2113 * RAStel 2 port modem, gerg@moreton.com.au
2114 */
2115 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2116 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2117 pbn_b2_bt_2_115200 },
2118
2119 /*
2120 * EKF addition for i960 Boards form EKF with serial port
2121 */
2122 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2123 0xE4BF, PCI_ANY_ID, 0, 0,
2124 pbn_intel_i960 },
2125
2126 /*
2127 * Xircom Cardbus/Ethernet combos
2128 */
2129 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2130 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2131 pbn_b0_1_115200 },
2132 /*
2133 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2134 */
2135 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2136 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2137 pbn_b0_1_115200 },
2138
2139 /*
2140 * Untested PCI modems, sent in from various folks...
2141 */
2142
2143 /*
2144 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2145 */
2146 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
2147 0x1048, 0x1500, 0, 0,
2148 pbn_b1_1_115200 },
2149
2150 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2151 0xFF00, 0, 0, 0,
2152 pbn_sgi_ioc3 },
2153
2154 /*
2155 * HP Diva card
2156 */
2157 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2158 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2159 pbn_b0_5_115200 },
2160 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2161 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2162 pbn_b2_1_115200 },
2163
2164 /*
2165 * NEC Vrc-5074 (Nile 4) builtin UART.
2166 */
2167 { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4,
2168 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2169 pbn_nec_nile4 },
2170
2171 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2172 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2173 pbn_b3_4_115200 },
2174 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2175 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2176 pbn_b3_8_115200 },
2177
2178 /*
2179 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2180 */
2181 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2182 PCI_ANY_ID, PCI_ANY_ID,
2183 0,
2184 0, pbn_exar_XR17C152 },
2185 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2186 PCI_ANY_ID, PCI_ANY_ID,
2187 0,
2188 0, pbn_exar_XR17C154 },
2189 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2190 PCI_ANY_ID, PCI_ANY_ID,
2191 0,
2192 0, pbn_exar_XR17C158 },
2193
2194 /*
2195 * These entries match devices with class COMMUNICATION_SERIAL,
2196 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2197 */
2198 { PCI_ANY_ID, PCI_ANY_ID,
2199 PCI_ANY_ID, PCI_ANY_ID,
2200 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2201 0xffff00, pbn_default },
2202 { PCI_ANY_ID, PCI_ANY_ID,
2203 PCI_ANY_ID, PCI_ANY_ID,
2204 PCI_CLASS_COMMUNICATION_MODEM << 8,
2205 0xffff00, pbn_default },
2206 { PCI_ANY_ID, PCI_ANY_ID,
2207 PCI_ANY_ID, PCI_ANY_ID,
2208 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2209 0xffff00, pbn_default },
2210 { 0, }
2211 };
2212
2213 static struct pci_driver serial_pci_driver = {
2214 .name = "serial",
2215 .probe = pciserial_init_one,
2216 .remove = __devexit_p(pciserial_remove_one),
2217 .suspend = pciserial_suspend_one,
2218 .resume = pciserial_resume_one,
2219 .id_table = serial_pci_tbl,
2220 };
2221
2222 static int __init serial8250_pci_init(void)
2223 {
2224 return pci_module_init(&serial_pci_driver);
2225 }
2226
2227 static void __exit serial8250_pci_exit(void)
2228 {
2229 pci_unregister_driver(&serial_pci_driver);
2230 }
2231
2232 module_init(serial8250_pci_init);
2233 module_exit(serial8250_pci_exit);
2234
2235 MODULE_LICENSE("GPL");
2236 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2237 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
MOXA 2.6.9 from sdlinux-moxaart.tgz