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MOXA linux-2.6.x / linux-2.6.9-uc0 from sdlinux-moxaart.tgz
[linux-2.6.9-moxart.git] / drivers / serial / pxa.c
blob3a7ab51d20cedbfa8b0811fa0a0532c741c771ff
1 /*
2 * linux/drivers/serial/pxa.c
3 *
4 * Based on drivers/serial/8250.c by Russell King.
5 *
6 * Author: Nicolas Pitre
7 * Created: Feb 20, 2003
8 * Copyright: (C) 2003 Monta Vista Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * Note 1: This driver is made separate from the already too overloaded
16 * 8250.c because it needs some kirks of its own and that'll make it
17 * easier to add DMA support.
18 *
19 * Note 2: I'm too sick of device allocation policies for serial ports.
20 * If someone else wants to request an "official" allocation of major/minor
21 * for this driver please be my guest. And don't forget that new hardware
22 * to come from Intel might have more than 3 or 4 of those UARTs. Let's
23 * hope for a better port registration and dynamic device allocation scheme
24 * with the serial core maintainer satisfaction to appear soon.
25 */
26
27 #include <linux/config.h>
28 #include <linux/module.h>
29 #include <linux/tty.h>
30 #include <linux/ioport.h>
31 #include <linux/init.h>
32 #include <linux/console.h>
33 #include <linux/sysrq.h>
34 #include <linux/serial_reg.h>
35 #include <linux/circ_buf.h>
36 #include <linux/delay.h>
37 #include <linux/interrupt.h>
38 #include <linux/device.h>
39
40 #include <asm/io.h>
41 #include <asm/hardware.h>
42 #include <asm/irq.h>
43 #include <asm/arch/pxa-regs.h>
44
45 #if defined(CONFIG_SERIAL_PXA_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
46 #define SUPPORT_SYSRQ
47 #endif
48
49 #include <linux/serial_core.h>
50
51
52 struct uart_pxa_port {
53 struct uart_port port;
54 unsigned char ier;
55 unsigned char lcr;
56 unsigned char mcr;
57 unsigned int lsr_break_flag;
58 unsigned int cken;
59 char *name;
60 };
61
62 static inline unsigned int serial_in(struct uart_pxa_port *up, int offset)
63 {
64 offset <<= 2;
65 return readl(up->port.membase + offset);
66 }
67
68 static inline void serial_out(struct uart_pxa_port *up, int offset, int value)
69 {
70 offset <<= 2;
71 writel(value, up->port.membase + offset);
72 }
73
74 static void serial_pxa_enable_ms(struct uart_port *port)
75 {
76 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
77
78 up->ier |= UART_IER_MSI;
79 serial_out(up, UART_IER, up->ier);
80 }
81
82 static void serial_pxa_stop_tx(struct uart_port *port, unsigned int tty_stop)
83 {
84 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
85
86 if (up->ier & UART_IER_THRI) {
87 up->ier &= ~UART_IER_THRI;
88 serial_out(up, UART_IER, up->ier);
89 }
90 }
91
92 static void serial_pxa_stop_rx(struct uart_port *port)
93 {
94 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
95
96 up->ier &= ~UART_IER_RLSI;
97 up->port.read_status_mask &= ~UART_LSR_DR;
98 serial_out(up, UART_IER, up->ier);
99 }
100
101 static inline void
102 receive_chars(struct uart_pxa_port *up, int *status, struct pt_regs *regs)
103 {
104 struct tty_struct *tty = up->port.info->tty;
105 unsigned char ch;
106 int max_count = 256;
107
108 do {
109 if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) {
110 /*
111 * FIXME: Deadlock can happen here if we're a
112 * low-latency port. We're holding the per-port
113 * spinlock, and we call flush_to_ldisc->
114 * n_tty_receive_buf->n_tty_receive_char->
115 * opost->uart_put_char.
116 */
117 tty->flip.work.func((void *)tty);
118 if (tty->flip.count >= TTY_FLIPBUF_SIZE)
119 return; // if TTY_DONT_FLIP is set
120 }
121 ch = serial_in(up, UART_RX);
122 *tty->flip.char_buf_ptr = ch;
123 *tty->flip.flag_buf_ptr = TTY_NORMAL;
124 up->port.icount.rx++;
125
126 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
127 UART_LSR_FE | UART_LSR_OE))) {
128 /*
129 * For statistics only
130 */
131 if (*status & UART_LSR_BI) {
132 *status &= ~(UART_LSR_FE | UART_LSR_PE);
133 up->port.icount.brk++;
134 /*
135 * We do the SysRQ and SAK checking
136 * here because otherwise the break
137 * may get masked by ignore_status_mask
138 * or read_status_mask.
139 */
140 if (uart_handle_break(&up->port))
141 goto ignore_char;
142 } else if (*status & UART_LSR_PE)
143 up->port.icount.parity++;
144 else if (*status & UART_LSR_FE)
145 up->port.icount.frame++;
146 if (*status & UART_LSR_OE)
147 up->port.icount.overrun++;
148
149 /*
150 * Mask off conditions which should be ignored.
151 */
152 *status &= up->port.read_status_mask;
153
154 #ifdef CONFIG_SERIAL_PXA_CONSOLE
155 if (up->port.line == up->port.cons->index) {
156 /* Recover the break flag from console xmit */
157 *status |= up->lsr_break_flag;
158 up->lsr_break_flag = 0;
159 }
160 #endif
161 if (*status & UART_LSR_BI) {
162 *tty->flip.flag_buf_ptr = TTY_BREAK;
163 } else if (*status & UART_LSR_PE)
164 *tty->flip.flag_buf_ptr = TTY_PARITY;
165 else if (*status & UART_LSR_FE)
166 *tty->flip.flag_buf_ptr = TTY_FRAME;
167 }
168 if (uart_handle_sysrq_char(&up->port, ch, regs))
169 goto ignore_char;
170 if ((*status & up->port.ignore_status_mask) == 0) {
171 tty->flip.flag_buf_ptr++;
172 tty->flip.char_buf_ptr++;
173 tty->flip.count++;
174 }
175 if ((*status & UART_LSR_OE) &&
176 tty->flip.count < TTY_FLIPBUF_SIZE) {
177 /*
178 * Overrun is special, since it's reported
179 * immediately, and doesn't affect the current
180 * character.
181 */
182 *tty->flip.flag_buf_ptr = TTY_OVERRUN;
183 tty->flip.flag_buf_ptr++;
184 tty->flip.char_buf_ptr++;
185 tty->flip.count++;
186 }
187 ignore_char:
188 *status = serial_in(up, UART_LSR);
189 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
190 tty_flip_buffer_push(tty);
191 }
192
193 static void transmit_chars(struct uart_pxa_port *up)
194 {
195 struct circ_buf *xmit = &up->port.info->xmit;
196 int count;
197
198 if (up->port.x_char) {
199 serial_out(up, UART_TX, up->port.x_char);
200 up->port.icount.tx++;
201 up->port.x_char = 0;
202 return;
203 }
204 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
205 serial_pxa_stop_tx(&up->port, 0);
206 return;
207 }
208
209 count = up->port.fifosize / 2;
210 do {
211 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
212 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
213 up->port.icount.tx++;
214 if (uart_circ_empty(xmit))
215 break;
216 } while (--count > 0);
217
218 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
219 uart_write_wakeup(&up->port);
220
221
222 if (uart_circ_empty(xmit))
223 serial_pxa_stop_tx(&up->port, 0);
224 }
225
226 static void serial_pxa_start_tx(struct uart_port *port, unsigned int tty_start)
227 {
228 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
229
230 if (!(up->ier & UART_IER_THRI)) {
231 up->ier |= UART_IER_THRI;
232 serial_out(up, UART_IER, up->ier);
233 }
234 }
235
236 static inline void check_modem_status(struct uart_pxa_port *up)
237 {
238 int status;
239
240 status = serial_in(up, UART_MSR);
241
242 if ((status & UART_MSR_ANY_DELTA) == 0)
243 return;
244
245 if (status & UART_MSR_TERI)
246 up->port.icount.rng++;
247 if (status & UART_MSR_DDSR)
248 up->port.icount.dsr++;
249 if (status & UART_MSR_DDCD)
250 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
251 if (status & UART_MSR_DCTS)
252 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
253
254 wake_up_interruptible(&up->port.info->delta_msr_wait);
255 }
256
257 /*
258 * This handles the interrupt from one port.
259 */
260 static inline irqreturn_t
261 serial_pxa_irq(int irq, void *dev_id, struct pt_regs *regs)
262 {
263 struct uart_pxa_port *up = (struct uart_pxa_port *)dev_id;
264 unsigned int iir, lsr;
265
266 iir = serial_in(up, UART_IIR);
267 if (iir & UART_IIR_NO_INT)
268 return IRQ_NONE;
269 lsr = serial_in(up, UART_LSR);
270 if (lsr & UART_LSR_DR)
271 receive_chars(up, &lsr, regs);
272 check_modem_status(up);
273 if (lsr & UART_LSR_THRE)
274 transmit_chars(up);
275 return IRQ_HANDLED;
276 }
277
278 static unsigned int serial_pxa_tx_empty(struct uart_port *port)
279 {
280 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
281 unsigned long flags;
282 unsigned int ret;
283
284 spin_lock_irqsave(&up->port.lock, flags);
285 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
286 spin_unlock_irqrestore(&up->port.lock, flags);
287
288 return ret;
289 }
290
291 static unsigned int serial_pxa_get_mctrl(struct uart_port *port)
292 {
293 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
294 unsigned long flags;
295 unsigned char status;
296 unsigned int ret;
297
298 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
299 spin_lock_irqsave(&up->port.lock, flags);
300 status = serial_in(up, UART_MSR);
301 spin_unlock_irqrestore(&up->port.lock, flags);
302
303 ret = 0;
304 if (status & UART_MSR_DCD)
305 ret |= TIOCM_CAR;
306 if (status & UART_MSR_RI)
307 ret |= TIOCM_RNG;
308 if (status & UART_MSR_DSR)
309 ret |= TIOCM_DSR;
310 if (status & UART_MSR_CTS)
311 ret |= TIOCM_CTS;
312 return ret;
313 }
314
315 static void serial_pxa_set_mctrl(struct uart_port *port, unsigned int mctrl)
316 {
317 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
318 unsigned char mcr = 0;
319
320 if (mctrl & TIOCM_RTS)
321 mcr |= UART_MCR_RTS;
322 if (mctrl & TIOCM_DTR)
323 mcr |= UART_MCR_DTR;
324 if (mctrl & TIOCM_OUT1)
325 mcr |= UART_MCR_OUT1;
326 if (mctrl & TIOCM_OUT2)
327 mcr |= UART_MCR_OUT2;
328 if (mctrl & TIOCM_LOOP)
329 mcr |= UART_MCR_LOOP;
330
331 mcr |= up->mcr;
332
333 serial_out(up, UART_MCR, mcr);
334 }
335
336 static void serial_pxa_break_ctl(struct uart_port *port, int break_state)
337 {
338 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
339 unsigned long flags;
340
341 spin_lock_irqsave(&up->port.lock, flags);
342 if (break_state == -1)
343 up->lcr |= UART_LCR_SBC;
344 else
345 up->lcr &= ~UART_LCR_SBC;
346 serial_out(up, UART_LCR, up->lcr);
347 spin_unlock_irqrestore(&up->port.lock, flags);
348 }
349
350 #if 0
351 static void serial_pxa_dma_init(struct pxa_uart *up)
352 {
353 up->rxdma =
354 pxa_request_dma(up->name, DMA_PRIO_LOW, pxa_receive_dma, up);
355 if (up->rxdma < 0)
356 goto out;
357 up->txdma =
358 pxa_request_dma(up->name, DMA_PRIO_LOW, pxa_transmit_dma, up);
359 if (up->txdma < 0)
360 goto err_txdma;
361 up->dmadesc = kmalloc(4 * sizeof(pxa_dma_desc), GFP_KERNEL);
362 if (!up->dmadesc)
363 goto err_alloc;
364
365 /* ... */
366 err_alloc:
367 pxa_free_dma(up->txdma);
368 err_rxdma:
369 pxa_free_dma(up->rxdma);
370 out:
371 return;
372 }
373 #endif
374
375 static int serial_pxa_startup(struct uart_port *port)
376 {
377 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
378 unsigned long flags;
379 int retval;
380
381 up->mcr = 0;
382
383 /*
384 * Allocate the IRQ
385 */
386 retval = request_irq(up->port.irq, serial_pxa_irq, 0, up->name, up);
387 if (retval)
388 return retval;
389
390 /*
391 * Clear the FIFO buffers and disable them.
392 * (they will be reenabled in set_termios())
393 */
394 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
395 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
396 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
397 serial_out(up, UART_FCR, 0);
398
399 /*
400 * Clear the interrupt registers.
401 */
402 (void) serial_in(up, UART_LSR);
403 (void) serial_in(up, UART_RX);
404 (void) serial_in(up, UART_IIR);
405 (void) serial_in(up, UART_MSR);
406
407 /*
408 * Now, initialize the UART
409 */
410 serial_out(up, UART_LCR, UART_LCR_WLEN8);
411
412 spin_lock_irqsave(&up->port.lock, flags);
413 up->port.mctrl |= TIOCM_OUT2;
414 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
415 spin_unlock_irqrestore(&up->port.lock, flags);
416
417 /*
418 * Finally, enable interrupts. Note: Modem status interrupts
419 * are set via set_termios(), which will be occuring imminently
420 * anyway, so we don't enable them here.
421 */
422 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE | UART_IER_UUE;
423 serial_out(up, UART_IER, up->ier);
424
425 /*
426 * And clear the interrupt registers again for luck.
427 */
428 (void) serial_in(up, UART_LSR);
429 (void) serial_in(up, UART_RX);
430 (void) serial_in(up, UART_IIR);
431 (void) serial_in(up, UART_MSR);
432
433 return 0;
434 }
435
436 static void serial_pxa_shutdown(struct uart_port *port)
437 {
438 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
439 unsigned long flags;
440
441 free_irq(up->port.irq, up);
442
443 /*
444 * Disable interrupts from this port
445 */
446 up->ier = 0;
447 serial_out(up, UART_IER, 0);
448
449 spin_lock_irqsave(&up->port.lock, flags);
450 up->port.mctrl &= ~TIOCM_OUT2;
451 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
452 spin_unlock_irqrestore(&up->port.lock, flags);
453
454 /*
455 * Disable break condition and FIFOs
456 */
457 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
458 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
459 UART_FCR_CLEAR_RCVR |
460 UART_FCR_CLEAR_XMIT);
461 serial_out(up, UART_FCR, 0);
462 }
463
464 static void
465 serial_pxa_set_termios(struct uart_port *port, struct termios *termios,
466 struct termios *old)
467 {
468 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
469 unsigned char cval, fcr = 0;
470 unsigned long flags;
471 unsigned int baud, quot;
472
473 switch (termios->c_cflag & CSIZE) {
474 case CS5:
475 cval = 0x00;
476 break;
477 case CS6:
478 cval = 0x01;
479 break;
480 case CS7:
481 cval = 0x02;
482 break;
483 default:
484 case CS8:
485 cval = 0x03;
486 break;
487 }
488
489 if (termios->c_cflag & CSTOPB)
490 cval |= 0x04;
491 if (termios->c_cflag & PARENB)
492 cval |= UART_LCR_PARITY;
493 if (!(termios->c_cflag & PARODD))
494 cval |= UART_LCR_EPAR;
495
496 /*
497 * Ask the core to calculate the divisor for us.
498 */
499 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
500 quot = uart_get_divisor(port, baud);
501
502 if ((up->port.uartclk / quot) < (2400 * 16))
503 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR1;
504 else
505 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR8;
506
507 /*
508 * Ok, we're now changing the port state. Do it with
509 * interrupts disabled.
510 */
511 spin_lock_irqsave(&up->port.lock, flags);
512
513 /*
514 * Ensure the port will be enabled.
515 * This is required especially for serial console.
516 */
517 up->ier |= IER_UUE;
518
519 /*
520 * Update the per-port timeout.
521 */
522 uart_update_timeout(port, termios->c_cflag, quot);
523
524 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
525 if (termios->c_iflag & INPCK)
526 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
527 if (termios->c_iflag & (BRKINT | PARMRK))
528 up->port.read_status_mask |= UART_LSR_BI;
529
530 /*
531 * Characters to ignore
532 */
533 up->port.ignore_status_mask = 0;
534 if (termios->c_iflag & IGNPAR)
535 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
536 if (termios->c_iflag & IGNBRK) {
537 up->port.ignore_status_mask |= UART_LSR_BI;
538 /*
539 * If we're ignoring parity and break indicators,
540 * ignore overruns too (for real raw support).
541 */
542 if (termios->c_iflag & IGNPAR)
543 up->port.ignore_status_mask |= UART_LSR_OE;
544 }
545
546 /*
547 * ignore all characters if CREAD is not set
548 */
549 if ((termios->c_cflag & CREAD) == 0)
550 up->port.ignore_status_mask |= UART_LSR_DR;
551
552 /*
553 * CTS flow control flag and modem status interrupts
554 */
555 up->ier &= ~UART_IER_MSI;
556 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
557 up->ier |= UART_IER_MSI;
558
559 serial_out(up, UART_IER, up->ier);
560
561 serial_out(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
562 serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */
563 serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
564 serial_out(up, UART_LCR, cval); /* reset DLAB */
565 up->lcr = cval; /* Save LCR */
566 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
567 serial_out(up, UART_FCR, fcr);
568 spin_unlock_irqrestore(&up->port.lock, flags);
569 }
570
571 static void
572 serial_pxa_pm(struct uart_port *port, unsigned int state,
573 unsigned int oldstate)
574 {
575 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
576 pxa_set_cken(up->cken, !state);
577 if (!state)
578 udelay(1);
579 }
580
581 static void serial_pxa_release_port(struct uart_port *port)
582 {
583 }
584
585 static int serial_pxa_request_port(struct uart_port *port)
586 {
587 return 0;
588 }
589
590 static void serial_pxa_config_port(struct uart_port *port, int flags)
591 {
592 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
593 up->port.type = PORT_PXA;
594 }
595
596 static int
597 serial_pxa_verify_port(struct uart_port *port, struct serial_struct *ser)
598 {
599 /* we don't want the core code to modify any port params */
600 return -EINVAL;
601 }
602
603 static const char *
604 serial_pxa_type(struct uart_port *port)
605 {
606 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
607 return up->name;
608 }
609
610 #ifdef CONFIG_SERIAL_PXA_CONSOLE
611
612 extern struct uart_pxa_port serial_pxa_ports[];
613 extern struct uart_driver serial_pxa_reg;
614
615 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
616
617 /*
618 * Wait for transmitter & holding register to empty
619 */
620 static inline void wait_for_xmitr(struct uart_pxa_port *up)
621 {
622 unsigned int status, tmout = 10000;
623
624 /* Wait up to 10ms for the character(s) to be sent. */
625 do {
626 status = serial_in(up, UART_LSR);
627
628 if (status & UART_LSR_BI)
629 up->lsr_break_flag = UART_LSR_BI;
630
631 if (--tmout == 0)
632 break;
633 udelay(1);
634 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
635
636 /* Wait up to 1s for flow control if necessary */
637 if (up->port.flags & UPF_CONS_FLOW) {
638 tmout = 1000000;
639 while (--tmout &&
640 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
641 udelay(1);
642 }
643 }
644
645 /*
646 * Print a string to the serial port trying not to disturb
647 * any possible real use of the port...
648 *
649 * The console_lock must be held when we get here.
650 */
651 static void
652 serial_pxa_console_write(struct console *co, const char *s, unsigned int count)
653 {
654 struct uart_pxa_port *up = &serial_pxa_ports[co->index];
655 unsigned int ier;
656 int i;
657
658 /*
659 * First save the UER then disable the interrupts
660 */
661 ier = serial_in(up, UART_IER);
662 serial_out(up, UART_IER, UART_IER_UUE);
663
664 /*
665 * Now, do each character
666 */
667 for (i = 0; i < count; i++, s++) {
668 wait_for_xmitr(up);
669
670 /*
671 * Send the character out.
672 * If a LF, also do CR...
673 */
674 serial_out(up, UART_TX, *s);
675 if (*s == 10) {
676 wait_for_xmitr(up);
677 serial_out(up, UART_TX, 13);
678 }
679 }
680
681 /*
682 * Finally, wait for transmitter to become empty
683 * and restore the IER
684 */
685 wait_for_xmitr(up);
686 serial_out(up, UART_IER, ier);
687 }
688
689 static int __init
690 serial_pxa_console_setup(struct console *co, char *options)
691 {
692 struct uart_pxa_port *up;
693 int baud = 9600;
694 int bits = 8;
695 int parity = 'n';
696 int flow = 'n';
697
698 if (co->index == -1 || co->index >= serial_pxa_reg.nr)
699 co->index = 0;
700 up = &serial_pxa_ports[co->index];
701
702 if (options)
703 uart_parse_options(options, &baud, &parity, &bits, &flow);
704
705 return uart_set_options(&up->port, co, baud, parity, bits, flow);
706 }
707
708 static struct console serial_pxa_console = {
709 .name = "ttyS",
710 .write = serial_pxa_console_write,
711 .device = uart_console_device,
712 .setup = serial_pxa_console_setup,
713 .flags = CON_PRINTBUFFER,
714 .index = -1,
715 .data = &serial_pxa_reg,
716 };
717
718 static int __init
719 serial_pxa_console_init(void)
720 {
721 register_console(&serial_pxa_console);
722 return 0;
723 }
724
725 console_initcall(serial_pxa_console_init);
726
727 #define PXA_CONSOLE &serial_pxa_console
728 #else
729 #define PXA_CONSOLE NULL
730 #endif
731
732 struct uart_ops serial_pxa_pops = {
733 .tx_empty = serial_pxa_tx_empty,
734 .set_mctrl = serial_pxa_set_mctrl,
735 .get_mctrl = serial_pxa_get_mctrl,
736 .stop_tx = serial_pxa_stop_tx,
737 .start_tx = serial_pxa_start_tx,
738 .stop_rx = serial_pxa_stop_rx,
739 .enable_ms = serial_pxa_enable_ms,
740 .break_ctl = serial_pxa_break_ctl,
741 .startup = serial_pxa_startup,
742 .shutdown = serial_pxa_shutdown,
743 .set_termios = serial_pxa_set_termios,
744 .pm = serial_pxa_pm,
745 .type = serial_pxa_type,
746 .release_port = serial_pxa_release_port,
747 .request_port = serial_pxa_request_port,
748 .config_port = serial_pxa_config_port,
749 .verify_port = serial_pxa_verify_port,
750 };
751
752 static struct uart_pxa_port serial_pxa_ports[] = {
753 { /* FFUART */
754 .name = "FFUART",
755 .cken = CKEN6_FFUART,
756 .port = {
757 .type = PORT_PXA,
758 .iotype = UPIO_MEM,
759 .membase = (void *)&FFUART,
760 .mapbase = __PREG(FFUART),
761 .irq = IRQ_FFUART,
762 .uartclk = 921600 * 16,
763 .fifosize = 64,
764 .ops = &serial_pxa_pops,
765 .line = 0,
766 },
767 }, { /* BTUART */
768 .name = "BTUART",
769 .cken = CKEN7_BTUART,
770 .port = {
771 .type = PORT_PXA,
772 .iotype = UPIO_MEM,
773 .membase = (void *)&BTUART,
774 .mapbase = __PREG(BTUART),
775 .irq = IRQ_BTUART,
776 .uartclk = 921600 * 16,
777 .fifosize = 64,
778 .ops = &serial_pxa_pops,
779 .line = 1,
780 },
781 }, { /* STUART */
782 .name = "STUART",
783 .cken = CKEN5_STUART,
784 .port = {
785 .type = PORT_PXA,
786 .iotype = UPIO_MEM,
787 .membase = (void *)&STUART,
788 .mapbase = __PREG(STUART),
789 .irq = IRQ_STUART,
790 .uartclk = 921600 * 16,
791 .fifosize = 64,
792 .ops = &serial_pxa_pops,
793 .line = 2,
794 },
795 }
796 };
797
798 static struct uart_driver serial_pxa_reg = {
799 .owner = THIS_MODULE,
800 .driver_name = "PXA serial",
801 .devfs_name = "tts/",
802 .dev_name = "ttyS",
803 .major = TTY_MAJOR,
804 .minor = 64,
805 .nr = ARRAY_SIZE(serial_pxa_ports),
806 .cons = PXA_CONSOLE,
807 };
808
809 static int serial_pxa_suspend(struct device *_dev, u32 state, u32 level)
810 {
811 struct uart_pxa_port *sport = dev_get_drvdata(_dev);
812
813 if (sport && level == SUSPEND_DISABLE)
814 uart_suspend_port(&serial_pxa_reg, &sport->port);
815
816 return 0;
817 }
818
819 static int serial_pxa_resume(struct device *_dev, u32 level)
820 {
821 struct uart_pxa_port *sport = dev_get_drvdata(_dev);
822
823 if (sport && level == RESUME_ENABLE)
824 uart_resume_port(&serial_pxa_reg, &sport->port);
825
826 return 0;
827 }
828
829 static int serial_pxa_probe(struct device *_dev)
830 {
831 struct platform_device *dev = to_platform_device(_dev);
832
833 serial_pxa_ports[dev->id].port.dev = _dev;
834 uart_add_one_port(&serial_pxa_reg, &serial_pxa_ports[dev->id].port);
835 dev_set_drvdata(_dev, &serial_pxa_ports[dev->id]);
836 return 0;
837 }
838
839 static int serial_pxa_remove(struct device *_dev)
840 {
841 struct uart_pxa_port *sport = dev_get_drvdata(_dev);
842
843 dev_set_drvdata(_dev, NULL);
844
845 if (sport)
846 uart_remove_one_port(&serial_pxa_reg, &sport->port);
847
848 return 0;
849 }
850
851 static struct device_driver serial_pxa_driver = {
852 .name = "pxa2xx-uart",
853 .bus = &platform_bus_type,
854 .probe = serial_pxa_probe,
855 .remove = serial_pxa_remove,
856
857 .suspend = serial_pxa_suspend,
858 .resume = serial_pxa_resume,
859 };
860
861 int __init serial_pxa_init(void)
862 {
863 int ret;
864
865 ret = uart_register_driver(&serial_pxa_reg);
866 if (ret != 0)
867 return ret;
868
869 ret = driver_register(&serial_pxa_driver);
870 if (ret != 0)
871 uart_unregister_driver(&serial_pxa_reg);
872
873 return ret;
874 }
875
876 void __exit serial_pxa_exit(void)
877 {
878 driver_unregister(&serial_pxa_driver);
879 uart_unregister_driver(&serial_pxa_reg);
880 }
881
882 module_init(serial_pxa_init);
883 module_exit(serial_pxa_exit);
884
885 MODULE_LICENSE("GPL");
886
MOXA 2.6.9 from sdlinux-moxaart.tgz