?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
MOXA linux-2.6.x / linux-2.6.9-uc0 from sdlinux-moxaart.tgz
[linux-2.6.9-moxart.git] / drivers / serial / sa1100.c
blobb60c5b60484c7ec0fb3496ae9e39906ac5f32131
1 /*
2 * linux/drivers/char/sa1100.c
3 *
4 * Driver for SA11x0 serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2000 Deep Blue Solutions Ltd.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 * $Id: sa1100.c,v 1.50 2002/07/29 14:41:04 rmk Exp $
25 *
26 */
27 #include <linux/config.h>
28 #include <linux/module.h>
29 #include <linux/tty.h>
30 #include <linux/ioport.h>
31 #include <linux/init.h>
32 #include <linux/serial.h>
33 #include <linux/console.h>
34 #include <linux/sysrq.h>
35 #include <linux/device.h>
36
37 #include <asm/io.h>
38 #include <asm/irq.h>
39 #include <asm/hardware.h>
40 #include <asm/mach/serial_sa1100.h>
41
42 #if defined(CONFIG_SERIAL_SA1100_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
43 #define SUPPORT_SYSRQ
44 #endif
45
46 #include <linux/serial_core.h>
47
48 /* We've been assigned a range on the "Low-density serial ports" major */
49 #define SERIAL_SA1100_MAJOR 204
50 #define MINOR_START 5
51
52 #define NR_PORTS 3
53
54 #define SA1100_ISR_PASS_LIMIT 256
55
56 /*
57 * Convert from ignore_status_mask or read_status_mask to UTSR[01]
58 */
59 #define SM_TO_UTSR0(x) ((x) & 0xff)
60 #define SM_TO_UTSR1(x) ((x) >> 8)
61 #define UTSR0_TO_SM(x) ((x))
62 #define UTSR1_TO_SM(x) ((x) << 8)
63
64 #define UART_GET_UTCR0(sport) __raw_readl((sport)->port.membase + UTCR0)
65 #define UART_GET_UTCR1(sport) __raw_readl((sport)->port.membase + UTCR1)
66 #define UART_GET_UTCR2(sport) __raw_readl((sport)->port.membase + UTCR2)
67 #define UART_GET_UTCR3(sport) __raw_readl((sport)->port.membase + UTCR3)
68 #define UART_GET_UTSR0(sport) __raw_readl((sport)->port.membase + UTSR0)
69 #define UART_GET_UTSR1(sport) __raw_readl((sport)->port.membase + UTSR1)
70 #define UART_GET_CHAR(sport) __raw_readl((sport)->port.membase + UTDR)
71
72 #define UART_PUT_UTCR0(sport,v) __raw_writel((v),(sport)->port.membase + UTCR0)
73 #define UART_PUT_UTCR1(sport,v) __raw_writel((v),(sport)->port.membase + UTCR1)
74 #define UART_PUT_UTCR2(sport,v) __raw_writel((v),(sport)->port.membase + UTCR2)
75 #define UART_PUT_UTCR3(sport,v) __raw_writel((v),(sport)->port.membase + UTCR3)
76 #define UART_PUT_UTSR0(sport,v) __raw_writel((v),(sport)->port.membase + UTSR0)
77 #define UART_PUT_UTSR1(sport,v) __raw_writel((v),(sport)->port.membase + UTSR1)
78 #define UART_PUT_CHAR(sport,v) __raw_writel((v),(sport)->port.membase + UTDR)
79
80 /*
81 * This is the size of our serial port register set.
82 */
83 #define UART_PORT_SIZE 0x24
84
85 /*
86 * This determines how often we check the modem status signals
87 * for any change. They generally aren't connected to an IRQ
88 * so we have to poll them. We also check immediately before
89 * filling the TX fifo incase CTS has been dropped.
90 */
91 #define MCTRL_TIMEOUT (250*HZ/1000)
92
93 struct sa1100_port {
94 struct uart_port port;
95 struct timer_list timer;
96 unsigned int old_status;
97 };
98
99 /*
100 * Handle any change of modem status signal since we were last called.
101 */
102 static void sa1100_mctrl_check(struct sa1100_port *sport)
103 {
104 unsigned int status, changed;
105
106 status = sport->port.ops->get_mctrl(&sport->port);
107 changed = status ^ sport->old_status;
108
109 if (changed == 0)
110 return;
111
112 sport->old_status = status;
113
114 if (changed & TIOCM_RI)
115 sport->port.icount.rng++;
116 if (changed & TIOCM_DSR)
117 sport->port.icount.dsr++;
118 if (changed & TIOCM_CAR)
119 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
120 if (changed & TIOCM_CTS)
121 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
122
123 wake_up_interruptible(&sport->port.info->delta_msr_wait);
124 }
125
126 /*
127 * This is our per-port timeout handler, for checking the
128 * modem status signals.
129 */
130 static void sa1100_timeout(unsigned long data)
131 {
132 struct sa1100_port *sport = (struct sa1100_port *)data;
133 unsigned long flags;
134
135 if (sport->port.info) {
136 spin_lock_irqsave(&sport->port.lock, flags);
137 sa1100_mctrl_check(sport);
138 spin_unlock_irqrestore(&sport->port.lock, flags);
139
140 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
141 }
142 }
143
144 /*
145 * interrupts disabled on entry
146 */
147 static void sa1100_stop_tx(struct uart_port *port, unsigned int tty_stop)
148 {
149 struct sa1100_port *sport = (struct sa1100_port *)port;
150 u32 utcr3;
151
152 utcr3 = UART_GET_UTCR3(sport);
153 UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_TIE);
154 sport->port.read_status_mask &= ~UTSR0_TO_SM(UTSR0_TFS);
155 }
156
157 /*
158 * interrupts may not be disabled on entry
159 */
160 static void sa1100_start_tx(struct uart_port *port, unsigned int tty_start)
161 {
162 struct sa1100_port *sport = (struct sa1100_port *)port;
163 unsigned long flags;
164 u32 utcr3;
165
166 spin_lock_irqsave(&sport->port.lock, flags);
167 utcr3 = UART_GET_UTCR3(sport);
168 sport->port.read_status_mask |= UTSR0_TO_SM(UTSR0_TFS);
169 UART_PUT_UTCR3(sport, utcr3 | UTCR3_TIE);
170 spin_unlock_irqrestore(&sport->port.lock, flags);
171 }
172
173 /*
174 * Interrupts enabled
175 */
176 static void sa1100_stop_rx(struct uart_port *port)
177 {
178 struct sa1100_port *sport = (struct sa1100_port *)port;
179 u32 utcr3;
180
181 utcr3 = UART_GET_UTCR3(sport);
182 UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_RIE);
183 }
184
185 /*
186 * Set the modem control timer to fire immediately.
187 */
188 static void sa1100_enable_ms(struct uart_port *port)
189 {
190 struct sa1100_port *sport = (struct sa1100_port *)port;
191
192 mod_timer(&sport->timer, jiffies);
193 }
194
195 static void
196 sa1100_rx_chars(struct sa1100_port *sport, struct pt_regs *regs)
197 {
198 struct tty_struct *tty = sport->port.info->tty;
199 unsigned int status, ch, flg, ignored = 0;
200
201 status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) |
202 UTSR0_TO_SM(UART_GET_UTSR0(sport));
203 while (status & UTSR1_TO_SM(UTSR1_RNE)) {
204 ch = UART_GET_CHAR(sport);
205
206 if (tty->flip.count >= TTY_FLIPBUF_SIZE)
207 goto ignore_char;
208 sport->port.icount.rx++;
209
210 flg = TTY_NORMAL;
211
212 /*
213 * note that the error handling code is
214 * out of the main execution path
215 */
216 if (status & UTSR1_TO_SM(UTSR1_PRE | UTSR1_FRE | UTSR1_ROR))
217 goto handle_error;
218
219 if (uart_handle_sysrq_char(&sport->port, ch, regs))
220 goto ignore_char;
221
222 error_return:
223 *tty->flip.flag_buf_ptr++ = flg;
224 *tty->flip.char_buf_ptr++ = ch;
225 tty->flip.count++;
226 ignore_char:
227 status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) |
228 UTSR0_TO_SM(UART_GET_UTSR0(sport));
229 }
230 out:
231 tty_flip_buffer_push(tty);
232 return;
233
234 handle_error:
235 if (status & UTSR1_TO_SM(UTSR1_PRE))
236 sport->port.icount.parity++;
237 else if (status & UTSR1_TO_SM(UTSR1_FRE))
238 sport->port.icount.frame++;
239 if (status & UTSR1_TO_SM(UTSR1_ROR))
240 sport->port.icount.overrun++;
241
242 if (status & sport->port.ignore_status_mask) {
243 if (++ignored > 100)
244 goto out;
245 goto ignore_char;
246 }
247
248 status &= sport->port.read_status_mask;
249
250 if (status & UTSR1_TO_SM(UTSR1_PRE))
251 flg = TTY_PARITY;
252 else if (status & UTSR1_TO_SM(UTSR1_FRE))
253 flg = TTY_FRAME;
254
255 if (status & UTSR1_TO_SM(UTSR1_ROR)) {
256 /*
257 * overrun does *not* affect the character
258 * we read from the FIFO
259 */
260 *tty->flip.flag_buf_ptr++ = flg;
261 *tty->flip.char_buf_ptr++ = ch;
262 tty->flip.count++;
263 if (tty->flip.count >= TTY_FLIPBUF_SIZE)
264 goto ignore_char;
265 ch = 0;
266 flg = TTY_OVERRUN;
267 }
268 #ifdef SUPPORT_SYSRQ
269 sport->port.sysrq = 0;
270 #endif
271 goto error_return;
272 }
273
274 static void sa1100_tx_chars(struct sa1100_port *sport)
275 {
276 struct circ_buf *xmit = &sport->port.info->xmit;
277
278 if (sport->port.x_char) {
279 UART_PUT_CHAR(sport, sport->port.x_char);
280 sport->port.icount.tx++;
281 sport->port.x_char = 0;
282 return;
283 }
284
285 /*
286 * Check the modem control lines before
287 * transmitting anything.
288 */
289 sa1100_mctrl_check(sport);
290
291 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
292 sa1100_stop_tx(&sport->port, 0);
293 return;
294 }
295
296 /*
297 * Tried using FIFO (not checking TNF) for fifo fill:
298 * still had the '4 bytes repeated' problem.
299 */
300 while (UART_GET_UTSR1(sport) & UTSR1_TNF) {
301 UART_PUT_CHAR(sport, xmit->buf[xmit->tail]);
302 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
303 sport->port.icount.tx++;
304 if (uart_circ_empty(xmit))
305 break;
306 }
307
308 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
309 uart_write_wakeup(&sport->port);
310
311 if (uart_circ_empty(xmit))
312 sa1100_stop_tx(&sport->port, 0);
313 }
314
315 static irqreturn_t sa1100_int(int irq, void *dev_id, struct pt_regs *regs)
316 {
317 struct sa1100_port *sport = dev_id;
318 unsigned int status, pass_counter = 0;
319
320 spin_lock(&sport->port.lock);
321 status = UART_GET_UTSR0(sport);
322 status &= SM_TO_UTSR0(sport->port.read_status_mask) | ~UTSR0_TFS;
323 do {
324 if (status & (UTSR0_RFS | UTSR0_RID)) {
325 /* Clear the receiver idle bit, if set */
326 if (status & UTSR0_RID)
327 UART_PUT_UTSR0(sport, UTSR0_RID);
328 sa1100_rx_chars(sport, regs);
329 }
330
331 /* Clear the relevant break bits */
332 if (status & (UTSR0_RBB | UTSR0_REB))
333 UART_PUT_UTSR0(sport, status & (UTSR0_RBB | UTSR0_REB));
334
335 if (status & UTSR0_RBB)
336 sport->port.icount.brk++;
337
338 if (status & UTSR0_REB)
339 uart_handle_break(&sport->port);
340
341 if (status & UTSR0_TFS)
342 sa1100_tx_chars(sport);
343 if (pass_counter++ > SA1100_ISR_PASS_LIMIT)
344 break;
345 status = UART_GET_UTSR0(sport);
346 status &= SM_TO_UTSR0(sport->port.read_status_mask) |
347 ~UTSR0_TFS;
348 } while (status & (UTSR0_TFS | UTSR0_RFS | UTSR0_RID));
349 spin_unlock(&sport->port.lock);
350
351 return IRQ_HANDLED;
352 }
353
354 /*
355 * Return TIOCSER_TEMT when transmitter is not busy.
356 */
357 static unsigned int sa1100_tx_empty(struct uart_port *port)
358 {
359 struct sa1100_port *sport = (struct sa1100_port *)port;
360
361 return UART_GET_UTSR1(sport) & UTSR1_TBY ? 0 : TIOCSER_TEMT;
362 }
363
364 static unsigned int sa1100_get_mctrl(struct uart_port *port)
365 {
366 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
367 }
368
369 static void sa1100_set_mctrl(struct uart_port *port, unsigned int mctrl)
370 {
371 }
372
373 /*
374 * Interrupts always disabled.
375 */
376 static void sa1100_break_ctl(struct uart_port *port, int break_state)
377 {
378 struct sa1100_port *sport = (struct sa1100_port *)port;
379 unsigned long flags;
380 unsigned int utcr3;
381
382 spin_lock_irqsave(&sport->port.lock, flags);
383 utcr3 = UART_GET_UTCR3(sport);
384 if (break_state == -1)
385 utcr3 |= UTCR3_BRK;
386 else
387 utcr3 &= ~UTCR3_BRK;
388 UART_PUT_UTCR3(sport, utcr3);
389 spin_unlock_irqrestore(&sport->port.lock, flags);
390 }
391
392 static int sa1100_startup(struct uart_port *port)
393 {
394 struct sa1100_port *sport = (struct sa1100_port *)port;
395 int retval;
396
397 /*
398 * Allocate the IRQ
399 */
400 retval = request_irq(sport->port.irq, sa1100_int, 0,
401 "sa11x0-uart", sport);
402 if (retval)
403 return retval;
404
405 /*
406 * Finally, clear and enable interrupts
407 */
408 UART_PUT_UTSR0(sport, -1);
409 UART_PUT_UTCR3(sport, UTCR3_RXE | UTCR3_TXE | UTCR3_RIE);
410
411 /*
412 * Enable modem status interrupts
413 */
414 spin_lock_irq(&sport->port.lock);
415 sa1100_enable_ms(&sport->port);
416 spin_unlock_irq(&sport->port.lock);
417
418 return 0;
419 }
420
421 static void sa1100_shutdown(struct uart_port *port)
422 {
423 struct sa1100_port *sport = (struct sa1100_port *)port;
424
425 /*
426 * Stop our timer.
427 */
428 del_timer_sync(&sport->timer);
429
430 /*
431 * Free the interrupt
432 */
433 free_irq(sport->port.irq, sport);
434
435 /*
436 * Disable all interrupts, port and break condition.
437 */
438 UART_PUT_UTCR3(sport, 0);
439 }
440
441 static void
442 sa1100_set_termios(struct uart_port *port, struct termios *termios,
443 struct termios *old)
444 {
445 struct sa1100_port *sport = (struct sa1100_port *)port;
446 unsigned long flags;
447 unsigned int utcr0, old_utcr3, baud, quot;
448 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
449
450 /*
451 * We only support CS7 and CS8.
452 */
453 while ((termios->c_cflag & CSIZE) != CS7 &&
454 (termios->c_cflag & CSIZE) != CS8) {
455 termios->c_cflag &= ~CSIZE;
456 termios->c_cflag |= old_csize;
457 old_csize = CS8;
458 }
459
460 if ((termios->c_cflag & CSIZE) == CS8)
461 utcr0 = UTCR0_DSS;
462 else
463 utcr0 = 0;
464
465 if (termios->c_cflag & CSTOPB)
466 utcr0 |= UTCR0_SBS;
467 if (termios->c_cflag & PARENB) {
468 utcr0 |= UTCR0_PE;
469 if (!(termios->c_cflag & PARODD))
470 utcr0 |= UTCR0_OES;
471 }
472
473 /*
474 * Ask the core to calculate the divisor for us.
475 */
476 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
477 quot = uart_get_divisor(port, baud);
478
479 spin_lock_irqsave(&sport->port.lock, flags);
480
481 sport->port.read_status_mask &= UTSR0_TO_SM(UTSR0_TFS);
482 sport->port.read_status_mask |= UTSR1_TO_SM(UTSR1_ROR);
483 if (termios->c_iflag & INPCK)
484 sport->port.read_status_mask |=
485 UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
486 if (termios->c_iflag & (BRKINT | PARMRK))
487 sport->port.read_status_mask |=
488 UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
489
490 /*
491 * Characters to ignore
492 */
493 sport->port.ignore_status_mask = 0;
494 if (termios->c_iflag & IGNPAR)
495 sport->port.ignore_status_mask |=
496 UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
497 if (termios->c_iflag & IGNBRK) {
498 sport->port.ignore_status_mask |=
499 UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
500 /*
501 * If we're ignoring parity and break indicators,
502 * ignore overruns too (for real raw support).
503 */
504 if (termios->c_iflag & IGNPAR)
505 sport->port.ignore_status_mask |=
506 UTSR1_TO_SM(UTSR1_ROR);
507 }
508
509 del_timer_sync(&sport->timer);
510
511 /*
512 * Update the per-port timeout.
513 */
514 uart_update_timeout(port, termios->c_cflag, baud);
515
516 /*
517 * disable interrupts and drain transmitter
518 */
519 old_utcr3 = UART_GET_UTCR3(sport);
520 UART_PUT_UTCR3(sport, old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE));
521
522 while (UART_GET_UTSR1(sport) & UTSR1_TBY)
523 barrier();
524
525 /* then, disable everything */
526 UART_PUT_UTCR3(sport, 0);
527
528 /* set the parity, stop bits and data size */
529 UART_PUT_UTCR0(sport, utcr0);
530
531 /* set the baud rate */
532 quot -= 1;
533 UART_PUT_UTCR1(sport, ((quot & 0xf00) >> 8));
534 UART_PUT_UTCR2(sport, (quot & 0xff));
535
536 UART_PUT_UTSR0(sport, -1);
537
538 UART_PUT_UTCR3(sport, old_utcr3);
539
540 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
541 sa1100_enable_ms(&sport->port);
542
543 spin_unlock_irqrestore(&sport->port.lock, flags);
544 }
545
546 static const char *sa1100_type(struct uart_port *port)
547 {
548 struct sa1100_port *sport = (struct sa1100_port *)port;
549
550 return sport->port.type == PORT_SA1100 ? "SA1100" : NULL;
551 }
552
553 /*
554 * Release the memory region(s) being used by 'port'.
555 */
556 static void sa1100_release_port(struct uart_port *port)
557 {
558 struct sa1100_port *sport = (struct sa1100_port *)port;
559
560 release_mem_region(sport->port.mapbase, UART_PORT_SIZE);
561 }
562
563 /*
564 * Request the memory region(s) being used by 'port'.
565 */
566 static int sa1100_request_port(struct uart_port *port)
567 {
568 struct sa1100_port *sport = (struct sa1100_port *)port;
569
570 return request_mem_region(sport->port.mapbase, UART_PORT_SIZE,
571 "sa11x0-uart") != NULL ? 0 : -EBUSY;
572 }
573
574 /*
575 * Configure/autoconfigure the port.
576 */
577 static void sa1100_config_port(struct uart_port *port, int flags)
578 {
579 struct sa1100_port *sport = (struct sa1100_port *)port;
580
581 if (flags & UART_CONFIG_TYPE &&
582 sa1100_request_port(&sport->port) == 0)
583 sport->port.type = PORT_SA1100;
584 }
585
586 /*
587 * Verify the new serial_struct (for TIOCSSERIAL).
588 * The only change we allow are to the flags and type, and
589 * even then only between PORT_SA1100 and PORT_UNKNOWN
590 */
591 static int
592 sa1100_verify_port(struct uart_port *port, struct serial_struct *ser)
593 {
594 struct sa1100_port *sport = (struct sa1100_port *)port;
595 int ret = 0;
596
597 if (ser->type != PORT_UNKNOWN && ser->type != PORT_SA1100)
598 ret = -EINVAL;
599 if (sport->port.irq != ser->irq)
600 ret = -EINVAL;
601 if (ser->io_type != SERIAL_IO_MEM)
602 ret = -EINVAL;
603 if (sport->port.uartclk / 16 != ser->baud_base)
604 ret = -EINVAL;
605 if ((void *)sport->port.mapbase != ser->iomem_base)
606 ret = -EINVAL;
607 if (sport->port.iobase != ser->port)
608 ret = -EINVAL;
609 if (ser->hub6 != 0)
610 ret = -EINVAL;
611 return ret;
612 }
613
614 static struct uart_ops sa1100_pops = {
615 .tx_empty = sa1100_tx_empty,
616 .set_mctrl = sa1100_set_mctrl,
617 .get_mctrl = sa1100_get_mctrl,
618 .stop_tx = sa1100_stop_tx,
619 .start_tx = sa1100_start_tx,
620 .stop_rx = sa1100_stop_rx,
621 .enable_ms = sa1100_enable_ms,
622 .break_ctl = sa1100_break_ctl,
623 .startup = sa1100_startup,
624 .shutdown = sa1100_shutdown,
625 .set_termios = sa1100_set_termios,
626 .type = sa1100_type,
627 .release_port = sa1100_release_port,
628 .request_port = sa1100_request_port,
629 .config_port = sa1100_config_port,
630 .verify_port = sa1100_verify_port,
631 };
632
633 static struct sa1100_port sa1100_ports[NR_PORTS];
634
635 /*
636 * Setup the SA1100 serial ports. Note that we don't include the IrDA
637 * port here since we have our own SIR/FIR driver (see drivers/net/irda)
638 *
639 * Note also that we support "console=ttySAx" where "x" is either 0 or 1.
640 * Which serial port this ends up being depends on the machine you're
641 * running this kernel on. I'm not convinced that this is a good idea,
642 * but that's the way it traditionally works.
643 *
644 * Note that NanoEngine UART3 becomes UART2, and UART2 is no longer
645 * used here.
646 */
647 static void __init sa1100_init_ports(void)
648 {
649 static int first = 1;
650 int i;
651
652 if (!first)
653 return;
654 first = 0;
655
656 for (i = 0; i < NR_PORTS; i++) {
657 sa1100_ports[i].port.uartclk = 3686400;
658 sa1100_ports[i].port.ops = &sa1100_pops;
659 sa1100_ports[i].port.fifosize = 8;
660 sa1100_ports[i].port.line = i;
661 sa1100_ports[i].port.iotype = SERIAL_IO_MEM;
662 init_timer(&sa1100_ports[i].timer);
663 sa1100_ports[i].timer.function = sa1100_timeout;
664 sa1100_ports[i].timer.data = (unsigned long)&sa1100_ports[i];
665 }
666
667 /*
668 * make transmit lines outputs, so that when the port
669 * is closed, the output is in the MARK state.
670 */
671 PPDR |= PPC_TXD1 | PPC_TXD3;
672 PPSR |= PPC_TXD1 | PPC_TXD3;
673 }
674
675 void __init sa1100_register_uart_fns(struct sa1100_port_fns *fns)
676 {
677 if (fns->get_mctrl)
678 sa1100_pops.get_mctrl = fns->get_mctrl;
679 if (fns->set_mctrl)
680 sa1100_pops.set_mctrl = fns->set_mctrl;
681
682 sa1100_pops.pm = fns->pm;
683 sa1100_pops.set_wake = fns->set_wake;
684 }
685
686 void __init sa1100_register_uart(int idx, int port)
687 {
688 if (idx >= NR_PORTS) {
689 printk(KERN_ERR "%s: bad index number %d\n", __FUNCTION__, idx);
690 return;
691 }
692
693 switch (port) {
694 case 1:
695 sa1100_ports[idx].port.membase = (void *)&Ser1UTCR0;
696 sa1100_ports[idx].port.mapbase = _Ser1UTCR0;
697 sa1100_ports[idx].port.irq = IRQ_Ser1UART;
698 sa1100_ports[idx].port.flags = ASYNC_BOOT_AUTOCONF;
699 break;
700
701 case 2:
702 sa1100_ports[idx].port.membase = (void *)&Ser2UTCR0;
703 sa1100_ports[idx].port.mapbase = _Ser2UTCR0;
704 sa1100_ports[idx].port.irq = IRQ_Ser2ICP;
705 sa1100_ports[idx].port.flags = ASYNC_BOOT_AUTOCONF;
706 break;
707
708 case 3:
709 sa1100_ports[idx].port.membase = (void *)&Ser3UTCR0;
710 sa1100_ports[idx].port.mapbase = _Ser3UTCR0;
711 sa1100_ports[idx].port.irq = IRQ_Ser3UART;
712 sa1100_ports[idx].port.flags = ASYNC_BOOT_AUTOCONF;
713 break;
714
715 default:
716 printk(KERN_ERR "%s: bad port number %d\n", __FUNCTION__, port);
717 }
718 }
719
720
721 #ifdef CONFIG_SERIAL_SA1100_CONSOLE
722
723 /*
724 * Interrupts are disabled on entering
725 */
726 static void
727 sa1100_console_write(struct console *co, const char *s, unsigned int count)
728 {
729 struct sa1100_port *sport = &sa1100_ports[co->index];
730 unsigned int old_utcr3, status, i;
731
732 /*
733 * First, save UTCR3 and then disable interrupts
734 */
735 old_utcr3 = UART_GET_UTCR3(sport);
736 UART_PUT_UTCR3(sport, (old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE)) |
737 UTCR3_TXE);
738
739 /*
740 * Now, do each character
741 */
742 for (i = 0; i < count; i++) {
743 do {
744 status = UART_GET_UTSR1(sport);
745 } while (!(status & UTSR1_TNF));
746 UART_PUT_CHAR(sport, s[i]);
747 if (s[i] == '\n') {
748 do {
749 status = UART_GET_UTSR1(sport);
750 } while (!(status & UTSR1_TNF));
751 UART_PUT_CHAR(sport, '\r');
752 }
753 }
754
755 /*
756 * Finally, wait for transmitter to become empty
757 * and restore UTCR3
758 */
759 do {
760 status = UART_GET_UTSR1(sport);
761 } while (status & UTSR1_TBY);
762 UART_PUT_UTCR3(sport, old_utcr3);
763 }
764
765 /*
766 * If the port was already initialised (eg, by a boot loader),
767 * try to determine the current setup.
768 */
769 static void __init
770 sa1100_console_get_options(struct sa1100_port *sport, int *baud,
771 int *parity, int *bits)
772 {
773 unsigned int utcr3;
774
775 utcr3 = UART_GET_UTCR3(sport) & (UTCR3_RXE | UTCR3_TXE);
776 if (utcr3 == (UTCR3_RXE | UTCR3_TXE)) {
777 /* ok, the port was enabled */
778 unsigned int utcr0, quot;
779
780 utcr0 = UART_GET_UTCR0(sport);
781
782 *parity = 'n';
783 if (utcr0 & UTCR0_PE) {
784 if (utcr0 & UTCR0_OES)
785 *parity = 'e';
786 else
787 *parity = 'o';
788 }
789
790 if (utcr0 & UTCR0_DSS)
791 *bits = 8;
792 else
793 *bits = 7;
794
795 quot = UART_GET_UTCR2(sport) | UART_GET_UTCR1(sport) << 8;
796 quot &= 0xfff;
797 *baud = sport->port.uartclk / (16 * (quot + 1));
798 }
799 }
800
801 static int __init
802 sa1100_console_setup(struct console *co, char *options)
803 {
804 struct sa1100_port *sport;
805 int baud = 9600;
806 int bits = 8;
807 int parity = 'n';
808 int flow = 'n';
809
810 /*
811 * Check whether an invalid uart number has been specified, and
812 * if so, search for the first available port that does have
813 * console support.
814 */
815 if (co->index == -1 || co->index >= NR_PORTS)
816 co->index = 0;
817 sport = &sa1100_ports[co->index];
818
819 if (options)
820 uart_parse_options(options, &baud, &parity, &bits, &flow);
821 else
822 sa1100_console_get_options(sport, &baud, &parity, &bits);
823
824 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
825 }
826
827 extern struct uart_driver sa1100_reg;
828 static struct console sa1100_console = {
829 .name = "ttySA",
830 .write = sa1100_console_write,
831 .device = uart_console_device,
832 .setup = sa1100_console_setup,
833 .flags = CON_PRINTBUFFER,
834 .index = -1,
835 .data = &sa1100_reg,
836 };
837
838 static int __init sa1100_rs_console_init(void)
839 {
840 sa1100_init_ports();
841 register_console(&sa1100_console);
842 return 0;
843 }
844 console_initcall(sa1100_rs_console_init);
845
846 #define SA1100_CONSOLE &sa1100_console
847 #else
848 #define SA1100_CONSOLE NULL
849 #endif
850
851 static struct uart_driver sa1100_reg = {
852 .owner = THIS_MODULE,
853 .driver_name = "ttySA",
854 .dev_name = "ttySA",
855 .devfs_name = "ttySA",
856 .major = SERIAL_SA1100_MAJOR,
857 .minor = MINOR_START,
858 .nr = NR_PORTS,
859 .cons = SA1100_CONSOLE,
860 };
861
862 static int sa1100_serial_suspend(struct device *_dev, u32 state, u32 level)
863 {
864 struct sa1100_port *sport = dev_get_drvdata(_dev);
865
866 if (sport && level == SUSPEND_DISABLE)
867 uart_suspend_port(&sa1100_reg, &sport->port);
868
869 return 0;
870 }
871
872 static int sa1100_serial_resume(struct device *_dev, u32 level)
873 {
874 struct sa1100_port *sport = dev_get_drvdata(_dev);
875
876 if (sport && level == RESUME_ENABLE)
877 uart_resume_port(&sa1100_reg, &sport->port);
878
879 return 0;
880 }
881
882 static int sa1100_serial_probe(struct device *_dev)
883 {
884 struct platform_device *dev = to_platform_device(_dev);
885 struct resource *res = dev->resource;
886 int i;
887
888 for (i = 0; i < dev->num_resources; i++, res++)
889 if (res->flags & IORESOURCE_MEM)
890 break;
891
892 if (i < dev->num_resources) {
893 for (i = 0; i < NR_PORTS; i++) {
894 if (sa1100_ports[i].port.mapbase != res->start)
895 continue;
896
897 sa1100_ports[i].port.dev = _dev;
898 uart_add_one_port(&sa1100_reg, &sa1100_ports[i].port);
899 dev_set_drvdata(_dev, &sa1100_ports[i]);
900 break;
901 }
902 }
903
904 return 0;
905 }
906
907 static int sa1100_serial_remove(struct device *_dev)
908 {
909 struct sa1100_port *sport = dev_get_drvdata(_dev);
910
911 dev_set_drvdata(_dev, NULL);
912
913 if (sport)
914 uart_remove_one_port(&sa1100_reg, &sport->port);
915
916 return 0;
917 }
918
919 static struct device_driver sa11x0_serial_driver = {
920 .name = "sa11x0-uart",
921 .bus = &platform_bus_type,
922 .probe = sa1100_serial_probe,
923 .remove = sa1100_serial_remove,
924 .suspend = sa1100_serial_suspend,
925 .resume = sa1100_serial_resume,
926 };
927
928 static int __init sa1100_serial_init(void)
929 {
930 int ret;
931
932 printk(KERN_INFO "Serial: SA11x0 driver $Revision: 1.50 $\n");
933
934 sa1100_init_ports();
935
936 ret = uart_register_driver(&sa1100_reg);
937 if (ret == 0) {
938 ret = driver_register(&sa11x0_serial_driver);
939 if (ret)
940 uart_unregister_driver(&sa1100_reg);
941 }
942 return ret;
943 }
944
945 static void __exit sa1100_serial_exit(void)
946 {
947 driver_unregister(&sa11x0_serial_driver);
948 uart_unregister_driver(&sa1100_reg);
949 }
950
951 module_init(sa1100_serial_init);
952 module_exit(sa1100_serial_exit);
953
954 MODULE_AUTHOR("Deep Blue Solutions Ltd");
955 MODULE_DESCRIPTION("SA1100 generic serial port driver $Revision: 1.50 $");
956 MODULE_LICENSE("GPL");
957 MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_SA1100_MAJOR);
MOXA 2.6.9 from sdlinux-moxaart.tgz