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MOXA linux-2.6.x / linux-2.6.9-uc0 from sdlinux-moxaart.tgz
[linux-2.6.9-moxart.git] / drivers / video / aty / aty128fb.c
blobf2d82d005f1249958977dc65fe15231d6e328b3a
1 /* $Id: aty128fb.c,v 1.1.1.1.36.1 1999/12/11 09:03:05 Exp $
2 * linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128
3 *
4 * Copyright (C) 1999-2003, Brad Douglas <brad@neruo.com>
5 * Copyright (C) 1999, Anthony Tong <atong@uiuc.edu>
6 *
7 * Ani Joshi / Jeff Garzik
8 * - Code cleanup
9 *
10 * Michel Danzer <michdaen@iiic.ethz.ch>
11 * - 15/16 bit cleanup
12 * - fix panning
13 *
14 * Benjamin Herrenschmidt
15 * - pmac-specific PM stuff
16 * - various fixes & cleanups
17 *
18 * Andreas Hundt <andi@convergence.de>
19 * - FB_ACTIVATE fixes
20 *
21 * Paul Mackerras <paulus@samba.org>
22 * - Convert to new framebuffer API,
23 * fix colormap setting at 16 bits/pixel (565)
24 *
25 * Paul Mundt
26 * - PCI hotplug
27 *
28 * Jon Smirl <jonsmirl@yahoo.com>
29 * - PCI ID update
30 * - replace ROM BIOS search
31 *
32 * Based off of Geert's atyfb.c and vfb.c.
33 *
34 * TODO:
35 * - monitor sensing (DDC)
36 * - virtual display
37 * - other platform support (only ppc/x86 supported)
38 * - hardware cursor support
39 *
40 * Please cc: your patches to brad@neruo.com.
41 */
42
43 /*
44 * A special note of gratitude to ATI's devrel for providing documentation,
45 * example code and hardware. Thanks Nitya. -atong and brad
46 */
47
48
49 #include <linux/config.h>
50 #include <linux/module.h>
51 #include <linux/moduleparam.h>
52 #include <linux/kernel.h>
53 #include <linux/errno.h>
54 #include <linux/string.h>
55 #include <linux/mm.h>
56 #include <linux/tty.h>
57 #include <linux/slab.h>
58 #include <linux/vmalloc.h>
59 #include <linux/delay.h>
60 #include <linux/interrupt.h>
61 #include <asm/uaccess.h>
62 #include <linux/fb.h>
63 #include <linux/init.h>
64 #include <linux/pci.h>
65 #include <linux/ioport.h>
66 #include <linux/console.h>
67 #include <asm/io.h>
68
69 #ifdef CONFIG_PPC_PMAC
70 #include <asm/prom.h>
71 #include <asm/pci-bridge.h>
72 #include "../macmodes.h"
73 #endif
74
75 #ifdef CONFIG_PMAC_BACKLIGHT
76 #include <asm/backlight.h>
77 #endif
78
79 #ifdef CONFIG_BOOTX_TEXT
80 #include <asm/btext.h>
81 #endif /* CONFIG_BOOTX_TEXT */
82
83 #ifdef CONFIG_MTRR
84 #include <asm/mtrr.h>
85 #endif
86
87 #include <video/aty128.h>
88
89 /* Debug flag */
90 #undef DEBUG
91
92 #ifdef DEBUG
93 #define DBG(fmt, args...) printk(KERN_DEBUG "aty128fb: %s " fmt, __FUNCTION__, ##args);
94 #else
95 #define DBG(fmt, args...)
96 #endif
97
98 #ifndef CONFIG_PPC_PMAC
99 /* default mode */
100 static struct fb_var_screeninfo default_var __initdata = {
101 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
102 640, 480, 640, 480, 0, 0, 8, 0,
103 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
104 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
105 0, FB_VMODE_NONINTERLACED
106 };
107
108 #else /* CONFIG_PPC_PMAC */
109 /* default to 1024x768 at 75Hz on PPC - this will work
110 * on the iMac, the usual 640x480 @ 60Hz doesn't. */
111 static struct fb_var_screeninfo default_var = {
112 /* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */
113 1024, 768, 1024, 768, 0, 0, 8, 0,
114 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
115 0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3,
116 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
117 FB_VMODE_NONINTERLACED
118 };
119 #endif /* CONFIG_PPC_PMAC */
120
121 /* default modedb mode */
122 /* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */
123 static struct fb_videomode defaultmode __initdata = {
124 .refresh = 60,
125 .xres = 640,
126 .yres = 480,
127 .pixclock = 39722,
128 .left_margin = 48,
129 .right_margin = 16,
130 .upper_margin = 33,
131 .lower_margin = 10,
132 .hsync_len = 96,
133 .vsync_len = 2,
134 .sync = 0,
135 .vmode = FB_VMODE_NONINTERLACED
136 };
137
138 /* Chip generations */
139 enum {
140 rage_128,
141 rage_128_pci,
142 rage_128_pro,
143 rage_128_pro_pci,
144 rage_M3,
145 rage_M3_pci,
146 rage_M4,
147 rage_128_ultra,
148 };
149
150 /* Must match above enum */
151 static const char *r128_family[] __devinitdata = {
152 "AGP",
153 "PCI",
154 "PRO AGP",
155 "PRO PCI",
156 "M3 AGP",
157 "M3 PCI",
158 "M4 AGP",
159 "Ultra AGP",
160 };
161
162 /*
163 * PCI driver prototypes
164 */
165 static int aty128_probe(struct pci_dev *pdev,
166 const struct pci_device_id *ent);
167 static void aty128_remove(struct pci_dev *pdev);
168 static int aty128_pci_suspend(struct pci_dev *pdev, u32 state);
169 static int aty128_pci_resume(struct pci_dev *pdev);
170
171 /* supported Rage128 chipsets */
172 static struct pci_device_id aty128_pci_tbl[] = {
173 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LE,
174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3_pci },
175 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LF,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3 },
177 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_MF,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
179 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_ML,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
181 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PA,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
183 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PB,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
185 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PC,
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
187 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PD,
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
189 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PE,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
191 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PF,
192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
193 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PG,
194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
195 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PH,
196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
197 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PI,
198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
199 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PJ,
200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
201 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PK,
202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
203 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PL,
204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
205 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PM,
206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
207 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PN,
208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
209 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PO,
210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
211 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PP,
212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
213 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PQ,
214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
215 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PR,
216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
217 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PS,
218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
219 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PT,
220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
221 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PU,
222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
223 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PV,
224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
225 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PW,
226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
227 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PX,
228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
229 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RE,
230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
231 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RF,
232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
233 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RG,
234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
235 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RK,
236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
237 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RL,
238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
239 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SE,
240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
241 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SF,
242 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
243 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SG,
244 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
245 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SH,
246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
247 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SK,
248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
249 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SL,
250 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
251 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SM,
252 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
253 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SN,
254 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
255 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TF,
256 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
257 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TL,
258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
259 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TR,
260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
261 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TS,
262 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
263 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TT,
264 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
265 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TU,
266 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
267 { 0, }
268 };
269
270 MODULE_DEVICE_TABLE(pci, aty128_pci_tbl);
271
272 static struct pci_driver aty128fb_driver = {
273 .name = "aty128fb",
274 .id_table = aty128_pci_tbl,
275 .probe = aty128_probe,
276 .remove = __devexit_p(aty128_remove),
277 .suspend = aty128_pci_suspend,
278 .resume = aty128_pci_resume,
279 };
280
281 /* packed BIOS settings */
282 #ifndef CONFIG_PPC
283 typedef struct {
284 u8 clock_chip_type;
285 u8 struct_size;
286 u8 accelerator_entry;
287 u8 VGA_entry;
288 u16 VGA_table_offset;
289 u16 POST_table_offset;
290 u16 XCLK;
291 u16 MCLK;
292 u8 num_PLL_blocks;
293 u8 size_PLL_blocks;
294 u16 PCLK_ref_freq;
295 u16 PCLK_ref_divider;
296 u32 PCLK_min_freq;
297 u32 PCLK_max_freq;
298 u16 MCLK_ref_freq;
299 u16 MCLK_ref_divider;
300 u32 MCLK_min_freq;
301 u32 MCLK_max_freq;
302 u16 XCLK_ref_freq;
303 u16 XCLK_ref_divider;
304 u32 XCLK_min_freq;
305 u32 XCLK_max_freq;
306 } __attribute__ ((packed)) PLL_BLOCK;
307 #endif /* !CONFIG_PPC */
308
309 /* onboard memory information */
310 struct aty128_meminfo {
311 u8 ML;
312 u8 MB;
313 u8 Trcd;
314 u8 Trp;
315 u8 Twr;
316 u8 CL;
317 u8 Tr2w;
318 u8 LoopLatency;
319 u8 DspOn;
320 u8 Rloop;
321 const char *name;
322 };
323
324 /* various memory configurations */
325 static const struct aty128_meminfo sdr_128 =
326 { 4, 4, 3, 3, 1, 3, 1, 16, 30, 16, "128-bit SDR SGRAM (1:1)" };
327 static const struct aty128_meminfo sdr_64 =
328 { 4, 8, 3, 3, 1, 3, 1, 17, 46, 17, "64-bit SDR SGRAM (1:1)" };
329 static const struct aty128_meminfo sdr_sgram =
330 { 4, 4, 1, 2, 1, 2, 1, 16, 24, 16, "64-bit SDR SGRAM (2:1)" };
331 static const struct aty128_meminfo ddr_sgram =
332 { 4, 4, 3, 3, 2, 3, 1, 16, 31, 16, "64-bit DDR SGRAM" };
333
334 static struct fb_fix_screeninfo aty128fb_fix __initdata = {
335 .id = "ATY Rage128",
336 .type = FB_TYPE_PACKED_PIXELS,
337 .visual = FB_VISUAL_PSEUDOCOLOR,
338 .xpanstep = 8,
339 .ypanstep = 1,
340 .mmio_len = 0x2000,
341 .accel = FB_ACCEL_ATI_RAGE128,
342 };
343
344 static char *mode_option __initdata = NULL;
345
346 #ifdef CONFIG_PPC_PMAC
347 static int default_vmode __initdata = VMODE_1024_768_60;
348 static int default_cmode __initdata = CMODE_8;
349 #endif
350
351 #ifdef CONFIG_PMAC_PBOOK
352 static int default_crt_on __initdata = 0;
353 static int default_lcd_on __initdata = 1;
354 #endif
355
356 #ifdef CONFIG_MTRR
357 static int mtrr = 1;
358 #endif
359
360 /* PLL constants */
361 struct aty128_constants {
362 u32 ref_clk;
363 u32 ppll_min;
364 u32 ppll_max;
365 u32 ref_divider;
366 u32 xclk;
367 u32 fifo_width;
368 u32 fifo_depth;
369 };
370
371 struct aty128_crtc {
372 u32 gen_cntl;
373 u32 h_total, h_sync_strt_wid;
374 u32 v_total, v_sync_strt_wid;
375 u32 pitch;
376 u32 offset, offset_cntl;
377 u32 xoffset, yoffset;
378 u32 vxres, vyres;
379 u32 depth, bpp;
380 };
381
382 struct aty128_pll {
383 u32 post_divider;
384 u32 feedback_divider;
385 u32 vclk;
386 };
387
388 struct aty128_ddafifo {
389 u32 dda_config;
390 u32 dda_on_off;
391 };
392
393 /* register values for a specific mode */
394 struct aty128fb_par {
395 struct aty128_crtc crtc;
396 struct aty128_pll pll;
397 struct aty128_ddafifo fifo_reg;
398 u32 accel_flags;
399 struct aty128_constants constants; /* PLL and others */
400 void *regbase; /* remapped mmio */
401 u32 vram_size; /* onboard video ram */
402 int chip_gen;
403 const struct aty128_meminfo *mem; /* onboard mem info */
404 #ifdef CONFIG_MTRR
405 struct { int vram; int vram_valid; } mtrr;
406 #endif
407 int blitter_may_be_busy;
408 int fifo_slots; /* free slots in FIFO (64 max) */
409
410 int pm_reg;
411 int crt_on, lcd_on;
412 struct pci_dev *pdev;
413 struct fb_info *next;
414 int asleep;
415 int lock_blank;
416
417 u8 red[32]; /* see aty128fb_setcolreg */
418 u8 green[64];
419 u8 blue[32];
420 u32 pseudo_palette[16]; /* used for TRUECOLOR */
421 };
422
423
424 #define round_div(n, d) ((n+(d/2))/d)
425
426 /*
427 * Interface used by the world
428 */
429 int aty128fb_init(void);
430
431 static int aty128fb_check_var(struct fb_var_screeninfo *var,
432 struct fb_info *info);
433 static int aty128fb_set_par(struct fb_info *info);
434 static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
435 u_int transp, struct fb_info *info);
436 static int aty128fb_pan_display(struct fb_var_screeninfo *var,
437 struct fb_info *fb);
438 static int aty128fb_blank(int blank, struct fb_info *fb);
439 static int aty128fb_ioctl(struct inode *inode, struct file *file, u_int cmd,
440 u_long arg, struct fb_info *info);
441 static int aty128fb_sync(struct fb_info *info);
442
443 /*
444 * Internal routines
445 */
446
447 static int aty128_encode_var(struct fb_var_screeninfo *var,
448 const struct aty128fb_par *par);
449 static int aty128_decode_var(struct fb_var_screeninfo *var,
450 struct aty128fb_par *par);
451 #if 0
452 static void __init aty128_get_pllinfo(struct aty128fb_par *par,
453 void *bios);
454 static void __init *aty128_map_ROM(struct pci_dev *pdev, const struct aty128fb_par *par);
455 static void __init aty128_unmap_ROM(struct pci_dev *dev, void * rom);
456 #endif
457 static void aty128_timings(struct aty128fb_par *par);
458 static void aty128_init_engine(struct aty128fb_par *par);
459 static void aty128_reset_engine(const struct aty128fb_par *par);
460 static void aty128_flush_pixel_cache(const struct aty128fb_par *par);
461 static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par);
462 static void wait_for_fifo(u16 entries, struct aty128fb_par *par);
463 static void wait_for_idle(struct aty128fb_par *par);
464 static u32 depth_to_dst(u32 depth);
465
466 #define BIOS_IN8(v) (readb(bios + (v)))
467 #define BIOS_IN16(v) (readb(bios + (v)) | \
468 (readb(bios + (v) + 1) << 8))
469 #define BIOS_IN32(v) (readb(bios + (v)) | \
470 (readb(bios + (v) + 1) << 8) | \
471 (readb(bios + (v) + 2) << 16) | \
472 (readb(bios + (v) + 3) << 24))
473
474
475 static struct fb_ops aty128fb_ops = {
476 .owner = THIS_MODULE,
477 .fb_check_var = aty128fb_check_var,
478 .fb_set_par = aty128fb_set_par,
479 .fb_setcolreg = aty128fb_setcolreg,
480 .fb_pan_display = aty128fb_pan_display,
481 .fb_blank = aty128fb_blank,
482 .fb_ioctl = aty128fb_ioctl,
483 .fb_sync = aty128fb_sync,
484 .fb_fillrect = cfb_fillrect,
485 .fb_copyarea = cfb_copyarea,
486 .fb_imageblit = cfb_imageblit,
487 .fb_cursor = soft_cursor,
488 };
489
490 #ifdef CONFIG_PMAC_BACKLIGHT
491 static int aty128_set_backlight_enable(int on, int level, void* data);
492 static int aty128_set_backlight_level(int level, void* data);
493
494 static struct backlight_controller aty128_backlight_controller = {
495 aty128_set_backlight_enable,
496 aty128_set_backlight_level
497 };
498 #endif /* CONFIG_PMAC_BACKLIGHT */
499
500 /*
501 * Functions to read from/write to the mmio registers
502 * - endian conversions may possibly be avoided by
503 * using the other register aperture. TODO.
504 */
505 static inline u32 _aty_ld_le32(volatile unsigned int regindex,
506 const struct aty128fb_par *par)
507 {
508 return readl (par->regbase + regindex);
509 }
510
511 static inline void _aty_st_le32(volatile unsigned int regindex, u32 val,
512 const struct aty128fb_par *par)
513 {
514 writel (val, par->regbase + regindex);
515 }
516
517 static inline u8 _aty_ld_8(unsigned int regindex,
518 const struct aty128fb_par *par)
519 {
520 return readb (par->regbase + regindex);
521 }
522
523 static inline void _aty_st_8(unsigned int regindex, u8 val,
524 const struct aty128fb_par *par)
525 {
526 writeb (val, par->regbase + regindex);
527 }
528
529 #define aty_ld_le32(regindex) _aty_ld_le32(regindex, par)
530 #define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, par)
531 #define aty_ld_8(regindex) _aty_ld_8(regindex, par)
532 #define aty_st_8(regindex, val) _aty_st_8(regindex, val, par)
533
534 /*
535 * Functions to read from/write to the pll registers
536 */
537
538 #define aty_ld_pll(pll_index) _aty_ld_pll(pll_index, par)
539 #define aty_st_pll(pll_index, val) _aty_st_pll(pll_index, val, par)
540
541
542 static u32 _aty_ld_pll(unsigned int pll_index,
543 const struct aty128fb_par *par)
544 {
545 aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x3F);
546 return aty_ld_le32(CLOCK_CNTL_DATA);
547 }
548
549
550 static void _aty_st_pll(unsigned int pll_index, u32 val,
551 const struct aty128fb_par *par)
552 {
553 aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN);
554 aty_st_le32(CLOCK_CNTL_DATA, val);
555 }
556
557
558 /* return true when the PLL has completed an atomic update */
559 static int aty_pll_readupdate(const struct aty128fb_par *par)
560 {
561 return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R);
562 }
563
564
565 static void aty_pll_wait_readupdate(const struct aty128fb_par *par)
566 {
567 unsigned long timeout = jiffies + HZ/100; // should be more than enough
568 int reset = 1;
569
570 while (time_before(jiffies, timeout))
571 if (aty_pll_readupdate(par)) {
572 reset = 0;
573 break;
574 }
575
576 if (reset) /* reset engine?? */
577 printk(KERN_DEBUG "aty128fb: PLL write timeout!\n");
578 }
579
580
581 /* tell PLL to update */
582 static void aty_pll_writeupdate(const struct aty128fb_par *par)
583 {
584 aty_pll_wait_readupdate(par);
585
586 aty_st_pll(PPLL_REF_DIV,
587 aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W);
588 }
589
590
591 /* write to the scratch register to test r/w functionality */
592 static int __init register_test(const struct aty128fb_par *par)
593 {
594 u32 val;
595 int flag = 0;
596
597 val = aty_ld_le32(BIOS_0_SCRATCH);
598
599 aty_st_le32(BIOS_0_SCRATCH, 0x55555555);
600 if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) {
601 aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA);
602
603 if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA)
604 flag = 1;
605 }
606
607 aty_st_le32(BIOS_0_SCRATCH, val); // restore value
608 return flag;
609 }
610
611
612 /*
613 * Accelerator engine functions
614 */
615 static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par)
616 {
617 int i;
618
619 for (;;) {
620 for (i = 0; i < 2000000; i++) {
621 par->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff;
622 if (par->fifo_slots >= entries)
623 return;
624 }
625 aty128_reset_engine(par);
626 }
627 }
628
629
630 static void wait_for_idle(struct aty128fb_par *par)
631 {
632 int i;
633
634 do_wait_for_fifo(64, par);
635
636 for (;;) {
637 for (i = 0; i < 2000000; i++) {
638 if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) {
639 aty128_flush_pixel_cache(par);
640 par->blitter_may_be_busy = 0;
641 return;
642 }
643 }
644 aty128_reset_engine(par);
645 }
646 }
647
648
649 static void wait_for_fifo(u16 entries, struct aty128fb_par *par)
650 {
651 if (par->fifo_slots < entries)
652 do_wait_for_fifo(64, par);
653 par->fifo_slots -= entries;
654 }
655
656
657 static void aty128_flush_pixel_cache(const struct aty128fb_par *par)
658 {
659 int i;
660 u32 tmp;
661
662 tmp = aty_ld_le32(PC_NGUI_CTLSTAT);
663 tmp &= ~(0x00ff);
664 tmp |= 0x00ff;
665 aty_st_le32(PC_NGUI_CTLSTAT, tmp);
666
667 for (i = 0; i < 2000000; i++)
668 if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY))
669 break;
670 }
671
672
673 static void aty128_reset_engine(const struct aty128fb_par *par)
674 {
675 u32 gen_reset_cntl, clock_cntl_index, mclk_cntl;
676
677 aty128_flush_pixel_cache(par);
678
679 clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX);
680 mclk_cntl = aty_ld_pll(MCLK_CNTL);
681
682 aty_st_pll(MCLK_CNTL, mclk_cntl | 0x00030000);
683
684 gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL);
685 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI);
686 aty_ld_le32(GEN_RESET_CNTL);
687 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI));
688 aty_ld_le32(GEN_RESET_CNTL);
689
690 aty_st_pll(MCLK_CNTL, mclk_cntl);
691 aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index);
692 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl);
693
694 /* use old pio mode */
695 aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4);
696
697 DBG("engine reset");
698 }
699
700
701 static void aty128_init_engine(struct aty128fb_par *par)
702 {
703 u32 pitch_value;
704
705 wait_for_idle(par);
706
707 /* 3D scaler not spoken here */
708 wait_for_fifo(1, par);
709 aty_st_le32(SCALE_3D_CNTL, 0x00000000);
710
711 aty128_reset_engine(par);
712
713 pitch_value = par->crtc.pitch;
714 if (par->crtc.bpp == 24) {
715 pitch_value = pitch_value * 3;
716 }
717
718 wait_for_fifo(4, par);
719 /* setup engine offset registers */
720 aty_st_le32(DEFAULT_OFFSET, 0x00000000);
721
722 /* setup engine pitch registers */
723 aty_st_le32(DEFAULT_PITCH, pitch_value);
724
725 /* set the default scissor register to max dimensions */
726 aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF);
727
728 /* set the drawing controls registers */
729 aty_st_le32(DP_GUI_MASTER_CNTL,
730 GMC_SRC_PITCH_OFFSET_DEFAULT |
731 GMC_DST_PITCH_OFFSET_DEFAULT |
732 GMC_SRC_CLIP_DEFAULT |
733 GMC_DST_CLIP_DEFAULT |
734 GMC_BRUSH_SOLIDCOLOR |
735 (depth_to_dst(par->crtc.depth) << 8) |
736 GMC_SRC_DSTCOLOR |
737 GMC_BYTE_ORDER_MSB_TO_LSB |
738 GMC_DP_CONVERSION_TEMP_6500 |
739 ROP3_PATCOPY |
740 GMC_DP_SRC_RECT |
741 GMC_3D_FCN_EN_CLR |
742 GMC_DST_CLR_CMP_FCN_CLEAR |
743 GMC_AUX_CLIP_CLEAR |
744 GMC_WRITE_MASK_SET);
745
746 wait_for_fifo(8, par);
747 /* clear the line drawing registers */
748 aty_st_le32(DST_BRES_ERR, 0);
749 aty_st_le32(DST_BRES_INC, 0);
750 aty_st_le32(DST_BRES_DEC, 0);
751
752 /* set brush color registers */
753 aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */
754 aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */
755
756 /* set source color registers */
757 aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF); /* white */
758 aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000); /* black */
759
760 /* default write mask */
761 aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF);
762
763 /* Wait for all the writes to be completed before returning */
764 wait_for_idle(par);
765 }
766
767
768 /* convert depth values to their register representation */
769 static u32 depth_to_dst(u32 depth)
770 {
771 if (depth <= 8)
772 return DST_8BPP;
773 else if (depth <= 15)
774 return DST_15BPP;
775 else if (depth == 16)
776 return DST_16BPP;
777 else if (depth <= 24)
778 return DST_24BPP;
779 else if (depth <= 32)
780 return DST_32BPP;
781
782 return -EINVAL;
783 }
784
785 /*
786 * PLL informations retreival
787 */
788
789
790 #ifndef __sparc__
791 static void __init aty128_unmap_ROM(struct pci_dev *dev, void * rom)
792 {
793 struct resource *r = &dev->resource[PCI_ROM_RESOURCE];
794
795 iounmap(rom);
796
797 /* Release the ROM resource if we used it in the first place */
798 if (r->parent && r->flags & PCI_ROM_ADDRESS_ENABLE) {
799 release_resource(r);
800 r->flags &= ~PCI_ROM_ADDRESS_ENABLE;
801 r->end -= r->start;
802 r->start = 0;
803 }
804 /* This will disable and set address to unassigned */
805 pci_write_config_dword(dev, dev->rom_base_reg, 0);
806 }
807
808
809 static void * __init aty128_map_ROM(const struct aty128fb_par *par, struct pci_dev *dev)
810 {
811 struct resource *r;
812 u16 dptr;
813 u8 rom_type;
814 void *bios;
815
816 /* Fix from ATI for problem with Rage128 hardware not leaving ROM enabled */
817 unsigned int temp;
818 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
819 temp &= 0x00ffffffu;
820 temp |= 0x04 << 24;
821 aty_st_le32(RAGE128_MPP_TB_CONFIG, temp);
822 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
823
824 /* no need to search for the ROM, just ask the card where it is. */
825 r = &dev->resource[PCI_ROM_RESOURCE];
826
827 /* assign the ROM an address if it doesn't have one */
828 if (r->parent == NULL)
829 pci_assign_resource(dev, PCI_ROM_RESOURCE);
830
831 /* enable if needed */
832 if (!(r->flags & PCI_ROM_ADDRESS_ENABLE)) {
833 pci_write_config_dword(dev, dev->rom_base_reg,
834 r->start | PCI_ROM_ADDRESS_ENABLE);
835 r->flags |= PCI_ROM_ADDRESS_ENABLE;
836 }
837
838 bios = ioremap(r->start, r->end - r->start + 1);
839 if (!bios) {
840 printk(KERN_ERR "aty128fb: ROM failed to map\n");
841 return NULL;
842 }
843
844 /* Very simple test to make sure it appeared */
845 if (BIOS_IN16(0) != 0xaa55) {
846 printk(KERN_ERR "aty128fb: Invalid ROM signature %x should be 0xaa55\n",
847 BIOS_IN16(0));
848 goto failed;
849 }
850
851 /* Look for the PCI data to check the ROM type */
852 dptr = BIOS_IN16(0x18);
853
854 /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
855 * for now, until I've verified this works everywhere. The goal here is more
856 * to phase out Open Firmware images.
857 *
858 * Currently, we only look at the first PCI data, we could iteratre and deal with
859 * them all, and we should use fb_bios_start relative to start of image and not
860 * relative start of ROM, but so far, I never found a dual-image ATI card
861 *
862 * typedef struct {
863 * u32 signature; + 0x00
864 * u16 vendor; + 0x04
865 * u16 device; + 0x06
866 * u16 reserved_1; + 0x08
867 * u16 dlen; + 0x0a
868 * u8 drevision; + 0x0c
869 * u8 class_hi; + 0x0d
870 * u16 class_lo; + 0x0e
871 * u16 ilen; + 0x10
872 * u16 irevision; + 0x12
873 * u8 type; + 0x14
874 * u8 indicator; + 0x15
875 * u16 reserved_2; + 0x16
876 * } pci_data_t;
877 */
878 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
879 printk(KERN_WARNING "aty128fb: PCI DATA signature in ROM incorrect: %08x\n",
880 BIOS_IN32(dptr));
881 goto anyway;
882 }
883 rom_type = BIOS_IN8(dptr + 0x14);
884 switch(rom_type) {
885 case 0:
886 printk(KERN_INFO "aty128fb: Found Intel x86 BIOS ROM Image\n");
887 break;
888 case 1:
889 printk(KERN_INFO "aty128fb: Found Open Firmware ROM Image\n");
890 goto failed;
891 case 2:
892 printk(KERN_INFO "aty128fb: Found HP PA-RISC ROM Image\n");
893 goto failed;
894 default:
895 printk(KERN_INFO "aty128fb: Found unknown type %d ROM Image\n", rom_type);
896 goto failed;
897 }
898 anyway:
899 return bios;
900
901 failed:
902 aty128_unmap_ROM(dev, bios);
903 return NULL;
904 }
905
906 static void __init aty128_get_pllinfo(struct aty128fb_par *par, unsigned char *bios)
907 {
908 unsigned int bios_hdr;
909 unsigned int bios_pll;
910
911 bios_hdr = BIOS_IN16(0x48);
912 bios_pll = BIOS_IN16(bios_hdr + 0x30);
913
914 par->constants.ppll_max = BIOS_IN32(bios_pll + 0x16);
915 par->constants.ppll_min = BIOS_IN32(bios_pll + 0x12);
916 par->constants.xclk = BIOS_IN16(bios_pll + 0x08);
917 par->constants.ref_divider = BIOS_IN16(bios_pll + 0x10);
918 par->constants.ref_clk = BIOS_IN16(bios_pll + 0x0e);
919
920 DBG("ppll_max %d ppll_min %d xclk %d ref_divider %d ref clock %d\n",
921 par->constants.ppll_max, par->constants.ppll_min,
922 par->constants.xclk, par->constants.ref_divider,
923 par->constants.ref_clk);
924
925 }
926
927 #ifdef CONFIG_X86
928 static void * __devinit aty128_find_mem_vbios(struct aty128fb_par *par)
929 {
930 /* I simplified this code as we used to miss the signatures in
931 * a lot of case. It's now closer to XFree, we just don't check
932 * for signatures at all... Something better will have to be done
933 * if we end up having conflicts
934 */
935 u32 segstart;
936 unsigned char *rom_base = NULL;
937
938 for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
939 rom_base = (char *)ioremap(segstart, 0x10000);
940 if (rom_base == NULL)
941 return NULL;
942 if ((*rom_base == 0x55) && (((*(rom_base + 1)) & 0xff) == 0xaa))
943 break;
944 iounmap(rom_base);
945 rom_base = NULL;
946 }
947 return rom_base;
948 }
949 #endif
950 #endif /* ndef(__sparc__) */
951
952 /* fill in known card constants if pll_block is not available */
953 static void __init aty128_timings(struct aty128fb_par *par)
954 {
955 #ifdef CONFIG_PPC_OF
956 /* instead of a table lookup, assume OF has properly
957 * setup the PLL registers and use their values
958 * to set the XCLK values and reference divider values */
959
960 u32 x_mpll_ref_fb_div;
961 u32 xclk_cntl;
962 u32 Nx, M;
963 unsigned PostDivSet[] = { 0, 1, 2, 4, 8, 3, 6, 12 };
964 #endif
965
966 if (!par->constants.ref_clk)
967 par->constants.ref_clk = 2950;
968
969 #ifdef CONFIG_PPC_OF
970 x_mpll_ref_fb_div = aty_ld_pll(X_MPLL_REF_FB_DIV);
971 xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7;
972 Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8;
973 M = x_mpll_ref_fb_div & 0x0000ff;
974
975 par->constants.xclk = round_div((2 * Nx * par->constants.ref_clk),
976 (M * PostDivSet[xclk_cntl]));
977
978 par->constants.ref_divider =
979 aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
980 #endif
981
982 if (!par->constants.ref_divider) {
983 par->constants.ref_divider = 0x3b;
984
985 aty_st_pll(X_MPLL_REF_FB_DIV, 0x004c4c1e);
986 aty_pll_writeupdate(par);
987 }
988 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider);
989 aty_pll_writeupdate(par);
990
991 /* from documentation */
992 if (!par->constants.ppll_min)
993 par->constants.ppll_min = 12500;
994 if (!par->constants.ppll_max)
995 par->constants.ppll_max = 25000; /* 23000 on some cards? */
996 if (!par->constants.xclk)
997 par->constants.xclk = 0x1d4d; /* same as mclk */
998
999 par->constants.fifo_width = 128;
1000 par->constants.fifo_depth = 32;
1001
1002 switch (aty_ld_le32(MEM_CNTL) & 0x3) {
1003 case 0:
1004 par->mem = &sdr_128;
1005 break;
1006 case 1:
1007 par->mem = &sdr_sgram;
1008 break;
1009 case 2:
1010 par->mem = &ddr_sgram;
1011 break;
1012 default:
1013 par->mem = &sdr_sgram;
1014 }
1015 }
1016
1017
1018
1019 /*
1020 * CRTC programming
1021 */
1022
1023 /* Program the CRTC registers */
1024 static void aty128_set_crtc(const struct aty128_crtc *crtc,
1025 const struct aty128fb_par *par)
1026 {
1027 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl);
1028 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total);
1029 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid);
1030 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total);
1031 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid);
1032 aty_st_le32(CRTC_PITCH, crtc->pitch);
1033 aty_st_le32(CRTC_OFFSET, crtc->offset);
1034 aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl);
1035 /* Disable ATOMIC updating. Is this the right place? */
1036 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~(0x00030000));
1037 }
1038
1039
1040 static int aty128_var_to_crtc(const struct fb_var_screeninfo *var,
1041 struct aty128_crtc *crtc,
1042 const struct aty128fb_par *par)
1043 {
1044 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp, dst;
1045 u32 left, right, upper, lower, hslen, vslen, sync, vmode;
1046 u32 h_total, h_disp, h_sync_strt, h_sync_wid, h_sync_pol;
1047 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1048 u32 depth, bytpp;
1049 u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 };
1050
1051 /* input */
1052 xres = var->xres;
1053 yres = var->yres;
1054 vxres = var->xres_virtual;
1055 vyres = var->yres_virtual;
1056 xoffset = var->xoffset;
1057 yoffset = var->yoffset;
1058 bpp = var->bits_per_pixel;
1059 left = var->left_margin;
1060 right = var->right_margin;
1061 upper = var->upper_margin;
1062 lower = var->lower_margin;
1063 hslen = var->hsync_len;
1064 vslen = var->vsync_len;
1065 sync = var->sync;
1066 vmode = var->vmode;
1067
1068 if (bpp != 16)
1069 depth = bpp;
1070 else
1071 depth = (var->green.length == 6) ? 16 : 15;
1072
1073 /* check for mode eligibility
1074 * accept only non interlaced modes */
1075 if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
1076 return -EINVAL;
1077
1078 /* convert (and round up) and validate */
1079 xres = (xres + 7) & ~7;
1080 xoffset = (xoffset + 7) & ~7;
1081
1082 if (vxres < xres + xoffset)
1083 vxres = xres + xoffset;
1084
1085 if (vyres < yres + yoffset)
1086 vyres = yres + yoffset;
1087
1088 /* convert depth into ATI register depth */
1089 dst = depth_to_dst(depth);
1090
1091 if (dst == -EINVAL) {
1092 printk(KERN_ERR "aty128fb: Invalid depth or RGBA\n");
1093 return -EINVAL;
1094 }
1095
1096 /* convert register depth to bytes per pixel */
1097 bytpp = mode_bytpp[dst];
1098
1099 /* make sure there is enough video ram for the mode */
1100 if ((u32)(vxres * vyres * bytpp) > par->vram_size) {
1101 printk(KERN_ERR "aty128fb: Not enough memory for mode\n");
1102 return -EINVAL;
1103 }
1104
1105 h_disp = (xres >> 3) - 1;
1106 h_total = (((xres + right + hslen + left) >> 3) - 1) & 0xFFFFL;
1107
1108 v_disp = yres - 1;
1109 v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL;
1110
1111 /* check to make sure h_total and v_total are in range */
1112 if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) {
1113 printk(KERN_ERR "aty128fb: invalid width ranges\n");
1114 return -EINVAL;
1115 }
1116
1117 h_sync_wid = (hslen + 7) >> 3;
1118 if (h_sync_wid == 0)
1119 h_sync_wid = 1;
1120 else if (h_sync_wid > 0x3f) /* 0x3f = max hwidth */
1121 h_sync_wid = 0x3f;
1122
1123 h_sync_strt = (h_disp << 3) + right;
1124
1125 v_sync_wid = vslen;
1126 if (v_sync_wid == 0)
1127 v_sync_wid = 1;
1128 else if (v_sync_wid > 0x1f) /* 0x1f = max vwidth */
1129 v_sync_wid = 0x1f;
1130
1131 v_sync_strt = v_disp + lower;
1132
1133 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1134 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1135
1136 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1137
1138 crtc->gen_cntl = 0x3000000L | c_sync | (dst << 8);
1139
1140 crtc->h_total = h_total | (h_disp << 16);
1141 crtc->v_total = v_total | (v_disp << 16);
1142
1143 crtc->h_sync_strt_wid = h_sync_strt | (h_sync_wid << 16) |
1144 (h_sync_pol << 23);
1145 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) |
1146 (v_sync_pol << 23);
1147
1148 crtc->pitch = vxres >> 3;
1149
1150 crtc->offset = 0;
1151
1152 if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
1153 crtc->offset_cntl = 0x00010000;
1154 else
1155 crtc->offset_cntl = 0;
1156
1157 crtc->vxres = vxres;
1158 crtc->vyres = vyres;
1159 crtc->xoffset = xoffset;
1160 crtc->yoffset = yoffset;
1161 crtc->depth = depth;
1162 crtc->bpp = bpp;
1163
1164 return 0;
1165 }
1166
1167
1168 static int aty128_pix_width_to_var(int pix_width, struct fb_var_screeninfo *var)
1169 {
1170
1171 /* fill in pixel info */
1172 var->red.msb_right = 0;
1173 var->green.msb_right = 0;
1174 var->blue.offset = 0;
1175 var->blue.msb_right = 0;
1176 var->transp.offset = 0;
1177 var->transp.length = 0;
1178 var->transp.msb_right = 0;
1179 switch (pix_width) {
1180 case CRTC_PIX_WIDTH_8BPP:
1181 var->bits_per_pixel = 8;
1182 var->red.offset = 0;
1183 var->red.length = 8;
1184 var->green.offset = 0;
1185 var->green.length = 8;
1186 var->blue.length = 8;
1187 break;
1188 case CRTC_PIX_WIDTH_15BPP:
1189 var->bits_per_pixel = 16;
1190 var->red.offset = 10;
1191 var->red.length = 5;
1192 var->green.offset = 5;
1193 var->green.length = 5;
1194 var->blue.length = 5;
1195 break;
1196 case CRTC_PIX_WIDTH_16BPP:
1197 var->bits_per_pixel = 16;
1198 var->red.offset = 11;
1199 var->red.length = 5;
1200 var->green.offset = 5;
1201 var->green.length = 6;
1202 var->blue.length = 5;
1203 break;
1204 case CRTC_PIX_WIDTH_24BPP:
1205 var->bits_per_pixel = 24;
1206 var->red.offset = 16;
1207 var->red.length = 8;
1208 var->green.offset = 8;
1209 var->green.length = 8;
1210 var->blue.length = 8;
1211 break;
1212 case CRTC_PIX_WIDTH_32BPP:
1213 var->bits_per_pixel = 32;
1214 var->red.offset = 16;
1215 var->red.length = 8;
1216 var->green.offset = 8;
1217 var->green.length = 8;
1218 var->blue.length = 8;
1219 var->transp.offset = 24;
1220 var->transp.length = 8;
1221 break;
1222 default:
1223 printk(KERN_ERR "aty128fb: Invalid pixel width\n");
1224 return -EINVAL;
1225 }
1226
1227 return 0;
1228 }
1229
1230
1231 static int aty128_crtc_to_var(const struct aty128_crtc *crtc,
1232 struct fb_var_screeninfo *var)
1233 {
1234 u32 xres, yres, left, right, upper, lower, hslen, vslen, sync;
1235 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
1236 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1237 u32 pix_width;
1238
1239 /* fun with masking */
1240 h_total = crtc->h_total & 0x1ff;
1241 h_disp = (crtc->h_total >> 16) & 0xff;
1242 h_sync_strt = (crtc->h_sync_strt_wid >> 3) & 0x1ff;
1243 h_sync_dly = crtc->h_sync_strt_wid & 0x7;
1244 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x3f;
1245 h_sync_pol = (crtc->h_sync_strt_wid >> 23) & 0x1;
1246 v_total = crtc->v_total & 0x7ff;
1247 v_disp = (crtc->v_total >> 16) & 0x7ff;
1248 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1249 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1250 v_sync_pol = (crtc->v_sync_strt_wid >> 23) & 0x1;
1251 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1252 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1253
1254 /* do conversions */
1255 xres = (h_disp + 1) << 3;
1256 yres = v_disp + 1;
1257 left = ((h_total - h_sync_strt - h_sync_wid) << 3) - h_sync_dly;
1258 right = ((h_sync_strt - h_disp) << 3) + h_sync_dly;
1259 hslen = h_sync_wid << 3;
1260 upper = v_total - v_sync_strt - v_sync_wid;
1261 lower = v_sync_strt - v_disp;
1262 vslen = v_sync_wid;
1263 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1264 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1265 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1266
1267 aty128_pix_width_to_var(pix_width, var);
1268
1269 var->xres = xres;
1270 var->yres = yres;
1271 var->xres_virtual = crtc->vxres;
1272 var->yres_virtual = crtc->vyres;
1273 var->xoffset = crtc->xoffset;
1274 var->yoffset = crtc->yoffset;
1275 var->left_margin = left;
1276 var->right_margin = right;
1277 var->upper_margin = upper;
1278 var->lower_margin = lower;
1279 var->hsync_len = hslen;
1280 var->vsync_len = vslen;
1281 var->sync = sync;
1282 var->vmode = FB_VMODE_NONINTERLACED;
1283
1284 return 0;
1285 }
1286
1287 #ifdef CONFIG_PMAC_PBOOK
1288 static void aty128_set_crt_enable(struct aty128fb_par *par, int on)
1289 {
1290 if (on) {
1291 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) | CRT_CRTC_ON);
1292 aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) | DAC_PALETTE2_SNOOP_EN));
1293 } else
1294 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) & ~CRT_CRTC_ON);
1295 }
1296
1297 static void aty128_set_lcd_enable(struct aty128fb_par *par, int on)
1298 {
1299 u32 reg;
1300
1301 if (on) {
1302 reg = aty_ld_le32(LVDS_GEN_CNTL);
1303 reg |= LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION;
1304 reg &= ~LVDS_DISPLAY_DIS;
1305 aty_st_le32(LVDS_GEN_CNTL, reg);
1306 #ifdef CONFIG_PMAC_BACKLIGHT
1307 aty128_set_backlight_enable(get_backlight_enable(),
1308 get_backlight_level(), par);
1309 #endif
1310 } else {
1311 #ifdef CONFIG_PMAC_BACKLIGHT
1312 aty128_set_backlight_enable(0, 0, par);
1313 #endif
1314 reg = aty_ld_le32(LVDS_GEN_CNTL);
1315 reg |= LVDS_DISPLAY_DIS;
1316 aty_st_le32(LVDS_GEN_CNTL, reg);
1317 mdelay(100);
1318 reg &= ~(LVDS_ON /*| LVDS_EN*/);
1319 aty_st_le32(LVDS_GEN_CNTL, reg);
1320 }
1321 }
1322 #endif /* CONFIG_PMAC_PBOOK */
1323
1324 static void aty128_set_pll(struct aty128_pll *pll, const struct aty128fb_par *par)
1325 {
1326 u32 div3;
1327
1328 unsigned char post_conv[] = /* register values for post dividers */
1329 { 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 };
1330
1331 /* select PPLL_DIV_3 */
1332 aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8));
1333
1334 /* reset PLL */
1335 aty_st_pll(PPLL_CNTL,
1336 aty_ld_pll(PPLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN);
1337
1338 /* write the reference divider */
1339 aty_pll_wait_readupdate(par);
1340 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider & 0x3ff);
1341 aty_pll_writeupdate(par);
1342
1343 div3 = aty_ld_pll(PPLL_DIV_3);
1344 div3 &= ~PPLL_FB3_DIV_MASK;
1345 div3 |= pll->feedback_divider;
1346 div3 &= ~PPLL_POST3_DIV_MASK;
1347 div3 |= post_conv[pll->post_divider] << 16;
1348
1349 /* write feedback and post dividers */
1350 aty_pll_wait_readupdate(par);
1351 aty_st_pll(PPLL_DIV_3, div3);
1352 aty_pll_writeupdate(par);
1353
1354 aty_pll_wait_readupdate(par);
1355 aty_st_pll(HTOTAL_CNTL, 0); /* no horiz crtc adjustment */
1356 aty_pll_writeupdate(par);
1357
1358 /* clear the reset, just in case */
1359 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~PPLL_RESET);
1360 }
1361
1362
1363 static int aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll,
1364 const struct aty128fb_par *par)
1365 {
1366 const struct aty128_constants c = par->constants;
1367 unsigned char post_dividers[] = {1,2,4,8,3,6,12};
1368 u32 output_freq;
1369 u32 vclk; /* in .01 MHz */
1370 int i;
1371 u32 n, d;
1372
1373 vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */
1374
1375 /* adjust pixel clock if necessary */
1376 if (vclk > c.ppll_max)
1377 vclk = c.ppll_max;
1378 if (vclk * 12 < c.ppll_min)
1379 vclk = c.ppll_min/12;
1380
1381 /* now, find an acceptable divider */
1382 for (i = 0; i < sizeof(post_dividers); i++) {
1383 output_freq = post_dividers[i] * vclk;
1384 if (output_freq >= c.ppll_min && output_freq <= c.ppll_max)
1385 break;
1386 }
1387
1388 /* calculate feedback divider */
1389 n = c.ref_divider * output_freq;
1390 d = c.ref_clk;
1391
1392 pll->post_divider = post_dividers[i];
1393 pll->feedback_divider = round_div(n, d);
1394 pll->vclk = vclk;
1395
1396 DBG("post %d feedback %d vlck %d output %d ref_divider %d "
1397 "vclk_per: %d\n", pll->post_divider,
1398 pll->feedback_divider, vclk, output_freq,
1399 c.ref_divider, period_in_ps);
1400
1401 return 0;
1402 }
1403
1404
1405 static int aty128_pll_to_var(const struct aty128_pll *pll, struct fb_var_screeninfo *var)
1406 {
1407 var->pixclock = 100000000 / pll->vclk;
1408
1409 return 0;
1410 }
1411
1412
1413 static void aty128_set_fifo(const struct aty128_ddafifo *dsp,
1414 const struct aty128fb_par *par)
1415 {
1416 aty_st_le32(DDA_CONFIG, dsp->dda_config);
1417 aty_st_le32(DDA_ON_OFF, dsp->dda_on_off);
1418 }
1419
1420
1421 static int aty128_ddafifo(struct aty128_ddafifo *dsp,
1422 const struct aty128_pll *pll,
1423 u32 depth,
1424 const struct aty128fb_par *par)
1425 {
1426 const struct aty128_meminfo *m = par->mem;
1427 u32 xclk = par->constants.xclk;
1428 u32 fifo_width = par->constants.fifo_width;
1429 u32 fifo_depth = par->constants.fifo_depth;
1430 s32 x, b, p, ron, roff;
1431 u32 n, d, bpp;
1432
1433 /* round up to multiple of 8 */
1434 bpp = (depth+7) & ~7;
1435
1436 n = xclk * fifo_width;
1437 d = pll->vclk * bpp;
1438 x = round_div(n, d);
1439
1440 ron = 4 * m->MB +
1441 3 * ((m->Trcd - 2 > 0) ? m->Trcd - 2 : 0) +
1442 2 * m->Trp +
1443 m->Twr +
1444 m->CL +
1445 m->Tr2w +
1446 x;
1447
1448 DBG("x %x\n", x);
1449
1450 b = 0;
1451 while (x) {
1452 x >>= 1;
1453 b++;
1454 }
1455 p = b + 1;
1456
1457 ron <<= (11 - p);
1458
1459 n <<= (11 - p);
1460 x = round_div(n, d);
1461 roff = x * (fifo_depth - 4);
1462
1463 if ((ron + m->Rloop) >= roff) {
1464 printk(KERN_ERR "aty128fb: Mode out of range!\n");
1465 return -EINVAL;
1466 }
1467
1468 DBG("p: %x rloop: %x x: %x ron: %x roff: %x\n",
1469 p, m->Rloop, x, ron, roff);
1470
1471 dsp->dda_config = p << 16 | m->Rloop << 20 | x;
1472 dsp->dda_on_off = ron << 16 | roff;
1473
1474 return 0;
1475 }
1476
1477
1478 /*
1479 * This actually sets the video mode.
1480 */
1481 static int aty128fb_set_par(struct fb_info *info)
1482 {
1483 struct aty128fb_par *par = info->par;
1484 u32 config;
1485 int err;
1486
1487 if ((err = aty128_decode_var(&info->var, par)) != 0)
1488 return err;
1489
1490 if (par->blitter_may_be_busy)
1491 wait_for_idle(par);
1492
1493 /* clear all registers that may interfere with mode setting */
1494 aty_st_le32(OVR_CLR, 0);
1495 aty_st_le32(OVR_WID_LEFT_RIGHT, 0);
1496 aty_st_le32(OVR_WID_TOP_BOTTOM, 0);
1497 aty_st_le32(OV0_SCALE_CNTL, 0);
1498 aty_st_le32(MPP_TB_CONFIG, 0);
1499 aty_st_le32(MPP_GP_CONFIG, 0);
1500 aty_st_le32(SUBPIC_CNTL, 0);
1501 aty_st_le32(VIPH_CONTROL, 0);
1502 aty_st_le32(I2C_CNTL_1, 0); /* turn off i2c */
1503 aty_st_le32(GEN_INT_CNTL, 0); /* turn off interrupts */
1504 aty_st_le32(CAP0_TRIG_CNTL, 0);
1505 aty_st_le32(CAP1_TRIG_CNTL, 0);
1506
1507 aty_st_8(CRTC_EXT_CNTL + 1, 4); /* turn video off */
1508
1509 aty128_set_crtc(&par->crtc, par);
1510 aty128_set_pll(&par->pll, par);
1511 aty128_set_fifo(&par->fifo_reg, par);
1512
1513 config = aty_ld_le32(CONFIG_CNTL) & ~3;
1514
1515 #if defined(__BIG_ENDIAN)
1516 if (par->crtc.bpp == 32)
1517 config |= 2; /* make aperture do 32 bit swapping */
1518 else if (par->crtc.bpp == 16)
1519 config |= 1; /* make aperture do 16 bit swapping */
1520 #endif
1521
1522 aty_st_le32(CONFIG_CNTL, config);
1523 aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */
1524
1525 info->fix.line_length = (par->crtc.vxres * par->crtc.bpp) >> 3;
1526 info->fix.visual = par->crtc.bpp == 8 ? FB_VISUAL_PSEUDOCOLOR
1527 : FB_VISUAL_DIRECTCOLOR;
1528
1529 #ifdef CONFIG_PMAC_PBOOK
1530 if (par->chip_gen == rage_M3) {
1531 aty128_set_crt_enable(par, par->crt_on);
1532 aty128_set_lcd_enable(par, par->lcd_on);
1533 }
1534 #endif
1535 if (par->accel_flags & FB_ACCELF_TEXT)
1536 aty128_init_engine(par);
1537
1538 #ifdef CONFIG_BOOTX_TEXT
1539 btext_update_display(info->fix.smem_start,
1540 (((par->crtc.h_total>>16) & 0xff)+1)*8,
1541 ((par->crtc.v_total>>16) & 0x7ff)+1,
1542 par->crtc.bpp,
1543 par->crtc.vxres*par->crtc.bpp/8);
1544 #endif /* CONFIG_BOOTX_TEXT */
1545
1546 return 0;
1547 }
1548
1549 /*
1550 * encode/decode the User Defined Part of the Display
1551 */
1552
1553 static int aty128_decode_var(struct fb_var_screeninfo *var, struct aty128fb_par *par)
1554 {
1555 int err;
1556 struct aty128_crtc crtc;
1557 struct aty128_pll pll;
1558 struct aty128_ddafifo fifo_reg;
1559
1560 if ((err = aty128_var_to_crtc(var, &crtc, par)))
1561 return err;
1562
1563 if ((err = aty128_var_to_pll(var->pixclock, &pll, par)))
1564 return err;
1565
1566 if ((err = aty128_ddafifo(&fifo_reg, &pll, crtc.depth, par)))
1567 return err;
1568
1569 par->crtc = crtc;
1570 par->pll = pll;
1571 par->fifo_reg = fifo_reg;
1572 par->accel_flags = var->accel_flags;
1573
1574 return 0;
1575 }
1576
1577
1578 static int aty128_encode_var(struct fb_var_screeninfo *var,
1579 const struct aty128fb_par *par)
1580 {
1581 int err;
1582
1583 if ((err = aty128_crtc_to_var(&par->crtc, var)))
1584 return err;
1585
1586 if ((err = aty128_pll_to_var(&par->pll, var)))
1587 return err;
1588
1589 var->nonstd = 0;
1590 var->activate = 0;
1591
1592 var->height = -1;
1593 var->width = -1;
1594 var->accel_flags = par->accel_flags;
1595
1596 return 0;
1597 }
1598
1599
1600 static int aty128fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1601 {
1602 struct aty128fb_par par;
1603 int err;
1604
1605 par = *(struct aty128fb_par *)info->par;
1606 if ((err = aty128_decode_var(var, &par)) != 0)
1607 return err;
1608 aty128_encode_var(var, &par);
1609 return 0;
1610 }
1611
1612
1613 /*
1614 * Pan or Wrap the Display
1615 */
1616 static int aty128fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *fb)
1617 {
1618 struct aty128fb_par *par = fb->par;
1619 u32 xoffset, yoffset;
1620 u32 offset;
1621 u32 xres, yres;
1622
1623 xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3;
1624 yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1;
1625
1626 xoffset = (var->xoffset +7) & ~7;
1627 yoffset = var->yoffset;
1628
1629 if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres)
1630 return -EINVAL;
1631
1632 par->crtc.xoffset = xoffset;
1633 par->crtc.yoffset = yoffset;
1634
1635 offset = ((yoffset * par->crtc.vxres + xoffset)*(par->crtc.bpp >> 3)) & ~7;
1636
1637 if (par->crtc.bpp == 24)
1638 offset += 8 * (offset % 3); /* Must be multiple of 8 and 3 */
1639
1640 aty_st_le32(CRTC_OFFSET, offset);
1641
1642 return 0;
1643 }
1644
1645
1646 /*
1647 * Helper function to store a single palette register
1648 */
1649 static void aty128_st_pal(u_int regno, u_int red, u_int green, u_int blue,
1650 struct aty128fb_par *par)
1651 {
1652 if (par->chip_gen == rage_M3) {
1653 #if 0
1654 /* Note: For now, on M3, we set palette on both heads, which may
1655 * be useless. Can someone with a M3 check this ?
1656 *
1657 * This code would still be useful if using the second CRTC to
1658 * do mirroring
1659 */
1660
1661 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PALETTE_ACCESS_CNTL);
1662 aty_st_8(PALETTE_INDEX, regno);
1663 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
1664 #endif
1665 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & ~DAC_PALETTE_ACCESS_CNTL);
1666 }
1667
1668 aty_st_8(PALETTE_INDEX, regno);
1669 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
1670 }
1671
1672 static int aty128fb_sync(struct fb_info *info)
1673 {
1674 struct aty128fb_par *par = info->par;
1675
1676 if (par->blitter_may_be_busy)
1677 wait_for_idle(par);
1678 return 0;
1679 }
1680
1681 int __init aty128fb_setup(char *options)
1682 {
1683 char *this_opt;
1684
1685 if (!options || !*options)
1686 return 0;
1687
1688 while ((this_opt = strsep(&options, ",")) != NULL) {
1689 #ifdef CONFIG_PMAC_PBOOK
1690 if (!strncmp(this_opt, "lcd:", 4)) {
1691 default_lcd_on = simple_strtoul(this_opt+4, NULL, 0);
1692 continue;
1693 } else if (!strncmp(this_opt, "crt:", 4)) {
1694 default_crt_on = simple_strtoul(this_opt+4, NULL, 0);
1695 continue;
1696 }
1697 #endif
1698 #ifdef CONFIG_MTRR
1699 if(!strncmp(this_opt, "nomtrr", 6)) {
1700 mtrr = 0;
1701 continue;
1702 }
1703 #endif
1704 #ifdef CONFIG_PPC_PMAC
1705 /* vmode and cmode deprecated */
1706 if (!strncmp(this_opt, "vmode:", 6)) {
1707 unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0);
1708 if (vmode > 0 && vmode <= VMODE_MAX)
1709 default_vmode = vmode;
1710 continue;
1711 } else if (!strncmp(this_opt, "cmode:", 6)) {
1712 unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0);
1713 switch (cmode) {
1714 case 0:
1715 case 8:
1716 default_cmode = CMODE_8;
1717 break;
1718 case 15:
1719 case 16:
1720 default_cmode = CMODE_16;
1721 break;
1722 case 24:
1723 case 32:
1724 default_cmode = CMODE_32;
1725 break;
1726 }
1727 continue;
1728 }
1729 #endif /* CONFIG_PPC_PMAC */
1730 mode_option = this_opt;
1731 }
1732 return 0;
1733 }
1734
1735
1736 /*
1737 * Initialisation
1738 */
1739
1740 static int __init aty128_init(struct pci_dev *pdev, const struct pci_device_id *ent)
1741 {
1742 struct fb_info *info = pci_get_drvdata(pdev);
1743 struct aty128fb_par *par = info->par;
1744 struct fb_var_screeninfo var;
1745 char video_card[DEVICE_NAME_SIZE];
1746 u8 chip_rev;
1747 u32 dac;
1748
1749 if (!par->vram_size) /* may have already been probed */
1750 par->vram_size = aty_ld_le32(CONFIG_MEMSIZE) & 0x03FFFFFF;
1751
1752 /* Get the chip revision */
1753 chip_rev = (aty_ld_le32(CONFIG_CNTL) >> 16) & 0x1F;
1754
1755 strcpy(video_card, "Rage128 XX ");
1756 video_card[8] = ent->device >> 8;
1757 video_card[9] = ent->device & 0xFF;
1758
1759 /* range check to make sure */
1760 if (ent->driver_data < (sizeof(r128_family)/sizeof(char *)))
1761 strncat(video_card, r128_family[ent->driver_data], sizeof(video_card));
1762
1763 printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev);
1764
1765 if (par->vram_size % (1024 * 1024) == 0)
1766 printk("%dM %s\n", par->vram_size / (1024*1024), par->mem->name);
1767 else
1768 printk("%dk %s\n", par->vram_size / 1024, par->mem->name);
1769
1770 par->chip_gen = ent->driver_data;
1771
1772 /* fill in info */
1773 info->fbops = &aty128fb_ops;
1774 info->flags = FBINFO_FLAG_DEFAULT;
1775
1776 #ifdef CONFIG_PMAC_PBOOK
1777 par->lcd_on = default_lcd_on;
1778 par->crt_on = default_crt_on;
1779 #endif
1780
1781 var = default_var;
1782 #ifdef CONFIG_PPC_PMAC
1783 if (_machine == _MACH_Pmac) {
1784 if (mode_option) {
1785 if (!mac_find_mode(&var, info, mode_option, 8))
1786 var = default_var;
1787 } else {
1788 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
1789 default_vmode = VMODE_1024_768_60;
1790
1791 /* iMacs need that resolution
1792 * PowerMac2,1 first r128 iMacs
1793 * PowerMac2,2 summer 2000 iMacs
1794 * PowerMac4,1 january 2001 iMacs "flower power"
1795 */
1796 if (machine_is_compatible("PowerMac2,1") ||
1797 machine_is_compatible("PowerMac2,2") ||
1798 machine_is_compatible("PowerMac4,1"))
1799 default_vmode = VMODE_1024_768_75;
1800
1801 /* iBook SE */
1802 if (machine_is_compatible("PowerBook2,2"))
1803 default_vmode = VMODE_800_600_60;
1804
1805 /* PowerBook Firewire (Pismo), iBook Dual USB */
1806 if (machine_is_compatible("PowerBook3,1") ||
1807 machine_is_compatible("PowerBook4,1"))
1808 default_vmode = VMODE_1024_768_60;
1809
1810 /* PowerBook Titanium */
1811 if (machine_is_compatible("PowerBook3,2"))
1812 default_vmode = VMODE_1152_768_60;
1813
1814 if (default_cmode > 16)
1815 default_cmode = CMODE_32;
1816 else if (default_cmode > 8)
1817 default_cmode = CMODE_16;
1818 else
1819 default_cmode = CMODE_8;
1820
1821 if (mac_vmode_to_var(default_vmode, default_cmode, &var))
1822 var = default_var;
1823 }
1824 } else
1825 #endif /* CONFIG_PPC_PMAC */
1826 {
1827 if (mode_option)
1828 if (fb_find_mode(&var, info, mode_option, NULL,
1829 0, &defaultmode, 8) == 0)
1830 var = default_var;
1831 }
1832
1833 var.accel_flags &= ~FB_ACCELF_TEXT;
1834 // var.accel_flags |= FB_ACCELF_TEXT;/* FIXME Will add accel later */
1835
1836 if (aty128fb_check_var(&var, info)) {
1837 printk(KERN_ERR "aty128fb: Cannot set default mode.\n");
1838 return 0;
1839 }
1840
1841 /* setup the DAC the way we like it */
1842 dac = aty_ld_le32(DAC_CNTL);
1843 dac |= (DAC_8BIT_EN | DAC_RANGE_CNTL);
1844 dac |= DAC_MASK;
1845 if (par->chip_gen == rage_M3)
1846 dac |= DAC_PALETTE2_SNOOP_EN;
1847 aty_st_le32(DAC_CNTL, dac);
1848
1849 /* turn off bus mastering, just in case */
1850 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS);
1851
1852 info->var = var;
1853 fb_alloc_cmap(&info->cmap, 256, 0);
1854
1855 var.activate = FB_ACTIVATE_NOW;
1856
1857 aty128_init_engine(par);
1858
1859 if (register_framebuffer(info) < 0)
1860 return 0;
1861
1862 #ifdef CONFIG_PMAC_BACKLIGHT
1863 /* Could be extended to Rage128Pro LVDS output too */
1864 if (par->chip_gen == rage_M3)
1865 register_backlight_controller(&aty128_backlight_controller, par, "ati");
1866 #endif /* CONFIG_PMAC_BACKLIGHT */
1867
1868 par->pm_reg = pci_find_capability(pdev, PCI_CAP_ID_PM);
1869 par->pdev = pdev;
1870 par->asleep = 0;
1871 par->lock_blank = 0;
1872
1873 printk(KERN_INFO "fb%d: %s frame buffer device on %s\n",
1874 info->node, info->fix.id, video_card);
1875
1876 return 1; /* success! */
1877 }
1878
1879 #ifdef CONFIG_PCI
1880 /* register a card ++ajoshi */
1881 static int __init aty128_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1882 {
1883 unsigned long fb_addr, reg_addr;
1884 struct aty128fb_par *par;
1885 struct fb_info *info;
1886 int err;
1887 #ifndef __sparc__
1888 void *bios = NULL;
1889 #endif
1890
1891 /* Enable device in PCI config */
1892 if ((err = pci_enable_device(pdev))) {
1893 printk(KERN_ERR "aty128fb: Cannot enable PCI device: %d\n",
1894 err);
1895 return -ENODEV;
1896 }
1897
1898 fb_addr = pci_resource_start(pdev, 0);
1899 if (!request_mem_region(fb_addr, pci_resource_len(pdev, 0),
1900 "aty128fb FB")) {
1901 printk(KERN_ERR "aty128fb: cannot reserve frame "
1902 "buffer memory\n");
1903 return -ENODEV;
1904 }
1905
1906 reg_addr = pci_resource_start(pdev, 2);
1907 if (!request_mem_region(reg_addr, pci_resource_len(pdev, 2),
1908 "aty128fb MMIO")) {
1909 printk(KERN_ERR "aty128fb: cannot reserve MMIO region\n");
1910 goto err_free_fb;
1911 }
1912
1913 /* We have the resources. Now virtualize them */
1914 info = framebuffer_alloc(sizeof(struct aty128fb_par), &pdev->dev);
1915 if (info == NULL) {
1916 printk(KERN_ERR "aty128fb: can't alloc fb_info_aty128\n");
1917 goto err_free_mmio;
1918 }
1919 par = info->par;
1920
1921 info->pseudo_palette = par->pseudo_palette;
1922 info->fix = aty128fb_fix;
1923
1924 /* Virtualize mmio region */
1925 info->fix.mmio_start = reg_addr;
1926 par->regbase = ioremap(reg_addr, pci_resource_len(pdev, 2));
1927 if (!par->regbase)
1928 goto err_free_info;
1929
1930 /* Grab memory size from the card */
1931 // How does this relate to the resource length from the PCI hardware?
1932 par->vram_size = aty_ld_le32(CONFIG_MEMSIZE) & 0x03FFFFFF;
1933
1934 /* Virtualize the framebuffer */
1935 info->screen_base = ioremap(fb_addr, par->vram_size);
1936 if (!info->screen_base)
1937 goto err_unmap_out;
1938
1939 /* Set up info->fix */
1940 info->fix = aty128fb_fix;
1941 info->fix.smem_start = fb_addr;
1942 info->fix.smem_len = par->vram_size;
1943 info->fix.mmio_start = reg_addr;
1944
1945 /* If we can't test scratch registers, something is seriously wrong */
1946 if (!register_test(par)) {
1947 printk(KERN_ERR "aty128fb: Can't write to video register!\n");
1948 goto err_out;
1949 }
1950
1951 #ifndef __sparc__
1952 bios = aty128_map_ROM(par, pdev);
1953 #ifdef CONFIG_X86
1954 if (bios == NULL)
1955 bios = aty128_find_mem_vbios(par);
1956 #endif
1957 if (bios == NULL)
1958 printk(KERN_INFO "aty128fb: BIOS not located, guessing timings.\n");
1959 else {
1960 printk(KERN_INFO "aty128fb: Rage128 BIOS located\n");
1961 aty128_get_pllinfo(par, bios);
1962 aty128_unmap_ROM(pdev, bios);
1963 }
1964 #endif /* __sparc__ */
1965
1966 aty128_timings(par);
1967 pci_set_drvdata(pdev, info);
1968
1969 if (!aty128_init(pdev, ent))
1970 goto err_out;
1971
1972 #ifdef CONFIG_MTRR
1973 if (mtrr) {
1974 par->mtrr.vram = mtrr_add(info->fix.smem_start,
1975 par->vram_size, MTRR_TYPE_WRCOMB, 1);
1976 par->mtrr.vram_valid = 1;
1977 /* let there be speed */
1978 printk(KERN_INFO "aty128fb: Rage128 MTRR set to ON\n");
1979 }
1980 #endif /* CONFIG_MTRR */
1981 return 0;
1982
1983 err_out:
1984 iounmap(info->screen_base);
1985 err_unmap_out:
1986 iounmap(par->regbase);
1987 err_free_info:
1988 framebuffer_release(info);
1989 err_free_mmio:
1990 release_mem_region(pci_resource_start(pdev, 2),
1991 pci_resource_len(pdev, 2));
1992 err_free_fb:
1993 release_mem_region(pci_resource_start(pdev, 0),
1994 pci_resource_len(pdev, 0));
1995 return -ENODEV;
1996 }
1997
1998 static void __devexit aty128_remove(struct pci_dev *pdev)
1999 {
2000 struct fb_info *info = pci_get_drvdata(pdev);
2001 struct aty128fb_par *par;
2002
2003 if (!info)
2004 return;
2005
2006 par = info->par;
2007
2008 unregister_framebuffer(info);
2009 #ifdef CONFIG_MTRR
2010 if (par->mtrr.vram_valid)
2011 mtrr_del(par->mtrr.vram, info->fix.smem_start,
2012 par->vram_size);
2013 #endif /* CONFIG_MTRR */
2014 iounmap(par->regbase);
2015 iounmap(info->screen_base);
2016
2017 release_mem_region(pci_resource_start(pdev, 0),
2018 pci_resource_len(pdev, 0));
2019 release_mem_region(pci_resource_start(pdev, 1),
2020 pci_resource_len(pdev, 1));
2021 release_mem_region(pci_resource_start(pdev, 2),
2022 pci_resource_len(pdev, 2));
2023 framebuffer_release(info);
2024 }
2025 #endif /* CONFIG_PCI */
2026
2027
2028
2029 /*
2030 * Blank the display.
2031 */
2032 static int aty128fb_blank(int blank, struct fb_info *fb)
2033 {
2034 struct aty128fb_par *par = fb->par;
2035 u8 state = 0;
2036
2037 if (par->lock_blank || par->asleep)
2038 return 0;
2039
2040 #ifdef CONFIG_PMAC_BACKLIGHT
2041 if ((_machine == _MACH_Pmac) && blank)
2042 set_backlight_enable(0);
2043 #endif /* CONFIG_PMAC_BACKLIGHT */
2044
2045 if (blank & VESA_VSYNC_SUSPEND)
2046 state |= 2;
2047 if (blank & VESA_HSYNC_SUSPEND)
2048 state |= 1;
2049 if (blank & VESA_POWERDOWN)
2050 state |= 4;
2051
2052 aty_st_8(CRTC_EXT_CNTL+1, state);
2053
2054 #ifdef CONFIG_PMAC_PBOOK
2055 if (par->chip_gen == rage_M3) {
2056 aty128_set_crt_enable(par, par->crt_on && !blank);
2057 aty128_set_lcd_enable(par, par->lcd_on && !blank);
2058 }
2059 #endif
2060 #ifdef CONFIG_PMAC_BACKLIGHT
2061 if ((_machine == _MACH_Pmac) && !blank)
2062 set_backlight_enable(1);
2063 #endif /* CONFIG_PMAC_BACKLIGHT */
2064 return 0;
2065 }
2066
2067 /*
2068 * Set a single color register. The values supplied are already
2069 * rounded down to the hardware's capabilities (according to the
2070 * entries in the var structure). Return != 0 for invalid regno.
2071 */
2072 static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2073 u_int transp, struct fb_info *info)
2074 {
2075 struct aty128fb_par *par = info->par;
2076
2077 if (regno > 255
2078 || (par->crtc.depth == 16 && regno > 63)
2079 || (par->crtc.depth == 15 && regno > 31))
2080 return 1;
2081
2082 red >>= 8;
2083 green >>= 8;
2084 blue >>= 8;
2085
2086 if (regno < 16) {
2087 int i;
2088 u32 *pal = info->pseudo_palette;
2089
2090 switch (par->crtc.depth) {
2091 case 15:
2092 pal[regno] = (regno << 10) | (regno << 5) | regno;
2093 break;
2094 case 16:
2095 pal[regno] = (regno << 11) | (regno << 6) | regno;
2096 break;
2097 case 24:
2098 pal[regno] = (regno << 16) | (regno << 8) | regno;
2099 break;
2100 case 32:
2101 i = (regno << 8) | regno;
2102 pal[regno] = (i << 16) | i;
2103 break;
2104 }
2105 }
2106
2107 if (par->crtc.depth == 16 && regno > 0) {
2108 /*
2109 * With the 5-6-5 split of bits for RGB at 16 bits/pixel, we
2110 * have 32 slots for R and B values but 64 slots for G values.
2111 * Thus the R and B values go in one slot but the G value
2112 * goes in a different slot, and we have to avoid disturbing
2113 * the other fields in the slots we touch.
2114 */
2115 par->green[regno] = green;
2116 if (regno < 32) {
2117 par->red[regno] = red;
2118 par->blue[regno] = blue;
2119 aty128_st_pal(regno * 8, red, par->green[regno*2],
2120 blue, par);
2121 }
2122 red = par->red[regno/2];
2123 blue = par->blue[regno/2];
2124 regno <<= 2;
2125 } else if (par->crtc.bpp == 16)
2126 regno <<= 3;
2127 aty128_st_pal(regno, red, green, blue, par);
2128
2129 return 0;
2130 }
2131
2132 #define ATY_MIRROR_LCD_ON 0x00000001
2133 #define ATY_MIRROR_CRT_ON 0x00000002
2134
2135 /* out param: u32* backlight value: 0 to 15 */
2136 #define FBIO_ATY128_GET_MIRROR _IOR('@', 1, __u32)
2137 /* in param: u32* backlight value: 0 to 15 */
2138 #define FBIO_ATY128_SET_MIRROR _IOW('@', 2, __u32)
2139
2140 static int aty128fb_ioctl(struct inode *inode, struct file *file, u_int cmd,
2141 u_long arg, struct fb_info *info)
2142 {
2143 #ifdef CONFIG_PMAC_PBOOK
2144 struct aty128fb_par *par = info->par;
2145 u32 value;
2146 int rc;
2147
2148 switch (cmd) {
2149 case FBIO_ATY128_SET_MIRROR:
2150 if (par->chip_gen != rage_M3)
2151 return -EINVAL;
2152 rc = get_user(value, (__u32 __user *)arg);
2153 if (rc)
2154 return rc;
2155 par->lcd_on = (value & 0x01) != 0;
2156 par->crt_on = (value & 0x02) != 0;
2157 if (!par->crt_on && !par->lcd_on)
2158 par->lcd_on = 1;
2159 aty128_set_crt_enable(par, par->crt_on);
2160 aty128_set_lcd_enable(par, par->lcd_on);
2161 return 0;
2162 case FBIO_ATY128_GET_MIRROR:
2163 if (par->chip_gen != rage_M3)
2164 return -EINVAL;
2165 value = (par->crt_on << 1) | par->lcd_on;
2166 return put_user(value, (__u32 __user *)arg);
2167 }
2168 #endif
2169 return -EINVAL;
2170 }
2171
2172 #ifdef CONFIG_PMAC_BACKLIGHT
2173 static int backlight_conv[] = {
2174 0xff, 0xc0, 0xb5, 0xaa, 0x9f, 0x94, 0x89, 0x7e,
2175 0x73, 0x68, 0x5d, 0x52, 0x47, 0x3c, 0x31, 0x24
2176 };
2177
2178 /* We turn off the LCD completely instead of just dimming the backlight.
2179 * This provides greater power saving and the display is useless without
2180 * backlight anyway
2181 */
2182 #define BACKLIGHT_LVDS_OFF
2183 /* That one prevents proper CRT output with LCD off */
2184 #undef BACKLIGHT_DAC_OFF
2185
2186 static int aty128_set_backlight_enable(int on, int level, void *data)
2187 {
2188 struct aty128fb_par *par = data;
2189 unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL);
2190
2191 if (!par->lcd_on)
2192 on = 0;
2193 reg |= LVDS_BL_MOD_EN | LVDS_BLON;
2194 if (on && level > BACKLIGHT_OFF) {
2195 reg |= LVDS_DIGION;
2196 if (!(reg & LVDS_ON)) {
2197 reg &= ~LVDS_BLON;
2198 aty_st_le32(LVDS_GEN_CNTL, reg);
2199 (void)aty_ld_le32(LVDS_GEN_CNTL);
2200 mdelay(10);
2201 reg |= LVDS_BLON;
2202 aty_st_le32(LVDS_GEN_CNTL, reg);
2203 }
2204 reg &= ~LVDS_BL_MOD_LEVEL_MASK;
2205 reg |= (backlight_conv[level] << LVDS_BL_MOD_LEVEL_SHIFT);
2206 #ifdef BACKLIGHT_LVDS_OFF
2207 reg |= LVDS_ON | LVDS_EN;
2208 reg &= ~LVDS_DISPLAY_DIS;
2209 #endif
2210 aty_st_le32(LVDS_GEN_CNTL, reg);
2211 #ifdef BACKLIGHT_DAC_OFF
2212 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN));
2213 #endif
2214 } else {
2215 reg &= ~LVDS_BL_MOD_LEVEL_MASK;
2216 reg |= (backlight_conv[0] << LVDS_BL_MOD_LEVEL_SHIFT);
2217 #ifdef BACKLIGHT_LVDS_OFF
2218 reg |= LVDS_DISPLAY_DIS;
2219 aty_st_le32(LVDS_GEN_CNTL, reg);
2220 (void)aty_ld_le32(LVDS_GEN_CNTL);
2221 udelay(10);
2222 reg &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION);
2223 #endif
2224 aty_st_le32(LVDS_GEN_CNTL, reg);
2225 #ifdef BACKLIGHT_DAC_OFF
2226 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN);
2227 #endif
2228 }
2229
2230 return 0;
2231 }
2232
2233 static int aty128_set_backlight_level(int level, void* data)
2234 {
2235 return aty128_set_backlight_enable(1, level, data);
2236 }
2237 #endif /* CONFIG_PMAC_BACKLIGHT */
2238
2239 #if 0
2240 /*
2241 * Accelerated functions
2242 */
2243
2244 static inline void aty128_rectcopy(int srcx, int srcy, int dstx, int dsty,
2245 u_int width, u_int height,
2246 struct fb_info_aty128 *par)
2247 {
2248 u32 save_dp_datatype, save_dp_cntl, dstval;
2249
2250 if (!width || !height)
2251 return;
2252
2253 dstval = depth_to_dst(par->current_par.crtc.depth);
2254 if (dstval == DST_24BPP) {
2255 srcx *= 3;
2256 dstx *= 3;
2257 width *= 3;
2258 } else if (dstval == -EINVAL) {
2259 printk("aty128fb: invalid depth or RGBA\n");
2260 return;
2261 }
2262
2263 wait_for_fifo(2, par);
2264 save_dp_datatype = aty_ld_le32(DP_DATATYPE);
2265 save_dp_cntl = aty_ld_le32(DP_CNTL);
2266
2267 wait_for_fifo(6, par);
2268 aty_st_le32(SRC_Y_X, (srcy << 16) | srcx);
2269 aty_st_le32(DP_MIX, ROP3_SRCCOPY | DP_SRC_RECT);
2270 aty_st_le32(DP_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM);
2271 aty_st_le32(DP_DATATYPE, save_dp_datatype | dstval | SRC_DSTCOLOR);
2272
2273 aty_st_le32(DST_Y_X, (dsty << 16) | dstx);
2274 aty_st_le32(DST_HEIGHT_WIDTH, (height << 16) | width);
2275
2276 par->blitter_may_be_busy = 1;
2277
2278 wait_for_fifo(2, par);
2279 aty_st_le32(DP_DATATYPE, save_dp_datatype);
2280 aty_st_le32(DP_CNTL, save_dp_cntl);
2281 }
2282
2283
2284 /*
2285 * Text mode accelerated functions
2286 */
2287
2288 static void fbcon_aty128_bmove(struct display *p, int sy, int sx, int dy, int dx,
2289 int height, int width)
2290 {
2291 sx *= fontwidth(p);
2292 sy *= fontheight(p);
2293 dx *= fontwidth(p);
2294 dy *= fontheight(p);
2295 width *= fontwidth(p);
2296 height *= fontheight(p);
2297
2298 aty128_rectcopy(sx, sy, dx, dy, width, height,
2299 (struct fb_info_aty128 *)p->fb_info);
2300 }
2301 #endif /* 0 */
2302
2303 static void aty128_set_suspend(struct aty128fb_par *par, int suspend)
2304 {
2305 u32 pmgt;
2306 u16 pwr_command;
2307 struct pci_dev *pdev = par->pdev;
2308
2309 if (!par->pm_reg)
2310 return;
2311
2312 /* Set the chip into the appropriate suspend mode (we use D2,
2313 * D3 would require a complete re-initialisation of the chip,
2314 * including PCI config registers, clocks, AGP configuration, ...)
2315 */
2316 if (suspend) {
2317 /* Make sure CRTC2 is reset. Remove that the day we decide to
2318 * actually use CRTC2 and replace it with real code for disabling
2319 * the CRTC2 output during sleep
2320 */
2321 aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) &
2322 ~(CRTC2_EN));
2323
2324 /* Set the power management mode to be PCI based */
2325 /* Use this magic value for now */
2326 pmgt = 0x0c005407;
2327 aty_st_pll(POWER_MANAGEMENT, pmgt);
2328 (void)aty_ld_pll(POWER_MANAGEMENT);
2329 aty_st_le32(BUS_CNTL1, 0x00000010);
2330 aty_st_le32(MEM_POWER_MISC, 0x0c830000);
2331 mdelay(100);
2332 pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command);
2333 /* Switch PCI power management to D2 */
2334 pci_write_config_word(pdev, par->pm_reg+PCI_PM_CTRL,
2335 (pwr_command & ~PCI_PM_CTRL_STATE_MASK) | 2);
2336 pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command);
2337 } else {
2338 /* Switch back PCI power management to D0 */
2339 mdelay(100);
2340 pci_write_config_word(pdev, par->pm_reg+PCI_PM_CTRL, 0);
2341 pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command);
2342 mdelay(100);
2343 }
2344 }
2345
2346 static int aty128_pci_suspend(struct pci_dev *pdev, u32 state)
2347 {
2348 struct fb_info *info = pci_get_drvdata(pdev);
2349 struct aty128fb_par *par = info->par;
2350
2351 /* We don't do anything but D2, for now we return 0, but
2352 * we may want to change that. How do we know if the BIOS
2353 * can properly take care of D3 ? Also, with swsusp, we
2354 * know we'll be rebooted, ...
2355 */
2356 #ifdef CONFIG_PPC_PMAC
2357 /* HACK ALERT ! Once I find a proper way to say to each driver
2358 * individually what will happen with it's PCI slot, I'll change
2359 * that. On laptops, the AGP slot is just unclocked, so D2 is
2360 * expected, while on desktops, the card is powered off
2361 */
2362 if (state >= 3)
2363 state = 2;
2364 #endif /* CONFIG_PPC_PMAC */
2365
2366 if (state != 2 || state == pdev->dev.power_state)
2367 return 0;
2368
2369 printk(KERN_DEBUG "aty128fb: suspending...\n");
2370
2371 acquire_console_sem();
2372
2373 fb_set_suspend(info, 1);
2374
2375 /* Make sure engine is reset */
2376 wait_for_idle(par);
2377 aty128_reset_engine(par);
2378 wait_for_idle(par);
2379
2380 /* Blank display and LCD */
2381 aty128fb_blank(VESA_POWERDOWN, info);
2382
2383 /* Sleep */
2384 par->asleep = 1;
2385 par->lock_blank = 1;
2386
2387 /* We need a way to make sure the fbdev layer will _not_ touch the
2388 * framebuffer before we put the chip to suspend state. On 2.4, I
2389 * used dummy fb ops, 2.5 need proper support for this at the
2390 * fbdev level
2391 */
2392 if (state == 2)
2393 aty128_set_suspend(par, 1);
2394
2395 release_console_sem();
2396
2397 pdev->dev.power_state = state;
2398
2399 return 0;
2400 }
2401
2402 static int aty128_pci_resume(struct pci_dev *pdev)
2403 {
2404 struct fb_info *info = pci_get_drvdata(pdev);
2405 struct aty128fb_par *par = info->par;
2406
2407 if (pdev->dev.power_state == 0)
2408 return 0;
2409
2410 acquire_console_sem();
2411
2412 /* Wakeup chip */
2413 if (pdev->dev.power_state == 2)
2414 aty128_set_suspend(par, 0);
2415 par->asleep = 0;
2416
2417 /* Restore display & engine */
2418 aty128_reset_engine(par);
2419 wait_for_idle(par);
2420 aty128fb_set_par(info);
2421 fb_pan_display(info, &info->var);
2422 fb_set_cmap(&info->cmap, info);
2423
2424 /* Refresh */
2425 fb_set_suspend(info, 0);
2426
2427 /* Unblank */
2428 par->lock_blank = 0;
2429 aty128fb_blank(0, info);
2430
2431 release_console_sem();
2432
2433 pdev->dev.power_state = 0;
2434
2435 printk(KERN_DEBUG "aty128fb: resumed !\n");
2436
2437 return 0;
2438 }
2439
2440 int __init aty128fb_init(void)
2441 {
2442 #ifndef MODULE
2443 char *option = NULL;
2444
2445 if (fb_get_options("aty128fb", &option))
2446 return -ENODEV;
2447 aty128fb_setup(option);
2448 #endif
2449
2450 return pci_module_init(&aty128fb_driver);
2451 }
2452
2453 static void __exit aty128fb_exit(void)
2454 {
2455 pci_unregister_driver(&aty128fb_driver);
2456 }
2457
2458 module_init(aty128fb_init);
2459
2460 #ifdef MODULE
2461 module_exit(aty128fb_exit);
2462
2463 MODULE_AUTHOR("(c)1999-2003 Brad Douglas <brad@neruo.com>");
2464 MODULE_DESCRIPTION("FBDev driver for ATI Rage128 / Pro cards");
2465 MODULE_LICENSE("GPL");
2466 module_param(mode_option, charp, 0);
2467 MODULE_PARM_DESC(mode, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2468 #ifdef CONFIG_MTRR
2469 module_param_named(nomtrr, mtrr, invbool, 0);
2470 MODULE_PARM_DESC(mtrr, "bool: Disable MTRR support (0 or 1=disabled) (default=0)");
2471 #endif
2472 #endif
2473
MOXA 2.6.9 from sdlinux-moxaart.tgz