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1 /***************************************************************************\
2 |* *|
3 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
4 |* *|
5 |* NOTICE TO USER: The source code is copyrighted under U.S. and *|
6 |* international laws. Users and possessors of this source code are *|
7 |* hereby granted a nonexclusive, royalty-free copyright license to *|
8 |* use this code in individual and commercial software. *|
9 |* *|
10 |* Any use of this source code must include, in the user documenta- *|
11 |* tion and internal comments to the code, notices to the end user *|
12 |* as follows: *|
13 |* *|
14 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
15 |* *|
16 |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
17 |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
18 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
19 |* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
20 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
21 |* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
22 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
24 |* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
25 |* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
26 |* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
27 |* *|
28 |* U.S. Government End Users. This source code is a "commercial *|
29 |* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
30 |* consisting of "commercial computer software" and "commercial *|
31 |* computer software documentation," as such terms are used in *|
32 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
33 |* ment only as a commercial end item. Consistent with 48 C.F.R. *|
34 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
35 |* all U.S. Government End Users acquire the source code with only *|
36 |* those rights set forth herein. *|
37 |* *|
38 \***************************************************************************/
41 * GPL licensing note -- nVidia is allowing a liberal interpretation of
42 * the documentation restriction above, to merely say that this nVidia's
43 * copyright and disclaimer should be included with all code derived
44 * from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99
47 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.h,v 1.21 2002/10/14 18:22:46 mvojkovi Exp $ */
48 #ifndef __RIVA_HW_H__
49 #define __RIVA_HW_H__
50 #define RIVA_SW_VERSION 0x00010003
52 #ifndef Bool
53 typedef int Bool;
54 #endif
56 #ifndef TRUE
57 #define TRUE 1
58 #endif
59 #ifndef FALSE
60 #define FALSE 0
61 #endif
62 #ifndef NULL
63 #define NULL 0
64 #endif
67 * Typedefs to force certain sized values.
69 typedef unsigned char U008;
70 typedef unsigned short U016;
71 typedef unsigned int U032;
74 * HW access macros.
76 #if defined(__powerpc__)
77 #include <asm/io.h>
78 #define NV_WR08(p,i,d) out_8(p+i, d)
79 #define NV_RD08(p,i) in_8(p+i)
80 #else
81 #define NV_WR08(p,i,d) (((U008 *)(p))[i]=(d))
82 #define NV_RD08(p,i) (((U008 *)(p))[i])
83 #endif
84 #define NV_WR16(p,i,d) (((U016 *)(p))[(i)/2]=(d))
85 #define NV_RD16(p,i) (((U016 *)(p))[(i)/2])
86 #define NV_WR32(p,i,d) (((U032 *)(p))[(i)/4]=(d))
87 #define NV_RD32(p,i) (((U032 *)(p))[(i)/4])
88 #define VGA_WR08(p,i,d) NV_WR08(p,i,d)
89 #define VGA_RD08(p,i) NV_RD08(p,i)
92 * Define different architectures.
94 #define NV_ARCH_03 0x03
95 #define NV_ARCH_04 0x04
96 #define NV_ARCH_10 0x10
97 #define NV_ARCH_20 0x20
98 #define NV_ARCH_30 0x30
99 #define NV_ARCH_40 0x40
101 /***************************************************************************\
103 * FIFO registers. *
105 \***************************************************************************/
108 * Raster OPeration. Windows style ROP3.
110 typedef volatile struct
112 U032 reserved00[4];
113 #ifdef __BIG_ENDIAN
114 U032 FifoFree;
115 #else
116 U016 FifoFree;
117 U016 Nop;
118 #endif
119 U032 reserved01[0x0BB];
120 U032 Rop3;
121 } RivaRop;
123 * 8X8 Monochrome pattern.
125 typedef volatile struct
127 U032 reserved00[4];
128 #ifdef __BIG_ENDIAN
129 U032 FifoFree;
130 #else
131 U016 FifoFree;
132 U016 Nop;
133 #endif
134 U032 reserved01[0x0BD];
135 U032 Shape;
136 U032 reserved03[0x001];
137 U032 Color0;
138 U032 Color1;
139 U032 Monochrome[2];
140 } RivaPattern;
142 * Scissor clip rectangle.
144 typedef volatile struct
146 U032 reserved00[4];
147 #ifdef __BIG_ENDIAN
148 U032 FifoFree;
149 #else
150 U016 FifoFree;
151 U016 Nop;
152 #endif
153 U032 reserved01[0x0BB];
154 U032 TopLeft;
155 U032 WidthHeight;
156 } RivaClip;
158 * 2D filled rectangle.
160 typedef volatile struct
162 U032 reserved00[4];
163 #ifdef __BIG_ENDIAN
164 U032 FifoFree;
165 #else
166 U016 FifoFree;
167 U016 Nop[1];
168 #endif
169 U032 reserved01[0x0BC];
170 U032 Color;
171 U032 reserved03[0x03E];
172 U032 TopLeft;
173 U032 WidthHeight;
174 } RivaRectangle;
176 * 2D screen-screen BLT.
178 typedef volatile struct
180 U032 reserved00[4];
181 #ifdef __BIG_ENDIAN
182 U032 FifoFree;
183 #else
184 U016 FifoFree;
185 U016 Nop;
186 #endif
187 U032 reserved01[0x0BB];
188 U032 TopLeftSrc;
189 U032 TopLeftDst;
190 U032 WidthHeight;
191 } RivaScreenBlt;
193 * 2D pixel BLT.
195 typedef volatile struct
197 U032 reserved00[4];
198 #ifdef __BIG_ENDIAN
199 U032 FifoFree;
200 #else
201 U016 FifoFree;
202 U016 Nop[1];
203 #endif
204 U032 reserved01[0x0BC];
205 U032 TopLeft;
206 U032 WidthHeight;
207 U032 WidthHeightIn;
208 U032 reserved02[0x03C];
209 U032 Pixels;
210 } RivaPixmap;
212 * Filled rectangle combined with monochrome expand. Useful for glyphs.
214 typedef volatile struct
216 U032 reserved00[4];
217 #ifdef __BIG_ENDIAN
218 U032 FifoFree;
219 #else
220 U016 FifoFree;
221 U016 Nop;
222 #endif
223 U032 reserved01[0x0BB];
224 U032 reserved03[(0x040)-1];
225 U032 Color1A;
226 struct
228 U032 TopLeft;
229 U032 WidthHeight;
230 } UnclippedRectangle[64];
231 U032 reserved04[(0x080)-3];
232 struct
234 U032 TopLeft;
235 U032 BottomRight;
236 } ClipB;
237 U032 Color1B;
238 struct
240 U032 TopLeft;
241 U032 BottomRight;
242 } ClippedRectangle[64];
243 U032 reserved05[(0x080)-5];
244 struct
246 U032 TopLeft;
247 U032 BottomRight;
248 } ClipC;
249 U032 Color1C;
250 U032 WidthHeightC;
251 U032 PointC;
252 U032 MonochromeData1C;
253 U032 reserved06[(0x080)+121];
254 struct
256 U032 TopLeft;
257 U032 BottomRight;
258 } ClipD;
259 U032 Color1D;
260 U032 WidthHeightInD;
261 U032 WidthHeightOutD;
262 U032 PointD;
263 U032 MonochromeData1D;
264 U032 reserved07[(0x080)+120];
265 struct
267 U032 TopLeft;
268 U032 BottomRight;
269 } ClipE;
270 U032 Color0E;
271 U032 Color1E;
272 U032 WidthHeightInE;
273 U032 WidthHeightOutE;
274 U032 PointE;
275 U032 MonochromeData01E;
276 } RivaBitmap;
278 * 3D textured, Z buffered triangle.
280 typedef volatile struct
282 U032 reserved00[4];
283 #ifdef __BIG_ENDIAN
284 U032 FifoFree;
285 #else
286 U016 FifoFree;
287 U016 Nop;
288 #endif
289 U032 reserved01[0x0BC];
290 U032 TextureOffset;
291 U032 TextureFormat;
292 U032 TextureFilter;
293 U032 FogColor;
294 /* This is a problem on LynxOS */
295 #ifdef Control
296 #undef Control
297 #endif
298 U032 Control;
299 U032 AlphaTest;
300 U032 reserved02[0x339];
301 U032 FogAndIndex;
302 U032 Color;
303 float ScreenX;
304 float ScreenY;
305 float ScreenZ;
306 float EyeM;
307 float TextureS;
308 float TextureT;
309 } RivaTexturedTriangle03;
310 typedef volatile struct
312 U032 reserved00[4];
313 #ifdef __BIG_ENDIAN
314 U032 FifoFree;
315 #else
316 U016 FifoFree;
317 U016 Nop;
318 #endif
319 U032 reserved01[0x0BB];
320 U032 ColorKey;
321 U032 TextureOffset;
322 U032 TextureFormat;
323 U032 TextureFilter;
324 U032 Blend;
325 /* This is a problem on LynxOS */
326 #ifdef Control
327 #undef Control
328 #endif
329 U032 Control;
330 U032 FogColor;
331 U032 reserved02[0x39];
332 struct
334 float ScreenX;
335 float ScreenY;
336 float ScreenZ;
337 float EyeM;
338 U032 Color;
339 U032 Specular;
340 float TextureS;
341 float TextureT;
342 } Vertex[16];
343 U032 DrawTriangle3D;
344 } RivaTexturedTriangle05;
346 * 2D line.
348 typedef volatile struct
350 U032 reserved00[4];
351 #ifdef __BIG_ENDIAN
352 U032 FifoFree;
353 #else
354 U016 FifoFree;
355 U016 Nop[1];
356 #endif
357 U032 reserved01[0x0BC];
358 U032 Color; /* source color 0304-0307*/
359 U032 Reserved02[0x03e];
360 struct { /* start aliased methods in array 0400- */
361 U032 point0; /* y_x S16_S16 in pixels 0- 3*/
362 U032 point1; /* y_x S16_S16 in pixels 4- 7*/
363 } Lin[16]; /* end of aliased methods in array -047f*/
364 struct { /* start aliased methods in array 0480- */
365 U032 point0X; /* in pixels, 0 at left 0- 3*/
366 U032 point0Y; /* in pixels, 0 at top 4- 7*/
367 U032 point1X; /* in pixels, 0 at left 8- b*/
368 U032 point1Y; /* in pixels, 0 at top c- f*/
369 } Lin32[8]; /* end of aliased methods in array -04ff*/
370 U032 PolyLin[32]; /* y_x S16_S16 in pixels 0500-057f*/
371 struct { /* start aliased methods in array 0580- */
372 U032 x; /* in pixels, 0 at left 0- 3*/
373 U032 y; /* in pixels, 0 at top 4- 7*/
374 } PolyLin32[16]; /* end of aliased methods in array -05ff*/
375 struct { /* start aliased methods in array 0600- */
376 U032 color; /* source color 0- 3*/
377 U032 point; /* y_x S16_S16 in pixels 4- 7*/
378 } ColorPolyLin[16]; /* end of aliased methods in array -067f*/
379 } RivaLine;
381 * 2D/3D surfaces
383 typedef volatile struct
385 U032 reserved00[4];
386 #ifdef __BIG_ENDIAN
387 U032 FifoFree;
388 #else
389 U016 FifoFree;
390 U016 Nop;
391 #endif
392 U032 reserved01[0x0BE];
393 U032 Offset;
394 } RivaSurface;
395 typedef volatile struct
397 U032 reserved00[4];
398 #ifdef __BIG_ENDIAN
399 U032 FifoFree;
400 #else
401 U016 FifoFree;
402 U016 Nop;
403 #endif
404 U032 reserved01[0x0BD];
405 U032 Pitch;
406 U032 RenderBufferOffset;
407 U032 ZBufferOffset;
408 } RivaSurface3D;
410 /***************************************************************************\
412 * Virtualized RIVA H/W interface. *
414 \***************************************************************************/
416 #define FP_ENABLE 1
417 #define FP_DITHER 2
419 struct _riva_hw_inst;
420 struct _riva_hw_state;
422 * Virtialized chip interface. Makes RIVA 128 and TNT look alike.
424 typedef struct _riva_hw_inst
427 * Chip specific settings.
429 U032 Architecture;
430 U032 Version;
431 U032 Chipset;
432 U032 CrystalFreqKHz;
433 U032 RamAmountKBytes;
434 U032 MaxVClockFreqKHz;
435 U032 RamBandwidthKBytesPerSec;
436 U032 EnableIRQ;
437 U032 IO;
438 U032 VBlankBit;
439 U032 FifoFreeCount;
440 U032 FifoEmptyCount;
441 U032 CursorStart;
442 U032 flatPanel;
443 Bool twoHeads;
445 * Non-FIFO registers.
447 volatile U032 *PCRTC0;
448 volatile U032 *PCRTC;
449 volatile U032 *PRAMDAC0;
450 volatile U032 *PFB;
451 volatile U032 *PFIFO;
452 volatile U032 *PGRAPH;
453 volatile U032 *PEXTDEV;
454 volatile U032 *PTIMER;
455 volatile U032 *PMC;
456 volatile U032 *PRAMIN;
457 volatile U032 *FIFO;
458 volatile U032 *CURSOR;
459 volatile U008 *PCIO0;
460 volatile U008 *PCIO;
461 volatile U008 *PVIO;
462 volatile U008 *PDIO0;
463 volatile U008 *PDIO;
464 volatile U032 *PRAMDAC;
466 * Common chip functions.
468 int (*Busy)(struct _riva_hw_inst *);
469 void (*CalcStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *,int,int,int,int,int);
470 void (*LoadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *);
471 void (*UnloadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *);
472 void (*SetStartAddress)(struct _riva_hw_inst *,U032);
473 void (*SetSurfaces2D)(struct _riva_hw_inst *,U032,U032);
474 void (*SetSurfaces3D)(struct _riva_hw_inst *,U032,U032);
475 int (*ShowHideCursor)(struct _riva_hw_inst *,int);
476 void (*LockUnlock)(struct _riva_hw_inst *, int);
478 * Current extended mode settings.
480 struct _riva_hw_state *CurrentState;
482 * FIFO registers.
484 RivaRop *Rop;
485 RivaPattern *Patt;
486 RivaClip *Clip;
487 RivaPixmap *Pixmap;
488 RivaScreenBlt *Blt;
489 RivaBitmap *Bitmap;
490 RivaLine *Line;
491 RivaTexturedTriangle03 *Tri03;
492 RivaTexturedTriangle05 *Tri05;
493 } RIVA_HW_INST;
495 * Extended mode state information.
497 typedef struct _riva_hw_state
499 U032 bpp;
500 U032 width;
501 U032 height;
502 U032 interlace;
503 U032 repaint0;
504 U032 repaint1;
505 U032 screen;
506 U032 scale;
507 U032 dither;
508 U032 extra;
509 U032 pixel;
510 U032 horiz;
511 U032 arbitration0;
512 U032 arbitration1;
513 U032 vpll;
514 U032 vpll2;
515 U032 pllsel;
516 U032 general;
517 U032 crtcOwner;
518 U032 head;
519 U032 head2;
520 U032 config;
521 U032 cursorConfig;
522 U032 cursor0;
523 U032 cursor1;
524 U032 cursor2;
525 U032 offset0;
526 U032 offset1;
527 U032 offset2;
528 U032 offset3;
529 U032 pitch0;
530 U032 pitch1;
531 U032 pitch2;
532 U032 pitch3;
533 } RIVA_HW_STATE;
535 * External routines.
537 int RivaGetConfig(RIVA_HW_INST *, unsigned int);
539 * FIFO Free Count. Should attempt to yield processor if RIVA is busy.
542 #define RIVA_FIFO_FREE(hwinst,hwptr,cnt) \
544 while ((hwinst).FifoFreeCount < (cnt)) \
545 (hwinst).FifoFreeCount = (hwinst).hwptr->FifoFree >> 2; \
546 (hwinst).FifoFreeCount -= (cnt); \
548 #endif /* __RIVA_HW_H__ */