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MOXA linux-2.6.x / linux-2.6.9-uc0 from sdlinux-moxaart.tgz
[linux-2.6.9-moxart.git] / drivers / video / tdfxfb.c
blob503ecc3569e88dcbebbd60cf22122c0be0dca94a
1 /*
2 *
3 * tdfxfb.c
4 *
5 * Author: Hannu Mallat <hmallat@cc.hut.fi>
6 *
7 * Copyright © 1999 Hannu Mallat
8 * All rights reserved
9 *
10 * Created : Thu Sep 23 18:17:43 1999, hmallat
11 * Last modified: Tue Nov 2 21:19:47 1999, hmallat
12 *
13 * Lots of the information here comes from the Daryll Strauss' Banshee
14 * patches to the XF86 server, and the rest comes from the 3dfx
15 * Banshee specification. I'm very much indebted to Daryll for his
16 * work on the X server.
17 *
18 * Voodoo3 support was contributed Harold Oga. Lots of additions
19 * (proper acceleration, 24 bpp, hardware cursor) and bug fixes by Attila
20 * Kesmarki. Thanks guys!
21 *
22 * Voodoo1 and Voodoo2 support aren't relevant to this driver as they
23 * behave very differently from the Voodoo3/4/5. For anyone wanting to
24 * use frame buffer on the Voodoo1/2, see the sstfb driver (which is
25 * located at http://www.sourceforge.net/projects/sstfb).
26 *
27 * While I _am_ grateful to 3Dfx for releasing the specs for Banshee,
28 * I do wish the next version is a bit more complete. Without the XF86
29 * patches I couldn't have gotten even this far... for instance, the
30 * extensions to the VGA register set go completely unmentioned in the
31 * spec! Also, lots of references are made to the 'SST core', but no
32 * spec is publicly available, AFAIK.
33 *
34 * The structure of this driver comes pretty much from the Permedia
35 * driver by Ilario Nardinocchi, which in turn is based on skeletonfb.
36 *
37 * TODO:
38 * - support for 16/32 bpp needs fixing (funky bootup penguin)
39 * - multihead support (basically need to support an array of fb_infos)
40 * - support other architectures (PPC, Alpha); does the fact that the VGA
41 * core can be accessed only thru I/O (not memory mapped) complicate
42 * things?
43 *
44 * Version history:
45 *
46 * 0.1.4 (released 2002-05-28) ported over to new fbdev api by James Simmons
47 *
48 * 0.1.3 (released 1999-11-02) added Attila's panning support, code
49 * reorg, hwcursor address page size alignment
50 * (for mmaping both frame buffer and regs),
51 * and my changes to get rid of hardcoded
52 * VGA i/o register locations (uses PCI
53 * configuration info now)
54 * 0.1.2 (released 1999-10-19) added Attila Kesmarki's bug fixes and
55 * improvements
56 * 0.1.1 (released 1999-10-07) added Voodoo3 support by Harold Oga.
57 * 0.1.0 (released 1999-10-06) initial version
58 *
59 */
60
61 #include <linux/config.h>
62 #include <linux/module.h>
63 #include <linux/kernel.h>
64 #include <linux/errno.h>
65 #include <linux/string.h>
66 #include <linux/mm.h>
67 #include <linux/tty.h>
68 #include <linux/slab.h>
69 #include <linux/delay.h>
70 #include <linux/interrupt.h>
71 #include <linux/fb.h>
72 #include <linux/init.h>
73 #include <linux/pci.h>
74 #include <linux/nvram.h>
75 #include <asm/io.h>
76 #include <linux/timer.h>
77 #include <linux/spinlock.h>
78
79 #include <video/tdfx.h>
80
81 #undef TDFXFB_DEBUG
82 #ifdef TDFXFB_DEBUG
83 #define DPRINTK(a,b...) printk(KERN_DEBUG "fb: %s: " a, __FUNCTION__ , ## b)
84 #else
85 #define DPRINTK(a,b...)
86 #endif
87
88 #define BANSHEE_MAX_PIXCLOCK 270000
89 #define VOODOO3_MAX_PIXCLOCK 300000
90 #define VOODOO5_MAX_PIXCLOCK 350000
91
92 static struct fb_fix_screeninfo tdfx_fix __initdata = {
93 .id = "3Dfx",
94 .type = FB_TYPE_PACKED_PIXELS,
95 .visual = FB_VISUAL_PSEUDOCOLOR,
96 .ypanstep = 1,
97 .ywrapstep = 1,
98 .accel = FB_ACCEL_3DFX_BANSHEE
99 };
100
101 static struct fb_var_screeninfo tdfx_var __initdata = {
102 /* "640x480, 8 bpp @ 60 Hz */
103 .xres = 640,
104 .yres = 480,
105 .xres_virtual = 640,
106 .yres_virtual = 1024,
107 .bits_per_pixel =8,
108 .red = {0, 8, 0},
109 .blue = {0, 8, 0},
110 .green = {0, 8, 0},
111 .activate = FB_ACTIVATE_NOW,
112 .height = -1,
113 .width = -1,
114 .accel_flags = FB_ACCELF_TEXT,
115 .pixclock = 39722,
116 .left_margin = 40,
117 .right_margin = 24,
118 .upper_margin = 32,
119 .lower_margin = 11,
120 .hsync_len = 96,
121 .vsync_len = 2,
122 .vmode = FB_VMODE_NONINTERLACED
123 };
124
125 /*
126 * PCI driver prototypes
127 */
128 static int __devinit tdfxfb_probe(struct pci_dev *pdev,
129 const struct pci_device_id *id);
130 static void __devexit tdfxfb_remove(struct pci_dev *pdev);
131
132 static struct pci_device_id tdfxfb_id_table[] = {
133 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_BANSHEE,
134 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
135 0xff0000, 0 },
136 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO3,
137 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
138 0xff0000, 0 },
139 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO5,
140 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
141 0xff0000, 0 },
142 { 0, }
143 };
144
145 static struct pci_driver tdfxfb_driver = {
146 .name = "tdfxfb",
147 .id_table = tdfxfb_id_table,
148 .probe = tdfxfb_probe,
149 .remove = __devexit_p(tdfxfb_remove),
150 };
151
152 MODULE_DEVICE_TABLE(pci, tdfxfb_id_table);
153
154 /*
155 * Frame buffer device API
156 */
157 int tdfxfb_init(void);
158 void tdfxfb_setup(char *options);
159
160 static int tdfxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *fb);
161 static int tdfxfb_set_par(struct fb_info *info);
162 static int tdfxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
163 u_int transp, struct fb_info *info);
164 static int tdfxfb_blank(int blank, struct fb_info *info);
165 static int tdfxfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
166 static int banshee_wait_idle(struct fb_info *info);
167 #ifdef CONFIG_FB_3DFX_ACCEL
168 static void tdfxfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect);
169 static void tdfxfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
170 static void tdfxfb_imageblit(struct fb_info *info, const struct fb_image *image);
171 #endif /* CONFIG_FB_3DFX_ACCEL */
172
173 static struct fb_ops tdfxfb_ops = {
174 .owner = THIS_MODULE,
175 .fb_check_var = tdfxfb_check_var,
176 .fb_set_par = tdfxfb_set_par,
177 .fb_setcolreg = tdfxfb_setcolreg,
178 .fb_blank = tdfxfb_blank,
179 .fb_pan_display = tdfxfb_pan_display,
180 .fb_sync = banshee_wait_idle,
181 #ifdef CONFIG_FB_3DFX_ACCEL
182 .fb_fillrect = tdfxfb_fillrect,
183 .fb_copyarea = tdfxfb_copyarea,
184 .fb_imageblit = tdfxfb_imageblit,
185 #else
186 .fb_fillrect = cfb_fillrect,
187 .fb_copyarea = cfb_copyarea,
188 .fb_imageblit = cfb_imageblit,
189 #endif
190 .fb_cursor = soft_cursor,
191 };
192
193 /*
194 * do_xxx: Hardware-specific functions
195 */
196 static u32 do_calc_pll(int freq, int *freq_out);
197 static void do_write_regs(struct fb_info *info, struct banshee_reg *reg);
198 static unsigned long do_lfb_size(struct tdfx_par *par, unsigned short);
199
200 /*
201 * Driver data
202 */
203 static int nopan = 0;
204 static int nowrap = 1; // not implemented (yet)
205 static int inverse = 0;
206 static char *mode_option __initdata = NULL;
207
208 /* -------------------------------------------------------------------------
209 * Hardware-specific funcions
210 * ------------------------------------------------------------------------- */
211
212 #ifdef VGA_REG_IO
213 static inline u8 vga_inb(struct tdfx_par *par, u32 reg) { return inb(reg); }
214 static inline u16 vga_inw(struct tdfx_par *par, u32 reg) { return inw(reg); }
215 static inline u16 vga_inl(struct tdfx_par *par, u32 reg) { return inl(reg); }
216
217 static inline void vga_outb(struct tdfx_par *par, u32 reg, u8 val) { outb(val, reg); }
218 static inline void vga_outw(struct tdfx_par *par, u32 reg, u16 val) { outw(val, reg); }
219 static inline void vga_outl(struct tdfx_par *par, u32 reg, u32 val) { outl(val, reg); }
220 #else
221 static inline u8 vga_inb(struct tdfx_par *par, u32 reg) {
222 return inb(par->iobase + reg - 0x300);
223 }
224 static inline u16 vga_inw(struct tdfx_par *par, u32 reg) {
225 return inw(par->iobase + reg - 0x300);
226 }
227 static inline u16 vga_inl(struct tdfx_par *par, u32 reg) {
228 return inl(par->iobase + reg - 0x300);
229 }
230 static inline void vga_outb(struct tdfx_par *par, u32 reg, u8 val) {
231 outb(val, par->iobase + reg - 0x300);
232 }
233 static inline void vga_outw(struct tdfx_par *par, u32 reg, u16 val) {
234 outw(val, par->iobase + reg - 0x300);
235 }
236 static inline void vga_outl(struct tdfx_par *par, u32 reg, u32 val) {
237 outl(val, par->iobase + reg - 0x300);
238 }
239 #endif
240
241 static inline void gra_outb(struct tdfx_par *par, u32 idx, u8 val) {
242 vga_outb(par, GRA_I, idx); vga_outb(par, GRA_D, val);
243 }
244
245 static inline u8 gra_inb(struct tdfx_par *par, u32 idx) {
246 vga_outb(par, GRA_I, idx); return vga_inb(par, GRA_D);
247 }
248
249 static inline void seq_outb(struct tdfx_par *par, u32 idx, u8 val) {
250 vga_outb(par, SEQ_I, idx); vga_outb(par, SEQ_D, val);
251 }
252
253 static inline u8 seq_inb(struct tdfx_par *par, u32 idx) {
254 vga_outb(par, SEQ_I, idx); return vga_inb(par, SEQ_D);
255 }
256
257 static inline void crt_outb(struct tdfx_par *par, u32 idx, u8 val) {
258 vga_outb(par, CRT_I, idx); vga_outb(par, CRT_D, val);
259 }
260
261 static inline u8 crt_inb(struct tdfx_par *par, u32 idx) {
262 vga_outb(par, CRT_I, idx); return vga_inb(par, CRT_D);
263 }
264
265 static inline void att_outb(struct tdfx_par *par, u32 idx, u8 val)
266 {
267 unsigned char tmp;
268
269 tmp = vga_inb(par, IS1_R);
270 vga_outb(par, ATT_IW, idx);
271 vga_outb(par, ATT_IW, val);
272 }
273
274 static inline u8 att_inb(struct tdfx_par *par, u32 idx)
275 {
276 unsigned char tmp;
277
278 tmp = vga_inb(par, IS1_R);
279 vga_outb(par, ATT_IW, idx);
280 return vga_inb(par, ATT_IW);
281 }
282
283 static inline void vga_disable_video(struct tdfx_par *par)
284 {
285 unsigned char s;
286
287 s = seq_inb(par, 0x01) | 0x20;
288 seq_outb(par, 0x00, 0x01);
289 seq_outb(par, 0x01, s);
290 seq_outb(par, 0x00, 0x03);
291 }
292
293 static inline void vga_enable_video(struct tdfx_par *par)
294 {
295 unsigned char s;
296
297 s = seq_inb(par, 0x01) & 0xdf;
298 seq_outb(par, 0x00, 0x01);
299 seq_outb(par, 0x01, s);
300 seq_outb(par, 0x00, 0x03);
301 }
302
303 static inline void vga_disable_palette(struct tdfx_par *par)
304 {
305 vga_inb(par, IS1_R);
306 vga_outb(par, ATT_IW, 0x00);
307 }
308
309 static inline void vga_enable_palette(struct tdfx_par *par)
310 {
311 vga_inb(par, IS1_R);
312 vga_outb(par, ATT_IW, 0x20);
313 }
314
315 static inline u32 tdfx_inl(struct tdfx_par *par, unsigned int reg)
316 {
317 return readl(par->regbase_virt + reg);
318 }
319
320 static inline void tdfx_outl(struct tdfx_par *par, unsigned int reg, u32 val)
321 {
322 writel(val, par->regbase_virt + reg);
323 }
324
325 static inline void banshee_make_room(struct tdfx_par *par, int size)
326 {
327 /* Note: The Voodoo3's onboard FIFO has 32 slots. This loop
328 * won't quit if you ask for more. */
329 while((tdfx_inl(par, STATUS) & 0x1f) < size-1);
330 }
331
332 static int banshee_wait_idle(struct fb_info *info)
333 {
334 struct tdfx_par *par = (struct tdfx_par *) info->par;
335 int i = 0;
336
337 banshee_make_room(par, 1);
338 tdfx_outl(par, COMMAND_3D, COMMAND_3D_NOP);
339
340 while(1) {
341 i = (tdfx_inl(par, STATUS) & STATUS_BUSY) ? 0 : i + 1;
342 if(i == 3) break;
343 }
344 return 0;
345 }
346
347 /*
348 * Set the color of a palette entry in 8bpp mode
349 */
350 static inline void do_setpalentry(struct tdfx_par *par, unsigned regno, u32 c)
351 {
352 banshee_make_room(par, 2);
353 tdfx_outl(par, DACADDR, regno);
354 tdfx_outl(par, DACDATA, c);
355 }
356
357 static u32 do_calc_pll(int freq, int* freq_out)
358 {
359 int m, n, k, best_m, best_n, best_k, f_cur, best_error;
360 int fref = 14318;
361
362 /* this really could be done with more intelligence --
363 255*63*4 = 64260 iterations is silly */
364 best_error = freq;
365 best_n = best_m = best_k = 0;
366 for (n = 1; n < 256; n++) {
367 for (m = 1; m < 64; m++) {
368 for (k = 0; k < 4; k++) {
369 f_cur = fref*(n + 2)/(m + 2)/(1 << k);
370 if (abs(f_cur - freq) < best_error) {
371 best_error = abs(f_cur-freq);
372 best_n = n;
373 best_m = m;
374 best_k = k;
375 }
376 }
377 }
378 }
379 n = best_n;
380 m = best_m;
381 k = best_k;
382 *freq_out = fref*(n + 2)/(m + 2)/(1 << k);
383 return (n << 8) | (m << 2) | k;
384 }
385
386 static void do_write_regs(struct fb_info *info, struct banshee_reg* reg)
387 {
388 struct tdfx_par *par = (struct tdfx_par *) info->par;
389 int i;
390
391 banshee_wait_idle(info);
392
393 tdfx_outl(par, MISCINIT1, tdfx_inl(par, MISCINIT1) | 0x01);
394
395 crt_outb(par, 0x11, crt_inb(par, 0x11) & 0x7f); /* CRT unprotect */
396
397 banshee_make_room(par, 3);
398 tdfx_outl(par, VGAINIT1, reg->vgainit1 & 0x001FFFFF);
399 tdfx_outl(par, VIDPROCCFG, reg->vidcfg & ~0x00000001);
400 #if 0
401 tdfx_outl(par, PLLCTRL1, reg->mempll);
402 tdfx_outl(par, PLLCTRL2, reg->gfxpll);
403 #endif
404 tdfx_outl(par, PLLCTRL0, reg->vidpll);
405
406 vga_outb(par, MISC_W, reg->misc[0x00] | 0x01);
407
408 for (i = 0; i < 5; i++)
409 seq_outb(par, i, reg->seq[i]);
410
411 for (i = 0; i < 25; i++)
412 crt_outb(par, i, reg->crt[i]);
413
414 for (i = 0; i < 9; i++)
415 gra_outb(par, i, reg->gra[i]);
416
417 for (i = 0; i < 21; i++)
418 att_outb(par, i, reg->att[i]);
419
420 crt_outb(par, 0x1a, reg->ext[0]);
421 crt_outb(par, 0x1b, reg->ext[1]);
422
423 vga_enable_palette(par);
424 vga_enable_video(par);
425
426 banshee_make_room(par, 11);
427 tdfx_outl(par, VGAINIT0, reg->vgainit0);
428 tdfx_outl(par, DACMODE, reg->dacmode);
429 tdfx_outl(par, VIDDESKSTRIDE, reg->stride);
430 tdfx_outl(par, HWCURPATADDR, 0);
431
432 tdfx_outl(par, VIDSCREENSIZE,reg->screensize);
433 tdfx_outl(par, VIDDESKSTART, reg->startaddr);
434 tdfx_outl(par, VIDPROCCFG, reg->vidcfg);
435 tdfx_outl(par, VGAINIT1, reg->vgainit1);
436 tdfx_outl(par, MISCINIT0, reg->miscinit0);
437
438 banshee_make_room(par, 8);
439 tdfx_outl(par, SRCBASE, reg->srcbase);
440 tdfx_outl(par, DSTBASE, reg->dstbase);
441 tdfx_outl(par, COMMANDEXTRA_2D, 0);
442 tdfx_outl(par, CLIP0MIN, 0);
443 tdfx_outl(par, CLIP0MAX, 0x0fff0fff);
444 tdfx_outl(par, CLIP1MIN, 0);
445 tdfx_outl(par, CLIP1MAX, 0x0fff0fff);
446 tdfx_outl(par, SRCXY, 0);
447
448 banshee_wait_idle(info);
449 }
450
451 static unsigned long do_lfb_size(struct tdfx_par *par, unsigned short dev_id)
452 {
453 u32 draminit0 = 0;
454 u32 draminit1 = 0;
455 u32 miscinit1 = 0;
456 u32 lfbsize = 0;
457 int sgram_p = 0;
458
459 draminit0 = tdfx_inl(par, DRAMINIT0);
460 draminit1 = tdfx_inl(par, DRAMINIT1);
461
462 if ((dev_id == PCI_DEVICE_ID_3DFX_BANSHEE) ||
463 (dev_id == PCI_DEVICE_ID_3DFX_VOODOO3)) {
464 sgram_p = (draminit1 & DRAMINIT1_MEM_SDRAM) ? 0 : 1;
465
466 lfbsize = sgram_p ?
467 (((draminit0 & DRAMINIT0_SGRAM_NUM) ? 2 : 1) *
468 ((draminit0 & DRAMINIT0_SGRAM_TYPE) ? 8 : 4) * 1024 * 1024) :
469 16 * 1024 * 1024;
470 } else {
471 /* Voodoo4/5 */
472 u32 chips, psize, banks;
473
474 chips = ((draminit0 & (1 << 26)) == 0) ? 4 : 8;
475 psize = 1 << ((draminit0 & 0x38000000) >> 28);
476 banks = ((draminit0 & (1 << 30)) == 0) ? 2 : 4;
477 lfbsize = chips * psize * banks;
478 lfbsize <<= 20;
479 }
480 /* disable block writes for SDRAM (why?) */
481 miscinit1 = tdfx_inl(par, MISCINIT1);
482 miscinit1 |= sgram_p ? 0 : MISCINIT1_2DBLOCK_DIS;
483 miscinit1 |= MISCINIT1_CLUT_INV;
484
485 banshee_make_room(par, 1);
486 tdfx_outl(par, MISCINIT1, miscinit1);
487 return lfbsize;
488 }
489
490 /* ------------------------------------------------------------------------- */
491
492 static int tdfxfb_check_var(struct fb_var_screeninfo *var,struct fb_info *info)
493 {
494 struct tdfx_par *par = (struct tdfx_par *) info->par;
495 u32 lpitch;
496
497 if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 &&
498 var->bits_per_pixel != 24 && var->bits_per_pixel != 32) {
499 DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
500 return -EINVAL;
501 }
502
503 if (var->xres != var->xres_virtual)
504 var->xres_virtual = var->xres;
505
506 if (var->yres > var->yres_virtual)
507 var->yres_virtual = var->yres;
508
509 if (var->xoffset) {
510 DPRINTK("xoffset not supported\n");
511 return -EINVAL;
512 }
513
514 /* Banshee doesn't support interlace, but Voodoo4/5 and probably Voodoo3 do. */
515 /* no direct information about device id now? use max_pixclock for this... */
516 if (((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) &&
517 (par->max_pixclock < VOODOO3_MAX_PIXCLOCK)) {
518 DPRINTK("interlace not supported\n");
519 return -EINVAL;
520 }
521
522 var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */
523 lpitch = var->xres * ((var->bits_per_pixel + 7)>>3);
524
525 if (var->xres < 320 || var->xres > 2048) {
526 DPRINTK("width not supported: %u\n", var->xres);
527 return -EINVAL;
528 }
529
530 if (var->yres < 200 || var->yres > 2048) {
531 DPRINTK("height not supported: %u\n", var->yres);
532 return -EINVAL;
533 }
534
535 if (lpitch * var->yres_virtual > info->fix.smem_len) {
536 var->yres_virtual = info->fix.smem_len/lpitch;
537 if (var->yres_virtual < var->yres) {
538 DPRINTK("no memory for screen (%ux%ux%u)\n",
539 var->xres, var->yres_virtual, var->bits_per_pixel);
540 return -EINVAL;
541 }
542 }
543
544 if (PICOS2KHZ(var->pixclock) > par->max_pixclock) {
545 DPRINTK("pixclock too high (%ldKHz)\n",PICOS2KHZ(var->pixclock));
546 return -EINVAL;
547 }
548
549 switch(var->bits_per_pixel) {
550 case 8:
551 var->red.length = var->green.length = var->blue.length = 8;
552 break;
553 case 16:
554 var->red.offset = 11;
555 var->red.length = 5;
556 var->green.offset = 5;
557 var->green.length = 6;
558 var->blue.offset = 0;
559 var->blue.length = 5;
560 break;
561 case 24:
562 var->red.offset=16;
563 var->green.offset=8;
564 var->blue.offset=0;
565 var->red.length = var->green.length = var->blue.length = 8;
566 case 32:
567 var->red.offset = 16;
568 var->green.offset = 8;
569 var->blue.offset = 0;
570 var->red.length = var->green.length = var->blue.length = 8;
571 break;
572 }
573 var->height = var->width = -1;
574
575 var->accel_flags = FB_ACCELF_TEXT;
576
577 DPRINTK("Checking graphics mode at %dx%d depth %d\n", var->xres, var->yres, var->bits_per_pixel);
578 return 0;
579 }
580
581 static int tdfxfb_set_par(struct fb_info *info)
582 {
583 struct tdfx_par *par = (struct tdfx_par *) info->par;
584 u32 hdispend, hsyncsta, hsyncend, htotal;
585 u32 hd, hs, he, ht, hbs, hbe;
586 u32 vd, vs, ve, vt, vbs, vbe;
587 struct banshee_reg reg;
588 int fout, freq;
589 u32 wd, cpp;
590
591 par->baseline = 0;
592
593 memset(&reg, 0, sizeof(reg));
594 cpp = (info->var.bits_per_pixel + 7)/8;
595
596 reg.vidcfg = VIDCFG_VIDPROC_ENABLE | VIDCFG_DESK_ENABLE | VIDCFG_CURS_X11 | ((cpp - 1) << VIDCFG_PIXFMT_SHIFT) | (cpp != 1 ? VIDCFG_CLUT_BYPASS : 0);
597
598 /* PLL settings */
599 freq = PICOS2KHZ(info->var.pixclock);
600
601 reg.dacmode = 0;
602 reg.vidcfg &= ~VIDCFG_2X;
603
604 hdispend = info->var.xres;
605 hsyncsta = hdispend + info->var.right_margin;
606 hsyncend = hsyncsta + info->var.hsync_len;
607 htotal = hsyncend + info->var.left_margin;
608
609 if (freq > par->max_pixclock/2) {
610 freq = freq > par->max_pixclock ? par->max_pixclock : freq;
611 reg.dacmode |= DACMODE_2X;
612 reg.vidcfg |= VIDCFG_2X;
613 hdispend >>= 1;
614 hsyncsta >>= 1;
615 hsyncend >>= 1;
616 htotal >>= 1;
617 }
618
619 hd = wd = (hdispend >> 3) - 1;
620 hs = (hsyncsta >> 3) - 1;
621 he = (hsyncend >> 3) - 1;
622 ht = (htotal >> 3) - 1;
623 hbs = hd;
624 hbe = ht;
625
626 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) {
627 vbs = vd = (info->var.yres << 1) - 1;
628 vs = vd + (info->var.lower_margin << 1);
629 ve = vs + (info->var.vsync_len << 1);
630 vbe = vt = ve + (info->var.upper_margin << 1) - 1;
631 } else {
632 vbs = vd = info->var.yres - 1;
633 vs = vd + info->var.lower_margin;
634 ve = vs + info->var.vsync_len;
635 vbe = vt = ve + info->var.upper_margin - 1;
636 }
637
638 /* this is all pretty standard VGA register stuffing */
639 reg.misc[0x00] = 0x0f |
640 (info->var.xres < 400 ? 0xa0 :
641 info->var.xres < 480 ? 0x60 :
642 info->var.xres < 768 ? 0xe0 : 0x20);
643
644 reg.gra[0x00] = 0x00;
645 reg.gra[0x01] = 0x00;
646 reg.gra[0x02] = 0x00;
647 reg.gra[0x03] = 0x00;
648 reg.gra[0x04] = 0x00;
649 reg.gra[0x05] = 0x40;
650 reg.gra[0x06] = 0x05;
651 reg.gra[0x07] = 0x0f;
652 reg.gra[0x08] = 0xff;
653
654 reg.att[0x00] = 0x00;
655 reg.att[0x01] = 0x01;
656 reg.att[0x02] = 0x02;
657 reg.att[0x03] = 0x03;
658 reg.att[0x04] = 0x04;
659 reg.att[0x05] = 0x05;
660 reg.att[0x06] = 0x06;
661 reg.att[0x07] = 0x07;
662 reg.att[0x08] = 0x08;
663 reg.att[0x09] = 0x09;
664 reg.att[0x0a] = 0x0a;
665 reg.att[0x0b] = 0x0b;
666 reg.att[0x0c] = 0x0c;
667 reg.att[0x0d] = 0x0d;
668 reg.att[0x0e] = 0x0e;
669 reg.att[0x0f] = 0x0f;
670 reg.att[0x10] = 0x41;
671 reg.att[0x11] = 0x00;
672 reg.att[0x12] = 0x0f;
673 reg.att[0x13] = 0x00;
674 reg.att[0x14] = 0x00;
675
676 reg.seq[0x00] = 0x03;
677 reg.seq[0x01] = 0x01; /* fixme: clkdiv2? */
678 reg.seq[0x02] = 0x0f;
679 reg.seq[0x03] = 0x00;
680 reg.seq[0x04] = 0x0e;
681
682 reg.crt[0x00] = ht - 4;
683 reg.crt[0x01] = hd;
684 reg.crt[0x02] = hbs;
685 reg.crt[0x03] = 0x80 | (hbe & 0x1f);
686 reg.crt[0x04] = hs;
687 reg.crt[0x05] = ((hbe & 0x20) << 2) | (he & 0x1f);
688 reg.crt[0x06] = vt;
689 reg.crt[0x07] = ((vs & 0x200) >> 2) |
690 ((vd & 0x200) >> 3) |
691 ((vt & 0x200) >> 4) | 0x10 |
692 ((vbs & 0x100) >> 5) |
693 ((vs & 0x100) >> 6) |
694 ((vd & 0x100) >> 7) |
695 ((vt & 0x100) >> 8);
696 reg.crt[0x08] = 0x00;
697 reg.crt[0x09] = 0x40 | ((vbs & 0x200) >> 4);
698 reg.crt[0x0a] = 0x00;
699 reg.crt[0x0b] = 0x00;
700 reg.crt[0x0c] = 0x00;
701 reg.crt[0x0d] = 0x00;
702 reg.crt[0x0e] = 0x00;
703 reg.crt[0x0f] = 0x00;
704 reg.crt[0x10] = vs;
705 reg.crt[0x11] = (ve & 0x0f) | 0x20;
706 reg.crt[0x12] = vd;
707 reg.crt[0x13] = wd;
708 reg.crt[0x14] = 0x00;
709 reg.crt[0x15] = vbs;
710 reg.crt[0x16] = vbe + 1;
711 reg.crt[0x17] = 0xc3;
712 reg.crt[0x18] = 0xff;
713
714 /* Banshee's nonvga stuff */
715 reg.ext[0x00] = (((ht & 0x100) >> 8) |
716 ((hd & 0x100) >> 6) |
717 ((hbs & 0x100) >> 4) |
718 ((hbe & 0x40) >> 1) |
719 ((hs & 0x100) >> 2) |
720 ((he & 0x20) << 2));
721 reg.ext[0x01] = (((vt & 0x400) >> 10) |
722 ((vd & 0x400) >> 8) |
723 ((vbs & 0x400) >> 6) |
724 ((vbe & 0x400) >> 4));
725
726 reg.vgainit0 = VGAINIT0_8BIT_DAC |
727 VGAINIT0_EXT_ENABLE |
728 VGAINIT0_WAKEUP_3C3 |
729 VGAINIT0_ALT_READBACK |
730 VGAINIT0_EXTSHIFTOUT;
731 reg.vgainit1 = tdfx_inl(par, VGAINIT1) & 0x1fffff;
732
733 reg.cursloc = 0;
734
735 reg.cursc0 = 0;
736 reg.cursc1 = 0xffffff;
737
738 reg.stride = info->var.xres * cpp;
739 reg.startaddr = par->baseline * reg.stride;
740 reg.srcbase = reg.startaddr;
741 reg.dstbase = reg.startaddr;
742
743 /* PLL settings */
744 freq = PICOS2KHZ(info->var.pixclock);
745
746 reg.dacmode &= ~DACMODE_2X;
747 reg.vidcfg &= ~VIDCFG_2X;
748 if (freq > par->max_pixclock/2) {
749 freq = freq > par->max_pixclock ? par->max_pixclock : freq;
750 reg.dacmode |= DACMODE_2X;
751 reg.vidcfg |= VIDCFG_2X;
752 }
753 reg.vidpll = do_calc_pll(freq, &fout);
754 #if 0
755 reg.mempll = do_calc_pll(..., &fout);
756 reg.gfxpll = do_calc_pll(..., &fout);
757 #endif
758
759 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) {
760 reg.screensize = info->var.xres | (info->var.yres << 13);
761 reg.vidcfg |= VIDCFG_HALF_MODE;
762 reg.crt[0x09] |= 0x80;
763 } else {
764 reg.screensize = info->var.xres | (info->var.yres << 12);
765 reg.vidcfg &= ~VIDCFG_HALF_MODE;
766 }
767 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
768 reg.vidcfg |= VIDCFG_INTERLACE;
769 reg.miscinit0 = tdfx_inl(par, MISCINIT0);
770
771 #if defined(__BIG_ENDIAN)
772 switch (info->var.bits_per_pixel) {
773 case 8:
774 case 24:
775 reg.miscinit0 &= ~(1 << 30);
776 reg.miscinit0 &= ~(1 << 31);
777 break;
778 case 16:
779 reg.miscinit0 |= (1 << 30);
780 reg.miscinit0 |= (1 << 31);
781 break;
782 case 32:
783 reg.miscinit0 |= (1 << 30);
784 reg.miscinit0 &= ~(1 << 31);
785 break;
786 }
787 #endif
788 do_write_regs(info, &reg);
789
790 /* Now change fb_fix_screeninfo according to changes in par */
791 info->fix.line_length = info->var.xres * ((info->var.bits_per_pixel + 7)>>3);
792 info->fix.visual = (info->var.bits_per_pixel == 8)
793 ? FB_VISUAL_PSEUDOCOLOR
794 : FB_VISUAL_TRUECOLOR;
795 DPRINTK("Graphics mode is now set at %dx%d depth %d\n", info->var.xres, info->var.yres, info->var.bits_per_pixel);
796 return 0;
797 }
798
799 /* A handy macro shamelessly pinched from matroxfb */
800 #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
801
802 static int tdfxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
803 unsigned blue,unsigned transp,struct fb_info *info)
804 {
805 struct tdfx_par *par = (struct tdfx_par *) info->par;
806 u32 rgbcol;
807
808 if (regno >= info->cmap.len || regno > 255) return 1;
809
810 switch (info->fix.visual) {
811 case FB_VISUAL_PSEUDOCOLOR:
812 rgbcol =(((u32)red & 0xff00) << 8) |
813 (((u32)green & 0xff00) << 0) |
814 (((u32)blue & 0xff00) >> 8);
815 do_setpalentry(par, regno, rgbcol);
816 break;
817 /* Truecolor has no hardware color palettes. */
818 case FB_VISUAL_TRUECOLOR:
819 rgbcol = (CNVT_TOHW( red, info->var.red.length) << info->var.red.offset) |
820 (CNVT_TOHW( green, info->var.green.length) << info->var.green.offset) |
821 (CNVT_TOHW( blue, info->var.blue.length) << info->var.blue.offset) |
822 (CNVT_TOHW( transp, info->var.transp.length) << info->var.transp.offset);
823 ((u32*)(info->pseudo_palette))[regno] = rgbcol;
824 break;
825 default:
826 DPRINTK("bad depth %u\n", info->var.bits_per_pixel);
827 break;
828 }
829 return 0;
830 }
831
832 /* 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off */
833 static int tdfxfb_blank(int blank, struct fb_info *info)
834 {
835 struct tdfx_par *par = (struct tdfx_par *) info->par;
836 u32 dacmode, state = 0, vgablank = 0;
837
838 dacmode = tdfx_inl(par, DACMODE);
839
840 switch (blank) {
841 case 0: /* Screen: On; HSync: On, VSync: On */
842 state = 0;
843 vgablank = 0;
844 break;
845 case 1: /* Screen: Off; HSync: On, VSync: On */
846 state = 0;
847 vgablank = 1;
848 break;
849 case 2: /* Screen: Off; HSync: On, VSync: Off */
850 state = BIT(3);
851 vgablank = 1;
852 break;
853 case 3: /* Screen: Off; HSync: Off, VSync: On */
854 state = BIT(1);
855 vgablank = 1;
856 break;
857 case 4: /* Screen: Off; HSync: Off, VSync: Off */
858 state = BIT(1) | BIT(3);
859 vgablank = 1;
860 break;
861 }
862
863 dacmode &= ~(BIT(1) | BIT(3));
864 dacmode |= state;
865 banshee_make_room(par, 1);
866 tdfx_outl(par, DACMODE, dacmode);
867 if (vgablank)
868 vga_disable_video(par);
869 else
870 vga_enable_video(par);
871 return 0;
872 }
873
874 /*
875 * Set the starting position of the visible screen to var->yoffset
876 */
877 static int tdfxfb_pan_display(struct fb_var_screeninfo *var,
878 struct fb_info *info)
879 {
880 struct tdfx_par *par = (struct tdfx_par *) info->par;
881 u32 addr;
882
883 if (nopan || var->xoffset || (var->yoffset > var->yres_virtual))
884 return -EINVAL;
885 if ((var->yoffset + var->yres > var->yres_virtual && nowrap))
886 return -EINVAL;
887
888 addr = var->yoffset * info->fix.line_length;
889 banshee_make_room(par, 1);
890 tdfx_outl(par, VIDDESKSTART, addr);
891
892 info->var.xoffset = var->xoffset;
893 info->var.yoffset = var->yoffset;
894 return 0;
895 }
896
897 #ifdef CONFIG_FB_3DFX_ACCEL
898 /*
899 * FillRect 2D command (solidfill or invert (via ROP_XOR))
900 */
901 static void tdfxfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
902 {
903 struct tdfx_par *par = (struct tdfx_par *) info->par;
904 u32 bpp = info->var.bits_per_pixel;
905 u32 stride = info->fix.line_length;
906 u32 fmt= stride | ((bpp+((bpp==8) ? 0 : 8)) << 13);
907 int tdfx_rop;
908
909 if (rect->rop == ROP_COPY)
910 tdfx_rop = TDFX_ROP_COPY;
911 else
912 tdfx_rop = TDFX_ROP_XOR;
913
914 banshee_make_room(par, 5);
915 tdfx_outl(par, DSTFORMAT, fmt);
916 if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR) {
917 tdfx_outl(par, COLORFORE, rect->color);
918 } else { /* FB_VISUAL_TRUECOLOR */
919 tdfx_outl(par, COLORFORE, ((u32*)(info->pseudo_palette))[rect->color]);
920 }
921 tdfx_outl(par, COMMAND_2D, COMMAND_2D_FILLRECT | (tdfx_rop << 24));
922 tdfx_outl(par, DSTSIZE, rect->width | (rect->height << 16));
923 tdfx_outl(par, LAUNCH_2D, rect->dx | (rect->dy << 16));
924 banshee_wait_idle(info);
925 }
926
927 /*
928 * Screen-to-Screen BitBlt 2D command (for the bmove fb op.)
929 */
930 static void tdfxfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
931 {
932 struct tdfx_par *par = (struct tdfx_par *) info->par;
933 u32 sx = area->sx, sy = area->sy, dx = area->dx, dy = area->dy;
934 u32 bpp = info->var.bits_per_pixel;
935 u32 stride = info->fix.line_length;
936 u32 blitcmd = COMMAND_2D_S2S_BITBLT | (TDFX_ROP_COPY << 24);
937 u32 fmt = stride | ((bpp+((bpp==8) ? 0 : 8)) << 13);
938
939 if (area->sx <= area->dx) {
940 //-X
941 blitcmd |= BIT(14);
942 sx += area->width - 1;
943 dx += area->width - 1;
944 }
945 if (area->sy <= area->dy) {
946 //-Y
947 blitcmd |= BIT(15);
948 sy += area->height - 1;
949 dy += area->height - 1;
950 }
951
952 banshee_make_room(par, 6);
953
954 tdfx_outl(par, SRCFORMAT, fmt);
955 tdfx_outl(par, DSTFORMAT, fmt);
956 tdfx_outl(par, COMMAND_2D, blitcmd);
957 tdfx_outl(par, DSTSIZE, area->width | (area->height << 16));
958 tdfx_outl(par, DSTXY, dx | (dy << 16));
959 tdfx_outl(par, LAUNCH_2D, sx | (sy << 16));
960 banshee_wait_idle(info);
961 }
962
963 static void tdfxfb_imageblit(struct fb_info *info, const struct fb_image *image)
964 {
965 struct tdfx_par *par = (struct tdfx_par *) info->par;
966 int size = image->height * ((image->width * image->depth + 7)>>3);
967 int fifo_free;
968 int i, stride = info->fix.line_length;
969 u32 bpp = info->var.bits_per_pixel;
970 u32 dstfmt = stride | ((bpp+((bpp==8) ? 0 : 8)) << 13);
971 u8 *chardata = (u8 *) image->data;
972 u32 srcfmt;
973
974 if (image->depth != 1) {
975 //banshee_make_room(par, 6 + ((size + 3) >> 2));
976 //srcfmt = stride | ((bpp+((bpp==8) ? 0 : 8)) << 13) | 0x400000;
977 cfb_imageblit(info, image);
978 return;
979 } else {
980 banshee_make_room(par, 8);
981 switch (info->fix.visual) {
982 case FB_VISUAL_PSEUDOCOLOR:
983 tdfx_outl(par, COLORFORE, image->fg_color);
984 tdfx_outl(par, COLORBACK, image->bg_color);
985 break;
986 case FB_VISUAL_TRUECOLOR:
987 default:
988 tdfx_outl(par, COLORFORE, ((u32*)(info->pseudo_palette))[image->fg_color]);
989 tdfx_outl(par, COLORBACK, ((u32*)(info->pseudo_palette))[image->bg_color]);
990 }
991 #ifdef __BIG_ENDIAN
992 srcfmt = 0x400000 | BIT(20);
993 #else
994 srcfmt = 0x400000;
995 #endif
996 }
997
998 tdfx_outl(par, SRCXY, 0);
999 tdfx_outl(par, DSTXY, image->dx | (image->dy << 16));
1000 tdfx_outl(par, COMMAND_2D, COMMAND_2D_H2S_BITBLT | (TDFX_ROP_COPY << 24));
1001 tdfx_outl(par, SRCFORMAT, srcfmt);
1002 tdfx_outl(par, DSTFORMAT, dstfmt);
1003 tdfx_outl(par, DSTSIZE, image->width | (image->height << 16));
1004
1005 /* A count of how many free FIFO entries we've requested.
1006 * When this goes negative, we need to request more. */
1007 fifo_free = 0;
1008
1009 /* Send four bytes at a time of data */
1010 for (i = (size >> 2) ; i > 0; i--) {
1011 if(--fifo_free < 0) {
1012 fifo_free=31;
1013 banshee_make_room(par,fifo_free);
1014 }
1015 tdfx_outl(par, LAUNCH_2D,*(u32*)chardata);
1016 chardata += 4;
1017 }
1018
1019 /* Send the leftovers now */
1020 banshee_make_room(par,3);
1021 i = size%4;
1022 switch (i) {
1023 case 0: break;
1024 case 1: tdfx_outl(par, LAUNCH_2D,*chardata); break;
1025 case 2: tdfx_outl(par, LAUNCH_2D,*(u16*)chardata); break;
1026 case 3: tdfx_outl(par, LAUNCH_2D,*(u16*)chardata | ((chardata[3]) << 24)); break;
1027 }
1028 banshee_wait_idle(info);
1029 }
1030 #endif /* CONFIG_FB_3DFX_ACCEL */
1031
1032 #ifdef TDFX_HARDWARE_CURSOR
1033 static int tdfxfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1034 {
1035 struct tdfx_par *par = (struct tdfx_par *) info->par;
1036 unsigned long flags;
1037
1038 /*
1039 * If the cursor is not be changed this means either we want the
1040 * current cursor state (if enable is set) or we want to query what
1041 * we can do with the cursor (if enable is not set)
1042 */
1043 if (!cursor->set) return 0;
1044
1045 /* Too large of a cursor :-( */
1046 if (cursor->image.width > 64 || cursor->image.height > 64)
1047 return -ENXIO;
1048
1049 /*
1050 * If we are going to be changing things we should disable
1051 * the cursor first
1052 */
1053 if (info->cursor.enable) {
1054 spin_lock_irqsave(&par->DAClock, flags);
1055 info->cursor.enable = 0;
1056 del_timer(&(par->hwcursor.timer));
1057 tdfx_outl(par, VIDPROCCFG, par->hwcursor.disable);
1058 spin_unlock_irqrestore(&par->DAClock, flags);
1059 }
1060
1061 /* Disable the Cursor */
1062 if ((cursor->set && FB_CUR_SETCUR) && !cursor->enable)
1063 return 0;
1064
1065 /* fix cursor color - XFree86 forgets to restore it properly */
1066 if (cursor->set && FB_CUR_SETCMAP) {
1067 struct fb_cmap cmap = cursor->image.cmap;
1068 unsigned long bg_color, fg_color;
1069
1070 cmap.len = 2; /* Voodoo 3+ only support 2 color cursors */
1071 fg_color = ((cmap.red[cmap.start] << 16) |
1072 (cmap.green[cmap.start] << 8) |
1073 (cmap.blue[cmap.start]));
1074 bg_color = ((cmap.red[cmap.start+1] << 16) |
1075 (cmap.green[cmap.start+1] << 8) |
1076 (cmap.blue[cmap.start+1]));
1077 fb_copy_cmap(&cmap, &info->cursor.image.cmap);
1078 spin_lock_irqsave(&par->DAClock, flags);
1079 banshee_make_room(par, 2);
1080 tdfx_outl(par, HWCURC0, bg_color);
1081 tdfx_outl(par, HWCURC1, fg_color);
1082 spin_unlock_irqrestore(&par->DAClock, flags);
1083 }
1084
1085 if (cursor->set && FB_CUR_SETPOS) {
1086 int x, y;
1087
1088 x = cursor->image.dx;
1089 y = cursor->image.dy;
1090 y -= info->var.yoffset;
1091 info->cursor.image.dx = x;
1092 info->cursor.image.dy = y;
1093 x += 63;
1094 y += 63;
1095 spin_lock_irqsave(&par->DAClock, flags);
1096 banshee_make_room(par, 1);
1097 tdfx_outl(par, HWCURLOC, (y << 16) + x);
1098 spin_unlock_irqrestore(&par->DAClock, flags);
1099 }
1100
1101 /* Not supported so we fake it */
1102 if (cursor->set && FB_CUR_SETHOT) {
1103 info->cursor.hot.x = cursor->hot.x;
1104 info->cursor.hot.y = cursor->hot.y;
1105 }
1106
1107 if (cursor->set && FB_CUR_SETSHAPE) {
1108 /*
1109 * Voodoo 3 and above cards use 2 monochrome cursor patterns.
1110 * The reason is so the card can fetch 8 words at a time
1111 * and are stored on chip for use for the next 8 scanlines.
1112 * This reduces the number of times for access to draw the
1113 * cursor for each screen refresh.
1114 * Each pattern is a bitmap of 64 bit wide and 64 bit high
1115 * (total of 8192 bits or 1024 Kbytes). The two patterns are
1116 * stored in such a way that pattern 0 always resides in the
1117 * lower half (least significant 64 bits) of a 128 bit word
1118 * and pattern 1 the upper half. If you examine the data of
1119 * the cursor image the graphics card uses then from the
1120 * begining you see line one of pattern 0, line one of
1121 * pattern 1, line two of pattern 0, line two of pattern 1,
1122 * etc etc. The linear stride for the cursor is always 16 bytes
1123 * (128 bits) which is the maximum cursor width times two for
1124 * the two monochrome patterns.
1125 */
1126 u8 *cursorbase = (u8 *) info->cursor.image.data;
1127 char *bitmap = (char *)cursor->image.data;
1128 char *mask = (char *) cursor->mask;
1129 int i, j, k, h = 0;
1130
1131 for (i = 0; i < 64; i++) {
1132 if (i < cursor->image.height) {
1133 j = (cursor->image.width + 7) >> 3;
1134 k = 8 - j;
1135
1136 for (;j > 0; j--) {
1137 /* Pattern 0. Copy the cursor bitmap to it */
1138 fb_writeb(*bitmap, cursorbase + h);
1139 bitmap++;
1140 /* Pattern 1. Copy the cursor mask to it */
1141 fb_writeb(*mask, cursorbase + h + 8);
1142 mask++;
1143 h++;
1144 }
1145 for (;k > 0; k--) {
1146 fb_writeb(0, cursorbase + h);
1147 fb_writeb(~0, cursorbase + h + 8);
1148 h++;
1149 }
1150 } else {
1151 fb_writel(0, cursorbase + h);
1152 fb_writel(0, cursorbase + h + 4);
1153 fb_writel(~0, cursorbase + h + 8);
1154 fb_writel(~0, cursorbase + h + 12);
1155 h += 16;
1156 }
1157 }
1158 }
1159 /* Turn the cursor on */
1160 cursor->enable = 1;
1161 info->cursor = *cursor;
1162 mod_timer(&par->hwcursor.timer, jiffies+HZ/2);
1163 spin_lock_irqsave(&par->DAClock, flags);
1164 banshee_make_room(par, 1);
1165 tdfx_outl(par, VIDPROCCFG, par->hwcursor.enable);
1166 spin_unlock_irqrestore(&par->DAClock, flags);
1167 return 0;
1168 }
1169 #endif
1170
1171 /**
1172 * tdfxfb_probe - Device Initializiation
1173 *
1174 * @pdev: PCI Device to initialize
1175 * @id: PCI Device ID
1176 *
1177 * Initializes and allocates resources for PCI device @pdev.
1178 *
1179 */
1180 static int __devinit tdfxfb_probe(struct pci_dev *pdev,
1181 const struct pci_device_id *id)
1182 {
1183 struct tdfx_par *default_par;
1184 struct fb_info *info;
1185 int size, err, lpitch;
1186
1187 if ((err = pci_enable_device(pdev))) {
1188 printk(KERN_WARNING "tdfxfb: Can't enable pdev: %d\n", err);
1189 return err;
1190 }
1191
1192 size = sizeof(struct tdfx_par)+256*sizeof(u32);
1193
1194 info = framebuffer_alloc(size, &pdev->dev);
1195
1196 if (!info) return -ENOMEM;
1197
1198 default_par = info->par;
1199
1200 /* Configure the default fb_fix_screeninfo first */
1201 switch (pdev->device) {
1202 case PCI_DEVICE_ID_3DFX_BANSHEE:
1203 strcat(tdfx_fix.id, " Banshee");
1204 default_par->max_pixclock = BANSHEE_MAX_PIXCLOCK;
1205 break;
1206 case PCI_DEVICE_ID_3DFX_VOODOO3:
1207 strcat(tdfx_fix.id, " Voodoo3");
1208 default_par->max_pixclock = VOODOO3_MAX_PIXCLOCK;
1209 break;
1210 case PCI_DEVICE_ID_3DFX_VOODOO5:
1211 strcat(tdfx_fix.id, " Voodoo5");
1212 default_par->max_pixclock = VOODOO5_MAX_PIXCLOCK;
1213 break;
1214 }
1215
1216 tdfx_fix.mmio_start = pci_resource_start(pdev, 0);
1217 tdfx_fix.mmio_len = pci_resource_len(pdev, 0);
1218 default_par->regbase_virt = ioremap_nocache(tdfx_fix.mmio_start, tdfx_fix.mmio_len);
1219 if (!default_par->regbase_virt) {
1220 printk("fb: Can't remap %s register area.\n", tdfx_fix.id);
1221 goto out_err;
1222 }
1223
1224 if (!request_mem_region(pci_resource_start(pdev, 0),
1225 pci_resource_len(pdev, 0), "tdfx regbase")) {
1226 printk(KERN_WARNING "tdfxfb: Can't reserve regbase\n");
1227 goto out_err;
1228 }
1229
1230 tdfx_fix.smem_start = pci_resource_start(pdev, 1);
1231 if (!(tdfx_fix.smem_len = do_lfb_size(default_par, pdev->device))) {
1232 printk("fb: Can't count %s memory.\n", tdfx_fix.id);
1233 release_mem_region(pci_resource_start(pdev, 0),
1234 pci_resource_len(pdev, 0));
1235 goto out_err;
1236 }
1237
1238 if (!request_mem_region(pci_resource_start(pdev, 1),
1239 pci_resource_len(pdev, 1), "tdfx smem")) {
1240 printk(KERN_WARNING "tdfxfb: Can't reserve smem\n");
1241 release_mem_region(pci_resource_start(pdev, 0),
1242 pci_resource_len(pdev, 0));
1243 goto out_err;
1244 }
1245
1246 info->screen_base = ioremap_nocache(tdfx_fix.smem_start,
1247 tdfx_fix.smem_len);
1248 if (!info->screen_base) {
1249 printk("fb: Can't remap %s framebuffer.\n", tdfx_fix.id);
1250 release_mem_region(pci_resource_start(pdev, 1),
1251 pci_resource_len(pdev, 1));
1252 release_mem_region(pci_resource_start(pdev, 0),
1253 pci_resource_len(pdev, 0));
1254 goto out_err;
1255 }
1256
1257 default_par->iobase = pci_resource_start(pdev, 2);
1258
1259 if (!request_region(pci_resource_start(pdev, 2),
1260 pci_resource_len(pdev, 2), "tdfx iobase")) {
1261 printk(KERN_WARNING "tdfxfb: Can't reserve iobase\n");
1262 release_mem_region(pci_resource_start(pdev, 1),
1263 pci_resource_len(pdev, 1));
1264 release_mem_region(pci_resource_start(pdev, 0),
1265 pci_resource_len(pdev, 0));
1266 goto out_err;
1267 }
1268
1269 printk("fb: %s memory = %dK\n", tdfx_fix.id, tdfx_fix.smem_len >> 10);
1270
1271 tdfx_fix.ypanstep = nopan ? 0 : 1;
1272 tdfx_fix.ywrapstep = nowrap ? 0 : 1;
1273
1274 info->fbops = &tdfxfb_ops;
1275 info->fix = tdfx_fix;
1276 info->pseudo_palette = (void *)(default_par + 1);
1277 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1278 #ifdef CONFIG_FB_3DFX_ACCEL
1279 info->flags |= FBINFO_HWACCEL_FILLRECT |
1280 FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_IMAGEBLIT;
1281 #endif
1282
1283 if (!mode_option)
1284 mode_option = "640x480@60";
1285
1286 err = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
1287 if (!err || err == 4)
1288 info->var = tdfx_var;
1289
1290 /* maximize virtual vertical length */
1291 lpitch = info->var.xres_virtual * ((info->var.bits_per_pixel + 7) >> 3);
1292 info->var.yres_virtual = info->fix.smem_len/lpitch;
1293 if (info->var.yres_virtual < info->var.yres)
1294 goto out_err;
1295
1296 #ifdef CONFIG_FB_3DFX_ACCEL
1297 /*
1298 * FIXME: Limit var->yres_virtual to 4096 because of screen artifacts
1299 * during scrolling. This is only present if 2D acceleration is
1300 * enabled.
1301 */
1302 if (info->var.yres_virtual > 4096)
1303 info->var.yres_virtual = 4096;
1304 #endif /* CONFIG_FB_3DFX_ACCEL */
1305
1306 if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
1307 printk(KERN_WARNING "tdfxfb: Can't allocate color map\n");
1308 goto out_err;
1309 }
1310
1311 if (register_framebuffer(info) < 0) {
1312 printk("tdfxfb: can't register framebuffer\n");
1313 fb_dealloc_cmap(&info->cmap);
1314 goto out_err;
1315 }
1316 /*
1317 * Our driver data
1318 */
1319 pci_set_drvdata(pdev, info);
1320 return 0;
1321
1322 out_err:
1323 /*
1324 * Cleanup after anything that was remapped/allocated.
1325 */
1326 if (default_par->regbase_virt)
1327 iounmap(default_par->regbase_virt);
1328 if (info->screen_base)
1329 iounmap(info->screen_base);
1330 framebuffer_release(info);
1331 return -ENXIO;
1332 }
1333
1334 /**
1335 * tdfxfb_remove - Device removal
1336 *
1337 * @pdev: PCI Device to cleanup
1338 *
1339 * Releases all resources allocated during the course of the driver's
1340 * lifetime for the PCI device @pdev.
1341 *
1342 */
1343 static void __devexit tdfxfb_remove(struct pci_dev *pdev)
1344 {
1345 struct fb_info *info = pci_get_drvdata(pdev);
1346 struct tdfx_par *par = (struct tdfx_par *) info->par;
1347
1348 unregister_framebuffer(info);
1349 iounmap(par->regbase_virt);
1350 iounmap(info->screen_base);
1351
1352 /* Clean up after reserved regions */
1353 release_region(pci_resource_start(pdev, 2),
1354 pci_resource_len(pdev, 2));
1355 release_mem_region(pci_resource_start(pdev, 1),
1356 pci_resource_len(pdev, 1));
1357 release_mem_region(pci_resource_start(pdev, 0),
1358 pci_resource_len(pdev, 0));
1359 pci_set_drvdata(pdev, NULL);
1360 framebuffer_release(info);
1361 }
1362
1363 int __init tdfxfb_init(void)
1364 {
1365 #ifndef MODULE
1366 char *option = NULL;
1367
1368 if (fb_get_options("tdfxfb", &option))
1369 return -ENODEV;
1370
1371 tdfxfb_setup(option);
1372 #endif
1373 return pci_module_init(&tdfxfb_driver);
1374 }
1375
1376 static void __exit tdfxfb_exit(void)
1377 {
1378 pci_unregister_driver(&tdfxfb_driver);
1379 }
1380
1381 MODULE_AUTHOR("Hannu Mallat <hmallat@cc.hut.fi>");
1382 MODULE_DESCRIPTION("3Dfx framebuffer device driver");
1383 MODULE_LICENSE("GPL");
1384
1385 module_init(tdfxfb_init);
1386 module_exit(tdfxfb_exit);
1387
1388
1389 #ifndef MODULE
1390 void tdfxfb_setup(char *options)
1391 {
1392 char* this_opt;
1393
1394 if (!options || !*options)
1395 return;
1396
1397 while ((this_opt = strsep(&options, ",")) != NULL) {
1398 if (!*this_opt)
1399 continue;
1400 if (!strcmp(this_opt, "inverse")) {
1401 inverse = 1;
1402 fb_invert_cmaps();
1403 } else if(!strcmp(this_opt, "nopan")) {
1404 nopan = 1;
1405 } else if(!strcmp(this_opt, "nowrap")) {
1406 nowrap = 1;
1407 } else {
1408 mode_option = this_opt;
1409 }
1410 }
1411 }
1412 #endif
1413
MOXA 2.6.9 from sdlinux-moxaart.tgz