?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
MOXA linux-2.6.x / linux-2.6.9-uc0 from sdlinux-moxaart.tgz
[linux-2.6.9-moxart.git] / drivers / video / tgafb.c
blob07ee3202e92cb61f7d293f12159fd6d109414800
1 /*
2 * linux/drivers/video/tgafb.c -- DEC 21030 TGA frame buffer device
3 *
4 * Copyright (C) 1995 Jay Estabrook
5 * Copyright (C) 1997 Geert Uytterhoeven
6 * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha
7 * Copyright (C) 2002 Richard Henderson
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file COPYING in the main directory of this archive for
11 * more details.
12 */
13
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/sched.h>
17 #include <linux/errno.h>
18 #include <linux/string.h>
19 #include <linux/mm.h>
20 #include <linux/tty.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/init.h>
24 #include <linux/fb.h>
25 #include <linux/pci.h>
26 #include <linux/selection.h>
27 #include <asm/io.h>
28 #include <video/tgafb.h>
29 #include <linux/selection.h>
30
31 /*
32 * Local functions.
33 */
34
35 static int tgafb_check_var(struct fb_var_screeninfo *, struct fb_info *);
36 static int tgafb_set_par(struct fb_info *);
37 static void tgafb_set_pll(struct tga_par *, int);
38 static int tgafb_setcolreg(unsigned, unsigned, unsigned, unsigned,
39 unsigned, struct fb_info *);
40 static int tgafb_blank(int, struct fb_info *);
41 static void tgafb_init_fix(struct fb_info *);
42
43 static void tgafb_imageblit(struct fb_info *, const struct fb_image *);
44 static void tgafb_fillrect(struct fb_info *, const struct fb_fillrect *);
45 static void tgafb_copyarea(struct fb_info *, const struct fb_copyarea *);
46
47 static int tgafb_pci_register(struct pci_dev *, const struct pci_device_id *);
48 #ifdef MODULE
49 static void tgafb_pci_unregister(struct pci_dev *);
50 #endif
51
52 static const char *mode_option = "640x480@60";
53
54
55 /*
56 * Frame buffer operations
57 */
58
59 static struct fb_ops tgafb_ops = {
60 .owner = THIS_MODULE,
61 .fb_check_var = tgafb_check_var,
62 .fb_set_par = tgafb_set_par,
63 .fb_setcolreg = tgafb_setcolreg,
64 .fb_blank = tgafb_blank,
65 .fb_fillrect = tgafb_fillrect,
66 .fb_copyarea = tgafb_copyarea,
67 .fb_imageblit = tgafb_imageblit,
68 .fb_cursor = soft_cursor,
69 };
70
71
72 /*
73 * PCI registration operations
74 */
75
76 static struct pci_device_id const tgafb_pci_table[] = {
77 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TGA, PCI_ANY_ID, PCI_ANY_ID,
78 0, 0, 0 }
79 };
80
81 static struct pci_driver tgafb_driver = {
82 .name = "tgafb",
83 .id_table = tgafb_pci_table,
84 .probe = tgafb_pci_register,
85 .remove = __devexit_p(tgafb_pci_unregister),
86 };
87
88
89 /**
90 * tgafb_check_var - Optional function. Validates a var passed in.
91 * @var: frame buffer variable screen structure
92 * @info: frame buffer structure that represents a single frame buffer
93 */
94 static int
95 tgafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
96 {
97 struct tga_par *par = (struct tga_par *)info->par;
98
99 if (par->tga_type == TGA_TYPE_8PLANE) {
100 if (var->bits_per_pixel != 8)
101 return -EINVAL;
102 } else {
103 if (var->bits_per_pixel != 32)
104 return -EINVAL;
105 }
106
107 if (var->xres_virtual != var->xres || var->yres_virtual != var->yres)
108 return -EINVAL;
109 if (var->nonstd)
110 return -EINVAL;
111 if (1000000000 / var->pixclock > TGA_PLL_MAX_FREQ)
112 return -EINVAL;
113 if ((var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
114 return -EINVAL;
115
116 /* Some of the acceleration routines assume the line width is
117 a multiple of 64 bytes. */
118 if (var->xres * (par->tga_type == TGA_TYPE_8PLANE ? 1 : 4) % 64)
119 return -EINVAL;
120
121 return 0;
122 }
123
124 /**
125 * tgafb_set_par - Optional function. Alters the hardware state.
126 * @info: frame buffer structure that represents a single frame buffer
127 */
128 static int
129 tgafb_set_par(struct fb_info *info)
130 {
131 static unsigned int const deep_presets[4] = {
132 0x00014000,
133 0x0001440d,
134 0xffffffff,
135 0x0001441d
136 };
137 static unsigned int const rasterop_presets[4] = {
138 0x00000003,
139 0x00000303,
140 0xffffffff,
141 0x00000303
142 };
143 static unsigned int const mode_presets[4] = {
144 0x00002000,
145 0x00002300,
146 0xffffffff,
147 0x00002300
148 };
149 static unsigned int const base_addr_presets[4] = {
150 0x00000000,
151 0x00000001,
152 0xffffffff,
153 0x00000001
154 };
155
156 struct tga_par *par = (struct tga_par *) info->par;
157 u32 htimings, vtimings, pll_freq;
158 u8 tga_type;
159 int i, j;
160
161 /* Encode video timings. */
162 htimings = (((info->var.xres/4) & TGA_HORIZ_ACT_LSB)
163 | (((info->var.xres/4) & 0x600 << 19) & TGA_HORIZ_ACT_MSB));
164 vtimings = (info->var.yres & TGA_VERT_ACTIVE);
165 htimings |= ((info->var.right_margin/4) << 9) & TGA_HORIZ_FP;
166 vtimings |= (info->var.lower_margin << 11) & TGA_VERT_FP;
167 htimings |= ((info->var.hsync_len/4) << 14) & TGA_HORIZ_SYNC;
168 vtimings |= (info->var.vsync_len << 16) & TGA_VERT_SYNC;
169 htimings |= ((info->var.left_margin/4) << 21) & TGA_HORIZ_BP;
170 vtimings |= (info->var.upper_margin << 22) & TGA_VERT_BP;
171
172 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
173 htimings |= TGA_HORIZ_POLARITY;
174 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
175 vtimings |= TGA_VERT_POLARITY;
176
177 par->htimings = htimings;
178 par->vtimings = vtimings;
179
180 par->sync_on_green = !!(info->var.sync & FB_SYNC_ON_GREEN);
181
182 /* Store other useful values in par. */
183 par->xres = info->var.xres;
184 par->yres = info->var.yres;
185 par->pll_freq = pll_freq = 1000000000 / info->var.pixclock;
186 par->bits_per_pixel = info->var.bits_per_pixel;
187
188 tga_type = par->tga_type;
189
190 /* First, disable video. */
191 TGA_WRITE_REG(par, TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG);
192
193 /* Write the DEEP register. */
194 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
195 continue;
196 mb();
197 TGA_WRITE_REG(par, deep_presets[tga_type], TGA_DEEP_REG);
198 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
199 continue;
200 mb();
201
202 /* Write some more registers. */
203 TGA_WRITE_REG(par, rasterop_presets[tga_type], TGA_RASTEROP_REG);
204 TGA_WRITE_REG(par, mode_presets[tga_type], TGA_MODE_REG);
205 TGA_WRITE_REG(par, base_addr_presets[tga_type], TGA_BASE_ADDR_REG);
206
207 /* Calculate & write the PLL. */
208 tgafb_set_pll(par, pll_freq);
209
210 /* Write some more registers. */
211 TGA_WRITE_REG(par, 0xffffffff, TGA_PLANEMASK_REG);
212 TGA_WRITE_REG(par, 0xffffffff, TGA_PIXELMASK_REG);
213
214 /* Init video timing regs. */
215 TGA_WRITE_REG(par, htimings, TGA_HORIZ_REG);
216 TGA_WRITE_REG(par, vtimings, TGA_VERT_REG);
217
218 /* Initalise RAMDAC. */
219 if (tga_type == TGA_TYPE_8PLANE) {
220
221 /* Init BT485 RAMDAC registers. */
222 BT485_WRITE(par, 0xa2 | (par->sync_on_green ? 0x8 : 0x0),
223 BT485_CMD_0);
224 BT485_WRITE(par, 0x01, BT485_ADDR_PAL_WRITE);
225 BT485_WRITE(par, 0x14, BT485_CMD_3); /* cursor 64x64 */
226 BT485_WRITE(par, 0x40, BT485_CMD_1);
227 BT485_WRITE(par, 0x20, BT485_CMD_2); /* cursor off, for now */
228 BT485_WRITE(par, 0xff, BT485_PIXEL_MASK);
229
230 /* Fill palette registers. */
231 BT485_WRITE(par, 0x00, BT485_ADDR_PAL_WRITE);
232 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
233
234 for (i = 0; i < 16; i++) {
235 j = color_table[i];
236 TGA_WRITE_REG(par, default_red[j]|(BT485_DATA_PAL<<8),
237 TGA_RAMDAC_REG);
238 TGA_WRITE_REG(par, default_grn[j]|(BT485_DATA_PAL<<8),
239 TGA_RAMDAC_REG);
240 TGA_WRITE_REG(par, default_blu[j]|(BT485_DATA_PAL<<8),
241 TGA_RAMDAC_REG);
242 }
243 for (i = 0; i < 240*3; i += 4) {
244 TGA_WRITE_REG(par, 0x55|(BT485_DATA_PAL<<8),
245 TGA_RAMDAC_REG);
246 TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
247 TGA_RAMDAC_REG);
248 TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
249 TGA_RAMDAC_REG);
250 TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
251 TGA_RAMDAC_REG);
252 }
253
254 } else { /* 24-plane or 24plusZ */
255
256 /* Init BT463 registers. */
257 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_0, 0x40);
258 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_1, 0x08);
259 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_2,
260 (par->sync_on_green ? 0x80 : 0x40));
261
262 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_0, 0xff);
263 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_1, 0xff);
264 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_2, 0xff);
265 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_3, 0x0f);
266
267 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_0, 0x00);
268 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_1, 0x00);
269 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_2, 0x00);
270 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_3, 0x00);
271
272 /* Fill the palette. */
273 BT463_LOAD_ADDR(par, 0x0000);
274 TGA_WRITE_REG(par, BT463_PALETTE<<2, TGA_RAMDAC_REG);
275
276 for (i = 0; i < 16; i++) {
277 j = color_table[i];
278 TGA_WRITE_REG(par, default_red[j]|(BT463_PALETTE<<10),
279 TGA_RAMDAC_REG);
280 TGA_WRITE_REG(par, default_grn[j]|(BT463_PALETTE<<10),
281 TGA_RAMDAC_REG);
282 TGA_WRITE_REG(par, default_blu[j]|(BT463_PALETTE<<10),
283 TGA_RAMDAC_REG);
284 }
285 for (i = 0; i < 512*3; i += 4) {
286 TGA_WRITE_REG(par, 0x55|(BT463_PALETTE<<10),
287 TGA_RAMDAC_REG);
288 TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
289 TGA_RAMDAC_REG);
290 TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
291 TGA_RAMDAC_REG);
292 TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
293 TGA_RAMDAC_REG);
294 }
295
296 /* Fill window type table after start of vertical retrace. */
297 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
298 continue;
299 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
300 mb();
301 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
302 continue;
303 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
304
305 BT463_LOAD_ADDR(par, BT463_WINDOW_TYPE_BASE);
306 TGA_WRITE_REG(par, BT463_REG_ACC<<2, TGA_RAMDAC_SETUP_REG);
307
308 for (i = 0; i < 16; i++) {
309 TGA_WRITE_REG(par, 0x00|(BT463_REG_ACC<<10),
310 TGA_RAMDAC_REG);
311 TGA_WRITE_REG(par, 0x01|(BT463_REG_ACC<<10),
312 TGA_RAMDAC_REG);
313 TGA_WRITE_REG(par, 0x80|(BT463_REG_ACC<<10),
314 TGA_RAMDAC_REG);
315 }
316
317 }
318
319 /* Finally, enable video scan (and pray for the monitor... :-) */
320 TGA_WRITE_REG(par, TGA_VALID_VIDEO, TGA_VALID_REG);
321
322 return 0;
323 }
324
325 #define DIFFCHECK(X) \
326 do { \
327 if (m <= 0x3f) { \
328 int delta = f - (TGA_PLL_BASE_FREQ * (X)) / (r << shift); \
329 if (delta < 0) \
330 delta = -delta; \
331 if (delta < min_diff) \
332 min_diff = delta, vm = m, va = a, vr = r; \
333 } \
334 } while (0)
335
336 static void
337 tgafb_set_pll(struct tga_par *par, int f)
338 {
339 int n, shift, base, min_diff, target;
340 int r,a,m,vm = 34, va = 1, vr = 30;
341
342 for (r = 0 ; r < 12 ; r++)
343 TGA_WRITE_REG(par, !r, TGA_CLOCK_REG);
344
345 if (f > TGA_PLL_MAX_FREQ)
346 f = TGA_PLL_MAX_FREQ;
347
348 if (f >= TGA_PLL_MAX_FREQ / 2)
349 shift = 0;
350 else if (f >= TGA_PLL_MAX_FREQ / 4)
351 shift = 1;
352 else
353 shift = 2;
354
355 TGA_WRITE_REG(par, shift & 1, TGA_CLOCK_REG);
356 TGA_WRITE_REG(par, shift >> 1, TGA_CLOCK_REG);
357
358 for (r = 0 ; r < 10 ; r++)
359 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
360
361 if (f <= 120000) {
362 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
363 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
364 }
365 else if (f <= 200000) {
366 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
367 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
368 }
369 else {
370 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
371 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
372 }
373
374 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
375 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
376 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
377 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
378 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
379 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
380
381 target = (f << shift) / TGA_PLL_BASE_FREQ;
382 min_diff = TGA_PLL_MAX_FREQ;
383
384 r = 7 / target;
385 if (!r) r = 1;
386
387 base = target * r;
388 while (base < 449) {
389 for (n = base < 7 ? 7 : base; n < base + target && n < 449; n++) {
390 m = ((n + 3) / 7) - 1;
391 a = 0;
392 DIFFCHECK((m + 1) * 7);
393 m++;
394 DIFFCHECK((m + 1) * 7);
395 m = (n / 6) - 1;
396 if ((a = n % 6))
397 DIFFCHECK(n);
398 }
399 r++;
400 base += target;
401 }
402
403 vr--;
404
405 for (r = 0; r < 8; r++)
406 TGA_WRITE_REG(par, (vm >> r) & 1, TGA_CLOCK_REG);
407 for (r = 0; r < 8 ; r++)
408 TGA_WRITE_REG(par, (va >> r) & 1, TGA_CLOCK_REG);
409 for (r = 0; r < 7 ; r++)
410 TGA_WRITE_REG(par, (vr >> r) & 1, TGA_CLOCK_REG);
411 TGA_WRITE_REG(par, ((vr >> 7) & 1)|2, TGA_CLOCK_REG);
412 }
413
414
415 /**
416 * tgafb_setcolreg - Optional function. Sets a color register.
417 * @regno: boolean, 0 copy local, 1 get_user() function
418 * @red: frame buffer colormap structure
419 * @green: The green value which can be up to 16 bits wide
420 * @blue: The blue value which can be up to 16 bits wide.
421 * @transp: If supported the alpha value which can be up to 16 bits wide.
422 * @info: frame buffer info structure
423 */
424 static int
425 tgafb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
426 unsigned transp, struct fb_info *info)
427 {
428 struct tga_par *par = (struct tga_par *) info->par;
429
430 if (regno > 255)
431 return 1;
432 red >>= 8;
433 green >>= 8;
434 blue >>= 8;
435
436 if (par->tga_type == TGA_TYPE_8PLANE) {
437 BT485_WRITE(par, regno, BT485_ADDR_PAL_WRITE);
438 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
439 TGA_WRITE_REG(par, red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
440 TGA_WRITE_REG(par, green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
441 TGA_WRITE_REG(par, blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
442 } else if (regno < 16) {
443 u32 value = (red << 16) | (green << 8) | blue;
444 ((u32 *)info->pseudo_palette)[regno] = value;
445 }
446
447 return 0;
448 }
449
450
451 /**
452 * tgafb_blank - Optional function. Blanks the display.
453 * @blank_mode: the blank mode we want.
454 * @info: frame buffer structure that represents a single frame buffer
455 */
456 static int
457 tgafb_blank(int blank, struct fb_info *info)
458 {
459 struct tga_par *par = (struct tga_par *) info->par;
460 u32 vhcr, vvcr, vvvr;
461 unsigned long flags;
462
463 local_irq_save(flags);
464
465 vhcr = TGA_READ_REG(par, TGA_HORIZ_REG);
466 vvcr = TGA_READ_REG(par, TGA_VERT_REG);
467 vvvr = TGA_READ_REG(par, TGA_VALID_REG);
468 vvvr &= ~(TGA_VALID_VIDEO | TGA_VALID_BLANK);
469
470 switch (blank) {
471 case 0: /* Unblanking */
472 if (par->vesa_blanked) {
473 TGA_WRITE_REG(par, vhcr & 0xbfffffff, TGA_HORIZ_REG);
474 TGA_WRITE_REG(par, vvcr & 0xbfffffff, TGA_VERT_REG);
475 par->vesa_blanked = 0;
476 }
477 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO, TGA_VALID_REG);
478 break;
479
480 case 1: /* Normal blanking */
481 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO | TGA_VALID_BLANK,
482 TGA_VALID_REG);
483 break;
484
485 case 2: /* VESA blank (vsync off) */
486 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
487 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
488 par->vesa_blanked = 1;
489 break;
490
491 case 3: /* VESA blank (hsync off) */
492 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
493 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
494 par->vesa_blanked = 1;
495 break;
496
497 case 4: /* Poweroff */
498 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
499 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
500 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
501 par->vesa_blanked = 1;
502 break;
503 }
504
505 local_irq_restore(flags);
506 return 0;
507 }
508
509
510 /*
511 * Acceleration.
512 */
513
514 /**
515 * tgafb_imageblit - REQUIRED function. Can use generic routines if
516 * non acclerated hardware and packed pixel based.
517 * Copies a image from system memory to the screen.
518 *
519 * @info: frame buffer structure that represents a single frame buffer
520 * @image: structure defining the image.
521 */
522 static void
523 tgafb_imageblit(struct fb_info *info, const struct fb_image *image)
524 {
525 static unsigned char const bitrev[256] = {
526 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
527 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
528 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
529 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
530 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
531 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
532 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
533 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
534 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
535 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
536 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
537 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
538 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
539 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
540 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
541 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
542 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
543 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
544 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
545 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
546 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
547 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
548 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
549 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
550 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
551 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
552 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
553 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
554 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
555 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
556 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
557 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff
558 };
559
560 struct tga_par *par = (struct tga_par *) info->par;
561 u32 fgcolor, bgcolor, dx, dy, width, height, vxres, vyres, pixelmask;
562 unsigned long rincr, line_length, shift, pos, is8bpp;
563 unsigned long i, j;
564 const unsigned char *data;
565 void *regs_base, *fb_base;
566
567 dx = image->dx;
568 dy = image->dy;
569 width = image->width;
570 height = image->height;
571 vxres = info->var.xres_virtual;
572 vyres = info->var.yres_virtual;
573 line_length = info->fix.line_length;
574 rincr = (width + 7) / 8;
575
576 /* Crop the image to the screen. */
577 if (dx > vxres || dy > vyres)
578 return;
579 if (dx + width > vxres)
580 width = vxres - dx;
581 if (dy + height > vyres)
582 height = vyres - dy;
583
584 /* For copies that aren't pixel expansion, there's little we
585 can do better than the generic code. */
586 /* ??? There is a DMA write mode; I wonder if that could be
587 made to pull the data from the image buffer... */
588 if (image->depth > 1) {
589 cfb_imageblit(info, image);
590 return;
591 }
592
593 regs_base = par->tga_regs_base;
594 fb_base = par->tga_fb_base;
595 is8bpp = info->var.bits_per_pixel == 8;
596
597 /* Expand the color values to fill 32-bits. */
598 /* ??? Would be nice to notice colour changes elsewhere, so
599 that we can do this only when necessary. */
600 fgcolor = image->fg_color;
601 bgcolor = image->bg_color;
602 if (is8bpp) {
603 fgcolor |= fgcolor << 8;
604 fgcolor |= fgcolor << 16;
605 bgcolor |= bgcolor << 8;
606 bgcolor |= bgcolor << 16;
607 } else {
608 if (fgcolor < 16)
609 fgcolor = ((u32 *)info->pseudo_palette)[fgcolor];
610 if (bgcolor < 16)
611 bgcolor = ((u32 *)info->pseudo_palette)[bgcolor];
612 }
613 __raw_writel(fgcolor, regs_base + TGA_FOREGROUND_REG);
614 __raw_writel(bgcolor, regs_base + TGA_BACKGROUND_REG);
615
616 /* Acquire proper alignment; set up the PIXELMASK register
617 so that we only write the proper character cell. */
618 pos = dy * line_length;
619 if (is8bpp) {
620 pos += dx;
621 shift = pos & 3;
622 pos &= -4;
623 } else {
624 pos += dx * 4;
625 shift = (pos & 7) >> 2;
626 pos &= -8;
627 }
628
629 data = (const unsigned char *) image->data;
630
631 /* Enable opaque stipple mode. */
632 __raw_writel((is8bpp
633 ? TGA_MODE_SBM_8BPP | TGA_MODE_OPAQUE_STIPPLE
634 : TGA_MODE_SBM_24BPP | TGA_MODE_OPAQUE_STIPPLE),
635 regs_base + TGA_MODE_REG);
636
637 if (width + shift <= 32) {
638 unsigned long bwidth;
639
640 /* Handle common case of imaging a single character, in
641 a font less than 32 pixels wide. */
642
643 pixelmask = (1 << width) - 1;
644 pixelmask <<= shift;
645 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
646 wmb();
647
648 bwidth = (width + 7) / 8;
649
650 for (i = 0; i < height; ++i) {
651 u32 mask = 0;
652
653 /* The image data is bit big endian; we need
654 little endian. */
655 for (j = 0; j < bwidth; ++j)
656 mask |= bitrev[data[j]] << (j * 8);
657
658 __raw_writel(mask << shift, fb_base + pos);
659
660 pos += line_length;
661 data += rincr;
662 }
663 wmb();
664 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
665 } else if (shift == 0) {
666 unsigned long pos0 = pos;
667 const unsigned char *data0 = data;
668 unsigned long bincr = (is8bpp ? 8 : 8*4);
669 unsigned long bwidth;
670
671 /* Handle another common case in which accel_putcs
672 generates a large bitmap, which happens to be aligned.
673 Allow the tail to be misaligned. This case is
674 interesting because we've not got to hold partial
675 bytes across the words being written. */
676
677 wmb();
678
679 bwidth = (width / 8) & -4;
680 for (i = 0; i < height; ++i) {
681 for (j = 0; j < bwidth; j += 4) {
682 u32 mask = 0;
683 mask |= bitrev[data[j+0]] << (0 * 8);
684 mask |= bitrev[data[j+1]] << (1 * 8);
685 mask |= bitrev[data[j+2]] << (2 * 8);
686 mask |= bitrev[data[j+3]] << (3 * 8);
687 __raw_writel(mask, fb_base + pos + j*bincr);
688 }
689 pos += line_length;
690 data += rincr;
691 }
692 wmb();
693
694 pixelmask = (1ul << (width & 31)) - 1;
695 if (pixelmask) {
696 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
697 wmb();
698
699 pos = pos0 + bwidth*bincr;
700 data = data0 + bwidth;
701 bwidth = ((width & 31) + 7) / 8;
702
703 for (i = 0; i < height; ++i) {
704 u32 mask = 0;
705 for (j = 0; j < bwidth; ++j)
706 mask |= bitrev[data[j]] << (j * 8);
707 __raw_writel(mask, fb_base + pos);
708 pos += line_length;
709 data += rincr;
710 }
711 wmb();
712 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
713 }
714 } else {
715 unsigned long pos0 = pos;
716 const unsigned char *data0 = data;
717 unsigned long bincr = (is8bpp ? 8 : 8*4);
718 unsigned long bwidth;
719
720 /* Finally, handle the generic case of misaligned start.
721 Here we split the write into 16-bit spans. This allows
722 us to use only one pixel mask, instead of four as would
723 be required by writing 24-bit spans. */
724
725 pixelmask = 0xffff << shift;
726 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
727 wmb();
728
729 bwidth = (width / 8) & -2;
730 for (i = 0; i < height; ++i) {
731 for (j = 0; j < bwidth; j += 2) {
732 u32 mask = 0;
733 mask |= bitrev[data[j+0]] << (0 * 8);
734 mask |= bitrev[data[j+1]] << (1 * 8);
735 mask <<= shift;
736 __raw_writel(mask, fb_base + pos + j*bincr);
737 }
738 pos += line_length;
739 data += rincr;
740 }
741 wmb();
742
743 pixelmask = ((1ul << (width & 15)) - 1) << shift;
744 if (pixelmask) {
745 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
746 wmb();
747
748 pos = pos0 + bwidth*bincr;
749 data = data0 + bwidth;
750 bwidth = (width & 15) > 8;
751
752 for (i = 0; i < height; ++i) {
753 u32 mask = bitrev[data[0]];
754 if (bwidth)
755 mask |= bitrev[data[1]] << 8;
756 mask <<= shift;
757 __raw_writel(mask, fb_base + pos);
758 pos += line_length;
759 data += rincr;
760 }
761 wmb();
762 }
763 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
764 }
765
766 /* Disable opaque stipple mode. */
767 __raw_writel((is8bpp
768 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
769 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
770 regs_base + TGA_MODE_REG);
771 }
772
773 /**
774 * tgafb_fillrect - REQUIRED function. Can use generic routines if
775 * non acclerated hardware and packed pixel based.
776 * Draws a rectangle on the screen.
777 *
778 * @info: frame buffer structure that represents a single frame buffer
779 * @rect: structure defining the rectagle and operation.
780 */
781 static void
782 tgafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
783 {
784 struct tga_par *par = (struct tga_par *) info->par;
785 int is8bpp = info->var.bits_per_pixel == 8;
786 u32 dx, dy, width, height, vxres, vyres, color;
787 unsigned long pos, align, line_length, i, j;
788 void *regs_base, *fb_base;
789
790 dx = rect->dx;
791 dy = rect->dy;
792 width = rect->width;
793 height = rect->height;
794 vxres = info->var.xres_virtual;
795 vyres = info->var.yres_virtual;
796 line_length = info->fix.line_length;
797 regs_base = par->tga_regs_base;
798 fb_base = par->tga_fb_base;
799
800 /* Crop the rectangle to the screen. */
801 if (dx > vxres || dy > vyres || !width || !height)
802 return;
803 if (dx + width > vxres)
804 width = vxres - dx;
805 if (dy + height > vyres)
806 height = vyres - dy;
807
808 pos = dy * line_length + dx * (is8bpp ? 1 : 4);
809
810 /* ??? We could implement ROP_XOR with opaque fill mode
811 and a RasterOp setting of GXxor, but as far as I can
812 tell, this mode is not actually used in the kernel.
813 Thus I am ignoring it for now. */
814 if (rect->rop != ROP_COPY) {
815 cfb_fillrect(info, rect);
816 return;
817 }
818
819 /* Expand the color value to fill 8 pixels. */
820 color = rect->color;
821 if (is8bpp) {
822 color |= color << 8;
823 color |= color << 16;
824 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
825 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
826 } else {
827 if (color < 16)
828 color = ((u32 *)info->pseudo_palette)[color];
829 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
830 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
831 __raw_writel(color, regs_base + TGA_BLOCK_COLOR2_REG);
832 __raw_writel(color, regs_base + TGA_BLOCK_COLOR3_REG);
833 __raw_writel(color, regs_base + TGA_BLOCK_COLOR4_REG);
834 __raw_writel(color, regs_base + TGA_BLOCK_COLOR5_REG);
835 __raw_writel(color, regs_base + TGA_BLOCK_COLOR6_REG);
836 __raw_writel(color, regs_base + TGA_BLOCK_COLOR7_REG);
837 }
838
839 /* The DATA register holds the fill mask for block fill mode.
840 Since we're not stippling, this is all ones. */
841 __raw_writel(0xffffffff, regs_base + TGA_DATA_REG);
842
843 /* Enable block fill mode. */
844 __raw_writel((is8bpp
845 ? TGA_MODE_SBM_8BPP | TGA_MODE_BLOCK_FILL
846 : TGA_MODE_SBM_24BPP | TGA_MODE_BLOCK_FILL),
847 regs_base + TGA_MODE_REG);
848 wmb();
849
850 /* We can fill 2k pixels per operation. Notice blocks that fit
851 the width of the screen so that we can take advantage of this
852 and fill more than one line per write. */
853 if (width == line_length)
854 width *= height, height = 1;
855
856 /* The write into the frame buffer must be aligned to 4 bytes,
857 but we are allowed to encode the offset within the word in
858 the data word written. */
859 align = (pos & 3) << 16;
860 pos &= -4;
861
862 if (width <= 2048) {
863 u32 data;
864
865 data = (width - 1) | align;
866
867 for (i = 0; i < height; ++i) {
868 __raw_writel(data, fb_base + pos);
869 pos += line_length;
870 }
871 } else {
872 unsigned long Bpp = (is8bpp ? 1 : 4);
873 unsigned long nwidth = width & -2048;
874 u32 fdata, ldata;
875
876 fdata = (2048 - 1) | align;
877 ldata = ((width & 2047) - 1) | align;
878
879 for (i = 0; i < height; ++i) {
880 for (j = 0; j < nwidth; j += 2048)
881 __raw_writel(fdata, fb_base + pos + j*Bpp);
882 if (j < width)
883 __raw_writel(ldata, fb_base + pos + j*Bpp);
884 pos += line_length;
885 }
886 }
887 wmb();
888
889 /* Disable block fill mode. */
890 __raw_writel((is8bpp
891 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
892 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
893 regs_base + TGA_MODE_REG);
894 }
895
896 /**
897 * tgafb_copyarea - REQUIRED function. Can use generic routines if
898 * non acclerated hardware and packed pixel based.
899 * Copies on area of the screen to another area.
900 *
901 * @info: frame buffer structure that represents a single frame buffer
902 * @area: structure defining the source and destination.
903 */
904
905 /* Handle the special case of copying entire lines, e.g. during scrolling.
906 We can avoid a lot of needless computation in this case. In the 8bpp
907 case we need to use the COPY64 registers instead of mask writes into
908 the frame buffer to achieve maximum performance. */
909
910 static inline void
911 copyarea_line_8bpp(struct fb_info *info, u32 dy, u32 sy,
912 u32 height, u32 width)
913 {
914 struct tga_par *par = (struct tga_par *) info->par;
915 void *tga_regs = par->tga_regs_base;
916 unsigned long dpos, spos, i, n64;
917
918 /* Set up the MODE and PIXELSHIFT registers. */
919 __raw_writel(TGA_MODE_SBM_8BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
920 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
921 wmb();
922
923 n64 = (height * width) / 64;
924
925 if (dy < sy) {
926 spos = (sy + height) * width;
927 dpos = (dy + height) * width;
928
929 for (i = 0; i < n64; ++i) {
930 spos -= 64;
931 dpos -= 64;
932 __raw_writel(spos, tga_regs+TGA_COPY64_SRC);
933 wmb();
934 __raw_writel(dpos, tga_regs+TGA_COPY64_DST);
935 wmb();
936 }
937 } else {
938 spos = sy * width;
939 dpos = dy * width;
940
941 for (i = 0; i < n64; ++i) {
942 __raw_writel(spos, tga_regs+TGA_COPY64_SRC);
943 wmb();
944 __raw_writel(dpos, tga_regs+TGA_COPY64_DST);
945 wmb();
946 spos += 64;
947 dpos += 64;
948 }
949 }
950
951 /* Reset the MODE register to normal. */
952 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
953 }
954
955 static inline void
956 copyarea_line_32bpp(struct fb_info *info, u32 dy, u32 sy,
957 u32 height, u32 width)
958 {
959 struct tga_par *par = (struct tga_par *) info->par;
960 void *tga_regs = par->tga_regs_base;
961 void *tga_fb = par->tga_fb_base;
962 void *src, *dst;
963 unsigned long i, n16;
964
965 /* Set up the MODE and PIXELSHIFT registers. */
966 __raw_writel(TGA_MODE_SBM_24BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
967 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
968 wmb();
969
970 n16 = (height * width) / 16;
971
972 if (dy < sy) {
973 src = tga_fb + (sy + height) * width * 4;
974 dst = tga_fb + (dy + height) * width * 4;
975
976 for (i = 0; i < n16; ++i) {
977 src -= 64;
978 dst -= 64;
979 __raw_writel(0xffff, src);
980 wmb();
981 __raw_writel(0xffff, dst);
982 wmb();
983 }
984 } else {
985 src = tga_fb + sy * width * 4;
986 dst = tga_fb + dy * width * 4;
987
988 for (i = 0; i < n16; ++i) {
989 __raw_writel(0xffff, src);
990 wmb();
991 __raw_writel(0xffff, dst);
992 wmb();
993 src += 64;
994 dst += 64;
995 }
996 }
997
998 /* Reset the MODE register to normal. */
999 __raw_writel(TGA_MODE_SBM_24BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1000 }
1001
1002 /* The general case of forward copy in 8bpp mode. */
1003 static inline void
1004 copyarea_foreward_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy,
1005 u32 height, u32 width, u32 line_length)
1006 {
1007 struct tga_par *par = (struct tga_par *) info->par;
1008 unsigned long i, copied, left;
1009 unsigned long dpos, spos, dalign, salign, yincr;
1010 u32 smask_first, dmask_first, dmask_last;
1011 int pixel_shift, need_prime, need_second;
1012 unsigned long n64, n32, xincr_first;
1013 void *tga_regs, *tga_fb;
1014
1015 yincr = line_length;
1016 if (dy > sy) {
1017 dy += height - 1;
1018 sy += height - 1;
1019 yincr = -yincr;
1020 }
1021
1022 /* Compute the offsets and alignments in the frame buffer.
1023 More than anything else, these control how we do copies. */
1024 dpos = dy * line_length + dx;
1025 spos = sy * line_length + sx;
1026 dalign = dpos & 7;
1027 salign = spos & 7;
1028 dpos &= -8;
1029 spos &= -8;
1030
1031 /* Compute the value for the PIXELSHIFT register. This controls
1032 both non-co-aligned source and destination and copy direction. */
1033 if (dalign >= salign)
1034 pixel_shift = dalign - salign;
1035 else
1036 pixel_shift = 8 - (salign - dalign);
1037
1038 /* Figure out if we need an additional priming step for the
1039 residue register. */
1040 need_prime = (salign > dalign);
1041 if (need_prime)
1042 dpos -= 8;
1043
1044 /* Begin by copying the leading unaligned destination. Copy enough
1045 to make the next destination address 32-byte aligned. */
1046 copied = 32 - (dalign + (dpos & 31));
1047 if (copied == 32)
1048 copied = 0;
1049 xincr_first = (copied + 7) & -8;
1050 smask_first = dmask_first = (1ul << copied) - 1;
1051 smask_first <<= salign;
1052 dmask_first <<= dalign + need_prime*8;
1053 if (need_prime && copied > 24)
1054 copied -= 8;
1055 left = width - copied;
1056
1057 /* Care for small copies. */
1058 if (copied > width) {
1059 u32 t;
1060 t = (1ul << width) - 1;
1061 t <<= dalign + need_prime*8;
1062 dmask_first &= t;
1063 left = 0;
1064 }
1065
1066 /* Attempt to use 64-byte copies. This is only possible if the
1067 source and destination are co-aligned at 64 bytes. */
1068 n64 = need_second = 0;
1069 if ((dpos & 63) == (spos & 63)
1070 && (height == 1 || line_length % 64 == 0)) {
1071 /* We may need a 32-byte copy to ensure 64 byte alignment. */
1072 need_second = (dpos + xincr_first) & 63;
1073 if ((need_second & 32) != need_second)
1074 printk(KERN_ERR "tgafb: need_second wrong\n");
1075 if (left >= need_second + 64) {
1076 left -= need_second;
1077 n64 = left / 64;
1078 left %= 64;
1079 } else
1080 need_second = 0;
1081 }
1082
1083 /* Copy trailing full 32-byte sections. This will be the main
1084 loop if the 64 byte loop can't be used. */
1085 n32 = left / 32;
1086 left %= 32;
1087
1088 /* Copy the trailing unaligned destination. */
1089 dmask_last = (1ul << left) - 1;
1090
1091 tga_regs = par->tga_regs_base;
1092 tga_fb = par->tga_fb_base;
1093
1094 /* Set up the MODE and PIXELSHIFT registers. */
1095 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1096 __raw_writel(pixel_shift, tga_regs+TGA_PIXELSHIFT_REG);
1097 wmb();
1098
1099 for (i = 0; i < height; ++i) {
1100 unsigned long j;
1101 void *sfb, *dfb;
1102
1103 sfb = tga_fb + spos;
1104 dfb = tga_fb + dpos;
1105 if (dmask_first) {
1106 __raw_writel(smask_first, sfb);
1107 wmb();
1108 __raw_writel(dmask_first, dfb);
1109 wmb();
1110 sfb += xincr_first;
1111 dfb += xincr_first;
1112 }
1113
1114 if (need_second) {
1115 __raw_writel(0xffffffff, sfb);
1116 wmb();
1117 __raw_writel(0xffffffff, dfb);
1118 wmb();
1119 sfb += 32;
1120 dfb += 32;
1121 }
1122
1123 if (n64 && (((long)sfb | (long)dfb) & 63))
1124 printk(KERN_ERR
1125 "tgafb: misaligned copy64 (s:%p, d:%p)\n",
1126 sfb, dfb);
1127
1128 for (j = 0; j < n64; ++j) {
1129 __raw_writel(sfb - tga_fb, tga_regs+TGA_COPY64_SRC);
1130 wmb();
1131 __raw_writel(dfb - tga_fb, tga_regs+TGA_COPY64_DST);
1132 wmb();
1133 sfb += 64;
1134 dfb += 64;
1135 }
1136
1137 for (j = 0; j < n32; ++j) {
1138 __raw_writel(0xffffffff, sfb);
1139 wmb();
1140 __raw_writel(0xffffffff, dfb);
1141 wmb();
1142 sfb += 32;
1143 dfb += 32;
1144 }
1145
1146 if (dmask_last) {
1147 __raw_writel(0xffffffff, sfb);
1148 wmb();
1149 __raw_writel(dmask_last, dfb);
1150 wmb();
1151 }
1152
1153 spos += yincr;
1154 dpos += yincr;
1155 }
1156
1157 /* Reset the MODE register to normal. */
1158 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1159 }
1160
1161 /* The (almost) general case of backward copy in 8bpp mode. */
1162 static inline void
1163 copyarea_backward_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy,
1164 u32 height, u32 width, u32 line_length,
1165 const struct fb_copyarea *area)
1166 {
1167 struct tga_par *par = (struct tga_par *) info->par;
1168 unsigned long i, left, yincr;
1169 unsigned long depos, sepos, dealign, sealign;
1170 u32 mask_first, mask_last;
1171 unsigned long n32;
1172 void *tga_regs, *tga_fb;
1173
1174 yincr = line_length;
1175 if (dy > sy) {
1176 dy += height - 1;
1177 sy += height - 1;
1178 yincr = -yincr;
1179 }
1180
1181 /* Compute the offsets and alignments in the frame buffer.
1182 More than anything else, these control how we do copies. */
1183 depos = dy * line_length + dx + width;
1184 sepos = sy * line_length + sx + width;
1185 dealign = depos & 7;
1186 sealign = sepos & 7;
1187
1188 /* ??? The documentation appears to be incorrect (or very
1189 misleading) wrt how pixel shifting works in backward copy
1190 mode, i.e. when PIXELSHIFT is negative. I give up for now.
1191 Do handle the common case of co-aligned backward copies,
1192 but frob everything else back on generic code. */
1193 if (dealign != sealign) {
1194 cfb_copyarea(info, area);
1195 return;
1196 }
1197
1198 /* We begin the copy with the trailing pixels of the
1199 unaligned destination. */
1200 mask_first = (1ul << dealign) - 1;
1201 left = width - dealign;
1202
1203 /* Care for small copies. */
1204 if (dealign > width) {
1205 mask_first ^= (1ul << (dealign - width)) - 1;
1206 left = 0;
1207 }
1208
1209 /* Next copy full words at a time. */
1210 n32 = left / 32;
1211 left %= 32;
1212
1213 /* Finally copy the unaligned head of the span. */
1214 mask_last = -1 << (32 - left);
1215
1216 tga_regs = par->tga_regs_base;
1217 tga_fb = par->tga_fb_base;
1218
1219 /* Set up the MODE and PIXELSHIFT registers. */
1220 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1221 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
1222 wmb();
1223
1224 for (i = 0; i < height; ++i) {
1225 unsigned long j;
1226 void *sfb, *dfb;
1227
1228 sfb = tga_fb + sepos;
1229 dfb = tga_fb + depos;
1230 if (mask_first) {
1231 __raw_writel(mask_first, sfb);
1232 wmb();
1233 __raw_writel(mask_first, dfb);
1234 wmb();
1235 }
1236
1237 for (j = 0; j < n32; ++j) {
1238 sfb -= 32;
1239 dfb -= 32;
1240 __raw_writel(0xffffffff, sfb);
1241 wmb();
1242 __raw_writel(0xffffffff, dfb);
1243 wmb();
1244 }
1245
1246 if (mask_last) {
1247 sfb -= 32;
1248 dfb -= 32;
1249 __raw_writel(mask_last, sfb);
1250 wmb();
1251 __raw_writel(mask_last, dfb);
1252 wmb();
1253 }
1254
1255 sepos += yincr;
1256 depos += yincr;
1257 }
1258
1259 /* Reset the MODE register to normal. */
1260 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1261 }
1262
1263 static void
1264 tgafb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
1265 {
1266 unsigned long dx, dy, width, height, sx, sy, vxres, vyres;
1267 unsigned long line_length, bpp;
1268
1269 dx = area->dx;
1270 dy = area->dy;
1271 width = area->width;
1272 height = area->height;
1273 sx = area->sx;
1274 sy = area->sy;
1275 vxres = info->var.xres_virtual;
1276 vyres = info->var.yres_virtual;
1277 line_length = info->fix.line_length;
1278
1279 /* The top left corners must be in the virtual screen. */
1280 if (dx > vxres || sx > vxres || dy > vyres || sy > vyres)
1281 return;
1282
1283 /* Clip the destination. */
1284 if (dx + width > vxres)
1285 width = vxres - dx;
1286 if (dy + height > vyres)
1287 height = vyres - dy;
1288
1289 /* The source must be completely inside the virtual screen. */
1290 if (sx + width > vxres || sy + height > vyres)
1291 return;
1292
1293 bpp = info->var.bits_per_pixel;
1294
1295 /* Detect copies of the entire line. */
1296 if (width * (bpp >> 3) == line_length) {
1297 if (bpp == 8)
1298 copyarea_line_8bpp(info, dy, sy, height, width);
1299 else
1300 copyarea_line_32bpp(info, dy, sy, height, width);
1301 }
1302
1303 /* ??? The documentation is unclear to me exactly how the pixelshift
1304 register works in 32bpp mode. Since I don't have hardware to test,
1305 give up for now and fall back on the generic routines. */
1306 else if (bpp == 32)
1307 cfb_copyarea(info, area);
1308
1309 /* Detect overlapping source and destination that requires
1310 a backward copy. */
1311 else if (dy == sy && dx > sx && dx < sx + width)
1312 copyarea_backward_8bpp(info, dx, dy, sx, sy, height,
1313 width, line_length, area);
1314 else
1315 copyarea_foreward_8bpp(info, dx, dy, sx, sy, height,
1316 width, line_length);
1317 }
1318
1319
1320 /*
1321 * Initialisation
1322 */
1323
1324 static void
1325 tgafb_init_fix(struct fb_info *info)
1326 {
1327 struct tga_par *par = (struct tga_par *)info->par;
1328 u8 tga_type = par->tga_type;
1329 const char *tga_type_name;
1330
1331 switch (tga_type) {
1332 case TGA_TYPE_8PLANE:
1333 tga_type_name = "Digital ZLXp-E1";
1334 break;
1335 case TGA_TYPE_24PLANE:
1336 tga_type_name = "Digital ZLXp-E2";
1337 break;
1338 case TGA_TYPE_24PLUSZ:
1339 tga_type_name = "Digital ZLXp-E3";
1340 break;
1341 default:
1342 tga_type_name = "Unknown";
1343 break;
1344 }
1345
1346 strlcpy(info->fix.id, tga_type_name, sizeof(info->fix.id));
1347
1348 info->fix.type = FB_TYPE_PACKED_PIXELS;
1349 info->fix.type_aux = 0;
1350 info->fix.visual = (tga_type == TGA_TYPE_8PLANE
1351 ? FB_VISUAL_PSEUDOCOLOR
1352 : FB_VISUAL_TRUECOLOR);
1353
1354 info->fix.line_length = par->xres * (par->bits_per_pixel >> 3);
1355 info->fix.smem_start = (size_t) par->tga_fb_base;
1356 info->fix.smem_len = info->fix.line_length * par->yres;
1357 info->fix.mmio_start = (size_t) par->tga_regs_base;
1358 info->fix.mmio_len = 512;
1359
1360 info->fix.xpanstep = 0;
1361 info->fix.ypanstep = 0;
1362 info->fix.ywrapstep = 0;
1363
1364 info->fix.accel = FB_ACCEL_DEC_TGA;
1365 }
1366
1367 static __devinit int
1368 tgafb_pci_register(struct pci_dev *pdev, const struct pci_device_id *ent)
1369 {
1370 static unsigned int const fb_offset_presets[4] = {
1371 TGA_8PLANE_FB_OFFSET,
1372 TGA_24PLANE_FB_OFFSET,
1373 0xffffffff,
1374 TGA_24PLUSZ_FB_OFFSET
1375 };
1376
1377 struct all_info {
1378 struct fb_info info;
1379 struct tga_par par;
1380 u32 pseudo_palette[16];
1381 } *all;
1382
1383 void *mem_base;
1384 unsigned long bar0_start, bar0_len;
1385 u8 tga_type;
1386 int ret;
1387
1388 /* Enable device in PCI config. */
1389 if (pci_enable_device(pdev)) {
1390 printk(KERN_ERR "tgafb: Cannot enable PCI device\n");
1391 return -ENODEV;
1392 }
1393
1394 /* Allocate the fb and par structures. */
1395 all = kmalloc(sizeof(*all), GFP_KERNEL);
1396 if (!all) {
1397 printk(KERN_ERR "tgafb: Cannot allocate memory\n");
1398 return -ENOMEM;
1399 }
1400 memset(all, 0, sizeof(*all));
1401 pci_set_drvdata(pdev, all);
1402
1403 /* Request the mem regions. */
1404 bar0_start = pci_resource_start(pdev, 0);
1405 bar0_len = pci_resource_len(pdev, 0);
1406 ret = -ENODEV;
1407 if (!request_mem_region (bar0_start, bar0_len, "tgafb")) {
1408 printk(KERN_ERR "tgafb: cannot reserve FB region\n");
1409 goto err0;
1410 }
1411
1412 /* Map the framebuffer. */
1413 mem_base = ioremap(bar0_start, bar0_len);
1414 if (!mem_base) {
1415 printk(KERN_ERR "tgafb: Cannot map MMIO\n");
1416 goto err1;
1417 }
1418
1419 /* Grab info about the card. */
1420 tga_type = (readl(mem_base) >> 12) & 0x0f;
1421 all->par.pdev = pdev;
1422 all->par.tga_mem_base = mem_base;
1423 all->par.tga_fb_base = mem_base + fb_offset_presets[tga_type];
1424 all->par.tga_regs_base = mem_base + TGA_REGS_OFFSET;
1425 all->par.tga_type = tga_type;
1426 pci_read_config_byte(pdev, PCI_REVISION_ID, &all->par.tga_chip_rev);
1427
1428 /* Setup framebuffer. */
1429 all->info.flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA |
1430 FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT;
1431 all->info.fbops = &tgafb_ops;
1432 all->info.screen_base = (char *) all->par.tga_fb_base;
1433 all->info.currcon = -1;
1434 all->info.par = &all->par;
1435 all->info.pseudo_palette = all->pseudo_palette;
1436
1437 /* This should give a reasonable default video mode. */
1438
1439 ret = fb_find_mode(&all->info.var, &all->info, mode_option,
1440 NULL, 0, NULL,
1441 tga_type == TGA_TYPE_8PLANE ? 8 : 32);
1442 if (ret == 0 || ret == 4) {
1443 printk(KERN_ERR "tgafb: Could not find valid video mode\n");
1444 ret = -EINVAL;
1445 goto err1;
1446 }
1447
1448 if (fb_alloc_cmap(&all->info.cmap, 256, 0)) {
1449 printk(KERN_ERR "tgafb: Could not allocate color map\n");
1450 ret = -ENOMEM;
1451 goto err1;
1452 }
1453
1454 tgafb_set_par(&all->info);
1455 tgafb_init_fix(&all->info);
1456
1457 if (register_framebuffer(&all->info) < 0) {
1458 printk(KERN_ERR "tgafb: Could not register framebuffer\n");
1459 ret = -EINVAL;
1460 goto err1;
1461 }
1462
1463 printk(KERN_INFO "tgafb: DC21030 [TGA] detected, rev=0x%02x\n",
1464 all->par.tga_chip_rev);
1465 printk(KERN_INFO "tgafb: at PCI bus %d, device %d, function %d\n",
1466 pdev->bus->number, PCI_SLOT(pdev->devfn),
1467 PCI_FUNC(pdev->devfn));
1468 printk(KERN_INFO "fb%d: %s frame buffer device at 0x%lx\n",
1469 all->info.node, all->info.fix.id, bar0_start);
1470
1471 return 0;
1472
1473 err1:
1474 release_mem_region(bar0_start, bar0_len);
1475 err0:
1476 kfree(all);
1477 return ret;
1478 }
1479
1480 #ifdef MODULE
1481 static void __exit
1482 tgafb_pci_unregister(struct pci_dev *pdev)
1483 {
1484 struct fb_info *info = pci_get_drvdata(pdev);
1485 struct tga_par *par = info->par;
1486
1487 if (!info)
1488 return;
1489 unregister_framebuffer(info);
1490 iounmap(par->tga_mem_base);
1491 release_mem_region(pci_resource_start(pdev, 0),
1492 pci_resource_len(pdev, 0));
1493 kfree(info);
1494 }
1495
1496 static void __exit
1497 tgafb_exit(void)
1498 {
1499 pci_unregister_driver(&tgafb_driver);
1500 }
1501 #endif /* MODULE */
1502
1503 #ifndef MODULE
1504 int __init
1505 tgafb_setup(char *arg)
1506 {
1507 char *this_opt;
1508
1509 if (arg && *arg) {
1510 while ((this_opt = strsep(&arg, ","))) {
1511 if (!*this_opt)
1512 continue;
1513 if (!strncmp(this_opt, "mode:", 5))
1514 mode_option = this_opt+5;
1515 else
1516 printk(KERN_ERR
1517 "tgafb: unknown parameter %s\n",
1518 this_opt);
1519 }
1520 }
1521
1522 return 0;
1523 }
1524 #endif /* !MODULE */
1525
1526 int __init
1527 tgafb_init(void)
1528 {
1529 #ifndef MODULE
1530 char *option = NULL;
1531
1532 if (fb_get_options("tgafb", &option))
1533 return -ENODEV;
1534 tgafb_setup(option);
1535 #endif
1536 return pci_module_init(&tgafb_driver);
1537 }
1538
1539 /*
1540 * Modularisation
1541 */
1542
1543 module_init(tgafb_init);
1544
1545 #ifdef MODULE
1546 module_exit(tgafb_exit);
1547 #endif
1548
1549 MODULE_DESCRIPTION("framebuffer driver for TGA chipset");
1550 MODULE_LICENSE("GPL");
MOXA 2.6.9 from sdlinux-moxaart.tgz