include/asm-m32r/system.h

   1 #ifndef _ASM_M32R_SYSTEM_H
   2 #define _ASM_M32R_SYSTEM_H
   3
   4 /*
   5  * This file is subject to the terms and conditions of the GNU General Public
   6  * License.  See the file "COPYING" in the main directory of this archive
   7  * for more details.
   8  *
   9  * Copyright (C) 2001  by Hiroyuki Kondo, Hirokazu Takata, and Hitoshi Yamamoto
  10  */
  11
  12 #include <linux/config.h>
  13
  14 #ifdef __KERNEL__
  15
  16 /*
  17  * switch_to(prev, next) should switch from task `prev' to `next'
  18  * `prev' will never be the same as `next'.
  19  *
  20  * `next' and `prev' should be struct task_struct, but it isn't always defined
  21  */
  22
  23 #ifndef CONFIG_SMP
  24 #define prepare_to_switch()  do { } while(0)
  25 #endif  /* not CONFIG_SMP */
  26
  27 #define switch_to(prev, next, last)  do { \
  28         register unsigned long  arg0 __asm__ ("r0") = (unsigned long)prev; \
  29         register unsigned long  arg1 __asm__ ("r1") = (unsigned long)next; \
  30         register unsigned long  *oldsp __asm__ ("r2") = &(prev->thread.sp); \
  31         register unsigned long  *newsp __asm__ ("r3") = &(next->thread.sp); \
  32         register unsigned long  *oldlr __asm__ ("r4") = &(prev->thread.lr); \
  33         register unsigned long  *newlr __asm__ ("r5") = &(next->thread.lr); \
  34         register struct task_struct  *__last __asm__ ("r6"); \
  35         __asm__ __volatile__ ( \
  36                 "st     r8, @-r15                                 \n\t" \
  37                 "st     r9, @-r15                                 \n\t" \
  38                 "st    r10, @-r15                                 \n\t" \
  39                 "st    r11, @-r15                                 \n\t" \
  40                 "st    r12, @-r15                                 \n\t" \
  41                 "st    r13, @-r15                                 \n\t" \
  42                 "st    r14, @-r15                                 \n\t" \
  43                 "seth  r14, #high(1f)                             \n\t" \
  44                 "or3   r14, r14, #low(1f)                         \n\t" \
  45                 "st    r14, @r4    ; store old LR                 \n\t" \
  46                 "st    r15, @r2    ; store old SP                 \n\t" \
  47                 "ld    r15, @r3    ; load new SP                  \n\t" \
  48                 "st     r0, @-r15  ; store 'prev' onto new stack  \n\t" \
  49                 "ld    r14, @r5    ; load new LR                  \n\t" \
  50                 "jmp   r14                                        \n\t" \
  51                 ".fillinsn                                        \n  " \
  52                 "1:                                               \n\t" \
  53                 "ld     r6, @r15+  ; load 'prev' from new stack   \n\t" \
  54                 "ld    r14, @r15+                                 \n\t" \
  55                 "ld    r13, @r15+                                 \n\t" \
  56                 "ld    r12, @r15+                                 \n\t" \
  57                 "ld    r11, @r15+                                 \n\t" \
  58                 "ld    r10, @r15+                                 \n\t" \
  59                 "ld     r9, @r15+                                 \n\t" \
  60                 "ld     r8, @r15+                                 \n\t" \
  61                 : "=&r" (__last) \
  62                 : "r" (arg0), "r" (arg1), "r" (oldsp), "r" (newsp), \
  63                   "r" (oldlr), "r" (newlr) \
  64                 : "memory" \
  65         ); \
  66         last = __last; \
  67 } while(0)
  68
  69 /* Interrupt Control */
  70 #if !defined(CONFIG_CHIP_M32102)
  71 #define local_irq_enable() \
  72         __asm__ __volatile__ ("setpsw #0x40 -> nop": : :"memory")
  73 #define local_irq_disable() \
  74         __asm__ __volatile__ ("clrpsw #0x40 -> nop": : :"memory")
  75 #else   /* CONFIG_CHIP_M32102 */
  76 static __inline__ void local_irq_enable(void)
  77 {
  78         unsigned long tmpreg;
  79         __asm__ __volatile__(
  80                 "mvfc   %0, psw;                \n\t"
  81                 "or3    %0, %0, #0x0040;        \n\t"
  82                 "mvtc   %0, psw;                \n\t"
  83         : "=&r" (tmpreg) : : "cbit", "memory");
  84 }
  85
  86 static __inline__ void local_irq_disable(void)
  87 {
  88         unsigned long tmpreg0, tmpreg1;
  89         __asm__ __volatile__(
  90                 "ld24   %0, #0  ; Use 32-bit insn. \n\t"
  91                 "mvfc   %1, psw ; No interrupt can be accepted here. \n\t"
  92                 "mvtc   %0, psw \n\t"
  93                 "and3   %0, %1, #0xffbf \n\t"
  94                 "mvtc   %0, psw \n\t"
  95         : "=&r" (tmpreg0), "=&r" (tmpreg1) : : "cbit", "memory");
  96 }
  97 #endif  /* CONFIG_CHIP_M32102 */
  98
  99 #define local_save_flags(x) \
 100         __asm__ __volatile__("mvfc %0,psw" : "=r"(x) : /* no input */)
 101
 102 #define local_irq_restore(x) \
 103         __asm__ __volatile__("mvtc %0,psw" : /* no outputs */ \
 104                 : "r" (x) : "cbit", "memory")
 105
 106 #if !defined(CONFIG_CHIP_M32102)
 107 #define local_irq_save(x)                               \
 108         __asm__ __volatile__(                           \
 109                 "mvfc   %0, psw;                \n\t"   \
 110                 "clrpsw #0x40 -> nop;           \n\t"   \
 111                 : "=r" (x) : /* no input */ : "memory")
 112 #else   /* CONFIG_CHIP_M32102 */
 113 #define local_irq_save(x)                               \
 114         ({                                              \
 115                 unsigned long tmpreg;                   \
 116                 __asm__ __volatile__(                   \
 117                         "ld24   %1, #0 \n\t"            \
 118                         "mvfc   %0, psw \n\t"           \
 119                         "mvtc   %1, psw \n\t"           \
 120                         "and3   %1, %0, #0xffbf \n\t"   \
 121                         "mvtc   %1, psw \n\t"           \
 122                         : "=r" (x), "=&r" (tmpreg)      \
 123                         : : "cbit", "memory");          \
 124         })
 125 #endif  /* CONFIG_CHIP_M32102 */
 126
 127 #define irqs_disabled()                                 \
 128         ({                                              \
 129                 unsigned long flags;                    \
 130                 local_save_flags(flags);                \
 131                 !(flags & 0x40);                        \
 132         })
 133
 134 #endif  /* __KERNEL__ */
 135
 136 #define nop()   __asm__ __volatile__ ("nop" : : )
 137
 138 #define xchg(ptr,x) \
 139         ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
 140
 141 #define tas(ptr)        (xchg((ptr),1))
 142
 143 #ifdef CONFIG_SMP
 144 extern void  __xchg_called_with_bad_pointer(void);
 145 #endif
 146
 147 #ifdef CONFIG_CHIP_M32700_TS1
 148 #define DCACHE_CLEAR(reg0, reg1, addr)                          \
 149         "seth   "reg1", #high(dcache_dummy);            \n\t"   \
 150         "or3    "reg1", "reg1", #low(dcache_dummy);     \n\t"   \
 151         "lock   "reg0", @"reg1";                        \n\t"   \
 152         "add3   "reg0", "addr", #0x1000;                \n\t"   \
 153         "ld     "reg0", @"reg0";                        \n\t"   \
 154         "add3   "reg0", "addr", #0x2000;                \n\t"   \
 155         "ld     "reg0", @"reg0";                        \n\t"   \
 156         "unlock "reg0", @"reg1";                        \n\t"
 157         /* FIXME: This workaround code cannot handle kenrel modules
 158          * correctly under SMP environment.
 159          */
 160 #else   /* CONFIG_CHIP_M32700_TS1 */
 161 #define DCACHE_CLEAR(reg0, reg1, addr)
 162 #endif  /* CONFIG_CHIP_M32700_TS1 */
 163
 164 static __inline__ unsigned long __xchg(unsigned long x, volatile void * ptr,
 165         int size)
 166 {
 167         unsigned long flags;
 168         unsigned long tmp = 0;
 169
 170         local_irq_save(flags);
 171
 172         switch (size) {
 173 #ifndef CONFIG_SMP
 174         case 1:
 175                 __asm__ __volatile__ (
 176                         "ldb    %0, @%2 \n\t"
 177                         "stb    %1, @%2 \n\t"
 178                         : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
 179                 break;
 180         case 2:
 181                 __asm__ __volatile__ (
 182                         "ldh    %0, @%2 \n\t"
 183                         "sth    %1, @%2 \n\t"
 184                         : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
 185                 break;
 186         case 4:
 187                 __asm__ __volatile__ (
 188                         "ld     %0, @%2 \n\t"
 189                         "st     %1, @%2 \n\t"
 190                         : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
 191                 break;
 192 #else  /* CONFIG_SMP */
 193         case 4:
 194                 __asm__ __volatile__ (
 195                         DCACHE_CLEAR("%0", "r4", "%2")
 196                         "lock   %0, @%2;        \n\t"
 197                         "unlock %1, @%2;        \n\t"
 198                         : "=&r" (tmp) : "r" (x), "r" (ptr)
 199                         : "memory"
 200 #ifdef CONFIG_CHIP_M32700_TS1
 201                         , "r4"
 202 #endif  /* CONFIG_CHIP_M32700_TS1 */
 203                 );
 204                 break;
 205         default:
 206                 __xchg_called_with_bad_pointer();
 207 #endif  /* CONFIG_SMP */
 208         }
 209
 210         local_irq_restore(flags);
 211
 212         return (tmp);
 213 }
 214
 215 /*
 216  * Memory barrier.
 217  *
 218  * mb() prevents loads and stores being reordered across this point.
 219  * rmb() prevents loads being reordered across this point.
 220  * wmb() prevents stores being reordered across this point.
 221  */
 222 #if 0
 223 #define mb()   __asm__ __volatile__ ("push r0; \n\t pop r0;" : : : "memory")
 224 #else
 225 #define mb()   __asm__ __volatile__ ("" : : : "memory")
 226 #endif
 227 #define rmb()  mb()
 228 #define wmb()  mb()
 229
 230 /**
 231  * read_barrier_depends - Flush all pending reads that subsequents reads
 232  * depend on.
 233  *
 234  * No data-dependent reads from memory-like regions are ever reordered
 235  * over this barrier.  All reads preceding this primitive are guaranteed
 236  * to access memory (but not necessarily other CPUs' caches) before any
 237  * reads following this primitive that depend on the data return by
 238  * any of the preceding reads.  This primitive is much lighter weight than
 239  * rmb() on most CPUs, and is never heavier weight than is
 240  * rmb().
 241  *
 242  * These ordering constraints are respected by both the local CPU
 243  * and the compiler.
 244  *
 245  * Ordering is not guaranteed by anything other than these primitives,
 246  * not even by data dependencies.  See the documentation for
 247  * memory_barrier() for examples and URLs to more information.
 248  *
 249  * For example, the following code would force ordering (the initial
 250  * value of "a" is zero, "b" is one, and "p" is "&a"):
 251  *
 252  * <programlisting>
 253  *      CPU 0                           CPU 1
 254  *
 255  *      b = 2;
 256  *      memory_barrier();
 257  *      p = &b;                         q = p;
 258  *                                      read_barrier_depends();
 259  *                                      d = *q;
 260  * </programlisting>
 261  *
 262  *
 263  * because the read of "*q" depends on the read of "p" and these
 264  * two reads are separated by a read_barrier_depends().  However,
 265  * the following code, with the same initial values for "a" and "b":
 266  *
 267  * <programlisting>
 268  *      CPU 0                           CPU 1
 269  *
 270  *      a = 2;
 271  *      memory_barrier();
 272  *      b = 3;                          y = b;
 273  *                                      read_barrier_depends();
 274  *                                      x = a;
 275  * </programlisting>
 276  *
 277  * does not enforce ordering, since there is no data dependency between
 278  * the read of "a" and the read of "b".  Therefore, on some CPUs, such
 279  * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
 280  * in cases like thiswhere there are no data dependencies.
 281  **/
 282
 283 #define read_barrier_depends()  do { } while (0)
 284
 285 #ifdef CONFIG_SMP
 286 #define smp_mb()        mb()
 287 #define smp_rmb()       rmb()
 288 #define smp_wmb()       wmb()
 289 #define smp_read_barrier_depends()      read_barrier_depends()
 290 #else
 291 #define smp_mb()        barrier()
 292 #define smp_rmb()       barrier()
 293 #define smp_wmb()       barrier()
 294 #define smp_read_barrier_depends()      do { } while (0)
 295 #endif
 296
 297 #define set_mb(var, value) do { xchg(&var, value); } while (0)
 298 #define set_wmb(var, value) do { var = value; wmb(); } while (0)
 299
 300 #endif  /* _ASM_M32R_SYSTEM_H */
 301