include/asm-mips/mach-db1x00/db1x00.h

   1 /*
   2  * AMD Alchemy DB1x00 Reference Boards
   3  *
   4  * Copyright 2001 MontaVista Software Inc.
   5  * Author: MontaVista Software, Inc.
   6  *              ppopov@mvista.com or source@mvista.com
   7  *
   8  * ########################################################################
   9  *
  10  *  This program is free software; you can distribute it and/or modify it
  11  *  under the terms of the GNU General Public License (Version 2) as
  12  *  published by the Free Software Foundation.
  13  *
  14  *  This program is distributed in the hope it will be useful, but WITHOUT
  15  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  17  *  for more details.
  18  *
  19  *  You should have received a copy of the GNU General Public License along
  20  *  with this program; if not, write to the Free Software Foundation, Inc.,
  21  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  22  *
  23  * ########################################################################
  24  *
  25  *
  26  */
  27 #ifndef __ASM_DB1X00_H
  28 #define __ASM_DB1X00_H
  29
  30 #ifdef CONFIG_MIPS_DB1550
  31 #define BCSR_KSEG1_ADDR 0xAF000000
  32 #else
  33 #define BCSR_KSEG1_ADDR 0xAE000000
  34 #endif
  35
  36 /*
  37  * Overlay data structure of the Db1x00 board registers.
  38  * Registers located at physical 0E0000xx, KSEG1 0xAE0000xx
  39  */
  40 typedef volatile struct
  41 {
  42         /*00*/  unsigned short whoami;
  43         unsigned short reserved0;
  44         /*04*/  unsigned short status;
  45         unsigned short reserved1;
  46         /*08*/  unsigned short switches;
  47         unsigned short reserved2;
  48         /*0C*/  unsigned short resets;
  49         unsigned short reserved3;
  50         /*10*/  unsigned short pcmcia;
  51         unsigned short reserved4;
  52         /*14*/  unsigned short specific;
  53         unsigned short reserved5;
  54         /*18*/  unsigned short leds;
  55         unsigned short reserved6;
  56         /*1C*/  unsigned short swreset;
  57         unsigned short reserved7;
  58
  59 } BCSR;
  60
  61
  62 /*
  63  * Register/mask bit definitions for the BCSRs
  64  */
  65 #define BCSR_WHOAMI_DCID                0x000F
  66 #define BCSR_WHOAMI_CPLD                0x00F0
  67 #define BCSR_WHOAMI_BOARD               0x0F00
  68
  69 #define BCSR_STATUS_PC0VS               0x0003
  70 #define BCSR_STATUS_PC1VS               0x000C
  71 #define BCSR_STATUS_PC0FI               0x0010
  72 #define BCSR_STATUS_PC1FI               0x0020
  73 #define BCSR_STATUS_FLASHBUSY           0x0100
  74 #define BCSR_STATUS_ROMBUSY             0x0400
  75 #define BCSR_STATUS_SWAPBOOT            0x2000
  76 #define BCSR_STATUS_FLASHDEN            0xC000
  77
  78 #define BCSR_SWITCHES_DIP               0x00FF
  79 #define BCSR_SWITCHES_DIP_1             0x0080
  80 #define BCSR_SWITCHES_DIP_2             0x0040
  81 #define BCSR_SWITCHES_DIP_3             0x0020
  82 #define BCSR_SWITCHES_DIP_4             0x0010
  83 #define BCSR_SWITCHES_DIP_5             0x0008
  84 #define BCSR_SWITCHES_DIP_6             0x0004
  85 #define BCSR_SWITCHES_DIP_7             0x0002
  86 #define BCSR_SWITCHES_DIP_8             0x0001
  87 #define BCSR_SWITCHES_ROTARY            0x0F00
  88
  89 #define BCSR_RESETS_PHY0                0x0001
  90 #define BCSR_RESETS_PHY1                0x0002
  91 #define BCSR_RESETS_DC                  0x0004
  92 #define BCSR_RESETS_FIR_SEL             0x2000
  93 #define BCSR_RESETS_IRDA_MODE_MASK      0xC000
  94 #define BCSR_RESETS_IRDA_MODE_FULL      0x0000
  95 #define BCSR_RESETS_IRDA_MODE_OFF       0x4000
  96 #define BCSR_RESETS_IRDA_MODE_2_3       0x8000
  97 #define BCSR_RESETS_IRDA_MODE_1_3       0xC000
  98
  99 #define BCSR_PCMCIA_PC0VPP              0x0003
 100 #define BCSR_PCMCIA_PC0VCC              0x000C
 101 #define BCSR_PCMCIA_PC0DRVEN            0x0010
 102 #define BCSR_PCMCIA_PC0RST              0x0080
 103 #define BCSR_PCMCIA_PC1VPP              0x0300
 104 #define BCSR_PCMCIA_PC1VCC              0x0C00
 105 #define BCSR_PCMCIA_PC1DRVEN            0x1000
 106 #define BCSR_PCMCIA_PC1RST              0x8000
 107
 108 #define BCSR_BOARD_PCIM66EN             0x0001
 109 #define BCSR_BOARD_SD0_PWR              0x0040
 110 #define BCSR_BOARD_SD1_PWR              0x0080
 111 #define BCSR_BOARD_PCIM33               0x0100
 112 #define BCSR_BOARD_GPIO200RST           0x0400
 113 #define BCSR_BOARD_PCICFG               0x1000
 114 #define BCSR_BOARD_SD0_WP               0x4000
 115 #define BCSR_BOARD_SD1_WP               0x8000
 116
 117 #define BCSR_LEDS_DECIMALS              0x0003
 118 #define BCSR_LEDS_LED0                  0x0100
 119 #define BCSR_LEDS_LED1                  0x0200
 120 #define BCSR_LEDS_LED2                  0x0400
 121 #define BCSR_LEDS_LED3                  0x0800
 122
 123 #define BCSR_SWRESET_RESET              0x0080
 124
 125 /* PCMCIA Db1x00 specific defines */
 126 #define PCMCIA_MAX_SOCK 1
 127 #define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
 128
 129 /* VPP/VCC */
 130 #define SET_VCC_VPP(VCC, VPP, SLOT)\
 131         ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
 132
 133 /* MTD CONFIG OPTIONS */
 134 #if defined(CONFIG_MTD_DB1X00_BOOT) && defined(CONFIG_MTD_DB1X00_USER)
 135 #define DB1X00_BOTH_BANKS
 136 #elif defined(CONFIG_MTD_DB1X00_BOOT) && !defined(CONFIG_MTD_DB1X00_USER)
 137 #define DB1X00_BOOT_ONLY
 138 #elif !defined(CONFIG_MTD_DB1X00_BOOT) && defined(CONFIG_MTD_DB1X00_USER)
 139 #define DB1X00_USER_ONLY
 140 #endif
 141
 142 /* SD controller macros */
 143 /*
 144  * Detect card.
 145  */
 146 #define mmc_card_inserted(_n_, _res_) \
 147         do { \
 148                 BCSR * const bcsr = (BCSR *)0xAE000000; \
 149                 unsigned long mmc_wp, board_specific; \
 150                 if ((_n_)) { \
 151                         mmc_wp = BCSR_BOARD_SD1_WP; \
 152                 } else { \
 153                         mmc_wp = BCSR_BOARD_SD0_WP; \
 154                 } \
 155                 board_specific = au_readl((unsigned long)(&bcsr->specific)); \
 156                 if (!(board_specific & mmc_wp)) {/* low means card present */ \
 157                         *(int *)(_res_) = 1; \
 158                 } else { \
 159                         *(int *)(_res_) = 0; \
 160                 } \
 161         } while (0)
 162
 163 /*
 164  * Apply power to card slot(s).
 165  */
 166 #define mmc_power_on(_n_) \
 167         do { \
 168                 BCSR * const bcsr = (BCSR *)0xAE000000; \
 169                 unsigned long mmc_pwr, mmc_wp, board_specific; \
 170                 if ((_n_)) { \
 171                         mmc_pwr = BCSR_BOARD_SD1_PWR; \
 172                         mmc_wp = BCSR_BOARD_SD1_WP; \
 173                 } else { \
 174                         mmc_pwr = BCSR_BOARD_SD0_PWR; \
 175                         mmc_wp = BCSR_BOARD_SD0_WP; \
 176                 } \
 177                 board_specific = au_readl((unsigned long)(&bcsr->specific)); \
 178                 if (!(board_specific & mmc_wp)) {/* low means card present */ \
 179                         board_specific |= mmc_pwr; \
 180                         au_writel(board_specific, (int)(&bcsr->specific)); \
 181                         au_sync(); \
 182                 } \
 183         } while (0)
 184
 185 #endif /* __ASM_DB1X00_H */
 186