include/asm-mips/mach-pb1x00/pb1550.h

   1 /*
   2  * AMD Alchemy Semi PB1550 Referrence Board
   3  * Board Registers defines.
   4  *
   5  * Copyright 2004 Embedded Edge LLC.
   6  *
   7  * ########################################################################
   8  *
   9  *  This program is free software; you can distribute it and/or modify it
  10  *  under the terms of the GNU General Public License (Version 2) as
  11  *  published by the Free Software Foundation.
  12  *
  13  *  This program is distributed in the hope it will be useful, but WITHOUT
  14  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  *  for more details.
  17  *
  18  *  You should have received a copy of the GNU General Public License along
  19  *  with this program; if not, write to the Free Software Foundation, Inc.,
  20  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  21  *
  22  * ########################################################################
  23  *
  24  *
  25  */
  26 #ifndef __ASM_PB1550_H
  27 #define __ASM_PB1550_H
  28
  29 #include <linux/types.h>
  30
  31 #define BCSR_PHYS_ADDR 0xAF000000
  32
  33 typedef volatile struct
  34 {
  35         /*00*/  u16 whoami;
  36                 u16 reserved0;
  37         /*04*/  u16 status;
  38                 u16 reserved1;
  39         /*08*/  u16 switches;
  40                 u16 reserved2;
  41         /*0C*/  u16 resets;
  42                 u16 reserved3;
  43         /*10*/  u16 pcmcia;
  44                 u16 reserved4;
  45         /*14*/  u16 pci;
  46                 u16 reserved5;
  47         /*18*/  u16 leds;
  48                 u16 reserved6;
  49         /*1C*/  u16 system;
  50                 u16 reserved7;
  51
  52 } BCSR;
  53
  54 static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
  55
  56 /*
  57  * Register bit definitions for the BCSRs
  58  */
  59 #define BCSR_WHOAMI_DCID        0x000F
  60 #define BCSR_WHOAMI_CPLD        0x00F0
  61 #define BCSR_WHOAMI_BOARD       0x0F00
  62
  63 #define BCSR_STATUS_PCMCIA0VS   0x0003
  64 #define BCSR_STATUS_PCMCIA1VS   0x000C
  65 #define BCSR_STATUS_PCMCIA0FI   0x0010
  66 #define BCSR_STATUS_PCMCIA1FI   0x0020
  67 #define BCSR_STATUS_SWAPBOOT    0x0040
  68 #define BCSR_STATUS_SRAMWIDTH   0x0080
  69 #define BCSR_STATUS_FLASHBUSY   0x0100
  70 #define BCSR_STATUS_ROMBUSY     0x0200
  71 #define BCSR_STATUS_USBOTGID    0x0800
  72 #define BCSR_STATUS_U0RXD       0x1000
  73 #define BCSR_STATUS_U1RXD       0x2000
  74 #define BCSR_STATUS_U3RXD       0x8000
  75
  76 #define BCSR_SWITCHES_OCTAL     0x00FF
  77 #define BCSR_SWITCHES_DIP_1     0x0080
  78 #define BCSR_SWITCHES_DIP_2     0x0040
  79 #define BCSR_SWITCHES_DIP_3     0x0020
  80 #define BCSR_SWITCHES_DIP_4     0x0010
  81 #define BCSR_SWITCHES_DIP_5     0x0008
  82 #define BCSR_SWITCHES_DIP_6     0x0004
  83 #define BCSR_SWITCHES_DIP_7     0x0002
  84 #define BCSR_SWITCHES_DIP_8     0x0001
  85 #define BCSR_SWITCHES_ROTARY    0x0F00
  86
  87 #define BCSR_RESETS_PHY0        0x0001
  88 #define BCSR_RESETS_PHY1        0x0002
  89 #define BCSR_RESETS_DC          0x0004
  90 #define BCSR_RESETS_WSC         0x2000
  91 #define BCSR_RESETS_SPISEL      0x4000
  92 #define BCSR_RESETS_DMAREQ      0x8000
  93
  94 #define BCSR_PCMCIA_PC0VPP      0x0003
  95 #define BCSR_PCMCIA_PC0VCC      0x000C
  96 #define BCSR_PCMCIA_PC0DRVEN    0x0010
  97 #define BCSR_PCMCIA_PC0RST      0x0080
  98 #define BCSR_PCMCIA_PC1VPP      0x0300
  99 #define BCSR_PCMCIA_PC1VCC      0x0C00
 100 #define BCSR_PCMCIA_PC1DRVEN    0x1000
 101 #define BCSR_PCMCIA_PC1RST      0x8000
 102
 103 #define BCSR_PCI_M66EN          0x0001
 104 #define BCSR_PCI_M33            0x0100
 105 #define BCSR_PCI_EXTERNARB      0x0200
 106 #define BCSR_PCI_GPIO200RST     0x0400
 107 #define BCSR_PCI_CLKOUT         0x0800
 108 #define BCSR_PCI_CFGHOST        0x1000
 109
 110 #define BCSR_LEDS_DECIMALS      0x00FF
 111 #define BCSR_LEDS_LED0          0x0100
 112 #define BCSR_LEDS_LED1          0x0200
 113 #define BCSR_LEDS_LED2          0x0400
 114 #define BCSR_LEDS_LED3          0x0800
 115
 116 #define BCSR_SYSTEM_VDDI        0x001F
 117 #define BCSR_SYSTEM_POWEROFF    0x4000
 118 #define BCSR_SYSTEM_RESET       0x8000
 119
 120 #define PCMCIA_MAX_SOCK 1
 121 #define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
 122
 123 /* VPP/VCC */
 124 #define SET_VCC_VPP(VCC, VPP, SLOT)\
 125         ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
 126
 127 #if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
 128 #define PB1550_BOTH_BANKS
 129 #elif defined(CONFIG_MTD_PB1550_BOOT) && !defined(CONFIG_MTD_PB1550_USER)
 130 #define PB1550_BOOT_ONLY
 131 #elif !defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
 132 #define PB1550_USER_ONLY
 133 #endif
 134
 135 /* Timing values as described in databook, * ns value stripped of
 136  * lower 2 bits.
 137  * These defines are here rather than an SOC1550 generic file because
 138  * the parts chosen on another board may be different and may require
 139  * different timings.
 140  */
 141 #define NAND_T_H                        (18 >> 2)
 142 #define NAND_T_PUL                      (30 >> 2)
 143 #define NAND_T_SU                       (30 >> 2)
 144 #define NAND_T_WH                       (30 >> 2)
 145
 146 /* Bitfield shift amounts */
 147 #define NAND_T_H_SHIFT          0
 148 #define NAND_T_PUL_SHIFT        4
 149 #define NAND_T_SU_SHIFT         8
 150 #define NAND_T_WH_SHIFT         12
 151
 152 #define NAND_TIMING     ((NAND_T_H   & 0xF)     << NAND_T_H_SHIFT)   | \
 153                         ((NAND_T_PUL & 0xF)     << NAND_T_PUL_SHIFT) | \
 154                         ((NAND_T_SU  & 0xF)     << NAND_T_SU_SHIFT)  | \
 155                         ((NAND_T_WH  & 0xF)     << NAND_T_WH_SHIFT)
 156
 157 #endif /* __ASM_PB1550_H */