include/asm-mips/vr41xx/vr41xx.h

   1 /*
   2  * include/asm-mips/vr41xx/vr41xx.h
   3  *
   4  * Include file for NEC VR4100 series.
   5  *
   6  * Copyright (C) 1999 Michael Klar
   7  * Copyright (C) 2001, 2002 Paul Mundt
   8  * Copyright (C) 2002 MontaVista Software, Inc.
   9  * Copyright (C) 2002 TimeSys Corp.
  10  * Copyright (C) 2003-2004 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
  11  *
  12  * This program is free software; you can redistribute it and/or modify it
  13  * under the terms of the GNU General Public License as published by the
  14  * Free Software Foundation; either version 2 of the License, or (at your
  15  * option) any later version.
  16  */
  17 #ifndef __NEC_VR41XX_H
  18 #define __NEC_VR41XX_H
  19
  20 #include <linux/interrupt.h>
  21
  22 /*
  23  * CPU Revision
  24  */
  25 /* VR4122 0x00000c70-0x00000c72 */
  26 #define PRID_VR4122_REV1_0      0x00000c70
  27 #define PRID_VR4122_REV2_0      0x00000c70
  28 #define PRID_VR4122_REV2_1      0x00000c70
  29 #define PRID_VR4122_REV3_0      0x00000c71
  30 #define PRID_VR4122_REV3_1      0x00000c72
  31
  32 /* VR4181A 0x00000c73-0x00000c7f */
  33 #define PRID_VR4181A_REV1_0     0x00000c73
  34 #define PRID_VR4181A_REV1_1     0x00000c74
  35
  36 /* VR4131 0x00000c80-0x00000c83 */
  37 #define PRID_VR4131_REV1_2      0x00000c80
  38 #define PRID_VR4131_REV2_0      0x00000c81
  39 #define PRID_VR4131_REV2_1      0x00000c82
  40 #define PRID_VR4131_REV2_2      0x00000c83
  41
  42 /* VR4133 0x00000c84- */
  43 #define PRID_VR4133             0x00000c84
  44
  45 /*
  46  * Bus Control Uint
  47  */
  48 extern unsigned long vr41xx_get_vtclock_frequency(void);
  49 extern unsigned long vr41xx_get_tclock_frequency(void);
  50
  51 /*
  52  * Clock Mask Unit
  53  */
  54 typedef enum {
  55         PIU_CLOCK,
  56         SIU_CLOCK,
  57         AIU_CLOCK,
  58         KIU_CLOCK,
  59         FIR_CLOCK,
  60         DSIU_CLOCK,
  61         CSI_CLOCK,
  62         PCIU_CLOCK,
  63         HSP_CLOCK,
  64         PCI_CLOCK,
  65         CEU_CLOCK,
  66         ETHER0_CLOCK,
  67         ETHER1_CLOCK
  68 } vr41xx_clock_t;
  69
  70 extern void vr41xx_supply_clock(vr41xx_clock_t clock);
  71 extern void vr41xx_mask_clock(vr41xx_clock_t clock);
  72
  73 /*
  74  * Interrupt Control Unit
  75  */
  76 /* CPU core Interrupt Numbers */
  77 #define MIPS_CPU_IRQ_BASE       0
  78 #define MIPS_CPU_IRQ(x)         (MIPS_CPU_IRQ_BASE + (x))
  79 #define MIPS_SOFTINT0_IRQ       MIPS_CPU_IRQ(0)
  80 #define MIPS_SOFTINT1_IRQ       MIPS_CPU_IRQ(1)
  81 #define INT0_CASCADE_IRQ        MIPS_CPU_IRQ(2)
  82 #define INT1_CASCADE_IRQ        MIPS_CPU_IRQ(3)
  83 #define INT2_CASCADE_IRQ        MIPS_CPU_IRQ(4)
  84 #define INT3_CASCADE_IRQ        MIPS_CPU_IRQ(5)
  85 #define INT4_CASCADE_IRQ        MIPS_CPU_IRQ(6)
  86 #define MIPS_COUNTER_IRQ        MIPS_CPU_IRQ(7)
  87
  88 /* SYINT1 Interrupt Numbers */
  89 #define SYSINT1_IRQ_BASE        8
  90 #define SYSINT1_IRQ(x)          (SYSINT1_IRQ_BASE + (x))
  91 #define BATTRY_IRQ              SYSINT1_IRQ(0)
  92 #define POWER_IRQ               SYSINT1_IRQ(1)
  93 #define RTCLONG1_IRQ            SYSINT1_IRQ(2)
  94 #define ELAPSEDTIME_IRQ         SYSINT1_IRQ(3)
  95 /* RFU */
  96 #define PIU_IRQ                 SYSINT1_IRQ(5)
  97 #define AIU_IRQ                 SYSINT1_IRQ(6)
  98 #define KIU_IRQ                 SYSINT1_IRQ(7)
  99 #define GIUINT_CASCADE_IRQ      SYSINT1_IRQ(8)
 100 #define SIU_IRQ                 SYSINT1_IRQ(9)
 101 #define BUSERR_IRQ              SYSINT1_IRQ(10)
 102 #define SOFTINT_IRQ             SYSINT1_IRQ(11)
 103 #define CLKRUN_IRQ              SYSINT1_IRQ(12)
 104 #define DOZEPIU_IRQ             SYSINT1_IRQ(13)
 105 #define SYSINT1_IRQ_LAST        DOZEPIU_IRQ
 106
 107 /* SYSINT2 Interrupt Numbers */
 108 #define SYSINT2_IRQ_BASE        24
 109 #define SYSINT2_IRQ(x)          (SYSINT2_IRQ_BASE + (x))
 110 #define RTCLONG2_IRQ            SYSINT2_IRQ(0)
 111 #define LED_IRQ                 SYSINT2_IRQ(1)
 112 #define HSP_IRQ                 SYSINT2_IRQ(2)
 113 #define TCLOCK_IRQ              SYSINT2_IRQ(3)
 114 #define FIR_IRQ                 SYSINT2_IRQ(4)
 115 #define CEU_IRQ                 SYSINT2_IRQ(4)  /* same number as FIR_IRQ */
 116 #define DSIU_IRQ                SYSINT2_IRQ(5)
 117 #define PCI_IRQ                 SYSINT2_IRQ(6)
 118 #define SCU_IRQ                 SYSINT2_IRQ(7)
 119 #define CSI_IRQ                 SYSINT2_IRQ(8)
 120 #define BCU_IRQ                 SYSINT2_IRQ(9)
 121 #define ETHERNET_IRQ            SYSINT2_IRQ(10)
 122 #define SYSINT2_IRQ_LAST        ETHERNET_IRQ
 123
 124 /* GIU Interrupt Numbers */
 125 #define GIU_IRQ_BASE            40
 126 #define GIU_IRQ(x)              (GIU_IRQ_BASE + (x))    /* IRQ 40-71 */
 127 #define GIU_IRQ_LAST            GIU_IRQ(31)
 128 #define GIU_IRQ_TO_PIN(x)       ((x) - GIU_IRQ_BASE)    /* Pin 0-31 */
 129
 130 extern int vr41xx_set_intassign(unsigned int irq, unsigned char intassign);
 131 extern int vr41xx_cascade_irq(unsigned int irq, int (*get_irq_number)(int irq));
 132
 133 #define PIUINT_COMMAND          0x0040
 134 #define PIUINT_DATA             0x0020
 135 #define PIUINT_PAGE1            0x0010
 136 #define PIUINT_PAGE0            0x0008
 137 #define PIUINT_DATALOST         0x0004
 138 #define PIUINT_STATUSCHANGE     0x0001
 139
 140 extern void vr41xx_enable_piuint(uint16_t mask);
 141 extern void vr41xx_disable_piuint(uint16_t mask);
 142
 143 #define AIUINT_INPUT_DMAEND     0x0800
 144 #define AIUINT_INPUT_DMAHALT    0x0400
 145 #define AIUINT_INPUT_DATALOST   0x0200
 146 #define AIUINT_INPUT_DATA       0x0100
 147 #define AIUINT_OUTPUT_DMAEND    0x0008
 148 #define AIUINT_OUTPUT_DMAHALT   0x0004
 149 #define AIUINT_OUTPUT_NODATA    0x0002
 150
 151 extern void vr41xx_enable_aiuint(uint16_t mask);
 152 extern void vr41xx_disable_aiuint(uint16_t mask);
 153
 154 #define KIUINT_DATALOST         0x0004
 155 #define KIUINT_DATAREADY        0x0002
 156 #define KIUINT_SCAN             0x0001
 157
 158 extern void vr41xx_enable_kiuint(uint16_t mask);
 159 extern void vr41xx_disable_kiuint(uint16_t mask);
 160
 161 #define DSIUINT_CTS             0x0800
 162 #define DSIUINT_RXERR           0x0400
 163 #define DSIUINT_RX              0x0200
 164 #define DSIUINT_TX              0x0100
 165 #define DSIUINT_ALL             0x0f00
 166
 167 extern void vr41xx_enable_dsiuint(uint16_t mask);
 168 extern void vr41xx_disable_dsiuint(uint16_t mask);
 169
 170 #define FIRINT_UNIT             0x0010
 171 #define FIRINT_RX_DMAEND        0x0008
 172 #define FIRINT_RX_DMAHALT       0x0004
 173 #define FIRINT_TX_DMAEND        0x0002
 174 #define FIRINT_TX_DMAHALT       0x0001
 175
 176 extern void vr41xx_enable_firint(uint16_t mask);
 177 extern void vr41xx_disable_firint(uint16_t mask);
 178
 179 extern void vr41xx_enable_pciint(void);
 180 extern void vr41xx_disable_pciint(void);
 181
 182 extern void vr41xx_enable_scuint(void);
 183 extern void vr41xx_disable_scuint(void);
 184
 185 #define CSIINT_TX_DMAEND        0x0040
 186 #define CSIINT_TX_DMAHALT       0x0020
 187 #define CSIINT_TX_DATA          0x0010
 188 #define CSIINT_TX_FIFOEMPTY     0x0008
 189 #define CSIINT_RX_DMAEND        0x0004
 190 #define CSIINT_RX_DMAHALT       0x0002
 191 #define CSIINT_RX_FIFOEMPTY     0x0001
 192
 193 extern void vr41xx_enable_csiint(uint16_t mask);
 194 extern void vr41xx_disable_csiint(uint16_t mask);
 195
 196 extern void vr41xx_enable_bcuint(void);
 197 extern void vr41xx_disable_bcuint(void);
 198
 199 /*
 200  * Power Management Unit
 201  */
 202
 203 /*
 204  * RTC
 205  */
 206 extern void vr41xx_set_rtclong1_cycle(uint32_t cycles);
 207 extern uint32_t vr41xx_read_rtclong1_counter(void);
 208
 209 extern void vr41xx_set_rtclong2_cycle(uint32_t cycles);
 210 extern uint32_t vr41xx_read_rtclong2_counter(void);
 211
 212 extern void vr41xx_set_tclock_cycle(uint32_t cycles);
 213 extern uint32_t vr41xx_read_tclock_counter(void);
 214
 215 /*
 216  * General-Purpose I/O Unit
 217  */
 218 enum {
 219         TRIGGER_LEVEL,
 220         TRIGGER_EDGE,
 221         TRIGGER_EDGE_FALLING,
 222         TRIGGER_EDGE_RISING
 223 };
 224
 225 enum {
 226         SIGNAL_THROUGH,
 227         SIGNAL_HOLD
 228 };
 229
 230 extern void vr41xx_set_irq_trigger(int pin, int trigger, int hold);
 231
 232 enum {
 233         LEVEL_LOW,
 234         LEVEL_HIGH
 235 };
 236
 237 extern void vr41xx_set_irq_level(int pin, int level);
 238
 239 enum {
 240         PIO_INPUT,
 241         PIO_OUTPUT
 242 };
 243
 244 enum {
 245         DATA_LOW,
 246         DATA_HIGH
 247 };
 248
 249 /*
 250  * Serial Interface Unit
 251  */
 252 extern void vr41xx_siu_init(void);
 253 extern int vr41xx_serial_ports;
 254
 255 /* SIU interfaces */
 256 typedef enum {
 257         SIU_RS232C,
 258         SIU_IRDA
 259 } siu_interface_t;
 260
 261 /* IrDA interfaces */
 262 typedef enum {
 263         IRDA_NONE,
 264         IRDA_SHARP,
 265         IRDA_TEMIC,
 266         IRDA_HP
 267 } irda_module_t;
 268
 269 extern void vr41xx_select_siu_interface(siu_interface_t interface,
 270                                         irda_module_t module);
 271
 272 /*
 273  * Debug Serial Interface Unit
 274  */
 275 extern void vr41xx_dsiu_init(void);
 276
 277 /*
 278  * PCI Control Unit
 279  */
 280 #define PCI_MASTER_ADDRESS_MASK 0x7fffffffU
 281
 282 struct pci_master_address_conversion {
 283         uint32_t bus_base_address;
 284         uint32_t address_mask;
 285         uint32_t pci_base_address;
 286 };
 287
 288 struct pci_target_address_conversion {
 289         uint32_t address_mask;
 290         uint32_t bus_base_address;
 291 };
 292
 293 typedef enum {
 294         CANNOT_LOCK_FROM_DEVICE,
 295         CAN_LOCK_FROM_DEVICE,
 296 } pci_exclusive_access_t;
 297
 298 struct pci_mailbox_address {
 299         uint32_t base_address;
 300 };
 301
 302 struct pci_target_address_window {
 303         uint32_t base_address;
 304 };
 305
 306 typedef enum {
 307         PCI_ARBITRATION_MODE_FAIR,
 308         PCI_ARBITRATION_MODE_ALTERNATE_0,
 309         PCI_ARBITRATION_MODE_ALTERNATE_B,
 310 } pci_arbiter_priority_control_t;
 311
 312 typedef enum {
 313         PCI_TAKE_AWAY_GNT_DISABLE,
 314         PCI_TAKE_AWAY_GNT_ENABLE,
 315 } pci_take_away_gnt_mode_t;
 316
 317 struct pci_controller_unit_setup {
 318         struct pci_master_address_conversion *master_memory1;
 319         struct pci_master_address_conversion *master_memory2;
 320
 321         struct pci_target_address_conversion *target_memory1;
 322         struct pci_target_address_conversion *target_memory2;
 323
 324         struct pci_master_address_conversion *master_io;
 325
 326         pci_exclusive_access_t exclusive_access;
 327
 328         uint32_t pci_clock_max;
 329         uint8_t wait_time_limit_from_irdy_to_trdy;      /* Only VR4122 is supported */
 330
 331         struct pci_mailbox_address *mailbox;
 332         struct pci_target_address_window *target_window1;
 333         struct pci_target_address_window *target_window2;
 334
 335         uint8_t master_latency_timer;
 336         uint8_t retry_limit;
 337
 338         pci_arbiter_priority_control_t arbiter_priority_control;
 339         pci_take_away_gnt_mode_t take_away_gnt_mode;
 340
 341         struct resource *mem_resource;
 342         struct resource *io_resource;
 343 };
 344
 345 extern void vr41xx_pciu_setup(struct pci_controller_unit_setup *setup);
 346
 347 #endif /* __NEC_VR41XX_H */