include/asm-ppc/io.h

   1 #ifdef __KERNEL__
   2 #ifndef _PPC_IO_H
   3 #define _PPC_IO_H
   4
   5 #include <linux/config.h>
   6 #include <linux/types.h>
   7
   8 #include <asm/page.h>
   9 #include <asm/byteorder.h>
  10 #include <asm/mmu.h>
  11
  12 #define SIO_CONFIG_RA   0x398
  13 #define SIO_CONFIG_RD   0x399
  14
  15 #define SLOW_DOWN_IO
  16
  17 #define PMAC_ISA_MEM_BASE       0
  18 #define PMAC_PCI_DRAM_OFFSET    0
  19 #define CHRP_ISA_IO_BASE        0xf8000000
  20 #define CHRP_ISA_MEM_BASE       0xf7000000
  21 #define CHRP_PCI_DRAM_OFFSET    0
  22 #define PREP_ISA_IO_BASE        0x80000000
  23 #define PREP_ISA_MEM_BASE       0xc0000000
  24 #define PREP_PCI_DRAM_OFFSET    0x80000000
  25
  26 #if defined(CONFIG_4xx)
  27 #include <asm/ibm4xx.h>
  28 #elif defined(CONFIG_8xx)
  29 #include <asm/mpc8xx.h>
  30 #elif defined(CONFIG_8260)
  31 #include <asm/mpc8260.h>
  32 #elif defined(CONFIG_85xx)
  33 #include <asm/mpc85xx.h>
  34 #elif defined(CONFIG_APUS)
  35 #define _IO_BASE        0
  36 #define _ISA_MEM_BASE   0
  37 #define PCI_DRAM_OFFSET 0
  38 #else /* Everyone else */
  39 #define _IO_BASE        isa_io_base
  40 #define _ISA_MEM_BASE   isa_mem_base
  41 #define PCI_DRAM_OFFSET pci_dram_offset
  42 #endif /* Platform-dependent I/O */
  43
  44 extern unsigned long isa_io_base;
  45 extern unsigned long isa_mem_base;
  46 extern unsigned long pci_dram_offset;
  47
  48 #define readb(addr) in_8((volatile u8 *)(addr))
  49 #define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
  50 #if defined(CONFIG_APUS)
  51 #define readw(addr) (*(volatile u16 *) (addr))
  52 #define readl(addr) (*(volatile u32 *) (addr))
  53 #define writew(b,addr) ((*(volatile u16 *) (addr)) = (b))
  54 #define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
  55 #else
  56 #define readw(addr) in_le16((volatile u16 *)(addr))
  57 #define readl(addr) in_le32((volatile u32 *)(addr))
  58 #define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
  59 #define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
  60 #endif /* CONFIG_APUS */
  61
  62 #define readb_relaxed(addr) readb(addr)
  63 #define readw_relaxed(addr) readw(addr)
  64 #define readl_relaxed(addr) readl(addr)
  65
  66 #define __raw_readb(addr)       (*(volatile unsigned char *)(addr))
  67 #define __raw_readw(addr)       (*(volatile unsigned short *)(addr))
  68 #define __raw_readl(addr)       (*(volatile unsigned int *)(addr))
  69 #define __raw_writeb(v, addr)   (*(volatile unsigned char *)(addr) = (v))
  70 #define __raw_writew(v, addr)   (*(volatile unsigned short *)(addr) = (v))
  71 #define __raw_writel(v, addr)   (*(volatile unsigned int *)(addr) = (v))
  72
  73 /*
  74  * The insw/outsw/insl/outsl macros don't do byte-swapping.
  75  * They are only used in practice for transferring buffers which
  76  * are arrays of bytes, and byte-swapping is not appropriate in
  77  * that case.  - paulus
  78  */
  79 #define insb(port, buf, ns)     _insb((u8 *)((port)+_IO_BASE), (buf), (ns))
  80 #define outsb(port, buf, ns)    _outsb((u8 *)((port)+_IO_BASE), (buf), (ns))
  81 #define insw(port, buf, ns)     _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
  82 #define outsw(port, buf, ns)    _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
  83 #define insl(port, buf, nl)     _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
  84 #define outsl(port, buf, nl)    _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
  85
  86 /*
  87  * On powermacs, we will get a machine check exception if we
  88  * try to read data from a non-existent I/O port.  Because the
  89  * machine check is an asynchronous exception, it isn't
  90  * well-defined which instruction SRR0 will point to when the
  91  * exception occurs.
  92  * With the sequence below (twi; isync; nop), we have found that
  93  * the machine check occurs on one of the three instructions on
  94  * all PPC implementations tested so far.  The twi and isync are
  95  * needed on the 601 (in fact twi; sync works too), the isync and
  96  * nop are needed on 604[e|r], and any of twi, sync or isync will
  97  * work on 603[e], 750, 74xx.
  98  * The twi creates an explicit data dependency on the returned
  99  * value which seems to be needed to make the 601 wait for the
 100  * load to finish.
 101  */
 102
 103 #define __do_in_asm(name, op)                           \
 104 extern __inline__ unsigned int name(unsigned int port)  \
 105 {                                                       \
 106         unsigned int x;                                 \
 107         __asm__ __volatile__(                           \
 108                         op "    %0,0,%1\n"              \
 109                 "1:     twi     0,%0,0\n"               \
 110                 "2:     isync\n"                        \
 111                 "3:     nop\n"                          \
 112                 "4:\n"                                  \
 113                 ".section .fixup,\"ax\"\n"              \
 114                 "5:     li      %0,-1\n"                \
 115                 "       b       4b\n"                   \
 116                 ".previous\n"                           \
 117                 ".section __ex_table,\"a\"\n"           \
 118                 "       .align  2\n"                    \
 119                 "       .long   1b,5b\n"                \
 120                 "       .long   2b,5b\n"                \
 121                 "       .long   3b,5b\n"                \
 122                 ".previous"                             \
 123                 : "=&r" (x)                             \
 124                 : "r" (port + _IO_BASE));               \
 125         return x;                                       \
 126 }
 127
 128 #define __do_out_asm(name, op)                          \
 129 extern __inline__ void name(unsigned int val, unsigned int port) \
 130 {                                                       \
 131         __asm__ __volatile__(                           \
 132                 op " %0,0,%1\n"                         \
 133                 "1:     sync\n"                         \
 134                 "2:\n"                                  \
 135                 ".section __ex_table,\"a\"\n"           \
 136                 "       .align  2\n"                    \
 137                 "       .long   1b,2b\n"                \
 138                 ".previous"                             \
 139                 : : "r" (val), "r" (port + _IO_BASE));  \
 140 }
 141
 142 __do_out_asm(outb, "stbx")
 143 #ifdef CONFIG_APUS
 144 __do_in_asm(inb, "lbzx")
 145 __do_in_asm(inw, "lhz%U1%X1")
 146 __do_in_asm(inl, "lwz%U1%X1")
 147 __do_out_asm(outl,"stw%U0%X0")
 148 __do_out_asm(outw, "sth%U0%X0")
 149 #elif defined (CONFIG_8260_PCI9)
 150 /* in asm cannot be defined if PCI9 workaround is used */
 151 #define inb(port)               in_8((u8 *)((port)+_IO_BASE))
 152 #define inw(port)               in_le16((u16 *)((port)+_IO_BASE))
 153 #define inl(port)               in_le32((u32 *)((port)+_IO_BASE))
 154 __do_out_asm(outw, "sthbrx")
 155 __do_out_asm(outl, "stwbrx")
 156 #else
 157 __do_in_asm(inb, "lbzx")
 158 __do_in_asm(inw, "lhbrx")
 159 __do_in_asm(inl, "lwbrx")
 160 __do_out_asm(outw, "sthbrx")
 161 __do_out_asm(outl, "stwbrx")
 162
 163 #endif
 164
 165 #define inb_p(port)             inb((port))
 166 #define outb_p(val, port)       outb((val), (port))
 167 #define inw_p(port)             inw((port))
 168 #define outw_p(val, port)       outw((val), (port))
 169 #define inl_p(port)             inl((port))
 170 #define outl_p(val, port)       outl((val), (port))
 171
 172 extern void _insb(volatile u8 *port, void *buf, int ns);
 173 extern void _outsb(volatile u8 *port, const void *buf, int ns);
 174 extern void _insw(volatile u16 *port, void *buf, int ns);
 175 extern void _outsw(volatile u16 *port, const void *buf, int ns);
 176 extern void _insl(volatile u32 *port, void *buf, int nl);
 177 extern void _outsl(volatile u32 *port, const void *buf, int nl);
 178 extern void _insw_ns(volatile u16 *port, void *buf, int ns);
 179 extern void _outsw_ns(volatile u16 *port, const void *buf, int ns);
 180 extern void _insl_ns(volatile u32 *port, void *buf, int nl);
 181 extern void _outsl_ns(volatile u32 *port, const void *buf, int nl);
 182
 183 /*
 184  * The *_ns versions below don't do byte-swapping.
 185  * Neither do the standard versions now, these are just here
 186  * for older code.
 187  */
 188 #define insw_ns(port, buf, ns)  _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
 189 #define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
 190 #define insl_ns(port, buf, nl)  _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
 191 #define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
 192
 193
 194 #define IO_SPACE_LIMIT ~0
 195
 196 #define memset_io(a,b,c)       memset((void *)(a),(b),(c))
 197 #define memcpy_fromio(a,b,c)   memcpy((a),(void *)(b),(c))
 198 #define memcpy_toio(a,b,c)      memcpy((void *)(a),(b),(c))
 199
 200 /*
 201  * Map in an area of physical address space, for accessing
 202  * I/O devices etc.
 203  */
 204 extern void *__ioremap(phys_addr_t address, unsigned long size,
 205                        unsigned long flags);
 206 extern void *ioremap(phys_addr_t address, unsigned long size);
 207 #ifdef CONFIG_44x
 208 extern void *ioremap64(unsigned long long address, unsigned long size);
 209 #endif
 210 #define ioremap_nocache(addr, size)     ioremap((addr), (size))
 211 extern void iounmap(void *addr);
 212 extern unsigned long iopa(unsigned long addr);
 213 extern unsigned long mm_ptov(unsigned long addr) __attribute_const__;
 214 extern void io_block_mapping(unsigned long virt, phys_addr_t phys,
 215                              unsigned int size, int flags);
 216
 217 /*
 218  * The PCI bus is inherently Little-Endian.  The PowerPC is being
 219  * run Big-Endian.  Thus all values which cross the [PCI] barrier
 220  * must be endian-adjusted.  Also, the local DRAM has a different
 221  * address from the PCI point of view, thus buffer addresses also
 222  * have to be modified [mapped] appropriately.
 223  */
 224 extern inline unsigned long virt_to_bus(volatile void * address)
 225 {
 226 #ifndef CONFIG_APUS
 227         if (address == (void *)0)
 228                 return 0;
 229         return (unsigned long)address - KERNELBASE + PCI_DRAM_OFFSET;
 230 #else
 231         return iopa ((unsigned long) address);
 232 #endif
 233 }
 234
 235 extern inline void * bus_to_virt(unsigned long address)
 236 {
 237 #ifndef CONFIG_APUS
 238         if (address == 0)
 239                 return NULL;
 240         return (void *)(address - PCI_DRAM_OFFSET + KERNELBASE);
 241 #else
 242         return (void*) mm_ptov (address);
 243 #endif
 244 }
 245
 246 /*
 247  * Change virtual addresses to physical addresses and vv, for
 248  * addresses in the area where the kernel has the RAM mapped.
 249  */
 250 extern inline unsigned long virt_to_phys(volatile void * address)
 251 {
 252 #ifndef CONFIG_APUS
 253         return (unsigned long) address - KERNELBASE;
 254 #else
 255         return iopa ((unsigned long) address);
 256 #endif
 257 }
 258
 259 extern inline void * phys_to_virt(unsigned long address)
 260 {
 261 #ifndef CONFIG_APUS
 262         return (void *) (address + KERNELBASE);
 263 #else
 264         return (void*) mm_ptov (address);
 265 #endif
 266 }
 267
 268 /*
 269  * Change "struct page" to physical address.
 270  */
 271 #define page_to_phys(page)      (page_to_pfn(page) << PAGE_SHIFT)
 272 #define page_to_bus(page)       (page_to_phys(page) + PCI_DRAM_OFFSET)
 273
 274 /*
 275  * Enforce In-order Execution of I/O:
 276  * Acts as a barrier to ensure all previous I/O accesses have
 277  * completed before any further ones are issued.
 278  */
 279 extern inline void eieio(void)
 280 {
 281         __asm__ __volatile__ ("eieio" : : : "memory");
 282 }
 283
 284 /* Enforce in-order execution of data I/O.
 285  * No distinction between read/write on PPC; use eieio for all three.
 286  */
 287 #define iobarrier_rw() eieio()
 288 #define iobarrier_r()  eieio()
 289 #define iobarrier_w()  eieio()
 290
 291 /*
 292  * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
 293  *
 294  * Read operations have additional twi & isync to make sure the read
 295  * is actually performed (i.e. the data has come back) before we start
 296  * executing any following instructions.
 297  */
 298 extern inline int in_8(volatile unsigned char *addr)
 299 {
 300         int ret;
 301
 302         __asm__ __volatile__(
 303                 "lbz%U1%X1 %0,%1;\n"
 304                 "twi 0,%0,0;\n"
 305                 "isync" : "=r" (ret) : "m" (*addr));
 306         return ret;
 307 }
 308
 309 extern inline void out_8(volatile unsigned char *addr, int val)
 310 {
 311         __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
 312 }
 313
 314 extern inline int in_le16(volatile unsigned short *addr)
 315 {
 316         int ret;
 317
 318         __asm__ __volatile__("lhbrx %0,0,%1;\n"
 319                              "twi 0,%0,0;\n"
 320                              "isync" : "=r" (ret) :
 321                               "r" (addr), "m" (*addr));
 322         return ret;
 323 }
 324
 325 extern inline int in_be16(volatile unsigned short *addr)
 326 {
 327         int ret;
 328
 329         __asm__ __volatile__("lhz%U1%X1 %0,%1;\n"
 330                              "twi 0,%0,0;\n"
 331                              "isync" : "=r" (ret) : "m" (*addr));
 332         return ret;
 333 }
 334
 335 extern inline void out_le16(volatile unsigned short *addr, int val)
 336 {
 337         __asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) :
 338                               "r" (val), "r" (addr));
 339 }
 340
 341 extern inline void out_be16(volatile unsigned short *addr, int val)
 342 {
 343         __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
 344 }
 345
 346 extern inline unsigned in_le32(volatile unsigned *addr)
 347 {
 348         unsigned ret;
 349
 350         __asm__ __volatile__("lwbrx %0,0,%1;\n"
 351                              "twi 0,%0,0;\n"
 352                              "isync" : "=r" (ret) :
 353                              "r" (addr), "m" (*addr));
 354         return ret;
 355 }
 356
 357 extern inline unsigned in_be32(volatile unsigned *addr)
 358 {
 359         unsigned ret;
 360
 361         __asm__ __volatile__("lwz%U1%X1 %0,%1;\n"
 362                              "twi 0,%0,0;\n"
 363                              "isync" : "=r" (ret) : "m" (*addr));
 364         return ret;
 365 }
 366
 367 extern inline void out_le32(volatile unsigned *addr, int val)
 368 {
 369         __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) :
 370                              "r" (val), "r" (addr));
 371 }
 372
 373 extern inline void out_be32(volatile unsigned *addr, int val)
 374 {
 375         __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
 376 }
 377
 378 static inline int check_signature(unsigned long io_addr,
 379         const unsigned char *signature, int length)
 380 {
 381         int retval = 0;
 382         do {
 383                 if (readb(io_addr) != *signature)
 384                         goto out;
 385                 io_addr++;
 386                 signature++;
 387                 length--;
 388         } while (length);
 389         retval = 1;
 390 out:
 391         return retval;
 392 }
 393
 394 /* Make some pcmcia drivers happy */
 395 static inline int isa_check_signature(unsigned long io_addr,
 396         const unsigned char *signature, int length)
 397 {
 398         return 0;
 399 }
 400
 401 /*
 402  * Here comes the ppc implementation of the IOMAP
 403  * interfaces.
 404  */
 405 static inline unsigned int ioread8(void __iomem *addr)
 406 {
 407         return readb(addr);
 408 }
 409
 410 static inline unsigned int ioread16(void __iomem *addr)
 411 {
 412         return readw(addr);
 413 }
 414
 415 static inline unsigned int ioread32(void __iomem *addr)
 416 {
 417         return readl(addr);
 418 }
 419
 420 static inline void iowrite8(u8 val, void __iomem *addr)
 421 {
 422         writeb(val, addr);
 423 }
 424
 425 static inline void iowrite16(u16 val, void __iomem *addr)
 426 {
 427         writew(val, addr);
 428 }
 429
 430 static inline void iowrite32(u32 val, void __iomem *addr)
 431 {
 432         writel(val, addr);
 433 }
 434
 435 static inline void ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
 436 {
 437         _insb((u8 __force *) addr, dst, count);
 438 }
 439
 440 static inline void ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
 441 {
 442         _insw_ns((u16 __force *) addr, dst, count);
 443 }
 444
 445 static inline void ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
 446 {
 447         _insl_ns((u32 __force *) addr, dst, count);
 448 }
 449
 450 static inline void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
 451 {
 452         _outsb((u8 __force *) addr, src, count);
 453 }
 454
 455 static inline void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
 456 {
 457         _outsw_ns((u16 __force *) addr, src, count);
 458 }
 459
 460 static inline void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
 461 {
 462         _outsl_ns((u32 __force *) addr, src, count);
 463 }
 464
 465 /* Create a virtual mapping cookie for an IO port range */
 466 extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
 467 extern void ioport_unmap(void __iomem *);
 468
 469 /* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
 470 struct pci_dev;
 471 extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
 472 extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
 473
 474 #endif /* _PPC_IO_H */
 475
 476 #ifdef CONFIG_8260_PCI9
 477 #include <asm/mpc8260_pci9.h>
 478 #endif
 479
 480 #endif /* __KERNEL__ */