include/asm-ppc/irq.h

   1 #ifdef __KERNEL__
   2 #ifndef _ASM_IRQ_H
   3 #define _ASM_IRQ_H
   4
   5 #include <linux/config.h>
   6 #include <asm/machdep.h>                /* ppc_md */
   7 #include <asm/atomic.h>
   8
   9 extern void disable_irq(unsigned int);
  10 extern void disable_irq_nosync(unsigned int);
  11 extern void enable_irq(unsigned int);
  12
  13 /*
  14  * These constants are used for passing information about interrupt
  15  * signal polarity and level/edge sensing to the low-level PIC chip
  16  * drivers.
  17  */
  18 #define IRQ_SENSE_MASK          0x1
  19 #define IRQ_SENSE_LEVEL         0x1     /* interrupt on active level */
  20 #define IRQ_SENSE_EDGE          0x0     /* interrupt triggered by edge */
  21
  22 #define IRQ_POLARITY_MASK       0x2
  23 #define IRQ_POLARITY_POSITIVE   0x2     /* high level or low->high edge */
  24 #define IRQ_POLARITY_NEGATIVE   0x0     /* low level or high->low edge */
  25
  26 #if defined(CONFIG_40x)
  27 #include <asm/ibm4xx.h>
  28
  29 #ifndef NR_BOARD_IRQS
  30 #define NR_BOARD_IRQS 0
  31 #endif
  32
  33 #ifndef UIC_WIDTH /* Number of interrupts per device */
  34 #define UIC_WIDTH 32
  35 #endif
  36
  37 #ifndef NR_UICS /* number  of UIC devices */
  38 #define NR_UICS 1
  39 #endif
  40
  41 #if defined (CONFIG_403)
  42 /*
  43  * The PowerPC 403 cores' Asynchronous Interrupt Controller (AIC) has
  44  * 32 possible interrupts, a majority of which are not implemented on
  45  * all cores. There are six configurable, external interrupt pins and
  46  * there are eight internal interrupts for the on-chip serial port
  47  * (SPU), DMA controller, and JTAG controller.
  48  *
  49  */
  50
  51 #define NR_AIC_IRQS 32
  52 #define NR_IRQS  (NR_AIC_IRQS + NR_BOARD_IRQS)
  53
  54 #elif !defined (CONFIG_403)
  55
  56 /*
  57  *  The PowerPC 405 cores' Universal Interrupt Controller (UIC) has 32
  58  * possible interrupts as well. There are seven, configurable external
  59  * interrupt pins and there are 17 internal interrupts for the on-chip
  60  * serial port, DMA controller, on-chip Ethernet controller, PCI, etc.
  61  *
  62  */
  63
  64
  65 #define NR_UIC_IRQS UIC_WIDTH
  66 #define NR_IRQS         ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
  67 #endif
  68 static __inline__ int
  69 irq_canonicalize(int irq)
  70 {
  71         return (irq);
  72 }
  73
  74 #elif defined(CONFIG_44x)
  75 #include <asm/ibm44x.h>
  76
  77 #define NR_UIC_IRQS     32
  78 #define NR_IRQS         ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
  79
  80 static __inline__ int
  81 irq_canonicalize(int irq)
  82 {
  83         return (irq);
  84 }
  85
  86 #elif defined(CONFIG_8xx)
  87
  88 /* The MPC8xx cores have 16 possible interrupts.  There are eight
  89  * possible level sensitive interrupts assigned and generated internally
  90  * from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer.
  91  * There are eight external interrupts (IRQs) that can be configured
  92  * as either level or edge sensitive.
  93  *
  94  * On some implementations, there is also the possibility of an 8259
  95  * through the PCI and PCI-ISA bridges.
  96  */
  97 #define NR_SIU_INTS     16
  98
  99 #define NR_IRQS (NR_SIU_INTS + NR_8259_INTS)
 100
 101 /* These values must be zero-based and map 1:1 with the SIU configuration.
 102  * They are used throughout the 8xx I/O subsystem to generate
 103  * interrupt masks, flags, and other control patterns.  This is why the
 104  * current kernel assumption of the 8259 as the base controller is such
 105  * a pain in the butt.
 106  */
 107 #define SIU_IRQ0        (0)     /* Highest priority */
 108 #define SIU_LEVEL0      (1)
 109 #define SIU_IRQ1        (2)
 110 #define SIU_LEVEL1      (3)
 111 #define SIU_IRQ2        (4)
 112 #define SIU_LEVEL2      (5)
 113 #define SIU_IRQ3        (6)
 114 #define SIU_LEVEL3      (7)
 115 #define SIU_IRQ4        (8)
 116 #define SIU_LEVEL4      (9)
 117 #define SIU_IRQ5        (10)
 118 #define SIU_LEVEL5      (11)
 119 #define SIU_IRQ6        (12)
 120 #define SIU_LEVEL6      (13)
 121 #define SIU_IRQ7        (14)
 122 #define SIU_LEVEL7      (15)
 123
 124 /* Now include the board configuration specific associations.
 125 */
 126 #include <asm/mpc8xx.h>
 127
 128 /* The internal interrupts we can configure as we see fit.
 129  * My personal preference is CPM at level 2, which puts it above the
 130  * MBX PCI/ISA/IDE interrupts.
 131  */
 132 #ifndef PIT_INTERRUPT
 133 #define PIT_INTERRUPT           SIU_LEVEL0
 134 #endif
 135 #ifndef CPM_INTERRUPT
 136 #define CPM_INTERRUPT           SIU_LEVEL2
 137 #endif
 138 #ifndef PCMCIA_INTERRUPT
 139 #define PCMCIA_INTERRUPT        SIU_LEVEL6
 140 #endif
 141 #ifndef DEC_INTERRUPT
 142 #define DEC_INTERRUPT           SIU_LEVEL7
 143 #endif
 144
 145 /* Some internal interrupt registers use an 8-bit mask for the interrupt
 146  * level instead of a number.
 147  */
 148 #define mk_int_int_mask(IL) (1 << (7 - (IL/2)))
 149
 150 /* always the same on 8xx -- Cort */
 151 static __inline__ int irq_canonicalize(int irq)
 152 {
 153         return irq;
 154 }
 155
 156 #elif defined(CONFIG_CPM2) && defined(CONFIG_85xx)
 157 /* Now include the board configuration specific associations.
 158 */
 159 #include <asm/mpc85xx.h>
 160
 161 /* The MPC8560 openpic has  32 internal interrupts and 12 external
 162  * interrupts.
 163  *
 164  * We are "flattening" the interrupt vectors of the cascaded CPM
 165  * so that we can uniquely identify any interrupt source with a
 166  * single integer.
 167  */
 168 #define NR_CPM_INTS     64
 169 #define NR_EPIC_INTS    44
 170 #ifndef NR_8259_INTS
 171 #define NR_8259_INTS 0
 172 #endif
 173 #define NUM_8259_INTERRUPTS NR_8259_INTS
 174
 175 #ifndef CPM_IRQ_OFFSET
 176 #define CPM_IRQ_OFFSET  0
 177 #endif
 178
 179 #define NR_IRQS (NR_EPIC_INTS + NR_CPM_INTS + NR_8259_INTS)
 180
 181 /* These values must be zero-based and map 1:1 with the EPIC configuration.
 182  * They are used throughout the 8560 I/O subsystem to generate
 183  * interrupt masks, flags, and other control patterns.  This is why the
 184  * current kernel assumption of the 8259 as the base controller is such
 185  * a pain in the butt.
 186  */
 187
 188 #define SIU_INT_ERROR           ((uint)0x00+CPM_IRQ_OFFSET)
 189 #define SIU_INT_I2C             ((uint)0x01+CPM_IRQ_OFFSET)
 190 #define SIU_INT_SPI             ((uint)0x02+CPM_IRQ_OFFSET)
 191 #define SIU_INT_RISC            ((uint)0x03+CPM_IRQ_OFFSET)
 192 #define SIU_INT_SMC1            ((uint)0x04+CPM_IRQ_OFFSET)
 193 #define SIU_INT_SMC2            ((uint)0x05+CPM_IRQ_OFFSET)
 194 #define SIU_INT_TIMER1          ((uint)0x0c+CPM_IRQ_OFFSET)
 195 #define SIU_INT_TIMER2          ((uint)0x0d+CPM_IRQ_OFFSET)
 196 #define SIU_INT_TIMER3          ((uint)0x0e+CPM_IRQ_OFFSET)
 197 #define SIU_INT_TIMER4          ((uint)0x0f+CPM_IRQ_OFFSET)
 198 #define SIU_INT_FCC1            ((uint)0x20+CPM_IRQ_OFFSET)
 199 #define SIU_INT_FCC2            ((uint)0x21+CPM_IRQ_OFFSET)
 200 #define SIU_INT_FCC3            ((uint)0x22+CPM_IRQ_OFFSET)
 201 #define SIU_INT_MCC1            ((uint)0x24+CPM_IRQ_OFFSET)
 202 #define SIU_INT_MCC2            ((uint)0x25+CPM_IRQ_OFFSET)
 203 #define SIU_INT_SCC1            ((uint)0x28+CPM_IRQ_OFFSET)
 204 #define SIU_INT_SCC2            ((uint)0x29+CPM_IRQ_OFFSET)
 205 #define SIU_INT_SCC3            ((uint)0x2a+CPM_IRQ_OFFSET)
 206 #define SIU_INT_SCC4            ((uint)0x2b+CPM_IRQ_OFFSET)
 207 #define SIU_INT_PC15            ((uint)0x30+CPM_IRQ_OFFSET)
 208 #define SIU_INT_PC14            ((uint)0x31+CPM_IRQ_OFFSET)
 209 #define SIU_INT_PC13            ((uint)0x32+CPM_IRQ_OFFSET)
 210 #define SIU_INT_PC12            ((uint)0x33+CPM_IRQ_OFFSET)
 211 #define SIU_INT_PC11            ((uint)0x34+CPM_IRQ_OFFSET)
 212 #define SIU_INT_PC10            ((uint)0x35+CPM_IRQ_OFFSET)
 213 #define SIU_INT_PC9             ((uint)0x36+CPM_IRQ_OFFSET)
 214 #define SIU_INT_PC8             ((uint)0x37+CPM_IRQ_OFFSET)
 215 #define SIU_INT_PC7             ((uint)0x38+CPM_IRQ_OFFSET)
 216 #define SIU_INT_PC6             ((uint)0x39+CPM_IRQ_OFFSET)
 217 #define SIU_INT_PC5             ((uint)0x3a+CPM_IRQ_OFFSET)
 218 #define SIU_INT_PC4             ((uint)0x3b+CPM_IRQ_OFFSET)
 219 #define SIU_INT_PC3             ((uint)0x3c+CPM_IRQ_OFFSET)
 220 #define SIU_INT_PC2             ((uint)0x3d+CPM_IRQ_OFFSET)
 221 #define SIU_INT_PC1             ((uint)0x3e+CPM_IRQ_OFFSET)
 222 #define SIU_INT_PC0             ((uint)0x3f+CPM_IRQ_OFFSET)
 223
 224 static __inline__ int irq_canonicalize(int irq)
 225 {
 226         return irq;
 227 }
 228
 229 #else /* CONFIG_40x + CONFIG_8xx */
 230 /*
 231  * this is the # irq's for all ppc arch's (pmac/chrp/prep)
 232  * so it is the max of them all
 233  */
 234 #define NR_IRQS                 256
 235
 236 #ifndef CONFIG_8260
 237
 238 #define NUM_8259_INTERRUPTS     16
 239
 240 #else /* CONFIG_8260 */
 241
 242 /* The 8260 has an internal interrupt controller with a maximum of
 243  * 64 IRQs.  We will use NR_IRQs from above since it is large enough.
 244  * Don't be confused by the 8260 documentation where they list an
 245  * "interrupt number" and "interrupt vector".  We are only interested
 246  * in the interrupt vector.  There are "reserved" holes where the
 247  * vector number increases, but the interrupt number in the table does not.
 248  * (Document errata updates have fixed this...make sure you have up to
 249  * date processor documentation -- Dan).
 250  */
 251 #define NR_SIU_INTS     64
 252
 253 #define SIU_INT_ERROR           ((uint)0x00)
 254 #define SIU_INT_I2C             ((uint)0x01)
 255 #define SIU_INT_SPI             ((uint)0x02)
 256 #define SIU_INT_RISC            ((uint)0x03)
 257 #define SIU_INT_SMC1            ((uint)0x04)
 258 #define SIU_INT_SMC2            ((uint)0x05)
 259 #define SIU_INT_IDMA1           ((uint)0x06)
 260 #define SIU_INT_IDMA2           ((uint)0x07)
 261 #define SIU_INT_IDMA3           ((uint)0x08)
 262 #define SIU_INT_IDMA4           ((uint)0x09)
 263 #define SIU_INT_SDMA            ((uint)0x0a)
 264 #define SIU_INT_TIMER1          ((uint)0x0c)
 265 #define SIU_INT_TIMER2          ((uint)0x0d)
 266 #define SIU_INT_TIMER3          ((uint)0x0e)
 267 #define SIU_INT_TIMER4          ((uint)0x0f)
 268 #define SIU_INT_TMCNT           ((uint)0x10)
 269 #define SIU_INT_PIT             ((uint)0x11)
 270 #define SIU_INT_IRQ1            ((uint)0x13)
 271 #define SIU_INT_IRQ2            ((uint)0x14)
 272 #define SIU_INT_IRQ3            ((uint)0x15)
 273 #define SIU_INT_IRQ4            ((uint)0x16)
 274 #define SIU_INT_IRQ5            ((uint)0x17)
 275 #define SIU_INT_IRQ6            ((uint)0x18)
 276 #define SIU_INT_IRQ7            ((uint)0x19)
 277 #define SIU_INT_FCC1            ((uint)0x20)
 278 #define SIU_INT_FCC2            ((uint)0x21)
 279 #define SIU_INT_FCC3            ((uint)0x22)
 280 #define SIU_INT_MCC1            ((uint)0x24)
 281 #define SIU_INT_MCC2            ((uint)0x25)
 282 #define SIU_INT_SCC1            ((uint)0x28)
 283 #define SIU_INT_SCC2            ((uint)0x29)
 284 #define SIU_INT_SCC3            ((uint)0x2a)
 285 #define SIU_INT_SCC4            ((uint)0x2b)
 286 #define SIU_INT_PC15            ((uint)0x30)
 287 #define SIU_INT_PC14            ((uint)0x31)
 288 #define SIU_INT_PC13            ((uint)0x32)
 289 #define SIU_INT_PC12            ((uint)0x33)
 290 #define SIU_INT_PC11            ((uint)0x34)
 291 #define SIU_INT_PC10            ((uint)0x35)
 292 #define SIU_INT_PC9             ((uint)0x36)
 293 #define SIU_INT_PC8             ((uint)0x37)
 294 #define SIU_INT_PC7             ((uint)0x38)
 295 #define SIU_INT_PC6             ((uint)0x39)
 296 #define SIU_INT_PC5             ((uint)0x3a)
 297 #define SIU_INT_PC4             ((uint)0x3b)
 298 #define SIU_INT_PC3             ((uint)0x3c)
 299 #define SIU_INT_PC2             ((uint)0x3d)
 300 #define SIU_INT_PC1             ((uint)0x3e)
 301 #define SIU_INT_PC0             ((uint)0x3f)
 302
 303 #endif /* CONFIG_8260 */
 304
 305 /*
 306  * This gets called from serial.c, which is now used on
 307  * powermacs as well as prep/chrp boxes.
 308  * Prep and chrp both have cascaded 8259 PICs.
 309  */
 310 static __inline__ int irq_canonicalize(int irq)
 311 {
 312         if (ppc_md.irq_canonicalize)
 313                 return ppc_md.irq_canonicalize(irq);
 314         return irq;
 315 }
 316
 317 #endif
 318
 319 #define NR_MASK_WORDS   ((NR_IRQS + 31) / 32)
 320 /* pedantic: these are long because they are used with set_bit --RR */
 321 extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
 322 extern unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
 323 extern atomic_t ppc_n_lost_interrupts;
 324
 325 struct irqaction;
 326 struct pt_regs;
 327 int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
 328
 329 #endif /* _ASM_IRQ_H */
 330 #endif /* __KERNEL__ */