include/asm-ppc64/pci.h

   1 #ifndef __PPC64_PCI_H
   2 #define __PPC64_PCI_H
   3 #ifdef __KERNEL__
   4
   5 /*
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #include <linux/types.h>
  13 #include <linux/slab.h>
  14 #include <linux/string.h>
  15 #include <linux/dma-mapping.h>
  16 #include <asm/scatterlist.h>
  17 #include <asm/io.h>
  18 #include <asm/prom.h>
  19
  20 #define PCIBIOS_MIN_IO          0x1000
  21 #define PCIBIOS_MIN_MEM         0x10000000
  22
  23 #ifdef CONFIG_PPC_ISERIES
  24 #define pcibios_scan_all_fns(a, b)      0
  25 #else
  26 extern int pcibios_scan_all_fns(struct pci_bus *bus, int devfn);
  27 #endif
  28
  29 static inline void pcibios_set_master(struct pci_dev *dev)
  30 {
  31         /* No special bus mastering setup handling */
  32 }
  33
  34 static inline void pcibios_penalize_isa_irq(int irq)
  35 {
  36         /* We don't do dynamic PCI IRQ allocation */
  37 }
  38
  39 struct pci_dev;
  40
  41 #define HAVE_ARCH_PCI_MWI 1
  42 static inline int pcibios_prep_mwi(struct pci_dev *dev)
  43 {
  44         /*
  45          * We would like to avoid touching the cacheline size or MWI bit
  46          * but we cant do that with the current pcibios_prep_mwi
  47          * interface. pSeries firmware sets the cacheline size (which is not
  48          * the cpu cacheline size in all cases) and hardware treats MWI
  49          * the same as memory write. So we dont touch the cacheline size
  50          * here and allow the generic code to set the MWI bit.
  51          */
  52         return 0;
  53 }
  54
  55 extern unsigned int pcibios_assign_all_busses(void);
  56
  57 /*
  58  * PCI DMA operations are abstracted for G5 vs. i/pSeries
  59  */
  60 struct pci_dma_ops {
  61         void *          (*pci_alloc_consistent)(struct pci_dev *hwdev, size_t size,
  62                                         dma_addr_t *dma_handle);
  63         void            (*pci_free_consistent)(struct pci_dev *hwdev, size_t size,
  64                                        void *vaddr, dma_addr_t dma_handle);
  65
  66         dma_addr_t      (*pci_map_single)(struct pci_dev *hwdev, void *ptr,
  67                                           size_t size, enum dma_data_direction direction);
  68         void            (*pci_unmap_single)(struct pci_dev *hwdev, dma_addr_t dma_addr,
  69                                             size_t size, enum dma_data_direction direction);
  70         int             (*pci_map_sg)(struct pci_dev *hwdev, struct scatterlist *sg,
  71                                       int nents, enum dma_data_direction direction);
  72         void            (*pci_unmap_sg)(struct pci_dev *hwdev, struct scatterlist *sg,
  73                                         int nents, enum dma_data_direction direction);
  74         int             (*pci_dma_supported)(struct pci_dev *hwdev, u64 mask);
  75         int             (*pci_dac_dma_supported)(struct pci_dev *hwdev, u64 mask);
  76 };
  77
  78 extern struct pci_dma_ops pci_dma_ops;
  79
  80 static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
  81                                          dma_addr_t *dma_handle)
  82 {
  83         return pci_dma_ops.pci_alloc_consistent(hwdev, size, dma_handle);
  84 }
  85
  86 static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
  87                                        void *vaddr, dma_addr_t dma_handle)
  88 {
  89         pci_dma_ops.pci_free_consistent(hwdev, size, vaddr, dma_handle);
  90 }
  91
  92 static inline dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr,
  93                                         size_t size, int direction)
  94 {
  95         return pci_dma_ops.pci_map_single(hwdev, ptr, size,
  96                         (enum dma_data_direction)direction);
  97 }
  98
  99 static inline void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr,
 100                                     size_t size, int direction)
 101 {
 102         pci_dma_ops.pci_unmap_single(hwdev, dma_addr, size,
 103                         (enum dma_data_direction)direction);
 104 }
 105
 106 static inline int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg,
 107                              int nents, int direction)
 108 {
 109         return pci_dma_ops.pci_map_sg(hwdev, sg, nents,
 110                         (enum dma_data_direction)direction);
 111 }
 112
 113 static inline void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg,
 114                                 int nents, int direction)
 115 {
 116         pci_dma_ops.pci_unmap_sg(hwdev, sg, nents,
 117                         (enum dma_data_direction)direction);
 118 }
 119
 120 static inline void pci_dma_sync_single_for_cpu(struct pci_dev *hwdev,
 121                                                dma_addr_t dma_handle,
 122                                                size_t size, int direction)
 123 {
 124         BUG_ON(direction == PCI_DMA_NONE);
 125         /* nothing to do */
 126 }
 127
 128 static inline void pci_dma_sync_single_for_device(struct pci_dev *hwdev,
 129                                                   dma_addr_t dma_handle,
 130                                                   size_t size, int direction)
 131 {
 132         BUG_ON(direction == PCI_DMA_NONE);
 133         /* nothing to do */
 134 }
 135
 136 static inline void pci_dma_sync_sg_for_cpu(struct pci_dev *hwdev,
 137                                            struct scatterlist *sg,
 138                                            int nelems, int direction)
 139 {
 140         BUG_ON(direction == PCI_DMA_NONE);
 141         /* nothing to do */
 142 }
 143
 144 static inline void pci_dma_sync_sg_for_device(struct pci_dev *hwdev,
 145                                               struct scatterlist *sg,
 146                                               int nelems, int direction)
 147 {
 148         BUG_ON(direction == PCI_DMA_NONE);
 149         /* nothing to do */
 150 }
 151
 152 /* Return whether the given PCI device DMA address mask can
 153  * be supported properly.  For example, if your device can
 154  * only drive the low 24-bits during PCI bus mastering, then
 155  * you would pass 0x00ffffff as the mask to this function.
 156  * We default to supporting only 32 bits DMA unless we have
 157  * an explicit override of this function in pci_dma_ops for
 158  * the platform
 159  */
 160 static inline int pci_dma_supported(struct pci_dev *hwdev, u64 mask)
 161 {
 162         if (pci_dma_ops.pci_dma_supported)
 163                 return pci_dma_ops.pci_dma_supported(hwdev, mask);
 164         return (mask < 0x100000000ull);
 165 }
 166
 167 /* For DAC DMA, we currently don't support it by default, but
 168  * we let the platform override this
 169  */
 170 static inline int pci_dac_dma_supported(struct pci_dev *hwdev,u64 mask)
 171 {
 172         if (pci_dma_ops.pci_dac_dma_supported)
 173                 return pci_dma_ops.pci_dac_dma_supported(hwdev, mask);
 174         return 0;
 175 }
 176
 177 static inline int pci_dma_mapping_error(dma_addr_t dma_addr)
 178 {
 179         return dma_mapping_error(dma_addr);
 180 }
 181
 182 extern int pci_domain_nr(struct pci_bus *bus);
 183
 184 /* Set the name of the bus as it appears in /proc/bus/pci */
 185 extern int pci_name_bus(char *name, struct pci_bus *bus);
 186
 187 struct vm_area_struct;
 188 /* Map a range of PCI memory or I/O space for a device into user space */
 189 int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
 190                         enum pci_mmap_state mmap_state, int write_combine);
 191
 192 /* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */
 193 #define HAVE_PCI_MMAP   1
 194
 195 #define pci_map_page(dev, page, off, size, dir) \
 196                 pci_map_single(dev, (page_address(page) + (off)), size, dir)
 197 #define pci_unmap_page(dev,addr,sz,dir) pci_unmap_single(dev,addr,sz,dir)
 198
 199 /* pci_unmap_{single,page} is not a nop, thus... */
 200 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)       \
 201         dma_addr_t ADDR_NAME;
 202 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME)         \
 203         __u32 LEN_NAME;
 204 #define pci_unmap_addr(PTR, ADDR_NAME)                  \
 205         ((PTR)->ADDR_NAME)
 206 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)         \
 207         (((PTR)->ADDR_NAME) = (VAL))
 208 #define pci_unmap_len(PTR, LEN_NAME)                    \
 209         ((PTR)->LEN_NAME)
 210 #define pci_unmap_len_set(PTR, LEN_NAME, VAL)           \
 211         (((PTR)->LEN_NAME) = (VAL))
 212
 213 /* The PCI address space does equal the physical memory
 214  * address space.  The networking and block device layers use
 215  * this boolean for bounce buffer decisions.
 216  */
 217 #define PCI_DMA_BUS_IS_PHYS     (0)
 218
 219 extern void
 220 pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
 221                         struct resource *res);
 222
 223 extern int
 224 unmap_bus_range(struct pci_bus *bus);
 225
 226 extern int
 227 remap_bus_range(struct pci_bus *bus);
 228
 229 extern void
 230 pcibios_fixup_device_resources(struct pci_dev *dev, struct pci_bus *bus);
 231
 232 extern int pci_read_irq_line(struct pci_dev *dev);
 233
 234 extern void pcibios_add_platform_entries(struct pci_dev *dev);
 235
 236 #endif  /* __KERNEL__ */
 237
 238 #endif /* __PPC64_PCI_H */