drivers/usb/host/ehci-pci.c

   1 /*
   2  * EHCI HCD (Host Controller Driver) PCI Bus Glue.
   3  *
   4  * Copyright (c) 2000-2004 by David Brownell
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License as published by the
   8  * Free Software Foundation; either version 2 of the License, or (at your
   9  * option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14  * for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20
  21 #ifndef CONFIG_PCI
  22 #error "This file is PCI bus glue.  CONFIG_PCI must be defined."
  23 #endif
  24
  25 /*-------------------------------------------------------------------------*/
  26
  27 /* called after powerup, by probe or system-pm "wakeup" */
  28 static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
  29 {
  30         int                     retval;
  31
  32         /* we expect static quirk code to handle the "extended capabilities"
  33          * (currently just BIOS handoff) allowed starting with EHCI 0.96
  34          */
  35
  36         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  37         retval = pci_set_mwi(pdev);
  38         if (!retval)
  39                 ehci_dbg(ehci, "MWI active\n");
  40
  41         return 0;
  42 }
  43
  44 /* called during probe() after chip reset completes */
  45 static int ehci_pci_setup(struct usb_hcd *hcd)
  46 {
  47         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
  48         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
  49         struct pci_dev          *p_smbus;
  50         u8                      rev;
  51         u32                     temp;
  52         int                     retval;
  53
  54         switch (pdev->vendor) {
  55         case PCI_VENDOR_ID_TOSHIBA_2:
  56                 /* celleb's companion chip */
  57                 if (pdev->device == 0x01b5) {
  58 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
  59                         ehci->big_endian_mmio = 1;
  60 #else
  61                         ehci_warn(ehci,
  62                                   "unsupported big endian Toshiba quirk\n");
  63 #endif
  64                 }
  65                 break;
  66         }
  67
  68         ehci->caps = hcd->regs;
  69         ehci->regs = hcd->regs +
  70                 HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
  71
  72         dbg_hcs_params(ehci, "reset");
  73         dbg_hcc_params(ehci, "reset");
  74
  75         /* ehci_init() causes memory for DMA transfers to be
  76          * allocated.  Thus, any vendor-specific workarounds based on
  77          * limiting the type of memory used for DMA transfers must
  78          * happen before ehci_init() is called. */
  79         switch (pdev->vendor) {
  80         case PCI_VENDOR_ID_NVIDIA:
  81                 /* NVidia reports that certain chips don't handle
  82                  * QH, ITD, or SITD addresses above 2GB.  (But TD,
  83                  * data buffer, and periodic schedule are normal.)
  84                  */
  85                 switch (pdev->device) {
  86                 case 0x003c:    /* MCP04 */
  87                 case 0x005b:    /* CK804 */
  88                 case 0x00d8:    /* CK8 */
  89                 case 0x00e8:    /* CK8S */
  90                         if (pci_set_consistent_dma_mask(pdev,
  91                                                 DMA_BIT_MASK(31)) < 0)
  92                                 ehci_warn(ehci, "can't enable NVidia "
  93                                         "workaround for >2GB RAM\n");
  94                         break;
  95                 }
  96                 break;
  97         }
  98
  99         /* cache this readonly data; minimize chip reads */
 100         ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
 101
 102         retval = ehci_halt(ehci);
 103         if (retval)
 104                 return retval;
 105
 106         /* data structure init */
 107         retval = ehci_init(hcd);
 108         if (retval)
 109                 return retval;
 110
 111         switch (pdev->vendor) {
 112         case PCI_VENDOR_ID_NEC:
 113                 ehci->need_io_watchdog = 0;
 114                 break;
 115         case PCI_VENDOR_ID_INTEL:
 116                 ehci->need_io_watchdog = 0;
 117                 ehci->fs_i_thresh = 1;
 118                 if (pdev->device == 0x27cc) {
 119                         ehci->broken_periodic = 1;
 120                         ehci_info(ehci, "using broken periodic workaround\n");
 121                 }
 122                 if (pdev->device == 0x0806 || pdev->device == 0x0811
 123                                 || pdev->device == 0x0829) {
 124                         ehci_info(ehci, "disable lpm for langwell/penwell\n");
 125                         ehci->has_lpm = 0;
 126                 }
 127                 break;
 128         case PCI_VENDOR_ID_TDI:
 129                 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
 130                         hcd->has_tt = 1;
 131                         tdi_reset(ehci);
 132                 }
 133                 break;
 134         case PCI_VENDOR_ID_AMD:
 135                 /* AMD8111 EHCI doesn't work, according to AMD errata */
 136                 if (pdev->device == 0x7463) {
 137                         ehci_info(ehci, "ignoring AMD8111 (errata)\n");
 138                         retval = -EIO;
 139                         goto done;
 140                 }
 141                 break;
 142         case PCI_VENDOR_ID_NVIDIA:
 143                 switch (pdev->device) {
 144                 /* Some NForce2 chips have problems with selective suspend;
 145                  * fixed in newer silicon.
 146                  */
 147                 case 0x0068:
 148                         if (pdev->revision < 0xa4)
 149                                 ehci->no_selective_suspend = 1;
 150                         break;
 151                 }
 152                 break;
 153         case PCI_VENDOR_ID_VIA:
 154                 if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
 155                         u8 tmp;
 156
 157                         /* The VT6212 defaults to a 1 usec EHCI sleep time which
 158                          * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
 159                          * that sleep time use the conventional 10 usec.
 160                          */
 161                         pci_read_config_byte(pdev, 0x4b, &tmp);
 162                         if (tmp & 0x20)
 163                                 break;
 164                         pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
 165                 }
 166                 break;
 167         case PCI_VENDOR_ID_ATI:
 168                 /* SB600 and old version of SB700 have a bug in EHCI controller,
 169                  * which causes usb devices lose response in some cases.
 170                  */
 171                 if ((pdev->device == 0x4386) || (pdev->device == 0x4396)) {
 172                         p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
 173                                                  PCI_DEVICE_ID_ATI_SBX00_SMBUS,
 174                                                  NULL);
 175                         if (!p_smbus)
 176                                 break;
 177                         rev = p_smbus->revision;
 178                         if ((pdev->device == 0x4386) || (rev == 0x3a)
 179                             || (rev == 0x3b)) {
 180                                 u8 tmp;
 181                                 ehci_info(ehci, "applying AMD SB600/SB700 USB "
 182                                         "freeze workaround\n");
 183                                 pci_read_config_byte(pdev, 0x53, &tmp);
 184                                 pci_write_config_byte(pdev, 0x53, tmp | (1<<3));
 185                         }
 186                         pci_dev_put(p_smbus);
 187                 }
 188                 break;
 189         }
 190
 191         /* optional debug port, normally in the first BAR */
 192         temp = pci_find_capability(pdev, 0x0a);
 193         if (temp) {
 194                 pci_read_config_dword(pdev, temp, &temp);
 195                 temp >>= 16;
 196                 if ((temp & (3 << 13)) == (1 << 13)) {
 197                         temp &= 0x1fff;
 198                         ehci->debug = ehci_to_hcd(ehci)->regs + temp;
 199                         temp = ehci_readl(ehci, &ehci->debug->control);
 200                         ehci_info(ehci, "debug port %d%s\n",
 201                                 HCS_DEBUG_PORT(ehci->hcs_params),
 202                                 (temp & DBGP_ENABLED)
 203                                         ? " IN USE"
 204                                         : "");
 205                         if (!(temp & DBGP_ENABLED))
 206                                 ehci->debug = NULL;
 207                 }
 208         }
 209
 210         ehci_reset(ehci);
 211
 212         /* at least the Genesys GL880S needs fixup here */
 213         temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
 214         temp &= 0x0f;
 215         if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
 216                 ehci_dbg(ehci, "bogus port configuration: "
 217                         "cc=%d x pcc=%d < ports=%d\n",
 218                         HCS_N_CC(ehci->hcs_params),
 219                         HCS_N_PCC(ehci->hcs_params),
 220                         HCS_N_PORTS(ehci->hcs_params));
 221
 222                 switch (pdev->vendor) {
 223                 case 0x17a0:            /* GENESYS */
 224                         /* GL880S: should be PORTS=2 */
 225                         temp |= (ehci->hcs_params & ~0xf);
 226                         ehci->hcs_params = temp;
 227                         break;
 228                 case PCI_VENDOR_ID_NVIDIA:
 229                         /* NF4: should be PCC=10 */
 230                         break;
 231                 }
 232         }
 233
 234         /* Serial Bus Release Number is at PCI 0x60 offset */
 235         pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
 236
 237         /* Keep this around for a while just in case some EHCI
 238          * implementation uses legacy PCI PM support.  This test
 239          * can be removed on 17 Dec 2009 if the dev_warn() hasn't
 240          * been triggered by then.
 241          */
 242         if (!device_can_wakeup(&pdev->dev)) {
 243                 u16     port_wake;
 244
 245                 pci_read_config_word(pdev, 0x62, &port_wake);
 246                 if (port_wake & 0x0001) {
 247                         dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
 248                         device_set_wakeup_capable(&pdev->dev, 1);
 249                 }
 250         }
 251
 252 #ifdef  CONFIG_USB_SUSPEND
 253         /* REVISIT: the controller works fine for wakeup iff the root hub
 254          * itself is "globally" suspended, but usbcore currently doesn't
 255          * understand such things.
 256          *
 257          * System suspend currently expects to be able to suspend the entire
 258          * device tree, device-at-a-time.  If we failed selective suspend
 259          * reports, system suspend would fail; so the root hub code must claim
 260          * success.  That's lying to usbcore, and it matters for runtime
 261          * PM scenarios with selective suspend and remote wakeup...
 262          */
 263         if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
 264                 ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
 265 #endif
 266
 267         ehci_port_power(ehci, 1);
 268         retval = ehci_pci_reinit(ehci, pdev);
 269 done:
 270         return retval;
 271 }
 272
 273 /*-------------------------------------------------------------------------*/
 274
 275 #ifdef  CONFIG_PM
 276
 277 /* suspend/resume, section 4.3 */
 278
 279 /* These routines rely on the PCI bus glue
 280  * to handle powerdown and wakeup, and currently also on
 281  * transceivers that don't need any software attention to set up
 282  * the right sort of wakeup.
 283  * Also they depend on separate root hub suspend/resume.
 284  */
 285
 286 static int ehci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 287 {
 288         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
 289         unsigned long           flags;
 290         int                     rc = 0;
 291
 292         if (time_before(jiffies, ehci->next_statechange))
 293                 msleep(10);
 294
 295         /* Root hub was already suspended. Disable irq emission and
 296          * mark HW unaccessible.  The PM and USB cores make sure that
 297          * the root hub is either suspended or stopped.
 298          */
 299         spin_lock_irqsave (&ehci->lock, flags);
 300         ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup);
 301         ehci_writel(ehci, 0, &ehci->regs->intr_enable);
 302         (void)ehci_readl(ehci, &ehci->regs->intr_enable);
 303
 304         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 305         spin_unlock_irqrestore (&ehci->lock, flags);
 306
 307         // could save FLADJ in case of Vaux power loss
 308         // ... we'd only use it to handle clock skew
 309
 310         return rc;
 311 }
 312
 313 static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 314 {
 315         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
 316         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 317
 318         // maybe restore FLADJ
 319
 320         if (time_before(jiffies, ehci->next_statechange))
 321                 msleep(100);
 322
 323         /* Mark hardware accessible again as we are out of D3 state by now */
 324         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 325
 326         /* If CF is still set and we aren't resuming from hibernation
 327          * then we maintained PCI Vaux power.
 328          * Just undo the effect of ehci_pci_suspend().
 329          */
 330         if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF &&
 331                                 !hibernated) {
 332                 int     mask = INTR_MASK;
 333
 334                 ehci_prepare_ports_for_controller_resume(ehci);
 335                 if (!hcd->self.root_hub->do_remote_wakeup)
 336                         mask &= ~STS_PCD;
 337                 ehci_writel(ehci, mask, &ehci->regs->intr_enable);
 338                 ehci_readl(ehci, &ehci->regs->intr_enable);
 339                 return 0;
 340         }
 341
 342         usb_root_hub_lost_power(hcd->self.root_hub);
 343
 344         /* Else reset, to cope with power loss or flush-to-storage
 345          * style "resume" having let BIOS kick in during reboot.
 346          */
 347         (void) ehci_halt(ehci);
 348         (void) ehci_reset(ehci);
 349         (void) ehci_pci_reinit(ehci, pdev);
 350
 351         /* emptying the schedule aborts any urbs */
 352         spin_lock_irq(&ehci->lock);
 353         if (ehci->reclaim)
 354                 end_unlink_async(ehci);
 355         ehci_work(ehci);
 356         spin_unlock_irq(&ehci->lock);
 357
 358         ehci_writel(ehci, ehci->command, &ehci->regs->command);
 359         ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
 360         ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
 361
 362         /* here we "know" root ports should always stay powered */
 363         ehci_port_power(ehci, 1);
 364
 365         hcd->state = HC_STATE_SUSPENDED;
 366         return 0;
 367 }
 368 #endif
 369
 370 static int ehci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
 371 {
 372         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 373         int rc = 0;
 374
 375         if (!udev->parent) /* udev is root hub itself, impossible */
 376                 rc = -1;
 377         /* we only support lpm device connected to root hub yet */
 378         if (ehci->has_lpm && !udev->parent->parent) {
 379                 rc = ehci_lpm_set_da(ehci, udev->devnum, udev->portnum);
 380                 if (!rc)
 381                         rc = ehci_lpm_check(ehci, udev->portnum);
 382         }
 383         return rc;
 384 }
 385
 386 static const struct hc_driver ehci_pci_hc_driver = {
 387         .description =          hcd_name,
 388         .product_desc =         "EHCI Host Controller",
 389         .hcd_priv_size =        sizeof(struct ehci_hcd),
 390
 391         /*
 392          * generic hardware linkage
 393          */
 394         .irq =                  ehci_irq,
 395         .flags =                HCD_MEMORY | HCD_USB2,
 396
 397         /*
 398          * basic lifecycle operations
 399          */
 400         .reset =                ehci_pci_setup,
 401         .start =                ehci_run,
 402 #ifdef  CONFIG_PM
 403         .pci_suspend =          ehci_pci_suspend,
 404         .pci_resume =           ehci_pci_resume,
 405 #endif
 406         .stop =                 ehci_stop,
 407         .shutdown =             ehci_shutdown,
 408
 409         /*
 410          * managing i/o requests and associated device resources
 411          */
 412         .urb_enqueue =          ehci_urb_enqueue,
 413         .urb_dequeue =          ehci_urb_dequeue,
 414         .endpoint_disable =     ehci_endpoint_disable,
 415         .endpoint_reset =       ehci_endpoint_reset,
 416
 417         /*
 418          * scheduling support
 419          */
 420         .get_frame_number =     ehci_get_frame,
 421
 422         /*
 423          * root hub support
 424          */
 425         .hub_status_data =      ehci_hub_status_data,
 426         .hub_control =          ehci_hub_control,
 427         .bus_suspend =          ehci_bus_suspend,
 428         .bus_resume =           ehci_bus_resume,
 429         .relinquish_port =      ehci_relinquish_port,
 430         .port_handed_over =     ehci_port_handed_over,
 431
 432         /*
 433          * call back when device connected and addressed
 434          */
 435         .update_device =        ehci_update_device,
 436
 437         .clear_tt_buffer_complete       = ehci_clear_tt_buffer_complete,
 438 };
 439
 440 /*-------------------------------------------------------------------------*/
 441
 442 /* PCI driver selection metadata; PCI hotplugging uses this */
 443 static const struct pci_device_id pci_ids [] = { {
 444         /* handle any USB 2.0 EHCI controller */
 445         PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
 446         .driver_data =  (unsigned long) &ehci_pci_hc_driver,
 447         },
 448         { /* end: all zeroes */ }
 449 };
 450 MODULE_DEVICE_TABLE(pci, pci_ids);
 451
 452 /* pci driver glue; this is a "new style" PCI driver module */
 453 static struct pci_driver ehci_pci_driver = {
 454         .name =         (char *) hcd_name,
 455         .id_table =     pci_ids,
 456
 457         .probe =        usb_hcd_pci_probe,
 458         .remove =       usb_hcd_pci_remove,
 459         .shutdown =     usb_hcd_pci_shutdown,
 460
 461 #ifdef CONFIG_PM_SLEEP
 462         .driver =       {
 463                 .pm =   &usb_hcd_pci_pm_ops
 464         },
 465 #endif
 466 };