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Linux 2.6.36-rc5
[linux-2.6/get_maintainer.git] / drivers / usb / musb / tusb6010.c
blob3c48e77a0aa2c6c73ec52fcb9832689bf557e5a0
1 /*
2 * TUSB6010 USB 2.0 OTG Dual Role controller
3 *
4 * Copyright (C) 2006 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Notes:
12 * - Driver assumes that interface to external host (main CPU) is
13 * configured for NOR FLASH interface instead of VLYNQ serial
14 * interface.
15 */
16
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/errno.h>
20 #include <linux/init.h>
21 #include <linux/usb.h>
22 #include <linux/irq.h>
23 #include <linux/platform_device.h>
24
25 #include "musb_core.h"
26
27 static void tusb_source_power(struct musb *musb, int is_on);
28
29 #define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf)
30 #define TUSB_REV_MINOR(reg_val) (reg_val & 0xf)
31
32 /*
33 * Checks the revision. We need to use the DMA register as 3.0 does not
34 * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
35 */
36 u8 tusb_get_revision(struct musb *musb)
37 {
38 void __iomem *tbase = musb->ctrl_base;
39 u32 die_id;
40 u8 rev;
41
42 rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
43 if (TUSB_REV_MAJOR(rev) == 3) {
44 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,
45 TUSB_DIDR1_HI));
46 if (die_id >= TUSB_DIDR1_HI_REV_31)
47 rev |= 1;
48 }
49
50 return rev;
51 }
52
53 static int __init tusb_print_revision(struct musb *musb)
54 {
55 void __iomem *tbase = musb->ctrl_base;
56 u8 rev;
57
58 rev = tusb_get_revision(musb);
59
60 pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n",
61 "prcm",
62 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),
63 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),
64 "int",
65 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
66 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
67 "gpio",
68 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),
69 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),
70 "dma",
71 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
72 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
73 "dieid",
74 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),
75 "rev",
76 TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev));
77
78 return tusb_get_revision(musb);
79 }
80
81 #define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \
82 | TUSB_PHY_OTG_CTRL_TESTM0)
83
84 /*
85 * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0.
86 * Disables power detection in PHY for the duration of idle.
87 */
88 static void tusb_wbus_quirk(struct musb *musb, int enabled)
89 {
90 void __iomem *tbase = musb->ctrl_base;
91 static u32 phy_otg_ctrl, phy_otg_ena;
92 u32 tmp;
93
94 if (enabled) {
95 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
96 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
97 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT
98 | phy_otg_ena | WBUS_QUIRK_MASK;
99 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
100 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
101 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
102 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
103 DBG(2, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
104 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
105 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
106 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
107 & TUSB_PHY_OTG_CTRL_TESTM2) {
108 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl;
109 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
110 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
111 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
112 DBG(2, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
113 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
114 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
115 phy_otg_ctrl = 0;
116 phy_otg_ena = 0;
117 }
118 }
119
120 /*
121 * TUSB 6010 may use a parallel bus that doesn't support byte ops;
122 * so both loading and unloading FIFOs need explicit byte counts.
123 */
124
125 static inline void
126 tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len)
127 {
128 u32 val;
129 int i;
130
131 if (len > 4) {
132 for (i = 0; i < (len >> 2); i++) {
133 memcpy(&val, buf, 4);
134 musb_writel(fifo, 0, val);
135 buf += 4;
136 }
137 len %= 4;
138 }
139 if (len > 0) {
140 /* Write the rest 1 - 3 bytes to FIFO */
141 memcpy(&val, buf, len);
142 musb_writel(fifo, 0, val);
143 }
144 }
145
146 static inline void tusb_fifo_read_unaligned(void __iomem *fifo,
147 void __iomem *buf, u16 len)
148 {
149 u32 val;
150 int i;
151
152 if (len > 4) {
153 for (i = 0; i < (len >> 2); i++) {
154 val = musb_readl(fifo, 0);
155 memcpy(buf, &val, 4);
156 buf += 4;
157 }
158 len %= 4;
159 }
160 if (len > 0) {
161 /* Read the rest 1 - 3 bytes from FIFO */
162 val = musb_readl(fifo, 0);
163 memcpy(buf, &val, len);
164 }
165 }
166
167 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
168 {
169 void __iomem *ep_conf = hw_ep->conf;
170 void __iomem *fifo = hw_ep->fifo;
171 u8 epnum = hw_ep->epnum;
172
173 prefetch(buf);
174
175 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
176 'T', epnum, fifo, len, buf);
177
178 if (epnum)
179 musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
180 TUSB_EP_CONFIG_XFR_SIZE(len));
181 else
182 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX |
183 TUSB_EP0_CONFIG_XFR_SIZE(len));
184
185 if (likely((0x01 & (unsigned long) buf) == 0)) {
186
187 /* Best case is 32bit-aligned destination address */
188 if ((0x02 & (unsigned long) buf) == 0) {
189 if (len >= 4) {
190 writesl(fifo, buf, len >> 2);
191 buf += (len & ~0x03);
192 len &= 0x03;
193 }
194 } else {
195 if (len >= 2) {
196 u32 val;
197 int i;
198
199 /* Cannot use writesw, fifo is 32-bit */
200 for (i = 0; i < (len >> 2); i++) {
201 val = (u32)(*(u16 *)buf);
202 buf += 2;
203 val |= (*(u16 *)buf) << 16;
204 buf += 2;
205 musb_writel(fifo, 0, val);
206 }
207 len &= 0x03;
208 }
209 }
210 }
211
212 if (len > 0)
213 tusb_fifo_write_unaligned(fifo, buf, len);
214 }
215
216 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
217 {
218 void __iomem *ep_conf = hw_ep->conf;
219 void __iomem *fifo = hw_ep->fifo;
220 u8 epnum = hw_ep->epnum;
221
222 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
223 'R', epnum, fifo, len, buf);
224
225 if (epnum)
226 musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
227 TUSB_EP_CONFIG_XFR_SIZE(len));
228 else
229 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len));
230
231 if (likely((0x01 & (unsigned long) buf) == 0)) {
232
233 /* Best case is 32bit-aligned destination address */
234 if ((0x02 & (unsigned long) buf) == 0) {
235 if (len >= 4) {
236 readsl(fifo, buf, len >> 2);
237 buf += (len & ~0x03);
238 len &= 0x03;
239 }
240 } else {
241 if (len >= 2) {
242 u32 val;
243 int i;
244
245 /* Cannot use readsw, fifo is 32-bit */
246 for (i = 0; i < (len >> 2); i++) {
247 val = musb_readl(fifo, 0);
248 *(u16 *)buf = (u16)(val & 0xffff);
249 buf += 2;
250 *(u16 *)buf = (u16)(val >> 16);
251 buf += 2;
252 }
253 len &= 0x03;
254 }
255 }
256 }
257
258 if (len > 0)
259 tusb_fifo_read_unaligned(fifo, buf, len);
260 }
261
262 static struct musb *the_musb;
263
264 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
265
266 /* This is used by gadget drivers, and OTG transceiver logic, allowing
267 * at most mA current to be drawn from VBUS during a Default-B session
268 * (that is, while VBUS exceeds 4.4V). In Default-A (including pure host
269 * mode), or low power Default-B sessions, something else supplies power.
270 * Caller must take care of locking.
271 */
272 static int tusb_draw_power(struct otg_transceiver *x, unsigned mA)
273 {
274 struct musb *musb = the_musb;
275 void __iomem *tbase = musb->ctrl_base;
276 u32 reg;
277
278 /*
279 * Keep clock active when enabled. Note that this is not tied to
280 * drawing VBUS, as with OTG mA can be less than musb->min_power.
281 */
282 if (musb->set_clock) {
283 if (mA)
284 musb->set_clock(musb->clock, 1);
285 else
286 musb->set_clock(musb->clock, 0);
287 }
288
289 /* tps65030 seems to consume max 100mA, with maybe 60mA available
290 * (measured on one board) for things other than tps and tusb.
291 *
292 * Boards sharing the CPU clock with CLKIN will need to prevent
293 * certain idle sleep states while the USB link is active.
294 *
295 * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }.
296 * The actual current usage would be very board-specific. For now,
297 * it's simpler to just use an aggregate (also board-specific).
298 */
299 if (x->default_a || mA < (musb->min_power << 1))
300 mA = 0;
301
302 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
303 if (mA) {
304 musb->is_bus_powered = 1;
305 reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN;
306 } else {
307 musb->is_bus_powered = 0;
308 reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
309 }
310 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
311
312 DBG(2, "draw max %d mA VBUS\n", mA);
313 return 0;
314 }
315
316 #else
317 #define tusb_draw_power NULL
318 #endif
319
320 /* workaround for issue 13: change clock during chip idle
321 * (to be fixed in rev3 silicon) ... symptoms include disconnect
322 * or looping suspend/resume cycles
323 */
324 static void tusb_set_clock_source(struct musb *musb, unsigned mode)
325 {
326 void __iomem *tbase = musb->ctrl_base;
327 u32 reg;
328
329 reg = musb_readl(tbase, TUSB_PRCM_CONF);
330 reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3);
331
332 /* 0 = refclk (clkin, XI)
333 * 1 = PHY 60 MHz (internal PLL)
334 * 2 = not supported
335 * 3 = what?
336 */
337 if (mode > 0)
338 reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3);
339
340 musb_writel(tbase, TUSB_PRCM_CONF, reg);
341
342 /* FIXME tusb6010_platform_retime(mode == 0); */
343 }
344
345 /*
346 * Idle TUSB6010 until next wake-up event; NOR access always wakes.
347 * Other code ensures that we idle unless we're connected _and_ the
348 * USB link is not suspended ... and tells us the relevant wakeup
349 * events. SW_EN for voltage is handled separately.
350 */
351 void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
352 {
353 void __iomem *tbase = musb->ctrl_base;
354 u32 reg;
355
356 if ((wakeup_enables & TUSB_PRCM_WBUS)
357 && (tusb_get_revision(musb) == TUSB_REV_30))
358 tusb_wbus_quirk(musb, 1);
359
360 tusb_set_clock_source(musb, 0);
361
362 wakeup_enables |= TUSB_PRCM_WNORCS;
363 musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables);
364
365 /* REVISIT writeup of WID implies that if WID set and ID is grounded,
366 * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared.
367 * Presumably that's mostly to save power, hence WID is immaterial ...
368 */
369
370 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
371 /* issue 4: when driving vbus, use hipower (vbus_det) comparator */
372 if (is_host_active(musb)) {
373 reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
374 reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
375 } else {
376 reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
377 reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
378 }
379 reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
380 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
381
382 DBG(6, "idle, wake on %02x\n", wakeup_enables);
383 }
384
385 /*
386 * Updates cable VBUS status. Caller must take care of locking.
387 */
388 int musb_platform_get_vbus_status(struct musb *musb)
389 {
390 void __iomem *tbase = musb->ctrl_base;
391 u32 otg_stat, prcm_mngmt;
392 int ret = 0;
393
394 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
395 prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);
396
397 /* Temporarily enable VBUS detection if it was disabled for
398 * suspend mode. Unless it's enabled otg_stat and devctl will
399 * not show correct VBUS state.
400 */
401 if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) {
402 u32 tmp = prcm_mngmt;
403 tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
404 musb_writel(tbase, TUSB_PRCM_MNGMT, tmp);
405 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
406 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt);
407 }
408
409 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID)
410 ret = 1;
411
412 return ret;
413 }
414
415 static struct timer_list musb_idle_timer;
416
417 static void musb_do_idle(unsigned long _musb)
418 {
419 struct musb *musb = (void *)_musb;
420 unsigned long flags;
421
422 spin_lock_irqsave(&musb->lock, flags);
423
424 switch (musb->xceiv->state) {
425 case OTG_STATE_A_WAIT_BCON:
426 if ((musb->a_wait_bcon != 0)
427 && (musb->idle_timeout == 0
428 || time_after(jiffies, musb->idle_timeout))) {
429 DBG(4, "Nothing connected %s, turning off VBUS\n",
430 otg_state_string(musb));
431 }
432 /* FALLTHROUGH */
433 case OTG_STATE_A_IDLE:
434 tusb_source_power(musb, 0);
435 default:
436 break;
437 }
438
439 if (!musb->is_active) {
440 u32 wakeups;
441
442 /* wait until khubd handles port change status */
443 if (is_host_active(musb) && (musb->port1_status >> 16))
444 goto done;
445
446 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
447 if (is_peripheral_enabled(musb) && !musb->gadget_driver)
448 wakeups = 0;
449 else {
450 wakeups = TUSB_PRCM_WHOSTDISCON
451 | TUSB_PRCM_WBUS
452 | TUSB_PRCM_WVBUS;
453 if (is_otg_enabled(musb))
454 wakeups |= TUSB_PRCM_WID;
455 }
456 #else
457 wakeups = TUSB_PRCM_WHOSTDISCON | TUSB_PRCM_WBUS;
458 #endif
459 tusb_allow_idle(musb, wakeups);
460 }
461 done:
462 spin_unlock_irqrestore(&musb->lock, flags);
463 }
464
465 /*
466 * Maybe put TUSB6010 into idle mode mode depending on USB link status,
467 * like "disconnected" or "suspended". We'll be woken out of it by
468 * connect, resume, or disconnect.
469 *
470 * Needs to be called as the last function everywhere where there is
471 * register access to TUSB6010 because of NOR flash wake-up.
472 * Caller should own controller spinlock.
473 *
474 * Delay because peripheral enables D+ pullup 3msec after SE0, and
475 * we don't want to treat that full speed J as a wakeup event.
476 * ... peripherals must draw only suspend current after 10 msec.
477 */
478 void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
479 {
480 unsigned long default_timeout = jiffies + msecs_to_jiffies(3);
481 static unsigned long last_timer;
482
483 if (timeout == 0)
484 timeout = default_timeout;
485
486 /* Never idle if active, or when VBUS timeout is not set as host */
487 if (musb->is_active || ((musb->a_wait_bcon == 0)
488 && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
489 DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
490 del_timer(&musb_idle_timer);
491 last_timer = jiffies;
492 return;
493 }
494
495 if (time_after(last_timer, timeout)) {
496 if (!timer_pending(&musb_idle_timer))
497 last_timer = timeout;
498 else {
499 DBG(4, "Longer idle timer already pending, ignoring\n");
500 return;
501 }
502 }
503 last_timer = timeout;
504
505 DBG(4, "%s inactive, for idle timer for %lu ms\n",
506 otg_state_string(musb),
507 (unsigned long)jiffies_to_msecs(timeout - jiffies));
508 mod_timer(&musb_idle_timer, timeout);
509 }
510
511 /* ticks of 60 MHz clock */
512 #define DEVCLOCK 60000000
513 #define OTG_TIMER_MS(msecs) ((msecs) \
514 ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \
515 | TUSB_DEV_OTG_TIMER_ENABLE) \
516 : 0)
517
518 static void tusb_source_power(struct musb *musb, int is_on)
519 {
520 void __iomem *tbase = musb->ctrl_base;
521 u32 conf, prcm, timer;
522 u8 devctl;
523
524 /* HDRC controls CPEN, but beware current surges during device
525 * connect. They can trigger transient overcurrent conditions
526 * that must be ignored.
527 */
528
529 prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);
530 conf = musb_readl(tbase, TUSB_DEV_CONF);
531 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
532
533 if (is_on) {
534 if (musb->set_clock)
535 musb->set_clock(musb->clock, 1);
536 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
537 musb->xceiv->default_a = 1;
538 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
539 devctl |= MUSB_DEVCTL_SESSION;
540
541 conf |= TUSB_DEV_CONF_USB_HOST_MODE;
542 MUSB_HST_MODE(musb);
543 } else {
544 u32 otg_stat;
545
546 timer = 0;
547
548 /* If ID pin is grounded, we want to be a_idle */
549 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
550 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) {
551 switch (musb->xceiv->state) {
552 case OTG_STATE_A_WAIT_VRISE:
553 case OTG_STATE_A_WAIT_BCON:
554 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
555 break;
556 case OTG_STATE_A_WAIT_VFALL:
557 musb->xceiv->state = OTG_STATE_A_IDLE;
558 break;
559 default:
560 musb->xceiv->state = OTG_STATE_A_IDLE;
561 }
562 musb->is_active = 0;
563 musb->xceiv->default_a = 1;
564 MUSB_HST_MODE(musb);
565 } else {
566 musb->is_active = 0;
567 musb->xceiv->default_a = 0;
568 musb->xceiv->state = OTG_STATE_B_IDLE;
569 MUSB_DEV_MODE(musb);
570 }
571
572 devctl &= ~MUSB_DEVCTL_SESSION;
573 conf &= ~TUSB_DEV_CONF_USB_HOST_MODE;
574 if (musb->set_clock)
575 musb->set_clock(musb->clock, 0);
576 }
577 prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
578
579 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm);
580 musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer);
581 musb_writel(tbase, TUSB_DEV_CONF, conf);
582 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
583
584 DBG(1, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
585 otg_state_string(musb),
586 musb_readb(musb->mregs, MUSB_DEVCTL),
587 musb_readl(tbase, TUSB_DEV_OTG_STAT),
588 conf, prcm);
589 }
590
591 /*
592 * Sets the mode to OTG, peripheral or host by changing the ID detection.
593 * Caller must take care of locking.
594 *
595 * Note that if a mini-A cable is plugged in the ID line will stay down as
596 * the weak ID pull-up is not able to pull the ID up.
597 *
598 * REVISIT: It would be possible to add support for changing between host
599 * and peripheral modes in non-OTG configurations by reconfiguring hardware
600 * and then setting musb->board_mode. For now, only support OTG mode.
601 */
602 int musb_platform_set_mode(struct musb *musb, u8 musb_mode)
603 {
604 void __iomem *tbase = musb->ctrl_base;
605 u32 otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf;
606
607 if (musb->board_mode != MUSB_OTG) {
608 ERR("Changing mode currently only supported in OTG mode\n");
609 return -EINVAL;
610 }
611
612 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
613 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
614 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
615 dev_conf = musb_readl(tbase, TUSB_DEV_CONF);
616
617 switch (musb_mode) {
618
619 #ifdef CONFIG_USB_MUSB_HDRC_HCD
620 case MUSB_HOST: /* Disable PHY ID detect, ground ID */
621 phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
622 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
623 dev_conf |= TUSB_DEV_CONF_ID_SEL;
624 dev_conf &= ~TUSB_DEV_CONF_SOFT_ID;
625 break;
626 #endif
627
628 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
629 case MUSB_PERIPHERAL: /* Disable PHY ID detect, keep ID pull-up on */
630 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
631 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
632 dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
633 break;
634 #endif
635
636 #ifdef CONFIG_USB_MUSB_OTG
637 case MUSB_OTG: /* Use PHY ID detection */
638 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
639 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
640 dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
641 break;
642 #endif
643
644 default:
645 DBG(2, "Trying to set mode %i\n", musb_mode);
646 return -EINVAL;
647 }
648
649 musb_writel(tbase, TUSB_PHY_OTG_CTRL,
650 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl);
651 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE,
652 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena);
653 musb_writel(tbase, TUSB_DEV_CONF, dev_conf);
654
655 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
656 if ((musb_mode == MUSB_PERIPHERAL) &&
657 !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS))
658 INFO("Cannot be peripheral with mini-A cable "
659 "otg_stat: %08x\n", otg_stat);
660
661 return 0;
662 }
663
664 static inline unsigned long
665 tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
666 {
667 u32 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
668 unsigned long idle_timeout = 0;
669
670 /* ID pin */
671 if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) {
672 int default_a;
673
674 if (is_otg_enabled(musb))
675 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
676 else
677 default_a = is_host_enabled(musb);
678 DBG(2, "Default-%c\n", default_a ? 'A' : 'B');
679 musb->xceiv->default_a = default_a;
680 tusb_source_power(musb, default_a);
681
682 /* Don't allow idling immediately */
683 if (default_a)
684 idle_timeout = jiffies + (HZ * 3);
685 }
686
687 /* VBUS state change */
688 if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) {
689
690 /* B-dev state machine: no vbus ~= disconnect */
691 if ((is_otg_enabled(musb) && !musb->xceiv->default_a)
692 || !is_host_enabled(musb)) {
693 #ifdef CONFIG_USB_MUSB_HDRC_HCD
694 /* ? musb_root_disconnect(musb); */
695 musb->port1_status &=
696 ~(USB_PORT_STAT_CONNECTION
697 | USB_PORT_STAT_ENABLE
698 | USB_PORT_STAT_LOW_SPEED
699 | USB_PORT_STAT_HIGH_SPEED
700 | USB_PORT_STAT_TEST
701 );
702 #endif
703
704 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
705 DBG(1, "Forcing disconnect (no interrupt)\n");
706 if (musb->xceiv->state != OTG_STATE_B_IDLE) {
707 /* INTR_DISCONNECT can hide... */
708 musb->xceiv->state = OTG_STATE_B_IDLE;
709 musb->int_usb |= MUSB_INTR_DISCONNECT;
710 }
711 musb->is_active = 0;
712 }
713 DBG(2, "vbus change, %s, otg %03x\n",
714 otg_state_string(musb), otg_stat);
715 idle_timeout = jiffies + (1 * HZ);
716 schedule_work(&musb->irq_work);
717
718 } else /* A-dev state machine */ {
719 DBG(2, "vbus change, %s, otg %03x\n",
720 otg_state_string(musb), otg_stat);
721
722 switch (musb->xceiv->state) {
723 case OTG_STATE_A_IDLE:
724 DBG(2, "Got SRP, turning on VBUS\n");
725 musb_set_vbus(musb, 1);
726
727 /* CONNECT can wake if a_wait_bcon is set */
728 if (musb->a_wait_bcon != 0)
729 musb->is_active = 0;
730 else
731 musb->is_active = 1;
732
733 /*
734 * OPT FS A TD.4.6 needs few seconds for
735 * A_WAIT_VRISE
736 */
737 idle_timeout = jiffies + (2 * HZ);
738
739 break;
740 case OTG_STATE_A_WAIT_VRISE:
741 /* ignore; A-session-valid < VBUS_VALID/2,
742 * we monitor this with the timer
743 */
744 break;
745 case OTG_STATE_A_WAIT_VFALL:
746 /* REVISIT this irq triggers during short
747 * spikes caused by enumeration ...
748 */
749 if (musb->vbuserr_retry) {
750 musb->vbuserr_retry--;
751 tusb_source_power(musb, 1);
752 } else {
753 musb->vbuserr_retry
754 = VBUSERR_RETRY_COUNT;
755 tusb_source_power(musb, 0);
756 }
757 break;
758 default:
759 break;
760 }
761 }
762 }
763
764 /* OTG timer expiration */
765 if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
766 u8 devctl;
767
768 DBG(4, "%s timer, %03x\n", otg_state_string(musb), otg_stat);
769
770 switch (musb->xceiv->state) {
771 case OTG_STATE_A_WAIT_VRISE:
772 /* VBUS has probably been valid for a while now,
773 * but may well have bounced out of range a bit
774 */
775 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
776 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
777 if ((devctl & MUSB_DEVCTL_VBUS)
778 != MUSB_DEVCTL_VBUS) {
779 DBG(2, "devctl %02x\n", devctl);
780 break;
781 }
782 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
783 musb->is_active = 0;
784 idle_timeout = jiffies
785 + msecs_to_jiffies(musb->a_wait_bcon);
786 } else {
787 /* REVISIT report overcurrent to hub? */
788 ERR("vbus too slow, devctl %02x\n", devctl);
789 tusb_source_power(musb, 0);
790 }
791 break;
792 case OTG_STATE_A_WAIT_BCON:
793 if (musb->a_wait_bcon != 0)
794 idle_timeout = jiffies
795 + msecs_to_jiffies(musb->a_wait_bcon);
796 break;
797 case OTG_STATE_A_SUSPEND:
798 break;
799 case OTG_STATE_B_WAIT_ACON:
800 break;
801 default:
802 break;
803 }
804 }
805 schedule_work(&musb->irq_work);
806
807 return idle_timeout;
808 }
809
810 static irqreturn_t tusb_interrupt(int irq, void *__hci)
811 {
812 struct musb *musb = __hci;
813 void __iomem *tbase = musb->ctrl_base;
814 unsigned long flags, idle_timeout = 0;
815 u32 int_mask, int_src;
816
817 spin_lock_irqsave(&musb->lock, flags);
818
819 /* Mask all interrupts to allow using both edge and level GPIO irq */
820 int_mask = musb_readl(tbase, TUSB_INT_MASK);
821 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
822
823 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
824 DBG(3, "TUSB IRQ %08x\n", int_src);
825
826 musb->int_usb = (u8) int_src;
827
828 /* Acknowledge wake-up source interrupts */
829 if (int_src & TUSB_INT_SRC_DEV_WAKEUP) {
830 u32 reg;
831 u32 i;
832
833 if (tusb_get_revision(musb) == TUSB_REV_30)
834 tusb_wbus_quirk(musb, 0);
835
836 /* there are issues re-locking the PLL on wakeup ... */
837
838 /* work around issue 8 */
839 for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) {
840 musb_writel(tbase, TUSB_SCRATCH_PAD, 0);
841 musb_writel(tbase, TUSB_SCRATCH_PAD, i);
842 reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
843 if (reg == i)
844 break;
845 DBG(6, "TUSB NOR not ready\n");
846 }
847
848 /* work around issue 13 (2nd half) */
849 tusb_set_clock_source(musb, 1);
850
851 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);
852 musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg);
853 if (reg & ~TUSB_PRCM_WNORCS) {
854 musb->is_active = 1;
855 schedule_work(&musb->irq_work);
856 }
857 DBG(3, "wake %sactive %02x\n",
858 musb->is_active ? "" : "in", reg);
859
860 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
861 }
862
863 if (int_src & TUSB_INT_SRC_USB_IP_CONN)
864 del_timer(&musb_idle_timer);
865
866 /* OTG state change reports (annoyingly) not issued by Mentor core */
867 if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG
868 | TUSB_INT_SRC_OTG_TIMEOUT
869 | TUSB_INT_SRC_ID_STATUS_CHNG))
870 idle_timeout = tusb_otg_ints(musb, int_src, tbase);
871
872 /* TX dma callback must be handled here, RX dma callback is
873 * handled in tusb_omap_dma_cb.
874 */
875 if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) {
876 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
877 u32 real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK);
878
879 DBG(3, "DMA IRQ %08x\n", dma_src);
880 real_dma_src = ~real_dma_src & dma_src;
881 if (tusb_dma_omap() && real_dma_src) {
882 int tx_source = (real_dma_src & 0xffff);
883 int i;
884
885 for (i = 1; i <= 15; i++) {
886 if (tx_source & (1 << i)) {
887 DBG(3, "completing ep%i %s\n", i, "tx");
888 musb_dma_completion(musb, i, 1);
889 }
890 }
891 }
892 musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src);
893 }
894
895 /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */
896 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) {
897 u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);
898
899 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src);
900 musb->int_rx = (((musb_src >> 16) & 0xffff) << 1);
901 musb->int_tx = (musb_src & 0xffff);
902 } else {
903 musb->int_rx = 0;
904 musb->int_tx = 0;
905 }
906
907 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff))
908 musb_interrupt(musb);
909
910 /* Acknowledge TUSB interrupts. Clear only non-reserved bits */
911 musb_writel(tbase, TUSB_INT_SRC_CLEAR,
912 int_src & ~TUSB_INT_MASK_RESERVED_BITS);
913
914 musb_platform_try_idle(musb, idle_timeout);
915
916 musb_writel(tbase, TUSB_INT_MASK, int_mask);
917 spin_unlock_irqrestore(&musb->lock, flags);
918
919 return IRQ_HANDLED;
920 }
921
922 static int dma_off;
923
924 /*
925 * Enables TUSB6010. Caller must take care of locking.
926 * REVISIT:
927 * - Check what is unnecessary in MGC_HdrcStart()
928 */
929 void musb_platform_enable(struct musb *musb)
930 {
931 void __iomem *tbase = musb->ctrl_base;
932
933 /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF.
934 * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */
935 musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF);
936
937 /* Setup TUSB interrupt, disable DMA and GPIO interrupts */
938 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0);
939 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
940 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
941
942 /* Clear all subsystem interrups */
943 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff);
944 musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff);
945 musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff);
946
947 /* Acknowledge pending interrupt(s) */
948 musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS);
949
950 /* Only 0 clock cycles for minimum interrupt de-assertion time and
951 * interrupt polarity active low seems to work reliably here */
952 musb_writel(tbase, TUSB_INT_CTRL_CONF,
953 TUSB_INT_CTRL_CONF_INT_RELCYC(0));
954
955 set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW);
956
957 /* maybe force into the Default-A OTG state machine */
958 if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)
959 & TUSB_DEV_OTG_STAT_ID_STATUS))
960 musb_writel(tbase, TUSB_INT_SRC_SET,
961 TUSB_INT_SRC_ID_STATUS_CHNG);
962
963 if (is_dma_capable() && dma_off)
964 printk(KERN_WARNING "%s %s: dma not reactivated\n",
965 __FILE__, __func__);
966 else
967 dma_off = 1;
968 }
969
970 /*
971 * Disables TUSB6010. Caller must take care of locking.
972 */
973 void musb_platform_disable(struct musb *musb)
974 {
975 void __iomem *tbase = musb->ctrl_base;
976
977 /* FIXME stop DMA, IRQs, timers, ... */
978
979 /* disable all IRQs */
980 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
981 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff);
982 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
983 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
984
985 del_timer(&musb_idle_timer);
986
987 if (is_dma_capable() && !dma_off) {
988 printk(KERN_WARNING "%s %s: dma still active\n",
989 __FILE__, __func__);
990 dma_off = 1;
991 }
992 }
993
994 /*
995 * Sets up TUSB6010 CPU interface specific signals and registers
996 * Note: Settings optimized for OMAP24xx
997 */
998 static void __init tusb_setup_cpu_interface(struct musb *musb)
999 {
1000 void __iomem *tbase = musb->ctrl_base;
1001
1002 /*
1003 * Disable GPIO[5:0] pullups (used as output DMA requests)
1004 * Don't disable GPIO[7:6] as they are needed for wake-up.
1005 */
1006 musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F);
1007
1008 /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */
1009 musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF);
1010
1011 /* Turn GPIO[5:0] to DMAREQ[5:0] signals */
1012 musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f));
1013
1014 /* Burst size 16x16 bits, all six DMA requests enabled, DMA request
1015 * de-assertion time 2 system clocks p 62 */
1016 musb_writel(tbase, TUSB_DMA_REQ_CONF,
1017 TUSB_DMA_REQ_CONF_BURST_SIZE(2) |
1018 TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) |
1019 TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
1020
1021 /* Set 0 wait count for synchronous burst access */
1022 musb_writel(tbase, TUSB_WAIT_COUNT, 1);
1023 }
1024
1025 static int __init tusb_start(struct musb *musb)
1026 {
1027 void __iomem *tbase = musb->ctrl_base;
1028 int ret = 0;
1029 unsigned long flags;
1030 u32 reg;
1031
1032 if (musb->board_set_power)
1033 ret = musb->board_set_power(1);
1034 if (ret != 0) {
1035 printk(KERN_ERR "tusb: Cannot enable TUSB6010\n");
1036 return ret;
1037 }
1038
1039 spin_lock_irqsave(&musb->lock, flags);
1040
1041 if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=
1042 TUSB_PROD_TEST_RESET_VAL) {
1043 printk(KERN_ERR "tusb: Unable to detect TUSB6010\n");
1044 goto err;
1045 }
1046
1047 ret = tusb_print_revision(musb);
1048 if (ret < 2) {
1049 printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n",
1050 ret);
1051 goto err;
1052 }
1053
1054 /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when
1055 * NOR FLASH interface is used */
1056 musb_writel(tbase, TUSB_VLYNQ_CTRL, 8);
1057
1058 /* Select PHY free running 60MHz as a system clock */
1059 tusb_set_clock_source(musb, 1);
1060
1061 /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for
1062 * power saving, enable VBus detect and session end comparators,
1063 * enable IDpullup, enable VBus charging */
1064 musb_writel(tbase, TUSB_PRCM_MNGMT,
1065 TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) |
1066 TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN |
1067 TUSB_PRCM_MNGMT_OTG_SESS_END_EN |
1068 TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN |
1069 TUSB_PRCM_MNGMT_OTG_ID_PULLUP);
1070 tusb_setup_cpu_interface(musb);
1071
1072 /* simplify: always sense/pullup ID pins, as if in OTG mode */
1073 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
1074 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1075 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg);
1076
1077 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
1078 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1079 musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg);
1080
1081 spin_unlock_irqrestore(&musb->lock, flags);
1082
1083 return 0;
1084
1085 err:
1086 spin_unlock_irqrestore(&musb->lock, flags);
1087
1088 if (musb->board_set_power)
1089 musb->board_set_power(0);
1090
1091 return -ENODEV;
1092 }
1093
1094 int __init musb_platform_init(struct musb *musb, void *board_data)
1095 {
1096 struct platform_device *pdev;
1097 struct resource *mem;
1098 void __iomem *sync = NULL;
1099 int ret;
1100
1101 usb_nop_xceiv_register();
1102 musb->xceiv = otg_get_transceiver();
1103 if (!musb->xceiv)
1104 return -ENODEV;
1105
1106 pdev = to_platform_device(musb->controller);
1107
1108 /* dma address for async dma */
1109 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1110 musb->async = mem->start;
1111
1112 /* dma address for sync dma */
1113 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1114 if (!mem) {
1115 pr_debug("no sync dma resource?\n");
1116 ret = -ENODEV;
1117 goto done;
1118 }
1119 musb->sync = mem->start;
1120
1121 sync = ioremap(mem->start, resource_size(mem));
1122 if (!sync) {
1123 pr_debug("ioremap for sync failed\n");
1124 ret = -ENOMEM;
1125 goto done;
1126 }
1127 musb->sync_va = sync;
1128
1129 /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400,
1130 * FIFOs at 0x600, TUSB at 0x800
1131 */
1132 musb->mregs += TUSB_BASE_OFFSET;
1133
1134 ret = tusb_start(musb);
1135 if (ret) {
1136 printk(KERN_ERR "Could not start tusb6010 (%d)\n",
1137 ret);
1138 goto done;
1139 }
1140 musb->isr = tusb_interrupt;
1141
1142 if (is_host_enabled(musb))
1143 musb->board_set_vbus = tusb_source_power;
1144 if (is_peripheral_enabled(musb)) {
1145 musb->xceiv->set_power = tusb_draw_power;
1146 the_musb = musb;
1147 }
1148
1149 setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
1150
1151 done:
1152 if (ret < 0) {
1153 if (sync)
1154 iounmap(sync);
1155 usb_nop_xceiv_unregister();
1156 }
1157 return ret;
1158 }
1159
1160 int musb_platform_exit(struct musb *musb)
1161 {
1162 del_timer_sync(&musb_idle_timer);
1163 the_musb = NULL;
1164
1165 if (musb->board_set_power)
1166 musb->board_set_power(0);
1167
1168 iounmap(musb->sync_va);
1169 usb_nop_xceiv_unregister();
1170 return 0;
1171 }
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