drivers/net/cxgb3/t3_cpl.h

   1 /*
   2  * Copyright (c) 2004-2007 Chelsio, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #ifndef T3_CPL_H
  33 #define T3_CPL_H
  34
  35 #if !defined(__LITTLE_ENDIAN_BITFIELD) && !defined(__BIG_ENDIAN_BITFIELD)
  36 # include <asm/byteorder.h>
  37 #endif
  38
  39 enum CPL_opcode {
  40         CPL_PASS_OPEN_REQ = 0x1,
  41         CPL_PASS_ACCEPT_RPL = 0x2,
  42         CPL_ACT_OPEN_REQ = 0x3,
  43         CPL_SET_TCB = 0x4,
  44         CPL_SET_TCB_FIELD = 0x5,
  45         CPL_GET_TCB = 0x6,
  46         CPL_PCMD = 0x7,
  47         CPL_CLOSE_CON_REQ = 0x8,
  48         CPL_CLOSE_LISTSRV_REQ = 0x9,
  49         CPL_ABORT_REQ = 0xA,
  50         CPL_ABORT_RPL = 0xB,
  51         CPL_TX_DATA = 0xC,
  52         CPL_RX_DATA_ACK = 0xD,
  53         CPL_TX_PKT = 0xE,
  54         CPL_RTE_DELETE_REQ = 0xF,
  55         CPL_RTE_WRITE_REQ = 0x10,
  56         CPL_RTE_READ_REQ = 0x11,
  57         CPL_L2T_WRITE_REQ = 0x12,
  58         CPL_L2T_READ_REQ = 0x13,
  59         CPL_SMT_WRITE_REQ = 0x14,
  60         CPL_SMT_READ_REQ = 0x15,
  61         CPL_TX_PKT_LSO = 0x16,
  62         CPL_PCMD_READ = 0x17,
  63         CPL_BARRIER = 0x18,
  64         CPL_TID_RELEASE = 0x1A,
  65
  66         CPL_CLOSE_LISTSRV_RPL = 0x20,
  67         CPL_ERROR = 0x21,
  68         CPL_GET_TCB_RPL = 0x22,
  69         CPL_L2T_WRITE_RPL = 0x23,
  70         CPL_PCMD_READ_RPL = 0x24,
  71         CPL_PCMD_RPL = 0x25,
  72         CPL_PEER_CLOSE = 0x26,
  73         CPL_RTE_DELETE_RPL = 0x27,
  74         CPL_RTE_WRITE_RPL = 0x28,
  75         CPL_RX_DDP_COMPLETE = 0x29,
  76         CPL_RX_PHYS_ADDR = 0x2A,
  77         CPL_RX_PKT = 0x2B,
  78         CPL_RX_URG_NOTIFY = 0x2C,
  79         CPL_SET_TCB_RPL = 0x2D,
  80         CPL_SMT_WRITE_RPL = 0x2E,
  81         CPL_TX_DATA_ACK = 0x2F,
  82
  83         CPL_ABORT_REQ_RSS = 0x30,
  84         CPL_ABORT_RPL_RSS = 0x31,
  85         CPL_CLOSE_CON_RPL = 0x32,
  86         CPL_ISCSI_HDR = 0x33,
  87         CPL_L2T_READ_RPL = 0x34,
  88         CPL_RDMA_CQE = 0x35,
  89         CPL_RDMA_CQE_READ_RSP = 0x36,
  90         CPL_RDMA_CQE_ERR = 0x37,
  91         CPL_RTE_READ_RPL = 0x38,
  92         CPL_RX_DATA = 0x39,
  93
  94         CPL_ACT_OPEN_RPL = 0x40,
  95         CPL_PASS_OPEN_RPL = 0x41,
  96         CPL_RX_DATA_DDP = 0x42,
  97         CPL_SMT_READ_RPL = 0x43,
  98
  99         CPL_ACT_ESTABLISH = 0x50,
 100         CPL_PASS_ESTABLISH = 0x51,
 101
 102         CPL_PASS_ACCEPT_REQ = 0x70,
 103
 104         CPL_ASYNC_NOTIF = 0x80, /* fake opcode for async notifications */
 105
 106         CPL_TX_DMA_ACK = 0xA0,
 107         CPL_RDMA_READ_REQ = 0xA1,
 108         CPL_RDMA_TERMINATE = 0xA2,
 109         CPL_TRACE_PKT = 0xA3,
 110         CPL_RDMA_EC_STATUS = 0xA5,
 111
 112         NUM_CPL_CMDS            /* must be last and previous entries must be sorted */
 113 };
 114
 115 enum CPL_error {
 116         CPL_ERR_NONE = 0,
 117         CPL_ERR_TCAM_PARITY = 1,
 118         CPL_ERR_TCAM_FULL = 3,
 119         CPL_ERR_CONN_RESET = 20,
 120         CPL_ERR_CONN_EXIST = 22,
 121         CPL_ERR_ARP_MISS = 23,
 122         CPL_ERR_BAD_SYN = 24,
 123         CPL_ERR_CONN_TIMEDOUT = 30,
 124         CPL_ERR_XMIT_TIMEDOUT = 31,
 125         CPL_ERR_PERSIST_TIMEDOUT = 32,
 126         CPL_ERR_FINWAIT2_TIMEDOUT = 33,
 127         CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
 128         CPL_ERR_RTX_NEG_ADVICE = 35,
 129         CPL_ERR_PERSIST_NEG_ADVICE = 36,
 130         CPL_ERR_ABORT_FAILED = 42,
 131         CPL_ERR_GENERAL = 99
 132 };
 133
 134 enum {
 135         CPL_CONN_POLICY_AUTO = 0,
 136         CPL_CONN_POLICY_ASK = 1,
 137         CPL_CONN_POLICY_DENY = 3
 138 };
 139
 140 enum {
 141         ULP_MODE_NONE = 0,
 142         ULP_MODE_ISCSI = 2,
 143         ULP_MODE_RDMA = 4,
 144         ULP_MODE_TCPDDP = 5
 145 };
 146
 147 enum {
 148         ULP_CRC_HEADER = 1 << 0,
 149         ULP_CRC_DATA = 1 << 1
 150 };
 151
 152 enum {
 153         CPL_PASS_OPEN_ACCEPT,
 154         CPL_PASS_OPEN_REJECT
 155 };
 156
 157 enum {
 158         CPL_ABORT_SEND_RST = 0,
 159         CPL_ABORT_NO_RST,
 160         CPL_ABORT_POST_CLOSE_REQ = 2
 161 };
 162
 163 enum {                          /* TX_PKT_LSO ethernet types */
 164         CPL_ETH_II,
 165         CPL_ETH_II_VLAN,
 166         CPL_ETH_802_3,
 167         CPL_ETH_802_3_VLAN
 168 };
 169
 170 enum {                          /* TCP congestion control algorithms */
 171         CONG_ALG_RENO,
 172         CONG_ALG_TAHOE,
 173         CONG_ALG_NEWRENO,
 174         CONG_ALG_HIGHSPEED
 175 };
 176
 177 union opcode_tid {
 178         __be32 opcode_tid;
 179         __u8 opcode;
 180 };
 181
 182 #define S_OPCODE 24
 183 #define V_OPCODE(x) ((x) << S_OPCODE)
 184 #define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF)
 185 #define G_TID(x)    ((x) & 0xFFFFFF)
 186
 187 /* tid is assumed to be 24-bits */
 188 #define MK_OPCODE_TID(opcode, tid) (V_OPCODE(opcode) | (tid))
 189
 190 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
 191
 192 /* extract the TID from a CPL command */
 193 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd))))
 194
 195 struct tcp_options {
 196         __be16 mss;
 197         __u8 wsf;
 198 #if defined(__LITTLE_ENDIAN_BITFIELD)
 199          __u8:5;
 200         __u8 ecn:1;
 201         __u8 sack:1;
 202         __u8 tstamp:1;
 203 #else
 204         __u8 tstamp:1;
 205         __u8 sack:1;
 206         __u8 ecn:1;
 207          __u8:5;
 208 #endif
 209 };
 210
 211 struct rss_header {
 212         __u8 opcode;
 213 #if defined(__LITTLE_ENDIAN_BITFIELD)
 214         __u8 cpu_idx:6;
 215         __u8 hash_type:2;
 216 #else
 217         __u8 hash_type:2;
 218         __u8 cpu_idx:6;
 219 #endif
 220         __be16 cq_idx;
 221         __be32 rss_hash_val;
 222 };
 223
 224 #ifndef CHELSIO_FW
 225 struct work_request_hdr {
 226         __be32 wr_hi;
 227         __be32 wr_lo;
 228 };
 229
 230 /* wr_hi fields */
 231 #define S_WR_SGE_CREDITS    0
 232 #define M_WR_SGE_CREDITS    0xFF
 233 #define V_WR_SGE_CREDITS(x) ((x) << S_WR_SGE_CREDITS)
 234 #define G_WR_SGE_CREDITS(x) (((x) >> S_WR_SGE_CREDITS) & M_WR_SGE_CREDITS)
 235
 236 #define S_WR_SGLSFLT    8
 237 #define M_WR_SGLSFLT    0xFF
 238 #define V_WR_SGLSFLT(x) ((x) << S_WR_SGLSFLT)
 239 #define G_WR_SGLSFLT(x) (((x) >> S_WR_SGLSFLT) & M_WR_SGLSFLT)
 240
 241 #define S_WR_BCNTLFLT    16
 242 #define M_WR_BCNTLFLT    0xF
 243 #define V_WR_BCNTLFLT(x) ((x) << S_WR_BCNTLFLT)
 244 #define G_WR_BCNTLFLT(x) (((x) >> S_WR_BCNTLFLT) & M_WR_BCNTLFLT)
 245
 246 #define S_WR_DATATYPE    20
 247 #define V_WR_DATATYPE(x) ((x) << S_WR_DATATYPE)
 248 #define F_WR_DATATYPE    V_WR_DATATYPE(1U)
 249
 250 #define S_WR_COMPL    21
 251 #define V_WR_COMPL(x) ((x) << S_WR_COMPL)
 252 #define F_WR_COMPL    V_WR_COMPL(1U)
 253
 254 #define S_WR_EOP    22
 255 #define V_WR_EOP(x) ((x) << S_WR_EOP)
 256 #define F_WR_EOP    V_WR_EOP(1U)
 257
 258 #define S_WR_SOP    23
 259 #define V_WR_SOP(x) ((x) << S_WR_SOP)
 260 #define F_WR_SOP    V_WR_SOP(1U)
 261
 262 #define S_WR_OP    24
 263 #define M_WR_OP    0xFF
 264 #define V_WR_OP(x) ((x) << S_WR_OP)
 265 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP)
 266
 267 /* wr_lo fields */
 268 #define S_WR_LEN    0
 269 #define M_WR_LEN    0xFF
 270 #define V_WR_LEN(x) ((x) << S_WR_LEN)
 271 #define G_WR_LEN(x) (((x) >> S_WR_LEN) & M_WR_LEN)
 272
 273 #define S_WR_TID    8
 274 #define M_WR_TID    0xFFFFF
 275 #define V_WR_TID(x) ((x) << S_WR_TID)
 276 #define G_WR_TID(x) (((x) >> S_WR_TID) & M_WR_TID)
 277
 278 #define S_WR_CR_FLUSH    30
 279 #define V_WR_CR_FLUSH(x) ((x) << S_WR_CR_FLUSH)
 280 #define F_WR_CR_FLUSH    V_WR_CR_FLUSH(1U)
 281
 282 #define S_WR_GEN    31
 283 #define V_WR_GEN(x) ((x) << S_WR_GEN)
 284 #define F_WR_GEN    V_WR_GEN(1U)
 285
 286 # define WR_HDR struct work_request_hdr wr
 287 # define RSS_HDR
 288 #else
 289 # define WR_HDR
 290 # define RSS_HDR struct rss_header rss_hdr;
 291 #endif
 292
 293 /* option 0 lower-half fields */
 294 #define S_CPL_STATUS    0
 295 #define M_CPL_STATUS    0xFF
 296 #define V_CPL_STATUS(x) ((x) << S_CPL_STATUS)
 297 #define G_CPL_STATUS(x) (((x) >> S_CPL_STATUS) & M_CPL_STATUS)
 298
 299 #define S_INJECT_TIMER    6
 300 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER)
 301 #define F_INJECT_TIMER    V_INJECT_TIMER(1U)
 302
 303 #define S_NO_OFFLOAD    7
 304 #define V_NO_OFFLOAD(x) ((x) << S_NO_OFFLOAD)
 305 #define F_NO_OFFLOAD    V_NO_OFFLOAD(1U)
 306
 307 #define S_ULP_MODE    8
 308 #define M_ULP_MODE    0xF
 309 #define V_ULP_MODE(x) ((x) << S_ULP_MODE)
 310 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE)
 311
 312 #define S_RCV_BUFSIZ    12
 313 #define M_RCV_BUFSIZ    0x3FFF
 314 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ)
 315 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ)
 316
 317 #define S_TOS    26
 318 #define M_TOS    0x3F
 319 #define V_TOS(x) ((x) << S_TOS)
 320 #define G_TOS(x) (((x) >> S_TOS) & M_TOS)
 321
 322 /* option 0 upper-half fields */
 323 #define S_DELACK    0
 324 #define V_DELACK(x) ((x) << S_DELACK)
 325 #define F_DELACK    V_DELACK(1U)
 326
 327 #define S_NO_CONG    1
 328 #define V_NO_CONG(x) ((x) << S_NO_CONG)
 329 #define F_NO_CONG    V_NO_CONG(1U)
 330
 331 #define S_SRC_MAC_SEL    2
 332 #define M_SRC_MAC_SEL    0x3
 333 #define V_SRC_MAC_SEL(x) ((x) << S_SRC_MAC_SEL)
 334 #define G_SRC_MAC_SEL(x) (((x) >> S_SRC_MAC_SEL) & M_SRC_MAC_SEL)
 335
 336 #define S_L2T_IDX    4
 337 #define M_L2T_IDX    0x7FF
 338 #define V_L2T_IDX(x) ((x) << S_L2T_IDX)
 339 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX)
 340
 341 #define S_TX_CHANNEL    15
 342 #define V_TX_CHANNEL(x) ((x) << S_TX_CHANNEL)
 343 #define F_TX_CHANNEL    V_TX_CHANNEL(1U)
 344
 345 #define S_TCAM_BYPASS    16
 346 #define V_TCAM_BYPASS(x) ((x) << S_TCAM_BYPASS)
 347 #define F_TCAM_BYPASS    V_TCAM_BYPASS(1U)
 348
 349 #define S_NAGLE    17
 350 #define V_NAGLE(x) ((x) << S_NAGLE)
 351 #define F_NAGLE    V_NAGLE(1U)
 352
 353 #define S_WND_SCALE    18
 354 #define M_WND_SCALE    0xF
 355 #define V_WND_SCALE(x) ((x) << S_WND_SCALE)
 356 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE)
 357
 358 #define S_KEEP_ALIVE    22
 359 #define V_KEEP_ALIVE(x) ((x) << S_KEEP_ALIVE)
 360 #define F_KEEP_ALIVE    V_KEEP_ALIVE(1U)
 361
 362 #define S_MAX_RETRANS    23
 363 #define M_MAX_RETRANS    0xF
 364 #define V_MAX_RETRANS(x) ((x) << S_MAX_RETRANS)
 365 #define G_MAX_RETRANS(x) (((x) >> S_MAX_RETRANS) & M_MAX_RETRANS)
 366
 367 #define S_MAX_RETRANS_OVERRIDE    27
 368 #define V_MAX_RETRANS_OVERRIDE(x) ((x) << S_MAX_RETRANS_OVERRIDE)
 369 #define F_MAX_RETRANS_OVERRIDE    V_MAX_RETRANS_OVERRIDE(1U)
 370
 371 #define S_MSS_IDX    28
 372 #define M_MSS_IDX    0xF
 373 #define V_MSS_IDX(x) ((x) << S_MSS_IDX)
 374 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX)
 375
 376 /* option 1 fields */
 377 #define S_RSS_ENABLE    0
 378 #define V_RSS_ENABLE(x) ((x) << S_RSS_ENABLE)
 379 #define F_RSS_ENABLE    V_RSS_ENABLE(1U)
 380
 381 #define S_RSS_MASK_LEN    1
 382 #define M_RSS_MASK_LEN    0x7
 383 #define V_RSS_MASK_LEN(x) ((x) << S_RSS_MASK_LEN)
 384 #define G_RSS_MASK_LEN(x) (((x) >> S_RSS_MASK_LEN) & M_RSS_MASK_LEN)
 385
 386 #define S_CPU_IDX    4
 387 #define M_CPU_IDX    0x3F
 388 #define V_CPU_IDX(x) ((x) << S_CPU_IDX)
 389 #define G_CPU_IDX(x) (((x) >> S_CPU_IDX) & M_CPU_IDX)
 390
 391 #define S_MAC_MATCH_VALID    18
 392 #define V_MAC_MATCH_VALID(x) ((x) << S_MAC_MATCH_VALID)
 393 #define F_MAC_MATCH_VALID    V_MAC_MATCH_VALID(1U)
 394
 395 #define S_CONN_POLICY    19
 396 #define M_CONN_POLICY    0x3
 397 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY)
 398 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY)
 399
 400 #define S_SYN_DEFENSE    21
 401 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE)
 402 #define F_SYN_DEFENSE    V_SYN_DEFENSE(1U)
 403
 404 #define S_VLAN_PRI    22
 405 #define M_VLAN_PRI    0x3
 406 #define V_VLAN_PRI(x) ((x) << S_VLAN_PRI)
 407 #define G_VLAN_PRI(x) (((x) >> S_VLAN_PRI) & M_VLAN_PRI)
 408
 409 #define S_VLAN_PRI_VALID    24
 410 #define V_VLAN_PRI_VALID(x) ((x) << S_VLAN_PRI_VALID)
 411 #define F_VLAN_PRI_VALID    V_VLAN_PRI_VALID(1U)
 412
 413 #define S_PKT_TYPE    25
 414 #define M_PKT_TYPE    0x3
 415 #define V_PKT_TYPE(x) ((x) << S_PKT_TYPE)
 416 #define G_PKT_TYPE(x) (((x) >> S_PKT_TYPE) & M_PKT_TYPE)
 417
 418 #define S_MAC_MATCH    27
 419 #define M_MAC_MATCH    0x1F
 420 #define V_MAC_MATCH(x) ((x) << S_MAC_MATCH)
 421 #define G_MAC_MATCH(x) (((x) >> S_MAC_MATCH) & M_MAC_MATCH)
 422
 423 /* option 2 fields */
 424 #define S_CPU_INDEX    0
 425 #define M_CPU_INDEX    0x7F
 426 #define V_CPU_INDEX(x) ((x) << S_CPU_INDEX)
 427 #define G_CPU_INDEX(x) (((x) >> S_CPU_INDEX) & M_CPU_INDEX)
 428
 429 #define S_CPU_INDEX_VALID    7
 430 #define V_CPU_INDEX_VALID(x) ((x) << S_CPU_INDEX_VALID)
 431 #define F_CPU_INDEX_VALID    V_CPU_INDEX_VALID(1U)
 432
 433 #define S_RX_COALESCE    8
 434 #define M_RX_COALESCE    0x3
 435 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE)
 436 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE)
 437
 438 #define S_RX_COALESCE_VALID    10
 439 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID)
 440 #define F_RX_COALESCE_VALID    V_RX_COALESCE_VALID(1U)
 441
 442 #define S_CONG_CONTROL_FLAVOR    11
 443 #define M_CONG_CONTROL_FLAVOR    0x3
 444 #define V_CONG_CONTROL_FLAVOR(x) ((x) << S_CONG_CONTROL_FLAVOR)
 445 #define G_CONG_CONTROL_FLAVOR(x) (((x) >> S_CONG_CONTROL_FLAVOR) & M_CONG_CONTROL_FLAVOR)
 446
 447 #define S_PACING_FLAVOR    13
 448 #define M_PACING_FLAVOR    0x3
 449 #define V_PACING_FLAVOR(x) ((x) << S_PACING_FLAVOR)
 450 #define G_PACING_FLAVOR(x) (((x) >> S_PACING_FLAVOR) & M_PACING_FLAVOR)
 451
 452 #define S_FLAVORS_VALID    15
 453 #define V_FLAVORS_VALID(x) ((x) << S_FLAVORS_VALID)
 454 #define F_FLAVORS_VALID    V_FLAVORS_VALID(1U)
 455
 456 #define S_RX_FC_DISABLE    16
 457 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE)
 458 #define F_RX_FC_DISABLE    V_RX_FC_DISABLE(1U)
 459
 460 #define S_RX_FC_VALID    17
 461 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID)
 462 #define F_RX_FC_VALID    V_RX_FC_VALID(1U)
 463
 464 struct cpl_pass_open_req {
 465         WR_HDR;
 466         union opcode_tid ot;
 467         __be16 local_port;
 468         __be16 peer_port;
 469         __be32 local_ip;
 470         __be32 peer_ip;
 471         __be32 opt0h;
 472         __be32 opt0l;
 473         __be32 peer_netmask;
 474         __be32 opt1;
 475 };
 476
 477 struct cpl_pass_open_rpl {
 478         RSS_HDR union opcode_tid ot;
 479         __be16 local_port;
 480         __be16 peer_port;
 481         __be32 local_ip;
 482         __be32 peer_ip;
 483         __u8 resvd[7];
 484         __u8 status;
 485 };
 486
 487 struct cpl_pass_establish {
 488         RSS_HDR union opcode_tid ot;
 489         __be16 local_port;
 490         __be16 peer_port;
 491         __be32 local_ip;
 492         __be32 peer_ip;
 493         __be32 tos_tid;
 494         __be16 l2t_idx;
 495         __be16 tcp_opt;
 496         __be32 snd_isn;
 497         __be32 rcv_isn;
 498 };
 499
 500 /* cpl_pass_establish.tos_tid fields */
 501 #define S_PASS_OPEN_TID    0
 502 #define M_PASS_OPEN_TID    0xFFFFFF
 503 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID)
 504 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID)
 505
 506 #define S_PASS_OPEN_TOS    24
 507 #define M_PASS_OPEN_TOS    0xFF
 508 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS)
 509 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS)
 510
 511 /* cpl_pass_establish.l2t_idx fields */
 512 #define S_L2T_IDX16    5
 513 #define M_L2T_IDX16    0x7FF
 514 #define V_L2T_IDX16(x) ((x) << S_L2T_IDX16)
 515 #define G_L2T_IDX16(x) (((x) >> S_L2T_IDX16) & M_L2T_IDX16)
 516
 517 /* cpl_pass_establish.tcp_opt fields (also applies act_open_establish) */
 518 #define G_TCPOPT_WSCALE_OK(x)  (((x) >> 5) & 1)
 519 #define G_TCPOPT_SACK(x)       (((x) >> 6) & 1)
 520 #define G_TCPOPT_TSTAMP(x)     (((x) >> 7) & 1)
 521 #define G_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf)
 522 #define G_TCPOPT_MSS(x)        (((x) >> 12) & 0xf)
 523
 524 struct cpl_pass_accept_req {
 525         RSS_HDR union opcode_tid ot;
 526         __be16 local_port;
 527         __be16 peer_port;
 528         __be32 local_ip;
 529         __be32 peer_ip;
 530         __be32 tos_tid;
 531         struct tcp_options tcp_options;
 532         __u8 dst_mac[6];
 533         __be16 vlan_tag;
 534         __u8 src_mac[6];
 535 #if defined(__LITTLE_ENDIAN_BITFIELD)
 536          __u8:3;
 537         __u8 addr_idx:3;
 538         __u8 port_idx:1;
 539         __u8 exact_match:1;
 540 #else
 541         __u8 exact_match:1;
 542         __u8 port_idx:1;
 543         __u8 addr_idx:3;
 544          __u8:3;
 545 #endif
 546         __u8 rsvd;
 547         __be32 rcv_isn;
 548         __be32 rsvd2;
 549 };
 550
 551 struct cpl_pass_accept_rpl {
 552         WR_HDR;
 553         union opcode_tid ot;
 554         __be32 opt2;
 555         __be32 rsvd;
 556         __be32 peer_ip;
 557         __be32 opt0h;
 558         __be32 opt0l_status;
 559 };
 560
 561 struct cpl_act_open_req {
 562         WR_HDR;
 563         union opcode_tid ot;
 564         __be16 local_port;
 565         __be16 peer_port;
 566         __be32 local_ip;
 567         __be32 peer_ip;
 568         __be32 opt0h;
 569         __be32 opt0l;
 570         __be32 params;
 571         __be32 opt2;
 572 };
 573
 574 /* cpl_act_open_req.params fields */
 575 #define S_AOPEN_VLAN_PRI    9
 576 #define M_AOPEN_VLAN_PRI    0x3
 577 #define V_AOPEN_VLAN_PRI(x) ((x) << S_AOPEN_VLAN_PRI)
 578 #define G_AOPEN_VLAN_PRI(x) (((x) >> S_AOPEN_VLAN_PRI) & M_AOPEN_VLAN_PRI)
 579
 580 #define S_AOPEN_VLAN_PRI_VALID    11
 581 #define V_AOPEN_VLAN_PRI_VALID(x) ((x) << S_AOPEN_VLAN_PRI_VALID)
 582 #define F_AOPEN_VLAN_PRI_VALID    V_AOPEN_VLAN_PRI_VALID(1U)
 583
 584 #define S_AOPEN_PKT_TYPE    12
 585 #define M_AOPEN_PKT_TYPE    0x3
 586 #define V_AOPEN_PKT_TYPE(x) ((x) << S_AOPEN_PKT_TYPE)
 587 #define G_AOPEN_PKT_TYPE(x) (((x) >> S_AOPEN_PKT_TYPE) & M_AOPEN_PKT_TYPE)
 588
 589 #define S_AOPEN_MAC_MATCH    14
 590 #define M_AOPEN_MAC_MATCH    0x1F
 591 #define V_AOPEN_MAC_MATCH(x) ((x) << S_AOPEN_MAC_MATCH)
 592 #define G_AOPEN_MAC_MATCH(x) (((x) >> S_AOPEN_MAC_MATCH) & M_AOPEN_MAC_MATCH)
 593
 594 #define S_AOPEN_MAC_MATCH_VALID    19
 595 #define V_AOPEN_MAC_MATCH_VALID(x) ((x) << S_AOPEN_MAC_MATCH_VALID)
 596 #define F_AOPEN_MAC_MATCH_VALID    V_AOPEN_MAC_MATCH_VALID(1U)
 597
 598 #define S_AOPEN_IFF_VLAN    20
 599 #define M_AOPEN_IFF_VLAN    0xFFF
 600 #define V_AOPEN_IFF_VLAN(x) ((x) << S_AOPEN_IFF_VLAN)
 601 #define G_AOPEN_IFF_VLAN(x) (((x) >> S_AOPEN_IFF_VLAN) & M_AOPEN_IFF_VLAN)
 602
 603 struct cpl_act_open_rpl {
 604         RSS_HDR union opcode_tid ot;
 605         __be16 local_port;
 606         __be16 peer_port;
 607         __be32 local_ip;
 608         __be32 peer_ip;
 609         __be32 atid;
 610         __u8 rsvd[3];
 611         __u8 status;
 612 };
 613
 614 struct cpl_act_establish {
 615         RSS_HDR union opcode_tid ot;
 616         __be16 local_port;
 617         __be16 peer_port;
 618         __be32 local_ip;
 619         __be32 peer_ip;
 620         __be32 tos_tid;
 621         __be16 l2t_idx;
 622         __be16 tcp_opt;
 623         __be32 snd_isn;
 624         __be32 rcv_isn;
 625 };
 626
 627 struct cpl_get_tcb {
 628         WR_HDR;
 629         union opcode_tid ot;
 630         __be16 cpuno;
 631         __be16 rsvd;
 632 };
 633
 634 struct cpl_get_tcb_rpl {
 635         RSS_HDR union opcode_tid ot;
 636         __u8 rsvd;
 637         __u8 status;
 638         __be16 len;
 639 };
 640
 641 struct cpl_set_tcb {
 642         WR_HDR;
 643         union opcode_tid ot;
 644         __u8 reply;
 645         __u8 cpu_idx;
 646         __be16 len;
 647 };
 648
 649 /* cpl_set_tcb.reply fields */
 650 #define S_NO_REPLY    7
 651 #define V_NO_REPLY(x) ((x) << S_NO_REPLY)
 652 #define F_NO_REPLY    V_NO_REPLY(1U)
 653
 654 struct cpl_set_tcb_field {
 655         WR_HDR;
 656         union opcode_tid ot;
 657         __u8 reply;
 658         __u8 cpu_idx;
 659         __be16 word;
 660         __be64 mask;
 661         __be64 val;
 662 };
 663
 664 struct cpl_set_tcb_rpl {
 665         RSS_HDR union opcode_tid ot;
 666         __u8 rsvd[3];
 667         __u8 status;
 668 };
 669
 670 struct cpl_pcmd {
 671         WR_HDR;
 672         union opcode_tid ot;
 673         __u8 rsvd[3];
 674 #if defined(__LITTLE_ENDIAN_BITFIELD)
 675         __u8 src:1;
 676         __u8 bundle:1;
 677         __u8 channel:1;
 678          __u8:5;
 679 #else
 680          __u8:5;
 681         __u8 channel:1;
 682         __u8 bundle:1;
 683         __u8 src:1;
 684 #endif
 685         __be32 pcmd_parm[2];
 686 };
 687
 688 struct cpl_pcmd_reply {
 689         RSS_HDR union opcode_tid ot;
 690         __u8 status;
 691         __u8 rsvd;
 692         __be16 len;
 693 };
 694
 695 struct cpl_close_con_req {
 696         WR_HDR;
 697         union opcode_tid ot;
 698         __be32 rsvd;
 699 };
 700
 701 struct cpl_close_con_rpl {
 702         RSS_HDR union opcode_tid ot;
 703         __u8 rsvd[3];
 704         __u8 status;
 705         __be32 snd_nxt;
 706         __be32 rcv_nxt;
 707 };
 708
 709 struct cpl_close_listserv_req {
 710         WR_HDR;
 711         union opcode_tid ot;
 712         __u8 rsvd0;
 713         __u8 cpu_idx;
 714         __be16 rsvd1;
 715 };
 716
 717 struct cpl_close_listserv_rpl {
 718         RSS_HDR union opcode_tid ot;
 719         __u8 rsvd[3];
 720         __u8 status;
 721 };
 722
 723 struct cpl_abort_req_rss {
 724         RSS_HDR union opcode_tid ot;
 725         __be32 rsvd0;
 726         __u8 rsvd1;
 727         __u8 status;
 728         __u8 rsvd2[6];
 729 };
 730
 731 struct cpl_abort_req {
 732         WR_HDR;
 733         union opcode_tid ot;
 734         __be32 rsvd0;
 735         __u8 rsvd1;
 736         __u8 cmd;
 737         __u8 rsvd2[6];
 738 };
 739
 740 struct cpl_abort_rpl_rss {
 741         RSS_HDR union opcode_tid ot;
 742         __be32 rsvd0;
 743         __u8 rsvd1;
 744         __u8 status;
 745         __u8 rsvd2[6];
 746 };
 747
 748 struct cpl_abort_rpl {
 749         WR_HDR;
 750         union opcode_tid ot;
 751         __be32 rsvd0;
 752         __u8 rsvd1;
 753         __u8 cmd;
 754         __u8 rsvd2[6];
 755 };
 756
 757 struct cpl_peer_close {
 758         RSS_HDR union opcode_tid ot;
 759         __be32 rcv_nxt;
 760 };
 761
 762 struct tx_data_wr {
 763         __be32 wr_hi;
 764         __be32 wr_lo;
 765         __be32 len;
 766         __be32 flags;
 767         __be32 sndseq;
 768         __be32 param;
 769 };
 770
 771 /* tx_data_wr.param fields */
 772 #define S_TX_PORT    0
 773 #define M_TX_PORT    0x7
 774 #define V_TX_PORT(x) ((x) << S_TX_PORT)
 775 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT)
 776
 777 #define S_TX_MSS    4
 778 #define M_TX_MSS    0xF
 779 #define V_TX_MSS(x) ((x) << S_TX_MSS)
 780 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS)
 781
 782 #define S_TX_QOS    8
 783 #define M_TX_QOS    0xFF
 784 #define V_TX_QOS(x) ((x) << S_TX_QOS)
 785 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS)
 786
 787 #define S_TX_SNDBUF 16
 788 #define M_TX_SNDBUF 0xFFFF
 789 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF)
 790 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF)
 791
 792 struct cpl_tx_data {
 793         union opcode_tid ot;
 794         __be32 len;
 795         __be32 rsvd;
 796         __be16 urg;
 797         __be16 flags;
 798 };
 799
 800 /* cpl_tx_data.flags fields */
 801 #define S_TX_ULP_SUBMODE    6
 802 #define M_TX_ULP_SUBMODE    0xF
 803 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE)
 804 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE)
 805
 806 #define S_TX_ULP_MODE    10
 807 #define M_TX_ULP_MODE    0xF
 808 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE)
 809 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE)
 810
 811 #define S_TX_SHOVE    14
 812 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE)
 813 #define F_TX_SHOVE    V_TX_SHOVE(1U)
 814
 815 #define S_TX_MORE    15
 816 #define V_TX_MORE(x) ((x) << S_TX_MORE)
 817 #define F_TX_MORE    V_TX_MORE(1U)
 818
 819 /* additional tx_data_wr.flags fields */
 820 #define S_TX_CPU_IDX    0
 821 #define M_TX_CPU_IDX    0x3F
 822 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX)
 823 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX)
 824
 825 #define S_TX_URG    16
 826 #define V_TX_URG(x) ((x) << S_TX_URG)
 827 #define F_TX_URG    V_TX_URG(1U)
 828
 829 #define S_TX_CLOSE    17
 830 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE)
 831 #define F_TX_CLOSE    V_TX_CLOSE(1U)
 832
 833 #define S_TX_INIT    18
 834 #define V_TX_INIT(x) ((x) << S_TX_INIT)
 835 #define F_TX_INIT    V_TX_INIT(1U)
 836
 837 #define S_TX_IMM_ACK    19
 838 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK)
 839 #define F_TX_IMM_ACK    V_TX_IMM_ACK(1U)
 840
 841 #define S_TX_IMM_DMA    20
 842 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA)
 843 #define F_TX_IMM_DMA    V_TX_IMM_DMA(1U)
 844
 845 struct cpl_tx_data_ack {
 846         RSS_HDR union opcode_tid ot;
 847         __be32 ack_seq;
 848 };
 849
 850 struct cpl_wr_ack {
 851         RSS_HDR union opcode_tid ot;
 852         __be16 credits;
 853         __be16 rsvd;
 854         __be32 snd_nxt;
 855         __be32 snd_una;
 856 };
 857
 858 struct cpl_rdma_ec_status {
 859         RSS_HDR union opcode_tid ot;
 860         __u8 rsvd[3];
 861         __u8 status;
 862 };
 863
 864 struct mngt_pktsched_wr {
 865         __be32 wr_hi;
 866         __be32 wr_lo;
 867         __u8 mngt_opcode;
 868         __u8 rsvd[7];
 869         __u8 sched;
 870         __u8 idx;
 871         __u8 min;
 872         __u8 max;
 873         __u8 binding;
 874         __u8 rsvd1[3];
 875 };
 876
 877 struct cpl_iscsi_hdr {
 878         RSS_HDR union opcode_tid ot;
 879         __be16 pdu_len_ddp;
 880         __be16 len;
 881         __be32 seq;
 882         __be16 urg;
 883         __u8 rsvd;
 884         __u8 status;
 885 };
 886
 887 /* cpl_iscsi_hdr.pdu_len_ddp fields */
 888 #define S_ISCSI_PDU_LEN    0
 889 #define M_ISCSI_PDU_LEN    0x7FFF
 890 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN)
 891 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN)
 892
 893 #define S_ISCSI_DDP    15
 894 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP)
 895 #define F_ISCSI_DDP    V_ISCSI_DDP(1U)
 896
 897 struct cpl_rx_data {
 898         RSS_HDR union opcode_tid ot;
 899         __be16 rsvd;
 900         __be16 len;
 901         __be32 seq;
 902         __be16 urg;
 903 #if defined(__LITTLE_ENDIAN_BITFIELD)
 904         __u8 dack_mode:2;
 905         __u8 psh:1;
 906         __u8 heartbeat:1;
 907          __u8:4;
 908 #else
 909          __u8:4;
 910         __u8 heartbeat:1;
 911         __u8 psh:1;
 912         __u8 dack_mode:2;
 913 #endif
 914         __u8 status;
 915 };
 916
 917 struct cpl_rx_data_ack {
 918         WR_HDR;
 919         union opcode_tid ot;
 920         __be32 credit_dack;
 921 };
 922
 923 /* cpl_rx_data_ack.ack_seq fields */
 924 #define S_RX_CREDITS    0
 925 #define M_RX_CREDITS    0x7FFFFFF
 926 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS)
 927 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS)
 928
 929 #define S_RX_MODULATE    27
 930 #define V_RX_MODULATE(x) ((x) << S_RX_MODULATE)
 931 #define F_RX_MODULATE    V_RX_MODULATE(1U)
 932
 933 #define S_RX_FORCE_ACK    28
 934 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK)
 935 #define F_RX_FORCE_ACK    V_RX_FORCE_ACK(1U)
 936
 937 #define S_RX_DACK_MODE    29
 938 #define M_RX_DACK_MODE    0x3
 939 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE)
 940 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE)
 941
 942 #define S_RX_DACK_CHANGE    31
 943 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE)
 944 #define F_RX_DACK_CHANGE    V_RX_DACK_CHANGE(1U)
 945
 946 struct cpl_rx_urg_notify {
 947         RSS_HDR union opcode_tid ot;
 948         __be32 seq;
 949 };
 950
 951 struct cpl_rx_ddp_complete {
 952         RSS_HDR union opcode_tid ot;
 953         __be32 ddp_report;
 954 };
 955
 956 struct cpl_rx_data_ddp {
 957         RSS_HDR union opcode_tid ot;
 958         __be16 urg;
 959         __be16 len;
 960         __be32 seq;
 961         union {
 962                 __be32 nxt_seq;
 963                 __be32 ddp_report;
 964         };
 965         __be32 ulp_crc;
 966         __be32 ddpvld_status;
 967 };
 968
 969 /* cpl_rx_data_ddp.ddpvld_status fields */
 970 #define S_DDP_STATUS    0
 971 #define M_DDP_STATUS    0xFF
 972 #define V_DDP_STATUS(x) ((x) << S_DDP_STATUS)
 973 #define G_DDP_STATUS(x) (((x) >> S_DDP_STATUS) & M_DDP_STATUS)
 974
 975 #define S_DDP_VALID    15
 976 #define M_DDP_VALID    0x1FFFF
 977 #define V_DDP_VALID(x) ((x) << S_DDP_VALID)
 978 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID)
 979
 980 #define S_DDP_PPOD_MISMATCH    15
 981 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH)
 982 #define F_DDP_PPOD_MISMATCH    V_DDP_PPOD_MISMATCH(1U)
 983
 984 #define S_DDP_PDU    16
 985 #define V_DDP_PDU(x) ((x) << S_DDP_PDU)
 986 #define F_DDP_PDU    V_DDP_PDU(1U)
 987
 988 #define S_DDP_LLIMIT_ERR    17
 989 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR)
 990 #define F_DDP_LLIMIT_ERR    V_DDP_LLIMIT_ERR(1U)
 991
 992 #define S_DDP_PPOD_PARITY_ERR    18
 993 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR)
 994 #define F_DDP_PPOD_PARITY_ERR    V_DDP_PPOD_PARITY_ERR(1U)
 995
 996 #define S_DDP_PADDING_ERR    19
 997 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR)
 998 #define F_DDP_PADDING_ERR    V_DDP_PADDING_ERR(1U)
 999
1000 #define S_DDP_HDRCRC_ERR    20
1001 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR)
1002 #define F_DDP_HDRCRC_ERR    V_DDP_HDRCRC_ERR(1U)
1003
1004 #define S_DDP_DATACRC_ERR    21
1005 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR)
1006 #define F_DDP_DATACRC_ERR    V_DDP_DATACRC_ERR(1U)
1007
1008 #define S_DDP_INVALID_TAG    22
1009 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG)
1010 #define F_DDP_INVALID_TAG    V_DDP_INVALID_TAG(1U)
1011
1012 #define S_DDP_ULIMIT_ERR    23
1013 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR)
1014 #define F_DDP_ULIMIT_ERR    V_DDP_ULIMIT_ERR(1U)
1015
1016 #define S_DDP_OFFSET_ERR    24
1017 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR)
1018 #define F_DDP_OFFSET_ERR    V_DDP_OFFSET_ERR(1U)
1019
1020 #define S_DDP_COLOR_ERR    25
1021 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR)
1022 #define F_DDP_COLOR_ERR    V_DDP_COLOR_ERR(1U)
1023
1024 #define S_DDP_TID_MISMATCH    26
1025 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH)
1026 #define F_DDP_TID_MISMATCH    V_DDP_TID_MISMATCH(1U)
1027
1028 #define S_DDP_INVALID_PPOD    27
1029 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD)
1030 #define F_DDP_INVALID_PPOD    V_DDP_INVALID_PPOD(1U)
1031
1032 #define S_DDP_ULP_MODE    28
1033 #define M_DDP_ULP_MODE    0xF
1034 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE)
1035 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE)
1036
1037 /* cpl_rx_data_ddp.ddp_report fields */
1038 #define S_DDP_OFFSET    0
1039 #define M_DDP_OFFSET    0x3FFFFF
1040 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET)
1041 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET)
1042
1043 #define S_DDP_URG    24
1044 #define V_DDP_URG(x) ((x) << S_DDP_URG)
1045 #define F_DDP_URG    V_DDP_URG(1U)
1046
1047 #define S_DDP_PSH    25
1048 #define V_DDP_PSH(x) ((x) << S_DDP_PSH)
1049 #define F_DDP_PSH    V_DDP_PSH(1U)
1050
1051 #define S_DDP_BUF_COMPLETE    26
1052 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE)
1053 #define F_DDP_BUF_COMPLETE    V_DDP_BUF_COMPLETE(1U)
1054
1055 #define S_DDP_BUF_TIMED_OUT    27
1056 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT)
1057 #define F_DDP_BUF_TIMED_OUT    V_DDP_BUF_TIMED_OUT(1U)
1058
1059 #define S_DDP_BUF_IDX    28
1060 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX)
1061 #define F_DDP_BUF_IDX    V_DDP_BUF_IDX(1U)
1062
1063 struct cpl_tx_pkt {
1064         WR_HDR;
1065         __be32 cntrl;
1066         __be32 len;
1067 };
1068
1069 struct cpl_tx_pkt_lso {
1070         WR_HDR;
1071         __be32 cntrl;
1072         __be32 len;
1073
1074         __be32 rsvd;
1075         __be32 lso_info;
1076 };
1077
1078 /* cpl_tx_pkt*.cntrl fields */
1079 #define S_TXPKT_VLAN    0
1080 #define M_TXPKT_VLAN    0xFFFF
1081 #define V_TXPKT_VLAN(x) ((x) << S_TXPKT_VLAN)
1082 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN)
1083
1084 #define S_TXPKT_INTF    16
1085 #define M_TXPKT_INTF    0xF
1086 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF)
1087 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF)
1088
1089 #define S_TXPKT_IPCSUM_DIS    20
1090 #define V_TXPKT_IPCSUM_DIS(x) ((x) << S_TXPKT_IPCSUM_DIS)
1091 #define F_TXPKT_IPCSUM_DIS    V_TXPKT_IPCSUM_DIS(1U)
1092
1093 #define S_TXPKT_L4CSUM_DIS    21
1094 #define V_TXPKT_L4CSUM_DIS(x) ((x) << S_TXPKT_L4CSUM_DIS)
1095 #define F_TXPKT_L4CSUM_DIS    V_TXPKT_L4CSUM_DIS(1U)
1096
1097 #define S_TXPKT_VLAN_VLD    22
1098 #define V_TXPKT_VLAN_VLD(x) ((x) << S_TXPKT_VLAN_VLD)
1099 #define F_TXPKT_VLAN_VLD    V_TXPKT_VLAN_VLD(1U)
1100
1101 #define S_TXPKT_LOOPBACK    23
1102 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK)
1103 #define F_TXPKT_LOOPBACK    V_TXPKT_LOOPBACK(1U)
1104
1105 #define S_TXPKT_OPCODE    24
1106 #define M_TXPKT_OPCODE    0xFF
1107 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE)
1108 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE)
1109
1110 /* cpl_tx_pkt_lso.lso_info fields */
1111 #define S_LSO_MSS    0
1112 #define M_LSO_MSS    0x3FFF
1113 #define V_LSO_MSS(x) ((x) << S_LSO_MSS)
1114 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS)
1115
1116 #define S_LSO_ETH_TYPE    14
1117 #define M_LSO_ETH_TYPE    0x3
1118 #define V_LSO_ETH_TYPE(x) ((x) << S_LSO_ETH_TYPE)
1119 #define G_LSO_ETH_TYPE(x) (((x) >> S_LSO_ETH_TYPE) & M_LSO_ETH_TYPE)
1120
1121 #define S_LSO_TCPHDR_WORDS    16
1122 #define M_LSO_TCPHDR_WORDS    0xF
1123 #define V_LSO_TCPHDR_WORDS(x) ((x) << S_LSO_TCPHDR_WORDS)
1124 #define G_LSO_TCPHDR_WORDS(x) (((x) >> S_LSO_TCPHDR_WORDS) & M_LSO_TCPHDR_WORDS)
1125
1126 #define S_LSO_IPHDR_WORDS    20
1127 #define M_LSO_IPHDR_WORDS    0xF
1128 #define V_LSO_IPHDR_WORDS(x) ((x) << S_LSO_IPHDR_WORDS)
1129 #define G_LSO_IPHDR_WORDS(x) (((x) >> S_LSO_IPHDR_WORDS) & M_LSO_IPHDR_WORDS)
1130
1131 #define S_LSO_IPV6    24
1132 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6)
1133 #define F_LSO_IPV6    V_LSO_IPV6(1U)
1134
1135 struct cpl_trace_pkt {
1136 #ifdef CHELSIO_FW
1137         __u8 rss_opcode;
1138 #if defined(__LITTLE_ENDIAN_BITFIELD)
1139         __u8 err:1;
1140          __u8:7;
1141 #else
1142          __u8:7;
1143         __u8 err:1;
1144 #endif
1145         __u8 rsvd0;
1146 #if defined(__LITTLE_ENDIAN_BITFIELD)
1147         __u8 qid:4;
1148          __u8:4;
1149 #else
1150          __u8:4;
1151         __u8 qid:4;
1152 #endif
1153         __be32 tstamp;
1154 #endif                          /* CHELSIO_FW */
1155
1156         __u8 opcode;
1157 #if defined(__LITTLE_ENDIAN_BITFIELD)
1158         __u8 iff:4;
1159          __u8:4;
1160 #else
1161          __u8:4;
1162         __u8 iff:4;
1163 #endif
1164         __u8 rsvd[4];
1165         __be16 len;
1166 };
1167
1168 struct cpl_rx_pkt {
1169         RSS_HDR __u8 opcode;
1170 #if defined(__LITTLE_ENDIAN_BITFIELD)
1171         __u8 iff:4;
1172         __u8 csum_valid:1;
1173         __u8 ipmi_pkt:1;
1174         __u8 vlan_valid:1;
1175         __u8 fragment:1;
1176 #else
1177         __u8 fragment:1;
1178         __u8 vlan_valid:1;
1179         __u8 ipmi_pkt:1;
1180         __u8 csum_valid:1;
1181         __u8 iff:4;
1182 #endif
1183         __be16 csum;
1184         __be16 vlan;
1185         __be16 len;
1186 };
1187
1188 struct cpl_l2t_write_req {
1189         WR_HDR;
1190         union opcode_tid ot;
1191         __be32 params;
1192         __u8 rsvd[2];
1193         __u8 dst_mac[6];
1194 };
1195
1196 /* cpl_l2t_write_req.params fields */
1197 #define S_L2T_W_IDX    0
1198 #define M_L2T_W_IDX    0x7FF
1199 #define V_L2T_W_IDX(x) ((x) << S_L2T_W_IDX)
1200 #define G_L2T_W_IDX(x) (((x) >> S_L2T_W_IDX) & M_L2T_W_IDX)
1201
1202 #define S_L2T_W_VLAN    11
1203 #define M_L2T_W_VLAN    0xFFF
1204 #define V_L2T_W_VLAN(x) ((x) << S_L2T_W_VLAN)
1205 #define G_L2T_W_VLAN(x) (((x) >> S_L2T_W_VLAN) & M_L2T_W_VLAN)
1206
1207 #define S_L2T_W_IFF    23
1208 #define M_L2T_W_IFF    0xF
1209 #define V_L2T_W_IFF(x) ((x) << S_L2T_W_IFF)
1210 #define G_L2T_W_IFF(x) (((x) >> S_L2T_W_IFF) & M_L2T_W_IFF)
1211
1212 #define S_L2T_W_PRIO    27
1213 #define M_L2T_W_PRIO    0x7
1214 #define V_L2T_W_PRIO(x) ((x) << S_L2T_W_PRIO)
1215 #define G_L2T_W_PRIO(x) (((x) >> S_L2T_W_PRIO) & M_L2T_W_PRIO)
1216
1217 struct cpl_l2t_write_rpl {
1218         RSS_HDR union opcode_tid ot;
1219         __u8 status;
1220         __u8 rsvd[3];
1221 };
1222
1223 struct cpl_l2t_read_req {
1224         WR_HDR;
1225         union opcode_tid ot;
1226         __be16 rsvd;
1227         __be16 l2t_idx;
1228 };
1229
1230 struct cpl_l2t_read_rpl {
1231         RSS_HDR union opcode_tid ot;
1232         __be32 params;
1233         __u8 rsvd[2];
1234         __u8 dst_mac[6];
1235 };
1236
1237 /* cpl_l2t_read_rpl.params fields */
1238 #define S_L2T_R_PRIO    0
1239 #define M_L2T_R_PRIO    0x7
1240 #define V_L2T_R_PRIO(x) ((x) << S_L2T_R_PRIO)
1241 #define G_L2T_R_PRIO(x) (((x) >> S_L2T_R_PRIO) & M_L2T_R_PRIO)
1242
1243 #define S_L2T_R_VLAN    8
1244 #define M_L2T_R_VLAN    0xFFF
1245 #define V_L2T_R_VLAN(x) ((x) << S_L2T_R_VLAN)
1246 #define G_L2T_R_VLAN(x) (((x) >> S_L2T_R_VLAN) & M_L2T_R_VLAN)
1247
1248 #define S_L2T_R_IFF    20
1249 #define M_L2T_R_IFF    0xF
1250 #define V_L2T_R_IFF(x) ((x) << S_L2T_R_IFF)
1251 #define G_L2T_R_IFF(x) (((x) >> S_L2T_R_IFF) & M_L2T_R_IFF)
1252
1253 #define S_L2T_STATUS    24
1254 #define M_L2T_STATUS    0xFF
1255 #define V_L2T_STATUS(x) ((x) << S_L2T_STATUS)
1256 #define G_L2T_STATUS(x) (((x) >> S_L2T_STATUS) & M_L2T_STATUS)
1257
1258 struct cpl_smt_write_req {
1259         WR_HDR;
1260         union opcode_tid ot;
1261         __u8 rsvd0;
1262 #if defined(__LITTLE_ENDIAN_BITFIELD)
1263         __u8 mtu_idx:4;
1264         __u8 iff:4;
1265 #else
1266         __u8 iff:4;
1267         __u8 mtu_idx:4;
1268 #endif
1269         __be16 rsvd2;
1270         __be16 rsvd3;
1271         __u8 src_mac1[6];
1272         __be16 rsvd4;
1273         __u8 src_mac0[6];
1274 };
1275
1276 struct cpl_smt_write_rpl {
1277         RSS_HDR union opcode_tid ot;
1278         __u8 status;
1279         __u8 rsvd[3];
1280 };
1281
1282 struct cpl_smt_read_req {
1283         WR_HDR;
1284         union opcode_tid ot;
1285         __u8 rsvd0;
1286 #if defined(__LITTLE_ENDIAN_BITFIELD)
1287          __u8:4;
1288         __u8 iff:4;
1289 #else
1290         __u8 iff:4;
1291          __u8:4;
1292 #endif
1293         __be16 rsvd2;
1294 };
1295
1296 struct cpl_smt_read_rpl {
1297         RSS_HDR union opcode_tid ot;
1298         __u8 status;
1299 #if defined(__LITTLE_ENDIAN_BITFIELD)
1300         __u8 mtu_idx:4;
1301          __u8:4;
1302 #else
1303          __u8:4;
1304         __u8 mtu_idx:4;
1305 #endif
1306         __be16 rsvd2;
1307         __be16 rsvd3;
1308         __u8 src_mac1[6];
1309         __be16 rsvd4;
1310         __u8 src_mac0[6];
1311 };
1312
1313 struct cpl_rte_delete_req {
1314         WR_HDR;
1315         union opcode_tid ot;
1316         __be32 params;
1317 };
1318
1319 /* { cpl_rte_delete_req, cpl_rte_read_req }.params fields */
1320 #define S_RTE_REQ_LUT_IX    8
1321 #define M_RTE_REQ_LUT_IX    0x7FF
1322 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX)
1323 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX)
1324
1325 #define S_RTE_REQ_LUT_BASE    19
1326 #define M_RTE_REQ_LUT_BASE    0x7FF
1327 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE)
1328 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE)
1329
1330 #define S_RTE_READ_REQ_SELECT    31
1331 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT)
1332 #define F_RTE_READ_REQ_SELECT    V_RTE_READ_REQ_SELECT(1U)
1333
1334 struct cpl_rte_delete_rpl {
1335         RSS_HDR union opcode_tid ot;
1336         __u8 status;
1337         __u8 rsvd[3];
1338 };
1339
1340 struct cpl_rte_write_req {
1341         WR_HDR;
1342         union opcode_tid ot;
1343 #if defined(__LITTLE_ENDIAN_BITFIELD)
1344          __u8:6;
1345         __u8 write_tcam:1;
1346         __u8 write_l2t_lut:1;
1347 #else
1348         __u8 write_l2t_lut:1;
1349         __u8 write_tcam:1;
1350          __u8:6;
1351 #endif
1352         __u8 rsvd[3];
1353         __be32 lut_params;
1354         __be16 rsvd2;
1355         __be16 l2t_idx;
1356         __be32 netmask;
1357         __be32 faddr;
1358 };
1359
1360 /* cpl_rte_write_req.lut_params fields */
1361 #define S_RTE_WRITE_REQ_LUT_IX    10
1362 #define M_RTE_WRITE_REQ_LUT_IX    0x7FF
1363 #define V_RTE_WRITE_REQ_LUT_IX(x) ((x) << S_RTE_WRITE_REQ_LUT_IX)
1364 #define G_RTE_WRITE_REQ_LUT_IX(x) (((x) >> S_RTE_WRITE_REQ_LUT_IX) & M_RTE_WRITE_REQ_LUT_IX)
1365
1366 #define S_RTE_WRITE_REQ_LUT_BASE    21
1367 #define M_RTE_WRITE_REQ_LUT_BASE    0x7FF
1368 #define V_RTE_WRITE_REQ_LUT_BASE(x) ((x) << S_RTE_WRITE_REQ_LUT_BASE)
1369 #define G_RTE_WRITE_REQ_LUT_BASE(x) (((x) >> S_RTE_WRITE_REQ_LUT_BASE) & M_RTE_WRITE_REQ_LUT_BASE)
1370
1371 struct cpl_rte_write_rpl {
1372         RSS_HDR union opcode_tid ot;
1373         __u8 status;
1374         __u8 rsvd[3];
1375 };
1376
1377 struct cpl_rte_read_req {
1378         WR_HDR;
1379         union opcode_tid ot;
1380         __be32 params;
1381 };
1382
1383 struct cpl_rte_read_rpl {
1384         RSS_HDR union opcode_tid ot;
1385         __u8 status;
1386         __u8 rsvd0;
1387         __be16 l2t_idx;
1388 #if defined(__LITTLE_ENDIAN_BITFIELD)
1389          __u8:7;
1390         __u8 select:1;
1391 #else
1392         __u8 select:1;
1393          __u8:7;
1394 #endif
1395         __u8 rsvd2[3];
1396         __be32 addr;
1397 };
1398
1399 struct cpl_tid_release {
1400         WR_HDR;
1401         union opcode_tid ot;
1402         __be32 rsvd;
1403 };
1404
1405 struct cpl_barrier {
1406         WR_HDR;
1407         __u8 opcode;
1408         __u8 rsvd[7];
1409 };
1410
1411 struct cpl_rdma_read_req {
1412         __u8 opcode;
1413         __u8 rsvd[15];
1414 };
1415
1416 struct cpl_rdma_terminate {
1417 #ifdef CHELSIO_FW
1418         __u8 opcode;
1419         __u8 rsvd[2];
1420 #if defined(__LITTLE_ENDIAN_BITFIELD)
1421         __u8 rspq:3;
1422          __u8:5;
1423 #else
1424          __u8:5;
1425         __u8 rspq:3;
1426 #endif
1427         __be32 tid_len;
1428 #endif
1429         __be32 msn;
1430         __be32 mo;
1431         __u8 data[0];
1432 };
1433
1434 /* cpl_rdma_terminate.tid_len fields */
1435 #define S_FLIT_CNT    0
1436 #define M_FLIT_CNT    0xFF
1437 #define V_FLIT_CNT(x) ((x) << S_FLIT_CNT)
1438 #define G_FLIT_CNT(x) (((x) >> S_FLIT_CNT) & M_FLIT_CNT)
1439
1440 #define S_TERM_TID    8
1441 #define M_TERM_TID    0xFFFFF
1442 #define V_TERM_TID(x) ((x) << S_TERM_TID)
1443 #define G_TERM_TID(x) (((x) >> S_TERM_TID) & M_TERM_TID)
1444 #endif                          /* T3_CPL_H */