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kmemtrace: SLOB hooks.
[linux-2.6/kmemtrace.git] / drivers / net / wan / dscc4.c
blobc6f26e28e3769ba12135a8dd7de19678956ee7ee
1 /*
2 * drivers/net/wan/dscc4/dscc4.c: a DSCC4 HDLC driver for Linux
3 *
4 * This software may be used and distributed according to the terms of the
5 * GNU General Public License.
6 *
7 * The author may be reached as romieu@cogenit.fr.
8 * Specific bug reports/asian food will be welcome.
9 *
10 * Special thanks to the nice people at CS-Telecom for the hardware and the
11 * access to the test/measure tools.
12 *
13 *
14 * Theory of Operation
15 *
16 * I. Board Compatibility
17 *
18 * This device driver is designed for the Siemens PEB20534 4 ports serial
19 * controller as found on Etinc PCISYNC cards. The documentation for the
20 * chipset is available at http://www.infineon.com:
21 * - Data Sheet "DSCC4, DMA Supported Serial Communication Controller with
22 * 4 Channels, PEB 20534 Version 2.1, PEF 20534 Version 2.1";
23 * - Application Hint "Management of DSCC4 on-chip FIFO resources".
24 * - Errata sheet DS5 (courtesy of Michael Skerritt).
25 * Jens David has built an adapter based on the same chipset. Take a look
26 * at http://www.afthd.tu-darmstadt.de/~dg1kjd/pciscc4 for a specific
27 * driver.
28 * Sample code (2 revisions) is available at Infineon.
29 *
30 * II. Board-specific settings
31 *
32 * Pcisync can transmit some clock signal to the outside world on the
33 * *first two* ports provided you put a quartz and a line driver on it and
34 * remove the jumpers. The operation is described on Etinc web site. If you
35 * go DCE on these ports, don't forget to use an adequate cable.
36 *
37 * Sharing of the PCI interrupt line for this board is possible.
38 *
39 * III. Driver operation
40 *
41 * The rx/tx operations are based on a linked list of descriptors. The driver
42 * doesn't use HOLD mode any more. HOLD mode is definitely buggy and the more
43 * I tried to fix it, the more it started to look like (convoluted) software
44 * mutation of LxDA method. Errata sheet DS5 suggests to use LxDA: consider
45 * this a rfc2119 MUST.
46 *
47 * Tx direction
48 * When the tx ring is full, the xmit routine issues a call to netdev_stop.
49 * The device is supposed to be enabled again during an ALLS irq (we could
50 * use HI but as it's easy to lose events, it's fscked).
51 *
52 * Rx direction
53 * The received frames aren't supposed to span over multiple receiving areas.
54 * I may implement it some day but it isn't the highest ranked item.
55 *
56 * IV. Notes
57 * The current error (XDU, RFO) recovery code is untested.
58 * So far, RDO takes his RX channel down and the right sequence to enable it
59 * again is still a mistery. If RDO happens, plan a reboot. More details
60 * in the code (NB: as this happens, TX still works).
61 * Don't mess the cables during operation, especially on DTE ports. I don't
62 * suggest it for DCE either but at least one can get some messages instead
63 * of a complete instant freeze.
64 * Tests are done on Rev. 20 of the silicium. The RDO handling changes with
65 * the documentation/chipset releases.
66 *
67 * TODO:
68 * - test X25.
69 * - use polling at high irq/s,
70 * - performance analysis,
71 * - endianness.
72 *
73 * 2001/12/10 Daniela Squassoni <daniela@cyclades.com>
74 * - Contribution to support the new generic HDLC layer.
75 *
76 * 2002/01 Ueimor
77 * - old style interface removal
78 * - dscc4_release_ring fix (related to DMA mapping)
79 * - hard_start_xmit fix (hint: TxSizeMax)
80 * - misc crapectomy.
81 */
82
83 #include <linux/module.h>
84 #include <linux/types.h>
85 #include <linux/errno.h>
86 #include <linux/list.h>
87 #include <linux/ioport.h>
88 #include <linux/pci.h>
89 #include <linux/kernel.h>
90 #include <linux/mm.h>
91
92 #include <asm/system.h>
93 #include <asm/cache.h>
94 #include <asm/byteorder.h>
95 #include <asm/uaccess.h>
96 #include <asm/io.h>
97 #include <asm/irq.h>
98
99 #include <linux/init.h>
100 #include <linux/string.h>
101
102 #include <linux/if_arp.h>
103 #include <linux/netdevice.h>
104 #include <linux/skbuff.h>
105 #include <linux/delay.h>
106 #include <net/syncppp.h>
107 #include <linux/hdlc.h>
108 #include <linux/mutex.h>
109
110 /* Version */
111 static const char version[] = "$Id: dscc4.c,v 1.173 2003/09/20 23:55:34 romieu Exp $ for Linux\n";
112 static int debug;
113 static int quartz;
114
115 #ifdef CONFIG_DSCC4_PCI_RST
116 static DEFINE_MUTEX(dscc4_mutex);
117 static u32 dscc4_pci_config_store[16];
118 #endif
119
120 #define DRV_NAME "dscc4"
121
122 #undef DSCC4_POLLING
123
124 /* Module parameters */
125
126 MODULE_AUTHOR("Maintainer: Francois Romieu <romieu@cogenit.fr>");
127 MODULE_DESCRIPTION("Siemens PEB20534 PCI Controler");
128 MODULE_LICENSE("GPL");
129 module_param(debug, int, 0);
130 MODULE_PARM_DESC(debug,"Enable/disable extra messages");
131 module_param(quartz, int, 0);
132 MODULE_PARM_DESC(quartz,"If present, on-board quartz frequency (Hz)");
133
134 /* Structures */
135
136 struct thingie {
137 int define;
138 u32 bits;
139 };
140
141 struct TxFD {
142 __le32 state;
143 __le32 next;
144 __le32 data;
145 __le32 complete;
146 u32 jiffies; /* Allows sizeof(TxFD) == sizeof(RxFD) + extra hack */
147 /* FWIW, datasheet calls that "dummy" and says that card
148 * never looks at it; neither does the driver */
149 };
150
151 struct RxFD {
152 __le32 state1;
153 __le32 next;
154 __le32 data;
155 __le32 state2;
156 __le32 end;
157 };
158
159 #define DUMMY_SKB_SIZE 64
160 #define TX_LOW 8
161 #define TX_RING_SIZE 32
162 #define RX_RING_SIZE 32
163 #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct TxFD)
164 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct RxFD)
165 #define IRQ_RING_SIZE 64 /* Keep it a multiple of 32 */
166 #define TX_TIMEOUT (HZ/10)
167 #define DSCC4_HZ_MAX 33000000
168 #define BRR_DIVIDER_MAX 64*0x00004000 /* Cf errata DS5 p.10 */
169 #define dev_per_card 4
170 #define SCC_REGISTERS_MAX 23 /* Cf errata DS5 p.4 */
171
172 #define SOURCE_ID(flags) (((flags) >> 28) & 0x03)
173 #define TO_SIZE(state) (((state) >> 16) & 0x1fff)
174
175 /*
176 * Given the operating range of Linux HDLC, the 2 defines below could be
177 * made simpler. However they are a fine reminder for the limitations of
178 * the driver: it's better to stay < TxSizeMax and < RxSizeMax.
179 */
180 #define TO_STATE_TX(len) cpu_to_le32(((len) & TxSizeMax) << 16)
181 #define TO_STATE_RX(len) cpu_to_le32((RX_MAX(len) % RxSizeMax) << 16)
182 #define RX_MAX(len) ((((len) >> 5) + 1) << 5) /* Cf RLCR */
183 #define SCC_REG_START(dpriv) (SCC_START+(dpriv->dev_id)*SCC_OFFSET)
184
185 struct dscc4_pci_priv {
186 __le32 *iqcfg;
187 int cfg_cur;
188 spinlock_t lock;
189 struct pci_dev *pdev;
190
191 struct dscc4_dev_priv *root;
192 dma_addr_t iqcfg_dma;
193 u32 xtal_hz;
194 };
195
196 struct dscc4_dev_priv {
197 struct sk_buff *rx_skbuff[RX_RING_SIZE];
198 struct sk_buff *tx_skbuff[TX_RING_SIZE];
199
200 struct RxFD *rx_fd;
201 struct TxFD *tx_fd;
202 __le32 *iqrx;
203 __le32 *iqtx;
204
205 /* FIXME: check all the volatile are required */
206 volatile u32 tx_current;
207 u32 rx_current;
208 u32 iqtx_current;
209 u32 iqrx_current;
210
211 volatile u32 tx_dirty;
212 volatile u32 ltda;
213 u32 rx_dirty;
214 u32 lrda;
215
216 dma_addr_t tx_fd_dma;
217 dma_addr_t rx_fd_dma;
218 dma_addr_t iqtx_dma;
219 dma_addr_t iqrx_dma;
220
221 u32 scc_regs[SCC_REGISTERS_MAX]; /* Cf errata DS5 p.4 */
222
223 struct timer_list timer;
224
225 struct dscc4_pci_priv *pci_priv;
226 spinlock_t lock;
227
228 int dev_id;
229 volatile u32 flags;
230 u32 timer_help;
231
232 unsigned short encoding;
233 unsigned short parity;
234 struct net_device *dev;
235 sync_serial_settings settings;
236 void __iomem *base_addr;
237 u32 __pad __attribute__ ((aligned (4)));
238 };
239
240 /* GLOBAL registers definitions */
241 #define GCMDR 0x00
242 #define GSTAR 0x04
243 #define GMODE 0x08
244 #define IQLENR0 0x0C
245 #define IQLENR1 0x10
246 #define IQRX0 0x14
247 #define IQTX0 0x24
248 #define IQCFG 0x3c
249 #define FIFOCR1 0x44
250 #define FIFOCR2 0x48
251 #define FIFOCR3 0x4c
252 #define FIFOCR4 0x34
253 #define CH0CFG 0x50
254 #define CH0BRDA 0x54
255 #define CH0BTDA 0x58
256 #define CH0FRDA 0x98
257 #define CH0FTDA 0xb0
258 #define CH0LRDA 0xc8
259 #define CH0LTDA 0xe0
260
261 /* SCC registers definitions */
262 #define SCC_START 0x0100
263 #define SCC_OFFSET 0x80
264 #define CMDR 0x00
265 #define STAR 0x04
266 #define CCR0 0x08
267 #define CCR1 0x0c
268 #define CCR2 0x10
269 #define BRR 0x2C
270 #define RLCR 0x40
271 #define IMR 0x54
272 #define ISR 0x58
273
274 #define GPDIR 0x0400
275 #define GPDATA 0x0404
276 #define GPIM 0x0408
277
278 /* Bit masks */
279 #define EncodingMask 0x00700000
280 #define CrcMask 0x00000003
281
282 #define IntRxScc0 0x10000000
283 #define IntTxScc0 0x01000000
284
285 #define TxPollCmd 0x00000400
286 #define RxActivate 0x08000000
287 #define MTFi 0x04000000
288 #define Rdr 0x00400000
289 #define Rdt 0x00200000
290 #define Idr 0x00100000
291 #define Idt 0x00080000
292 #define TxSccRes 0x01000000
293 #define RxSccRes 0x00010000
294 #define TxSizeMax 0x1fff /* Datasheet DS1 - 11.1.1.1 */
295 #define RxSizeMax 0x1ffc /* Datasheet DS1 - 11.1.2.1 */
296
297 #define Ccr0ClockMask 0x0000003f
298 #define Ccr1LoopMask 0x00000200
299 #define IsrMask 0x000fffff
300 #define BrrExpMask 0x00000f00
301 #define BrrMultMask 0x0000003f
302 #define EncodingMask 0x00700000
303 #define Hold cpu_to_le32(0x40000000)
304 #define SccBusy 0x10000000
305 #define PowerUp 0x80000000
306 #define Vis 0x00001000
307 #define FrameOk (FrameVfr | FrameCrc)
308 #define FrameVfr 0x80
309 #define FrameRdo 0x40
310 #define FrameCrc 0x20
311 #define FrameRab 0x10
312 #define FrameAborted cpu_to_le32(0x00000200)
313 #define FrameEnd cpu_to_le32(0x80000000)
314 #define DataComplete cpu_to_le32(0x40000000)
315 #define LengthCheck 0x00008000
316 #define SccEvt 0x02000000
317 #define NoAck 0x00000200
318 #define Action 0x00000001
319 #define HiDesc cpu_to_le32(0x20000000)
320
321 /* SCC events */
322 #define RxEvt 0xf0000000
323 #define TxEvt 0x0f000000
324 #define Alls 0x00040000
325 #define Xdu 0x00010000
326 #define Cts 0x00004000
327 #define Xmr 0x00002000
328 #define Xpr 0x00001000
329 #define Rdo 0x00000080
330 #define Rfs 0x00000040
331 #define Cd 0x00000004
332 #define Rfo 0x00000002
333 #define Flex 0x00000001
334
335 /* DMA core events */
336 #define Cfg 0x00200000
337 #define Hi 0x00040000
338 #define Fi 0x00020000
339 #define Err 0x00010000
340 #define Arf 0x00000002
341 #define ArAck 0x00000001
342
343 /* State flags */
344 #define Ready 0x00000000
345 #define NeedIDR 0x00000001
346 #define NeedIDT 0x00000002
347 #define RdoSet 0x00000004
348 #define FakeReset 0x00000008
349
350 /* Don't mask RDO. Ever. */
351 #ifdef DSCC4_POLLING
352 #define EventsMask 0xfffeef7f
353 #else
354 #define EventsMask 0xfffa8f7a
355 #endif
356
357 /* Functions prototypes */
358 static void dscc4_rx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *);
359 static void dscc4_tx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *);
360 static int dscc4_found1(struct pci_dev *, void __iomem *ioaddr);
361 static int dscc4_init_one(struct pci_dev *, const struct pci_device_id *ent);
362 static int dscc4_open(struct net_device *);
363 static int dscc4_start_xmit(struct sk_buff *, struct net_device *);
364 static int dscc4_close(struct net_device *);
365 static int dscc4_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
366 static int dscc4_init_ring(struct net_device *);
367 static void dscc4_release_ring(struct dscc4_dev_priv *);
368 static void dscc4_timer(unsigned long);
369 static void dscc4_tx_timeout(struct net_device *);
370 static irqreturn_t dscc4_irq(int irq, void *dev_id);
371 static int dscc4_hdlc_attach(struct net_device *, unsigned short, unsigned short);
372 static int dscc4_set_iface(struct dscc4_dev_priv *, struct net_device *);
373 #ifdef DSCC4_POLLING
374 static int dscc4_tx_poll(struct dscc4_dev_priv *, struct net_device *);
375 #endif
376
377 static inline struct dscc4_dev_priv *dscc4_priv(struct net_device *dev)
378 {
379 return dev_to_hdlc(dev)->priv;
380 }
381
382 static inline struct net_device *dscc4_to_dev(struct dscc4_dev_priv *p)
383 {
384 return p->dev;
385 }
386
387 static void scc_patchl(u32 mask, u32 value, struct dscc4_dev_priv *dpriv,
388 struct net_device *dev, int offset)
389 {
390 u32 state;
391
392 /* Cf scc_writel for concern regarding thread-safety */
393 state = dpriv->scc_regs[offset >> 2];
394 state &= ~mask;
395 state |= value;
396 dpriv->scc_regs[offset >> 2] = state;
397 writel(state, dpriv->base_addr + SCC_REG_START(dpriv) + offset);
398 }
399
400 static void scc_writel(u32 bits, struct dscc4_dev_priv *dpriv,
401 struct net_device *dev, int offset)
402 {
403 /*
404 * Thread-UNsafe.
405 * As of 2002/02/16, there are no thread racing for access.
406 */
407 dpriv->scc_regs[offset >> 2] = bits;
408 writel(bits, dpriv->base_addr + SCC_REG_START(dpriv) + offset);
409 }
410
411 static inline u32 scc_readl(struct dscc4_dev_priv *dpriv, int offset)
412 {
413 return dpriv->scc_regs[offset >> 2];
414 }
415
416 static u32 scc_readl_star(struct dscc4_dev_priv *dpriv, struct net_device *dev)
417 {
418 /* Cf errata DS5 p.4 */
419 readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR);
420 return readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR);
421 }
422
423 static inline void dscc4_do_tx(struct dscc4_dev_priv *dpriv,
424 struct net_device *dev)
425 {
426 dpriv->ltda = dpriv->tx_fd_dma +
427 ((dpriv->tx_current-1)%TX_RING_SIZE)*sizeof(struct TxFD);
428 writel(dpriv->ltda, dpriv->base_addr + CH0LTDA + dpriv->dev_id*4);
429 /* Flush posted writes *NOW* */
430 readl(dpriv->base_addr + CH0LTDA + dpriv->dev_id*4);
431 }
432
433 static inline void dscc4_rx_update(struct dscc4_dev_priv *dpriv,
434 struct net_device *dev)
435 {
436 dpriv->lrda = dpriv->rx_fd_dma +
437 ((dpriv->rx_dirty - 1)%RX_RING_SIZE)*sizeof(struct RxFD);
438 writel(dpriv->lrda, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
439 }
440
441 static inline unsigned int dscc4_tx_done(struct dscc4_dev_priv *dpriv)
442 {
443 return dpriv->tx_current == dpriv->tx_dirty;
444 }
445
446 static inline unsigned int dscc4_tx_quiescent(struct dscc4_dev_priv *dpriv,
447 struct net_device *dev)
448 {
449 return readl(dpriv->base_addr + CH0FTDA + dpriv->dev_id*4) == dpriv->ltda;
450 }
451
452 static int state_check(u32 state, struct dscc4_dev_priv *dpriv,
453 struct net_device *dev, const char *msg)
454 {
455 int ret = 0;
456
457 if (debug > 1) {
458 if (SOURCE_ID(state) != dpriv->dev_id) {
459 printk(KERN_DEBUG "%s (%s): Source Id=%d, state=%08x\n",
460 dev->name, msg, SOURCE_ID(state), state );
461 ret = -1;
462 }
463 if (state & 0x0df80c00) {
464 printk(KERN_DEBUG "%s (%s): state=%08x (UFO alert)\n",
465 dev->name, msg, state);
466 ret = -1;
467 }
468 }
469 return ret;
470 }
471
472 static void dscc4_tx_print(struct net_device *dev,
473 struct dscc4_dev_priv *dpriv,
474 char *msg)
475 {
476 printk(KERN_DEBUG "%s: tx_current=%02d tx_dirty=%02d (%s)\n",
477 dev->name, dpriv->tx_current, dpriv->tx_dirty, msg);
478 }
479
480 static void dscc4_release_ring(struct dscc4_dev_priv *dpriv)
481 {
482 struct pci_dev *pdev = dpriv->pci_priv->pdev;
483 struct TxFD *tx_fd = dpriv->tx_fd;
484 struct RxFD *rx_fd = dpriv->rx_fd;
485 struct sk_buff **skbuff;
486 int i;
487
488 pci_free_consistent(pdev, TX_TOTAL_SIZE, tx_fd, dpriv->tx_fd_dma);
489 pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma);
490
491 skbuff = dpriv->tx_skbuff;
492 for (i = 0; i < TX_RING_SIZE; i++) {
493 if (*skbuff) {
494 pci_unmap_single(pdev, le32_to_cpu(tx_fd->data),
495 (*skbuff)->len, PCI_DMA_TODEVICE);
496 dev_kfree_skb(*skbuff);
497 }
498 skbuff++;
499 tx_fd++;
500 }
501
502 skbuff = dpriv->rx_skbuff;
503 for (i = 0; i < RX_RING_SIZE; i++) {
504 if (*skbuff) {
505 pci_unmap_single(pdev, le32_to_cpu(rx_fd->data),
506 RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE);
507 dev_kfree_skb(*skbuff);
508 }
509 skbuff++;
510 rx_fd++;
511 }
512 }
513
514 static inline int try_get_rx_skb(struct dscc4_dev_priv *dpriv,
515 struct net_device *dev)
516 {
517 unsigned int dirty = dpriv->rx_dirty%RX_RING_SIZE;
518 struct RxFD *rx_fd = dpriv->rx_fd + dirty;
519 const int len = RX_MAX(HDLC_MAX_MRU);
520 struct sk_buff *skb;
521 int ret = 0;
522
523 skb = dev_alloc_skb(len);
524 dpriv->rx_skbuff[dirty] = skb;
525 if (skb) {
526 skb->protocol = hdlc_type_trans(skb, dev);
527 rx_fd->data = cpu_to_le32(pci_map_single(dpriv->pci_priv->pdev,
528 skb->data, len, PCI_DMA_FROMDEVICE));
529 } else {
530 rx_fd->data = 0;
531 ret = -1;
532 }
533 return ret;
534 }
535
536 /*
537 * IRQ/thread/whatever safe
538 */
539 static int dscc4_wait_ack_cec(struct dscc4_dev_priv *dpriv,
540 struct net_device *dev, char *msg)
541 {
542 s8 i = 0;
543
544 do {
545 if (!(scc_readl_star(dpriv, dev) & SccBusy)) {
546 printk(KERN_DEBUG "%s: %s ack (%d try)\n", dev->name,
547 msg, i);
548 goto done;
549 }
550 schedule_timeout_uninterruptible(10);
551 rmb();
552 } while (++i > 0);
553 printk(KERN_ERR "%s: %s timeout\n", dev->name, msg);
554 done:
555 return (i >= 0) ? i : -EAGAIN;
556 }
557
558 static int dscc4_do_action(struct net_device *dev, char *msg)
559 {
560 void __iomem *ioaddr = dscc4_priv(dev)->base_addr;
561 s16 i = 0;
562
563 writel(Action, ioaddr + GCMDR);
564 ioaddr += GSTAR;
565 do {
566 u32 state = readl(ioaddr);
567
568 if (state & ArAck) {
569 printk(KERN_DEBUG "%s: %s ack\n", dev->name, msg);
570 writel(ArAck, ioaddr);
571 goto done;
572 } else if (state & Arf) {
573 printk(KERN_ERR "%s: %s failed\n", dev->name, msg);
574 writel(Arf, ioaddr);
575 i = -1;
576 goto done;
577 }
578 rmb();
579 } while (++i > 0);
580 printk(KERN_ERR "%s: %s timeout\n", dev->name, msg);
581 done:
582 return i;
583 }
584
585 static inline int dscc4_xpr_ack(struct dscc4_dev_priv *dpriv)
586 {
587 int cur = dpriv->iqtx_current%IRQ_RING_SIZE;
588 s8 i = 0;
589
590 do {
591 if (!(dpriv->flags & (NeedIDR | NeedIDT)) ||
592 (dpriv->iqtx[cur] & cpu_to_le32(Xpr)))
593 break;
594 smp_rmb();
595 schedule_timeout_uninterruptible(10);
596 } while (++i > 0);
597
598 return (i >= 0 ) ? i : -EAGAIN;
599 }
600
601 #if 0 /* dscc4_{rx/tx}_reset are both unreliable - more tweak needed */
602 static void dscc4_rx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev)
603 {
604 unsigned long flags;
605
606 spin_lock_irqsave(&dpriv->pci_priv->lock, flags);
607 /* Cf errata DS5 p.6 */
608 writel(0x00000000, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
609 scc_patchl(PowerUp, 0, dpriv, dev, CCR0);
610 readl(dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
611 writel(MTFi|Rdr, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG);
612 writel(Action, dpriv->base_addr + GCMDR);
613 spin_unlock_irqrestore(&dpriv->pci_priv->lock, flags);
614 }
615
616 #endif
617
618 #if 0
619 static void dscc4_tx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev)
620 {
621 u16 i = 0;
622
623 /* Cf errata DS5 p.7 */
624 scc_patchl(PowerUp, 0, dpriv, dev, CCR0);
625 scc_writel(0x00050000, dpriv, dev, CCR2);
626 /*
627 * Must be longer than the time required to fill the fifo.
628 */
629 while (!dscc4_tx_quiescent(dpriv, dev) && ++i) {
630 udelay(1);
631 wmb();
632 }
633
634 writel(MTFi|Rdt, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG);
635 if (dscc4_do_action(dev, "Rdt") < 0)
636 printk(KERN_ERR "%s: Tx reset failed\n", dev->name);
637 }
638 #endif
639
640 /* TODO: (ab)use this function to refill a completely depleted RX ring. */
641 static inline void dscc4_rx_skb(struct dscc4_dev_priv *dpriv,
642 struct net_device *dev)
643 {
644 struct RxFD *rx_fd = dpriv->rx_fd + dpriv->rx_current%RX_RING_SIZE;
645 struct net_device_stats *stats = hdlc_stats(dev);
646 struct pci_dev *pdev = dpriv->pci_priv->pdev;
647 struct sk_buff *skb;
648 int pkt_len;
649
650 skb = dpriv->rx_skbuff[dpriv->rx_current++%RX_RING_SIZE];
651 if (!skb) {
652 printk(KERN_DEBUG "%s: skb=0 (%s)\n", dev->name, __FUNCTION__);
653 goto refill;
654 }
655 pkt_len = TO_SIZE(le32_to_cpu(rx_fd->state2));
656 pci_unmap_single(pdev, le32_to_cpu(rx_fd->data),
657 RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE);
658 if ((skb->data[--pkt_len] & FrameOk) == FrameOk) {
659 stats->rx_packets++;
660 stats->rx_bytes += pkt_len;
661 skb_put(skb, pkt_len);
662 if (netif_running(dev))
663 skb->protocol = hdlc_type_trans(skb, dev);
664 skb->dev->last_rx = jiffies;
665 netif_rx(skb);
666 } else {
667 if (skb->data[pkt_len] & FrameRdo)
668 stats->rx_fifo_errors++;
669 else if (!(skb->data[pkt_len] | ~FrameCrc))
670 stats->rx_crc_errors++;
671 else if (!(skb->data[pkt_len] | ~(FrameVfr | FrameRab)))
672 stats->rx_length_errors++;
673 else
674 stats->rx_errors++;
675 dev_kfree_skb_irq(skb);
676 }
677 refill:
678 while ((dpriv->rx_dirty - dpriv->rx_current) % RX_RING_SIZE) {
679 if (try_get_rx_skb(dpriv, dev) < 0)
680 break;
681 dpriv->rx_dirty++;
682 }
683 dscc4_rx_update(dpriv, dev);
684 rx_fd->state2 = 0x00000000;
685 rx_fd->end = cpu_to_le32(0xbabeface);
686 }
687
688 static void dscc4_free1(struct pci_dev *pdev)
689 {
690 struct dscc4_pci_priv *ppriv;
691 struct dscc4_dev_priv *root;
692 int i;
693
694 ppriv = pci_get_drvdata(pdev);
695 root = ppriv->root;
696
697 for (i = 0; i < dev_per_card; i++)
698 unregister_hdlc_device(dscc4_to_dev(root + i));
699
700 pci_set_drvdata(pdev, NULL);
701
702 for (i = 0; i < dev_per_card; i++)
703 free_netdev(root[i].dev);
704 kfree(root);
705 kfree(ppriv);
706 }
707
708 static int __devinit dscc4_init_one(struct pci_dev *pdev,
709 const struct pci_device_id *ent)
710 {
711 struct dscc4_pci_priv *priv;
712 struct dscc4_dev_priv *dpriv;
713 void __iomem *ioaddr;
714 int i, rc;
715
716 printk(KERN_DEBUG "%s", version);
717
718 rc = pci_enable_device(pdev);
719 if (rc < 0)
720 goto out;
721
722 rc = pci_request_region(pdev, 0, "registers");
723 if (rc < 0) {
724 printk(KERN_ERR "%s: can't reserve MMIO region (regs)\n",
725 DRV_NAME);
726 goto err_disable_0;
727 }
728 rc = pci_request_region(pdev, 1, "LBI interface");
729 if (rc < 0) {
730 printk(KERN_ERR "%s: can't reserve MMIO region (lbi)\n",
731 DRV_NAME);
732 goto err_free_mmio_region_1;
733 }
734
735 ioaddr = ioremap(pci_resource_start(pdev, 0),
736 pci_resource_len(pdev, 0));
737 if (!ioaddr) {
738 printk(KERN_ERR "%s: cannot remap MMIO region %llx @ %llx\n",
739 DRV_NAME, (unsigned long long)pci_resource_len(pdev, 0),
740 (unsigned long long)pci_resource_start(pdev, 0));
741 rc = -EIO;
742 goto err_free_mmio_regions_2;
743 }
744 printk(KERN_DEBUG "Siemens DSCC4, MMIO at %#llx (regs), %#llx (lbi), IRQ %d\n",
745 (unsigned long long)pci_resource_start(pdev, 0),
746 (unsigned long long)pci_resource_start(pdev, 1), pdev->irq);
747
748 /* Cf errata DS5 p.2 */
749 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xf8);
750 pci_set_master(pdev);
751
752 rc = dscc4_found1(pdev, ioaddr);
753 if (rc < 0)
754 goto err_iounmap_3;
755
756 priv = pci_get_drvdata(pdev);
757
758 rc = request_irq(pdev->irq, dscc4_irq, IRQF_SHARED, DRV_NAME, priv->root);
759 if (rc < 0) {
760 printk(KERN_WARNING "%s: IRQ %d busy\n", DRV_NAME, pdev->irq);
761 goto err_release_4;
762 }
763
764 /* power up/little endian/dma core controlled via lrda/ltda */
765 writel(0x00000001, ioaddr + GMODE);
766 /* Shared interrupt queue */
767 {
768 u32 bits;
769
770 bits = (IRQ_RING_SIZE >> 5) - 1;
771 bits |= bits << 4;
772 bits |= bits << 8;
773 bits |= bits << 16;
774 writel(bits, ioaddr + IQLENR0);
775 }
776 /* Global interrupt queue */
777 writel((u32)(((IRQ_RING_SIZE >> 5) - 1) << 20), ioaddr + IQLENR1);
778 priv->iqcfg = (__le32 *) pci_alloc_consistent(pdev,
779 IRQ_RING_SIZE*sizeof(__le32), &priv->iqcfg_dma);
780 if (!priv->iqcfg)
781 goto err_free_irq_5;
782 writel(priv->iqcfg_dma, ioaddr + IQCFG);
783
784 rc = -ENOMEM;
785
786 /*
787 * SCC 0-3 private rx/tx irq structures
788 * IQRX/TXi needs to be set soon. Learned it the hard way...
789 */
790 for (i = 0; i < dev_per_card; i++) {
791 dpriv = priv->root + i;
792 dpriv->iqtx = (__le32 *) pci_alloc_consistent(pdev,
793 IRQ_RING_SIZE*sizeof(u32), &dpriv->iqtx_dma);
794 if (!dpriv->iqtx)
795 goto err_free_iqtx_6;
796 writel(dpriv->iqtx_dma, ioaddr + IQTX0 + i*4);
797 }
798 for (i = 0; i < dev_per_card; i++) {
799 dpriv = priv->root + i;
800 dpriv->iqrx = (__le32 *) pci_alloc_consistent(pdev,
801 IRQ_RING_SIZE*sizeof(u32), &dpriv->iqrx_dma);
802 if (!dpriv->iqrx)
803 goto err_free_iqrx_7;
804 writel(dpriv->iqrx_dma, ioaddr + IQRX0 + i*4);
805 }
806
807 /* Cf application hint. Beware of hard-lock condition on threshold. */
808 writel(0x42104000, ioaddr + FIFOCR1);
809 //writel(0x9ce69800, ioaddr + FIFOCR2);
810 writel(0xdef6d800, ioaddr + FIFOCR2);
811 //writel(0x11111111, ioaddr + FIFOCR4);
812 writel(0x18181818, ioaddr + FIFOCR4);
813 // FIXME: should depend on the chipset revision
814 writel(0x0000000e, ioaddr + FIFOCR3);
815
816 writel(0xff200001, ioaddr + GCMDR);
817
818 rc = 0;
819 out:
820 return rc;
821
822 err_free_iqrx_7:
823 while (--i >= 0) {
824 dpriv = priv->root + i;
825 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
826 dpriv->iqrx, dpriv->iqrx_dma);
827 }
828 i = dev_per_card;
829 err_free_iqtx_6:
830 while (--i >= 0) {
831 dpriv = priv->root + i;
832 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
833 dpriv->iqtx, dpriv->iqtx_dma);
834 }
835 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), priv->iqcfg,
836 priv->iqcfg_dma);
837 err_free_irq_5:
838 free_irq(pdev->irq, priv->root);
839 err_release_4:
840 dscc4_free1(pdev);
841 err_iounmap_3:
842 iounmap (ioaddr);
843 err_free_mmio_regions_2:
844 pci_release_region(pdev, 1);
845 err_free_mmio_region_1:
846 pci_release_region(pdev, 0);
847 err_disable_0:
848 pci_disable_device(pdev);
849 goto out;
850 };
851
852 /*
853 * Let's hope the default values are decent enough to protect my
854 * feet from the user's gun - Ueimor
855 */
856 static void dscc4_init_registers(struct dscc4_dev_priv *dpriv,
857 struct net_device *dev)
858 {
859 /* No interrupts, SCC core disabled. Let's relax */
860 scc_writel(0x00000000, dpriv, dev, CCR0);
861
862 scc_writel(LengthCheck | (HDLC_MAX_MRU >> 5), dpriv, dev, RLCR);
863
864 /*
865 * No address recognition/crc-CCITT/cts enabled
866 * Shared flags transmission disabled - cf errata DS5 p.11
867 * Carrier detect disabled - cf errata p.14
868 * FIXME: carrier detection/polarity may be handled more gracefully.
869 */
870 scc_writel(0x02408000, dpriv, dev, CCR1);
871
872 /* crc not forwarded - Cf errata DS5 p.11 */
873 scc_writel(0x00050008 & ~RxActivate, dpriv, dev, CCR2);
874 // crc forwarded
875 //scc_writel(0x00250008 & ~RxActivate, dpriv, dev, CCR2);
876 }
877
878 static inline int dscc4_set_quartz(struct dscc4_dev_priv *dpriv, int hz)
879 {
880 int ret = 0;
881
882 if ((hz < 0) || (hz > DSCC4_HZ_MAX))
883 ret = -EOPNOTSUPP;
884 else
885 dpriv->pci_priv->xtal_hz = hz;
886
887 return ret;
888 }
889
890 static int dscc4_found1(struct pci_dev *pdev, void __iomem *ioaddr)
891 {
892 struct dscc4_pci_priv *ppriv;
893 struct dscc4_dev_priv *root;
894 int i, ret = -ENOMEM;
895
896 root = kcalloc(dev_per_card, sizeof(*root), GFP_KERNEL);
897 if (!root) {
898 printk(KERN_ERR "%s: can't allocate data\n", DRV_NAME);
899 goto err_out;
900 }
901
902 for (i = 0; i < dev_per_card; i++) {
903 root[i].dev = alloc_hdlcdev(root + i);
904 if (!root[i].dev)
905 goto err_free_dev;
906 }
907
908 ppriv = kzalloc(sizeof(*ppriv), GFP_KERNEL);
909 if (!ppriv) {
910 printk(KERN_ERR "%s: can't allocate private data\n", DRV_NAME);
911 goto err_free_dev;
912 }
913
914 ppriv->root = root;
915 spin_lock_init(&ppriv->lock);
916
917 for (i = 0; i < dev_per_card; i++) {
918 struct dscc4_dev_priv *dpriv = root + i;
919 struct net_device *d = dscc4_to_dev(dpriv);
920 hdlc_device *hdlc = dev_to_hdlc(d);
921
922 d->base_addr = (unsigned long)ioaddr;
923 d->init = NULL;
924 d->irq = pdev->irq;
925 d->open = dscc4_open;
926 d->stop = dscc4_close;
927 d->set_multicast_list = NULL;
928 d->do_ioctl = dscc4_ioctl;
929 d->tx_timeout = dscc4_tx_timeout;
930 d->watchdog_timeo = TX_TIMEOUT;
931 SET_NETDEV_DEV(d, &pdev->dev);
932
933 dpriv->dev_id = i;
934 dpriv->pci_priv = ppriv;
935 dpriv->base_addr = ioaddr;
936 spin_lock_init(&dpriv->lock);
937
938 hdlc->xmit = dscc4_start_xmit;
939 hdlc->attach = dscc4_hdlc_attach;
940
941 dscc4_init_registers(dpriv, d);
942 dpriv->parity = PARITY_CRC16_PR0_CCITT;
943 dpriv->encoding = ENCODING_NRZ;
944
945 ret = dscc4_init_ring(d);
946 if (ret < 0)
947 goto err_unregister;
948
949 ret = register_hdlc_device(d);
950 if (ret < 0) {
951 printk(KERN_ERR "%s: unable to register\n", DRV_NAME);
952 dscc4_release_ring(dpriv);
953 goto err_unregister;
954 }
955 }
956
957 ret = dscc4_set_quartz(root, quartz);
958 if (ret < 0)
959 goto err_unregister;
960
961 pci_set_drvdata(pdev, ppriv);
962 return ret;
963
964 err_unregister:
965 while (i-- > 0) {
966 dscc4_release_ring(root + i);
967 unregister_hdlc_device(dscc4_to_dev(root + i));
968 }
969 kfree(ppriv);
970 i = dev_per_card;
971 err_free_dev:
972 while (i-- > 0)
973 free_netdev(root[i].dev);
974 kfree(root);
975 err_out:
976 return ret;
977 };
978
979 /* FIXME: get rid of the unneeded code */
980 static void dscc4_timer(unsigned long data)
981 {
982 struct net_device *dev = (struct net_device *)data;
983 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
984 // struct dscc4_pci_priv *ppriv;
985
986 goto done;
987 done:
988 dpriv->timer.expires = jiffies + TX_TIMEOUT;
989 add_timer(&dpriv->timer);
990 }
991
992 static void dscc4_tx_timeout(struct net_device *dev)
993 {
994 /* FIXME: something is missing there */
995 }
996
997 static int dscc4_loopback_check(struct dscc4_dev_priv *dpriv)
998 {
999 sync_serial_settings *settings = &dpriv->settings;
1000
1001 if (settings->loopback && (settings->clock_type != CLOCK_INT)) {
1002 struct net_device *dev = dscc4_to_dev(dpriv);
1003
1004 printk(KERN_INFO "%s: loopback requires clock\n", dev->name);
1005 return -1;
1006 }
1007 return 0;
1008 }
1009
1010 #ifdef CONFIG_DSCC4_PCI_RST
1011 /*
1012 * Some DSCC4-based cards wires the GPIO port and the PCI #RST pin together
1013 * so as to provide a safe way to reset the asic while not the whole machine
1014 * rebooting.
1015 *
1016 * This code doesn't need to be efficient. Keep It Simple
1017 */
1018 static void dscc4_pci_reset(struct pci_dev *pdev, void __iomem *ioaddr)
1019 {
1020 int i;
1021
1022 mutex_lock(&dscc4_mutex);
1023 for (i = 0; i < 16; i++)
1024 pci_read_config_dword(pdev, i << 2, dscc4_pci_config_store + i);
1025
1026 /* Maximal LBI clock divider (who cares ?) and whole GPIO range. */
1027 writel(0x001c0000, ioaddr + GMODE);
1028 /* Configure GPIO port as output */
1029 writel(0x0000ffff, ioaddr + GPDIR);
1030 /* Disable interruption */
1031 writel(0x0000ffff, ioaddr + GPIM);
1032
1033 writel(0x0000ffff, ioaddr + GPDATA);
1034 writel(0x00000000, ioaddr + GPDATA);
1035
1036 /* Flush posted writes */
1037 readl(ioaddr + GSTAR);
1038
1039 schedule_timeout_uninterruptible(10);
1040
1041 for (i = 0; i < 16; i++)
1042 pci_write_config_dword(pdev, i << 2, dscc4_pci_config_store[i]);
1043 mutex_unlock(&dscc4_mutex);
1044 }
1045 #else
1046 #define dscc4_pci_reset(pdev,ioaddr) do {} while (0)
1047 #endif /* CONFIG_DSCC4_PCI_RST */
1048
1049 static int dscc4_open(struct net_device *dev)
1050 {
1051 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1052 struct dscc4_pci_priv *ppriv;
1053 int ret = -EAGAIN;
1054
1055 if ((dscc4_loopback_check(dpriv) < 0) || !dev->hard_start_xmit)
1056 goto err;
1057
1058 if ((ret = hdlc_open(dev)))
1059 goto err;
1060
1061 ppriv = dpriv->pci_priv;
1062
1063 /*
1064 * Due to various bugs, there is no way to reliably reset a
1065 * specific port (manufacturer's dependant special PCI #RST wiring
1066 * apart: it affects all ports). Thus the device goes in the best
1067 * silent mode possible at dscc4_close() time and simply claims to
1068 * be up if it's opened again. It still isn't possible to change
1069 * the HDLC configuration without rebooting but at least the ports
1070 * can be up/down ifconfig'ed without killing the host.
1071 */
1072 if (dpriv->flags & FakeReset) {
1073 dpriv->flags &= ~FakeReset;
1074 scc_patchl(0, PowerUp, dpriv, dev, CCR0);
1075 scc_patchl(0, 0x00050000, dpriv, dev, CCR2);
1076 scc_writel(EventsMask, dpriv, dev, IMR);
1077 printk(KERN_INFO "%s: up again.\n", dev->name);
1078 goto done;
1079 }
1080
1081 /* IDT+IDR during XPR */
1082 dpriv->flags = NeedIDR | NeedIDT;
1083
1084 scc_patchl(0, PowerUp | Vis, dpriv, dev, CCR0);
1085
1086 /*
1087 * The following is a bit paranoid...
1088 *
1089 * NB: the datasheet "...CEC will stay active if the SCC is in
1090 * power-down mode or..." and CCR2.RAC = 1 are two different
1091 * situations.
1092 */
1093 if (scc_readl_star(dpriv, dev) & SccBusy) {
1094 printk(KERN_ERR "%s busy. Try later\n", dev->name);
1095 ret = -EAGAIN;
1096 goto err_out;
1097 } else
1098 printk(KERN_INFO "%s: available. Good\n", dev->name);
1099
1100 scc_writel(EventsMask, dpriv, dev, IMR);
1101
1102 /* Posted write is flushed in the wait_ack loop */
1103 scc_writel(TxSccRes | RxSccRes, dpriv, dev, CMDR);
1104
1105 if ((ret = dscc4_wait_ack_cec(dpriv, dev, "Cec")) < 0)
1106 goto err_disable_scc_events;
1107
1108 /*
1109 * I would expect XPR near CE completion (before ? after ?).
1110 * At worst, this code won't see a late XPR and people
1111 * will have to re-issue an ifconfig (this is harmless).
1112 * WARNING, a really missing XPR usually means a hardware
1113 * reset is needed. Suggestions anyone ?
1114 */
1115 if ((ret = dscc4_xpr_ack(dpriv)) < 0) {
1116 printk(KERN_ERR "%s: %s timeout\n", DRV_NAME, "XPR");
1117 goto err_disable_scc_events;
1118 }
1119
1120 if (debug > 2)
1121 dscc4_tx_print(dev, dpriv, "Open");
1122
1123 done:
1124 netif_start_queue(dev);
1125
1126 init_timer(&dpriv->timer);
1127 dpriv->timer.expires = jiffies + 10*HZ;
1128 dpriv->timer.data = (unsigned long)dev;
1129 dpriv->timer.function = &dscc4_timer;
1130 add_timer(&dpriv->timer);
1131 netif_carrier_on(dev);
1132
1133 return 0;
1134
1135 err_disable_scc_events:
1136 scc_writel(0xffffffff, dpriv, dev, IMR);
1137 scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
1138 err_out:
1139 hdlc_close(dev);
1140 err:
1141 return ret;
1142 }
1143
1144 #ifdef DSCC4_POLLING
1145 static int dscc4_tx_poll(struct dscc4_dev_priv *dpriv, struct net_device *dev)
1146 {
1147 /* FIXME: it's gonna be easy (TM), for sure */
1148 }
1149 #endif /* DSCC4_POLLING */
1150
1151 static int dscc4_start_xmit(struct sk_buff *skb, struct net_device *dev)
1152 {
1153 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1154 struct dscc4_pci_priv *ppriv = dpriv->pci_priv;
1155 struct TxFD *tx_fd;
1156 int next;
1157
1158 next = dpriv->tx_current%TX_RING_SIZE;
1159 dpriv->tx_skbuff[next] = skb;
1160 tx_fd = dpriv->tx_fd + next;
1161 tx_fd->state = FrameEnd | TO_STATE_TX(skb->len);
1162 tx_fd->data = cpu_to_le32(pci_map_single(ppriv->pdev, skb->data, skb->len,
1163 PCI_DMA_TODEVICE));
1164 tx_fd->complete = 0x00000000;
1165 tx_fd->jiffies = jiffies;
1166 mb();
1167
1168 #ifdef DSCC4_POLLING
1169 spin_lock(&dpriv->lock);
1170 while (dscc4_tx_poll(dpriv, dev));
1171 spin_unlock(&dpriv->lock);
1172 #endif
1173
1174 dev->trans_start = jiffies;
1175
1176 if (debug > 2)
1177 dscc4_tx_print(dev, dpriv, "Xmit");
1178 /* To be cleaned(unsigned int)/optimized. Later, ok ? */
1179 if (!((++dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE))
1180 netif_stop_queue(dev);
1181
1182 if (dscc4_tx_quiescent(dpriv, dev))
1183 dscc4_do_tx(dpriv, dev);
1184
1185 return 0;
1186 }
1187
1188 static int dscc4_close(struct net_device *dev)
1189 {
1190 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1191
1192 del_timer_sync(&dpriv->timer);
1193 netif_stop_queue(dev);
1194
1195 scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
1196 scc_patchl(0x00050000, 0, dpriv, dev, CCR2);
1197 scc_writel(0xffffffff, dpriv, dev, IMR);
1198
1199 dpriv->flags |= FakeReset;
1200
1201 hdlc_close(dev);
1202
1203 return 0;
1204 }
1205
1206 static inline int dscc4_check_clock_ability(int port)
1207 {
1208 int ret = 0;
1209
1210 #ifdef CONFIG_DSCC4_PCISYNC
1211 if (port >= 2)
1212 ret = -1;
1213 #endif
1214 return ret;
1215 }
1216
1217 /*
1218 * DS1 p.137: "There are a total of 13 different clocking modes..."
1219 * ^^
1220 * Design choices:
1221 * - by default, assume a clock is provided on pin RxClk/TxClk (clock mode 0a).
1222 * Clock mode 3b _should_ work but the testing seems to make this point
1223 * dubious (DIY testing requires setting CCR0 at 0x00000033).
1224 * This is supposed to provide least surprise "DTE like" behavior.
1225 * - if line rate is specified, clocks are assumed to be locally generated.
1226 * A quartz must be available (on pin XTAL1). Modes 6b/7b are used. Choosing
1227 * between these it automagically done according on the required frequency
1228 * scaling. Of course some rounding may take place.
1229 * - no high speed mode (40Mb/s). May be trivial to do but I don't have an
1230 * appropriate external clocking device for testing.
1231 * - no time-slot/clock mode 5: shameless lazyness.
1232 *
1233 * The clock signals wiring can be (is ?) manufacturer dependant. Good luck.
1234 *
1235 * BIG FAT WARNING: if the device isn't provided enough clocking signal, it
1236 * won't pass the init sequence. For example, straight back-to-back DTE without
1237 * external clock will fail when dscc4_open() (<- 'ifconfig hdlcx xxx') is
1238 * called.
1239 *
1240 * Typos lurk in datasheet (missing divier in clock mode 7a figure 51 p.153
1241 * DS0 for example)
1242 *
1243 * Clock mode related bits of CCR0:
1244 * +------------ TOE: output TxClk (0b/2b/3a/3b/6b/7a/7b only)
1245 * | +---------- SSEL: sub-mode select 0 -> a, 1 -> b
1246 * | | +-------- High Speed: say 0
1247 * | | | +-+-+-- Clock Mode: 0..7
1248 * | | | | | |
1249 * -+-+-+-+-+-+-+-+
1250 * x|x|5|4|3|2|1|0| lower bits
1251 *
1252 * Division factor of BRR: k = (N+1)x2^M (total divider = 16xk in mode 6b)
1253 * +-+-+-+------------------ M (0..15)
1254 * | | | | +-+-+-+-+-+-- N (0..63)
1255 * 0 0 0 0 | | | | 0 0 | | | | | |
1256 * ...-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1257 * f|e|d|c|b|a|9|8|7|6|5|4|3|2|1|0| lower bits
1258 *
1259 */
1260 static int dscc4_set_clock(struct net_device *dev, u32 *bps, u32 *state)
1261 {
1262 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1263 int ret = -1;
1264 u32 brr;
1265
1266 *state &= ~Ccr0ClockMask;
1267 if (*bps) { /* Clock generated - required for DCE */
1268 u32 n = 0, m = 0, divider;
1269 int xtal;
1270
1271 xtal = dpriv->pci_priv->xtal_hz;
1272 if (!xtal)
1273 goto done;
1274 if (dscc4_check_clock_ability(dpriv->dev_id) < 0)
1275 goto done;
1276 divider = xtal / *bps;
1277 if (divider > BRR_DIVIDER_MAX) {
1278 divider >>= 4;
1279 *state |= 0x00000036; /* Clock mode 6b (BRG/16) */
1280 } else
1281 *state |= 0x00000037; /* Clock mode 7b (BRG) */
1282 if (divider >> 22) {
1283 n = 63;
1284 m = 15;
1285 } else if (divider) {
1286 /* Extraction of the 6 highest weighted bits */
1287 m = 0;
1288 while (0xffffffc0 & divider) {
1289 m++;
1290 divider >>= 1;
1291 }
1292 n = divider;
1293 }
1294 brr = (m << 8) | n;
1295 divider = n << m;
1296 if (!(*state & 0x00000001)) /* ?b mode mask => clock mode 6b */
1297 divider <<= 4;
1298 *bps = xtal / divider;
1299 } else {
1300 /*
1301 * External clock - DTE
1302 * "state" already reflects Clock mode 0a (CCR0 = 0xzzzzzz00).
1303 * Nothing more to be done
1304 */
1305 brr = 0;
1306 }
1307 scc_writel(brr, dpriv, dev, BRR);
1308 ret = 0;
1309 done:
1310 return ret;
1311 }
1312
1313 static int dscc4_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1314 {
1315 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1316 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1317 const size_t size = sizeof(dpriv->settings);
1318 int ret = 0;
1319
1320 if (dev->flags & IFF_UP)
1321 return -EBUSY;
1322
1323 if (cmd != SIOCWANDEV)
1324 return -EOPNOTSUPP;
1325
1326 switch(ifr->ifr_settings.type) {
1327 case IF_GET_IFACE:
1328 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1329 if (ifr->ifr_settings.size < size) {
1330 ifr->ifr_settings.size = size; /* data size wanted */
1331 return -ENOBUFS;
1332 }
1333 if (copy_to_user(line, &dpriv->settings, size))
1334 return -EFAULT;
1335 break;
1336
1337 case IF_IFACE_SYNC_SERIAL:
1338 if (!capable(CAP_NET_ADMIN))
1339 return -EPERM;
1340
1341 if (dpriv->flags & FakeReset) {
1342 printk(KERN_INFO "%s: please reset the device"
1343 " before this command\n", dev->name);
1344 return -EPERM;
1345 }
1346 if (copy_from_user(&dpriv->settings, line, size))
1347 return -EFAULT;
1348 ret = dscc4_set_iface(dpriv, dev);
1349 break;
1350
1351 default:
1352 ret = hdlc_ioctl(dev, ifr, cmd);
1353 break;
1354 }
1355
1356 return ret;
1357 }
1358
1359 static int dscc4_match(struct thingie *p, int value)
1360 {
1361 int i;
1362
1363 for (i = 0; p[i].define != -1; i++) {
1364 if (value == p[i].define)
1365 break;
1366 }
1367 if (p[i].define == -1)
1368 return -1;
1369 else
1370 return i;
1371 }
1372
1373 static int dscc4_clock_setting(struct dscc4_dev_priv *dpriv,
1374 struct net_device *dev)
1375 {
1376 sync_serial_settings *settings = &dpriv->settings;
1377 int ret = -EOPNOTSUPP;
1378 u32 bps, state;
1379
1380 bps = settings->clock_rate;
1381 state = scc_readl(dpriv, CCR0);
1382 if (dscc4_set_clock(dev, &bps, &state) < 0)
1383 goto done;
1384 if (bps) { /* DCE */
1385 printk(KERN_DEBUG "%s: generated RxClk (DCE)\n", dev->name);
1386 if (settings->clock_rate != bps) {
1387 printk(KERN_DEBUG "%s: clock adjusted (%08d -> %08d)\n",
1388 dev->name, settings->clock_rate, bps);
1389 settings->clock_rate = bps;
1390 }
1391 } else { /* DTE */
1392 state |= PowerUp | Vis;
1393 printk(KERN_DEBUG "%s: external RxClk (DTE)\n", dev->name);
1394 }
1395 scc_writel(state, dpriv, dev, CCR0);
1396 ret = 0;
1397 done:
1398 return ret;
1399 }
1400
1401 static int dscc4_encoding_setting(struct dscc4_dev_priv *dpriv,
1402 struct net_device *dev)
1403 {
1404 struct thingie encoding[] = {
1405 { ENCODING_NRZ, 0x00000000 },
1406 { ENCODING_NRZI, 0x00200000 },
1407 { ENCODING_FM_MARK, 0x00400000 },
1408 { ENCODING_FM_SPACE, 0x00500000 },
1409 { ENCODING_MANCHESTER, 0x00600000 },
1410 { -1, 0}
1411 };
1412 int i, ret = 0;
1413
1414 i = dscc4_match(encoding, dpriv->encoding);
1415 if (i >= 0)
1416 scc_patchl(EncodingMask, encoding[i].bits, dpriv, dev, CCR0);
1417 else
1418 ret = -EOPNOTSUPP;
1419 return ret;
1420 }
1421
1422 static int dscc4_loopback_setting(struct dscc4_dev_priv *dpriv,
1423 struct net_device *dev)
1424 {
1425 sync_serial_settings *settings = &dpriv->settings;
1426 u32 state;
1427
1428 state = scc_readl(dpriv, CCR1);
1429 if (settings->loopback) {
1430 printk(KERN_DEBUG "%s: loopback\n", dev->name);
1431 state |= 0x00000100;
1432 } else {
1433 printk(KERN_DEBUG "%s: normal\n", dev->name);
1434 state &= ~0x00000100;
1435 }
1436 scc_writel(state, dpriv, dev, CCR1);
1437 return 0;
1438 }
1439
1440 static int dscc4_crc_setting(struct dscc4_dev_priv *dpriv,
1441 struct net_device *dev)
1442 {
1443 struct thingie crc[] = {
1444 { PARITY_CRC16_PR0_CCITT, 0x00000010 },
1445 { PARITY_CRC16_PR1_CCITT, 0x00000000 },
1446 { PARITY_CRC32_PR0_CCITT, 0x00000011 },
1447 { PARITY_CRC32_PR1_CCITT, 0x00000001 }
1448 };
1449 int i, ret = 0;
1450
1451 i = dscc4_match(crc, dpriv->parity);
1452 if (i >= 0)
1453 scc_patchl(CrcMask, crc[i].bits, dpriv, dev, CCR1);
1454 else
1455 ret = -EOPNOTSUPP;
1456 return ret;
1457 }
1458
1459 static int dscc4_set_iface(struct dscc4_dev_priv *dpriv, struct net_device *dev)
1460 {
1461 struct {
1462 int (*action)(struct dscc4_dev_priv *, struct net_device *);
1463 } *p, do_setting[] = {
1464 { dscc4_encoding_setting },
1465 { dscc4_clock_setting },
1466 { dscc4_loopback_setting },
1467 { dscc4_crc_setting },
1468 { NULL }
1469 };
1470 int ret = 0;
1471
1472 for (p = do_setting; p->action; p++) {
1473 if ((ret = p->action(dpriv, dev)) < 0)
1474 break;
1475 }
1476 return ret;
1477 }
1478
1479 static irqreturn_t dscc4_irq(int irq, void *token)
1480 {
1481 struct dscc4_dev_priv *root = token;
1482 struct dscc4_pci_priv *priv;
1483 struct net_device *dev;
1484 void __iomem *ioaddr;
1485 u32 state;
1486 unsigned long flags;
1487 int i, handled = 1;
1488
1489 priv = root->pci_priv;
1490 dev = dscc4_to_dev(root);
1491
1492 spin_lock_irqsave(&priv->lock, flags);
1493
1494 ioaddr = root->base_addr;
1495
1496 state = readl(ioaddr + GSTAR);
1497 if (!state) {
1498 handled = 0;
1499 goto out;
1500 }
1501 if (debug > 3)
1502 printk(KERN_DEBUG "%s: GSTAR = 0x%08x\n", DRV_NAME, state);
1503 writel(state, ioaddr + GSTAR);
1504
1505 if (state & Arf) {
1506 printk(KERN_ERR "%s: failure (Arf). Harass the maintener\n",
1507 dev->name);
1508 goto out;
1509 }
1510 state &= ~ArAck;
1511 if (state & Cfg) {
1512 if (debug > 0)
1513 printk(KERN_DEBUG "%s: CfgIV\n", DRV_NAME);
1514 if (priv->iqcfg[priv->cfg_cur++%IRQ_RING_SIZE] & cpu_to_le32(Arf))
1515 printk(KERN_ERR "%s: %s failed\n", dev->name, "CFG");
1516 if (!(state &= ~Cfg))
1517 goto out;
1518 }
1519 if (state & RxEvt) {
1520 i = dev_per_card - 1;
1521 do {
1522 dscc4_rx_irq(priv, root + i);
1523 } while (--i >= 0);
1524 state &= ~RxEvt;
1525 }
1526 if (state & TxEvt) {
1527 i = dev_per_card - 1;
1528 do {
1529 dscc4_tx_irq(priv, root + i);
1530 } while (--i >= 0);
1531 state &= ~TxEvt;
1532 }
1533 out:
1534 spin_unlock_irqrestore(&priv->lock, flags);
1535 return IRQ_RETVAL(handled);
1536 }
1537
1538 static void dscc4_tx_irq(struct dscc4_pci_priv *ppriv,
1539 struct dscc4_dev_priv *dpriv)
1540 {
1541 struct net_device *dev = dscc4_to_dev(dpriv);
1542 u32 state;
1543 int cur, loop = 0;
1544
1545 try:
1546 cur = dpriv->iqtx_current%IRQ_RING_SIZE;
1547 state = le32_to_cpu(dpriv->iqtx[cur]);
1548 if (!state) {
1549 if (debug > 4)
1550 printk(KERN_DEBUG "%s: Tx ISR = 0x%08x\n", dev->name,
1551 state);
1552 if ((debug > 1) && (loop > 1))
1553 printk(KERN_DEBUG "%s: Tx irq loop=%d\n", dev->name, loop);
1554 if (loop && netif_queue_stopped(dev))
1555 if ((dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE)
1556 netif_wake_queue(dev);
1557
1558 if (netif_running(dev) && dscc4_tx_quiescent(dpriv, dev) &&
1559 !dscc4_tx_done(dpriv))
1560 dscc4_do_tx(dpriv, dev);
1561 return;
1562 }
1563 loop++;
1564 dpriv->iqtx[cur] = 0;
1565 dpriv->iqtx_current++;
1566
1567 if (state_check(state, dpriv, dev, "Tx") < 0)
1568 return;
1569
1570 if (state & SccEvt) {
1571 if (state & Alls) {
1572 struct net_device_stats *stats = hdlc_stats(dev);
1573 struct sk_buff *skb;
1574 struct TxFD *tx_fd;
1575
1576 if (debug > 2)
1577 dscc4_tx_print(dev, dpriv, "Alls");
1578 /*
1579 * DataComplete can't be trusted for Tx completion.
1580 * Cf errata DS5 p.8
1581 */
1582 cur = dpriv->tx_dirty%TX_RING_SIZE;
1583 tx_fd = dpriv->tx_fd + cur;
1584 skb = dpriv->tx_skbuff[cur];
1585 if (skb) {
1586 pci_unmap_single(ppriv->pdev, le32_to_cpu(tx_fd->data),
1587 skb->len, PCI_DMA_TODEVICE);
1588 if (tx_fd->state & FrameEnd) {
1589 stats->tx_packets++;
1590 stats->tx_bytes += skb->len;
1591 }
1592 dev_kfree_skb_irq(skb);
1593 dpriv->tx_skbuff[cur] = NULL;
1594 ++dpriv->tx_dirty;
1595 } else {
1596 if (debug > 1)
1597 printk(KERN_ERR "%s Tx: NULL skb %d\n",
1598 dev->name, cur);
1599 }
1600 /*
1601 * If the driver ends sending crap on the wire, it
1602 * will be way easier to diagnose than the (not so)
1603 * random freeze induced by null sized tx frames.
1604 */
1605 tx_fd->data = tx_fd->next;
1606 tx_fd->state = FrameEnd | TO_STATE_TX(2*DUMMY_SKB_SIZE);
1607 tx_fd->complete = 0x00000000;
1608 tx_fd->jiffies = 0;
1609
1610 if (!(state &= ~Alls))
1611 goto try;
1612 }
1613 /*
1614 * Transmit Data Underrun
1615 */
1616 if (state & Xdu) {
1617 printk(KERN_ERR "%s: XDU. Ask maintainer\n", DRV_NAME);
1618 dpriv->flags = NeedIDT;
1619 /* Tx reset */
1620 writel(MTFi | Rdt,
1621 dpriv->base_addr + 0x0c*dpriv->dev_id + CH0CFG);
1622 writel(Action, dpriv->base_addr + GCMDR);
1623 return;
1624 }
1625 if (state & Cts) {
1626 printk(KERN_INFO "%s: CTS transition\n", dev->name);
1627 if (!(state &= ~Cts)) /* DEBUG */
1628 goto try;
1629 }
1630 if (state & Xmr) {
1631 /* Frame needs to be sent again - FIXME */
1632 printk(KERN_ERR "%s: Xmr. Ask maintainer\n", DRV_NAME);
1633 if (!(state &= ~Xmr)) /* DEBUG */
1634 goto try;
1635 }
1636 if (state & Xpr) {
1637 void __iomem *scc_addr;
1638 unsigned long ring;
1639 int i;
1640
1641 /*
1642 * - the busy condition happens (sometimes);
1643 * - it doesn't seem to make the handler unreliable.
1644 */
1645 for (i = 1; i; i <<= 1) {
1646 if (!(scc_readl_star(dpriv, dev) & SccBusy))
1647 break;
1648 }
1649 if (!i)
1650 printk(KERN_INFO "%s busy in irq\n", dev->name);
1651
1652 scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id;
1653 /* Keep this order: IDT before IDR */
1654 if (dpriv->flags & NeedIDT) {
1655 if (debug > 2)
1656 dscc4_tx_print(dev, dpriv, "Xpr");
1657 ring = dpriv->tx_fd_dma +
1658 (dpriv->tx_dirty%TX_RING_SIZE)*
1659 sizeof(struct TxFD);
1660 writel(ring, scc_addr + CH0BTDA);
1661 dscc4_do_tx(dpriv, dev);
1662 writel(MTFi | Idt, scc_addr + CH0CFG);
1663 if (dscc4_do_action(dev, "IDT") < 0)
1664 goto err_xpr;
1665 dpriv->flags &= ~NeedIDT;
1666 }
1667 if (dpriv->flags & NeedIDR) {
1668 ring = dpriv->rx_fd_dma +
1669 (dpriv->rx_current%RX_RING_SIZE)*
1670 sizeof(struct RxFD);
1671 writel(ring, scc_addr + CH0BRDA);
1672 dscc4_rx_update(dpriv, dev);
1673 writel(MTFi | Idr, scc_addr + CH0CFG);
1674 if (dscc4_do_action(dev, "IDR") < 0)
1675 goto err_xpr;
1676 dpriv->flags &= ~NeedIDR;
1677 smp_wmb();
1678 /* Activate receiver and misc */
1679 scc_writel(0x08050008, dpriv, dev, CCR2);
1680 }
1681 err_xpr:
1682 if (!(state &= ~Xpr))
1683 goto try;
1684 }
1685 if (state & Cd) {
1686 if (debug > 0)
1687 printk(KERN_INFO "%s: CD transition\n", dev->name);
1688 if (!(state &= ~Cd)) /* DEBUG */
1689 goto try;
1690 }
1691 } else { /* ! SccEvt */
1692 if (state & Hi) {
1693 #ifdef DSCC4_POLLING
1694 while (!dscc4_tx_poll(dpriv, dev));
1695 #endif
1696 printk(KERN_INFO "%s: Tx Hi\n", dev->name);
1697 state &= ~Hi;
1698 }
1699 if (state & Err) {
1700 printk(KERN_INFO "%s: Tx ERR\n", dev->name);
1701 hdlc_stats(dev)->tx_errors++;
1702 state &= ~Err;
1703 }
1704 }
1705 goto try;
1706 }
1707
1708 static void dscc4_rx_irq(struct dscc4_pci_priv *priv,
1709 struct dscc4_dev_priv *dpriv)
1710 {
1711 struct net_device *dev = dscc4_to_dev(dpriv);
1712 u32 state;
1713 int cur;
1714
1715 try:
1716 cur = dpriv->iqrx_current%IRQ_RING_SIZE;
1717 state = le32_to_cpu(dpriv->iqrx[cur]);
1718 if (!state)
1719 return;
1720 dpriv->iqrx[cur] = 0;
1721 dpriv->iqrx_current++;
1722
1723 if (state_check(state, dpriv, dev, "Rx") < 0)
1724 return;
1725
1726 if (!(state & SccEvt)){
1727 struct RxFD *rx_fd;
1728
1729 if (debug > 4)
1730 printk(KERN_DEBUG "%s: Rx ISR = 0x%08x\n", dev->name,
1731 state);
1732 state &= 0x00ffffff;
1733 if (state & Err) { /* Hold or reset */
1734 printk(KERN_DEBUG "%s: Rx ERR\n", dev->name);
1735 cur = dpriv->rx_current%RX_RING_SIZE;
1736 rx_fd = dpriv->rx_fd + cur;
1737 /*
1738 * Presume we're not facing a DMAC receiver reset.
1739 * As We use the rx size-filtering feature of the
1740 * DSCC4, the beginning of a new frame is waiting in
1741 * the rx fifo. I bet a Receive Data Overflow will
1742 * happen most of time but let's try and avoid it.
1743 * Btw (as for RDO) if one experiences ERR whereas
1744 * the system looks rather idle, there may be a
1745 * problem with latency. In this case, increasing
1746 * RX_RING_SIZE may help.
1747 */
1748 //while (dpriv->rx_needs_refill) {
1749 while (!(rx_fd->state1 & Hold)) {
1750 rx_fd++;
1751 cur++;
1752 if (!(cur = cur%RX_RING_SIZE))
1753 rx_fd = dpriv->rx_fd;
1754 }
1755 //dpriv->rx_needs_refill--;
1756 try_get_rx_skb(dpriv, dev);
1757 if (!rx_fd->data)
1758 goto try;
1759 rx_fd->state1 &= ~Hold;
1760 rx_fd->state2 = 0x00000000;
1761 rx_fd->end = cpu_to_le32(0xbabeface);
1762 //}
1763 goto try;
1764 }
1765 if (state & Fi) {
1766 dscc4_rx_skb(dpriv, dev);
1767 goto try;
1768 }
1769 if (state & Hi ) { /* HI bit */
1770 printk(KERN_INFO "%s: Rx Hi\n", dev->name);
1771 state &= ~Hi;
1772 goto try;
1773 }
1774 } else { /* SccEvt */
1775 if (debug > 1) {
1776 //FIXME: verifier la presence de tous les evenements
1777 static struct {
1778 u32 mask;
1779 const char *irq_name;
1780 } evts[] = {
1781 { 0x00008000, "TIN"},
1782 { 0x00000020, "RSC"},
1783 { 0x00000010, "PCE"},
1784 { 0x00000008, "PLLA"},
1785 { 0, NULL}
1786 }, *evt;
1787
1788 for (evt = evts; evt->irq_name; evt++) {
1789 if (state & evt->mask) {
1790 printk(KERN_DEBUG "%s: %s\n",
1791 dev->name, evt->irq_name);
1792 if (!(state &= ~evt->mask))
1793 goto try;
1794 }
1795 }
1796 } else {
1797 if (!(state &= ~0x0000c03c))
1798 goto try;
1799 }
1800 if (state & Cts) {
1801 printk(KERN_INFO "%s: CTS transition\n", dev->name);
1802 if (!(state &= ~Cts)) /* DEBUG */
1803 goto try;
1804 }
1805 /*
1806 * Receive Data Overflow (FIXME: fscked)
1807 */
1808 if (state & Rdo) {
1809 struct RxFD *rx_fd;
1810 void __iomem *scc_addr;
1811 int cur;
1812
1813 //if (debug)
1814 // dscc4_rx_dump(dpriv);
1815 scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id;
1816
1817 scc_patchl(RxActivate, 0, dpriv, dev, CCR2);
1818 /*
1819 * This has no effect. Why ?
1820 * ORed with TxSccRes, one sees the CFG ack (for
1821 * the TX part only).
1822 */
1823 scc_writel(RxSccRes, dpriv, dev, CMDR);
1824 dpriv->flags |= RdoSet;
1825
1826 /*
1827 * Let's try and save something in the received data.
1828 * rx_current must be incremented at least once to
1829 * avoid HOLD in the BRDA-to-be-pointed desc.
1830 */
1831 do {
1832 cur = dpriv->rx_current++%RX_RING_SIZE;
1833 rx_fd = dpriv->rx_fd + cur;
1834 if (!(rx_fd->state2 & DataComplete))
1835 break;
1836 if (rx_fd->state2 & FrameAborted) {
1837 hdlc_stats(dev)->rx_over_errors++;
1838 rx_fd->state1 |= Hold;
1839 rx_fd->state2 = 0x00000000;
1840 rx_fd->end = cpu_to_le32(0xbabeface);
1841 } else
1842 dscc4_rx_skb(dpriv, dev);
1843 } while (1);
1844
1845 if (debug > 0) {
1846 if (dpriv->flags & RdoSet)
1847 printk(KERN_DEBUG
1848 "%s: no RDO in Rx data\n", DRV_NAME);
1849 }
1850 #ifdef DSCC4_RDO_EXPERIMENTAL_RECOVERY
1851 /*
1852 * FIXME: must the reset be this violent ?
1853 */
1854 #warning "FIXME: CH0BRDA"
1855 writel(dpriv->rx_fd_dma +
1856 (dpriv->rx_current%RX_RING_SIZE)*
1857 sizeof(struct RxFD), scc_addr + CH0BRDA);
1858 writel(MTFi|Rdr|Idr, scc_addr + CH0CFG);
1859 if (dscc4_do_action(dev, "RDR") < 0) {
1860 printk(KERN_ERR "%s: RDO recovery failed(%s)\n",
1861 dev->name, "RDR");
1862 goto rdo_end;
1863 }
1864 writel(MTFi|Idr, scc_addr + CH0CFG);
1865 if (dscc4_do_action(dev, "IDR") < 0) {
1866 printk(KERN_ERR "%s: RDO recovery failed(%s)\n",
1867 dev->name, "IDR");
1868 goto rdo_end;
1869 }
1870 rdo_end:
1871 #endif
1872 scc_patchl(0, RxActivate, dpriv, dev, CCR2);
1873 goto try;
1874 }
1875 if (state & Cd) {
1876 printk(KERN_INFO "%s: CD transition\n", dev->name);
1877 if (!(state &= ~Cd)) /* DEBUG */
1878 goto try;
1879 }
1880 if (state & Flex) {
1881 printk(KERN_DEBUG "%s: Flex. Ttttt...\n", DRV_NAME);
1882 if (!(state &= ~Flex))
1883 goto try;
1884 }
1885 }
1886 }
1887
1888 /*
1889 * I had expected the following to work for the first descriptor
1890 * (tx_fd->state = 0xc0000000)
1891 * - Hold=1 (don't try and branch to the next descripto);
1892 * - No=0 (I want an empty data section, i.e. size=0);
1893 * - Fe=1 (required by No=0 or we got an Err irq and must reset).
1894 * It failed and locked solid. Thus the introduction of a dummy skb.
1895 * Problem is acknowledged in errata sheet DS5. Joy :o/
1896 */
1897 static struct sk_buff *dscc4_init_dummy_skb(struct dscc4_dev_priv *dpriv)
1898 {
1899 struct sk_buff *skb;
1900
1901 skb = dev_alloc_skb(DUMMY_SKB_SIZE);
1902 if (skb) {
1903 int last = dpriv->tx_dirty%TX_RING_SIZE;
1904 struct TxFD *tx_fd = dpriv->tx_fd + last;
1905
1906 skb->len = DUMMY_SKB_SIZE;
1907 skb_copy_to_linear_data(skb, version,
1908 strlen(version) % DUMMY_SKB_SIZE);
1909 tx_fd->state = FrameEnd | TO_STATE_TX(DUMMY_SKB_SIZE);
1910 tx_fd->data = cpu_to_le32(pci_map_single(dpriv->pci_priv->pdev,
1911 skb->data, DUMMY_SKB_SIZE,
1912 PCI_DMA_TODEVICE));
1913 dpriv->tx_skbuff[last] = skb;
1914 }
1915 return skb;
1916 }
1917
1918 static int dscc4_init_ring(struct net_device *dev)
1919 {
1920 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1921 struct pci_dev *pdev = dpriv->pci_priv->pdev;
1922 struct TxFD *tx_fd;
1923 struct RxFD *rx_fd;
1924 void *ring;
1925 int i;
1926
1927 ring = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &dpriv->rx_fd_dma);
1928 if (!ring)
1929 goto err_out;
1930 dpriv->rx_fd = rx_fd = (struct RxFD *) ring;
1931
1932 ring = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &dpriv->tx_fd_dma);
1933 if (!ring)
1934 goto err_free_dma_rx;
1935 dpriv->tx_fd = tx_fd = (struct TxFD *) ring;
1936
1937 memset(dpriv->tx_skbuff, 0, sizeof(struct sk_buff *)*TX_RING_SIZE);
1938 dpriv->tx_dirty = 0xffffffff;
1939 i = dpriv->tx_current = 0;
1940 do {
1941 tx_fd->state = FrameEnd | TO_STATE_TX(2*DUMMY_SKB_SIZE);
1942 tx_fd->complete = 0x00000000;
1943 /* FIXME: NULL should be ok - to be tried */
1944 tx_fd->data = cpu_to_le32(dpriv->tx_fd_dma);
1945 (tx_fd++)->next = cpu_to_le32(dpriv->tx_fd_dma +
1946 (++i%TX_RING_SIZE)*sizeof(*tx_fd));
1947 } while (i < TX_RING_SIZE);
1948
1949 if (!dscc4_init_dummy_skb(dpriv))
1950 goto err_free_dma_tx;
1951
1952 memset(dpriv->rx_skbuff, 0, sizeof(struct sk_buff *)*RX_RING_SIZE);
1953 i = dpriv->rx_dirty = dpriv->rx_current = 0;
1954 do {
1955 /* size set by the host. Multiple of 4 bytes please */
1956 rx_fd->state1 = HiDesc;
1957 rx_fd->state2 = 0x00000000;
1958 rx_fd->end = cpu_to_le32(0xbabeface);
1959 rx_fd->state1 |= TO_STATE_RX(HDLC_MAX_MRU);
1960 // FIXME: return value verifiee mais traitement suspect
1961 if (try_get_rx_skb(dpriv, dev) >= 0)
1962 dpriv->rx_dirty++;
1963 (rx_fd++)->next = cpu_to_le32(dpriv->rx_fd_dma +
1964 (++i%RX_RING_SIZE)*sizeof(*rx_fd));
1965 } while (i < RX_RING_SIZE);
1966
1967 return 0;
1968
1969 err_free_dma_tx:
1970 pci_free_consistent(pdev, TX_TOTAL_SIZE, ring, dpriv->tx_fd_dma);
1971 err_free_dma_rx:
1972 pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma);
1973 err_out:
1974 return -ENOMEM;
1975 }
1976
1977 static void __devexit dscc4_remove_one(struct pci_dev *pdev)
1978 {
1979 struct dscc4_pci_priv *ppriv;
1980 struct dscc4_dev_priv *root;
1981 void __iomem *ioaddr;
1982 int i;
1983
1984 ppriv = pci_get_drvdata(pdev);
1985 root = ppriv->root;
1986
1987 ioaddr = root->base_addr;
1988
1989 dscc4_pci_reset(pdev, ioaddr);
1990
1991 free_irq(pdev->irq, root);
1992 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), ppriv->iqcfg,
1993 ppriv->iqcfg_dma);
1994 for (i = 0; i < dev_per_card; i++) {
1995 struct dscc4_dev_priv *dpriv = root + i;
1996
1997 dscc4_release_ring(dpriv);
1998 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
1999 dpriv->iqrx, dpriv->iqrx_dma);
2000 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
2001 dpriv->iqtx, dpriv->iqtx_dma);
2002 }
2003
2004 dscc4_free1(pdev);
2005
2006 iounmap(ioaddr);
2007
2008 pci_release_region(pdev, 1);
2009 pci_release_region(pdev, 0);
2010
2011 pci_disable_device(pdev);
2012 }
2013
2014 static int dscc4_hdlc_attach(struct net_device *dev, unsigned short encoding,
2015 unsigned short parity)
2016 {
2017 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
2018
2019 if (encoding != ENCODING_NRZ &&
2020 encoding != ENCODING_NRZI &&
2021 encoding != ENCODING_FM_MARK &&
2022 encoding != ENCODING_FM_SPACE &&
2023 encoding != ENCODING_MANCHESTER)
2024 return -EINVAL;
2025
2026 if (parity != PARITY_NONE &&
2027 parity != PARITY_CRC16_PR0_CCITT &&
2028 parity != PARITY_CRC16_PR1_CCITT &&
2029 parity != PARITY_CRC32_PR0_CCITT &&
2030 parity != PARITY_CRC32_PR1_CCITT)
2031 return -EINVAL;
2032
2033 dpriv->encoding = encoding;
2034 dpriv->parity = parity;
2035 return 0;
2036 }
2037
2038 #ifndef MODULE
2039 static int __init dscc4_setup(char *str)
2040 {
2041 int *args[] = { &debug, &quartz, NULL }, **p = args;
2042
2043 while (*p && (get_option(&str, *p) == 2))
2044 p++;
2045 return 1;
2046 }
2047
2048 __setup("dscc4.setup=", dscc4_setup);
2049 #endif
2050
2051 static struct pci_device_id dscc4_pci_tbl[] = {
2052 { PCI_VENDOR_ID_SIEMENS, PCI_DEVICE_ID_SIEMENS_DSCC4,
2053 PCI_ANY_ID, PCI_ANY_ID, },
2054 { 0,}
2055 };
2056 MODULE_DEVICE_TABLE(pci, dscc4_pci_tbl);
2057
2058 static struct pci_driver dscc4_driver = {
2059 .name = DRV_NAME,
2060 .id_table = dscc4_pci_tbl,
2061 .probe = dscc4_init_one,
2062 .remove = __devexit_p(dscc4_remove_one),
2063 };
2064
2065 static int __init dscc4_init_module(void)
2066 {
2067 return pci_register_driver(&dscc4_driver);
2068 }
2069
2070 static void __exit dscc4_cleanup_module(void)
2071 {
2072 pci_unregister_driver(&dscc4_driver);
2073 }
2074
2075 module_init(dscc4_init_module);
2076 module_exit(dscc4_cleanup_module);
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