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kmemtrace: SLOB hooks.
[linux-2.6/kmemtrace.git] / drivers / spi / spi_mpc83xx.c
blob6832da6f7109c32a379c169b1943abd56ac6af99
1 /*
2 * MPC83xx SPI controller driver.
3 *
4 * Maintainer: Kumar Gala
5 *
6 * Copyright (C) 2006 Polycom, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/completion.h>
18 #include <linux/interrupt.h>
19 #include <linux/delay.h>
20 #include <linux/irq.h>
21 #include <linux/device.h>
22 #include <linux/spi/spi.h>
23 #include <linux/spi/spi_bitbang.h>
24 #include <linux/platform_device.h>
25 #include <linux/fsl_devices.h>
26
27 #include <asm/irq.h>
28 #include <asm/io.h>
29
30 /* SPI Controller registers */
31 struct mpc83xx_spi_reg {
32 u8 res1[0x20];
33 __be32 mode;
34 __be32 event;
35 __be32 mask;
36 __be32 command;
37 __be32 transmit;
38 __be32 receive;
39 };
40
41 /* SPI Controller mode register definitions */
42 #define SPMODE_LOOP (1 << 30)
43 #define SPMODE_CI_INACTIVEHIGH (1 << 29)
44 #define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
45 #define SPMODE_DIV16 (1 << 27)
46 #define SPMODE_REV (1 << 26)
47 #define SPMODE_MS (1 << 25)
48 #define SPMODE_ENABLE (1 << 24)
49 #define SPMODE_LEN(x) ((x) << 20)
50 #define SPMODE_PM(x) ((x) << 16)
51 #define SPMODE_OP (1 << 14)
52 #define SPMODE_CG(x) ((x) << 7)
53
54 /*
55 * Default for SPI Mode:
56 * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
57 */
58 #define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
59 SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
60
61 /* SPIE register values */
62 #define SPIE_NE 0x00000200 /* Not empty */
63 #define SPIE_NF 0x00000100 /* Not full */
64
65 /* SPIM register values */
66 #define SPIM_NE 0x00000200 /* Not empty */
67 #define SPIM_NF 0x00000100 /* Not full */
68
69 /* SPI Controller driver's private data. */
70 struct mpc83xx_spi {
71 struct mpc83xx_spi_reg __iomem *base;
72
73 /* rx & tx bufs from the spi_transfer */
74 const void *tx;
75 void *rx;
76
77 /* functions to deal with different sized buffers */
78 void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
79 u32(*get_tx) (struct mpc83xx_spi *);
80
81 unsigned int count;
82 int irq;
83
84 unsigned nsecs; /* (clock cycle time)/2 */
85
86 u32 spibrg; /* SPIBRG input clock */
87 u32 rx_shift; /* RX data reg shift when in qe mode */
88 u32 tx_shift; /* TX data reg shift when in qe mode */
89
90 bool qe_mode;
91
92 void (*activate_cs) (u8 cs, u8 polarity);
93 void (*deactivate_cs) (u8 cs, u8 polarity);
94
95 u8 busy;
96
97 struct workqueue_struct *workqueue;
98 struct work_struct work;
99
100 struct list_head queue;
101 spinlock_t lock;
102
103 struct completion done;
104 };
105
106 struct spi_mpc83xx_cs {
107 /* functions to deal with different sized buffers */
108 void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
109 u32 (*get_tx) (struct mpc83xx_spi *);
110 u32 rx_shift; /* RX data reg shift when in qe mode */
111 u32 tx_shift; /* TX data reg shift when in qe mode */
112 u32 hw_mode; /* Holds HW mode register settings */
113 };
114
115 static inline void mpc83xx_spi_write_reg(__be32 __iomem * reg, u32 val)
116 {
117 out_be32(reg, val);
118 }
119
120 static inline u32 mpc83xx_spi_read_reg(__be32 __iomem * reg)
121 {
122 return in_be32(reg);
123 }
124
125 #define MPC83XX_SPI_RX_BUF(type) \
126 void mpc83xx_spi_rx_buf_##type(u32 data, struct mpc83xx_spi *mpc83xx_spi) \
127 { \
128 type * rx = mpc83xx_spi->rx; \
129 *rx++ = (type)(data >> mpc83xx_spi->rx_shift); \
130 mpc83xx_spi->rx = rx; \
131 }
132
133 #define MPC83XX_SPI_TX_BUF(type) \
134 u32 mpc83xx_spi_tx_buf_##type(struct mpc83xx_spi *mpc83xx_spi) \
135 { \
136 u32 data; \
137 const type * tx = mpc83xx_spi->tx; \
138 if (!tx) \
139 return 0; \
140 data = *tx++ << mpc83xx_spi->tx_shift; \
141 mpc83xx_spi->tx = tx; \
142 return data; \
143 }
144
145 MPC83XX_SPI_RX_BUF(u8)
146 MPC83XX_SPI_RX_BUF(u16)
147 MPC83XX_SPI_RX_BUF(u32)
148 MPC83XX_SPI_TX_BUF(u8)
149 MPC83XX_SPI_TX_BUF(u16)
150 MPC83XX_SPI_TX_BUF(u32)
151
152 static void mpc83xx_spi_chipselect(struct spi_device *spi, int value)
153 {
154 struct mpc83xx_spi *mpc83xx_spi;
155 u8 pol = spi->mode & SPI_CS_HIGH ? 1 : 0;
156 struct spi_mpc83xx_cs *cs = spi->controller_state;
157
158 mpc83xx_spi = spi_master_get_devdata(spi->master);
159
160 if (value == BITBANG_CS_INACTIVE) {
161 if (mpc83xx_spi->deactivate_cs)
162 mpc83xx_spi->deactivate_cs(spi->chip_select, pol);
163 }
164
165 if (value == BITBANG_CS_ACTIVE) {
166 u32 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
167
168 mpc83xx_spi->rx_shift = cs->rx_shift;
169 mpc83xx_spi->tx_shift = cs->tx_shift;
170 mpc83xx_spi->get_rx = cs->get_rx;
171 mpc83xx_spi->get_tx = cs->get_tx;
172
173 if (cs->hw_mode != regval) {
174 unsigned long flags;
175 void *tmp_ptr = &mpc83xx_spi->base->mode;
176
177 regval = cs->hw_mode;
178 /* Turn off IRQs locally to minimize time that
179 * SPI is disabled
180 */
181 local_irq_save(flags);
182 /* Turn off SPI unit prior changing mode */
183 mpc83xx_spi_write_reg(tmp_ptr, regval & ~SPMODE_ENABLE);
184 mpc83xx_spi_write_reg(tmp_ptr, regval);
185 local_irq_restore(flags);
186 }
187 if (mpc83xx_spi->activate_cs)
188 mpc83xx_spi->activate_cs(spi->chip_select, pol);
189 }
190 }
191
192 static
193 int mpc83xx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
194 {
195 struct mpc83xx_spi *mpc83xx_spi;
196 u32 regval;
197 u8 bits_per_word, pm;
198 u32 hz;
199 struct spi_mpc83xx_cs *cs = spi->controller_state;
200
201 mpc83xx_spi = spi_master_get_devdata(spi->master);
202
203 if (t) {
204 bits_per_word = t->bits_per_word;
205 hz = t->speed_hz;
206 } else {
207 bits_per_word = 0;
208 hz = 0;
209 }
210
211 /* spi_transfer level calls that work per-word */
212 if (!bits_per_word)
213 bits_per_word = spi->bits_per_word;
214
215 /* Make sure its a bit width we support [4..16, 32] */
216 if ((bits_per_word < 4)
217 || ((bits_per_word > 16) && (bits_per_word != 32)))
218 return -EINVAL;
219
220 if (!hz)
221 hz = spi->max_speed_hz;
222
223 cs->rx_shift = 0;
224 cs->tx_shift = 0;
225 if (bits_per_word <= 8) {
226 cs->get_rx = mpc83xx_spi_rx_buf_u8;
227 cs->get_tx = mpc83xx_spi_tx_buf_u8;
228 if (mpc83xx_spi->qe_mode) {
229 cs->rx_shift = 16;
230 cs->tx_shift = 24;
231 }
232 } else if (bits_per_word <= 16) {
233 cs->get_rx = mpc83xx_spi_rx_buf_u16;
234 cs->get_tx = mpc83xx_spi_tx_buf_u16;
235 if (mpc83xx_spi->qe_mode) {
236 cs->rx_shift = 16;
237 cs->tx_shift = 16;
238 }
239 } else if (bits_per_word <= 32) {
240 cs->get_rx = mpc83xx_spi_rx_buf_u32;
241 cs->get_tx = mpc83xx_spi_tx_buf_u32;
242 } else
243 return -EINVAL;
244
245 if (mpc83xx_spi->qe_mode && spi->mode & SPI_LSB_FIRST) {
246 cs->tx_shift = 0;
247 if (bits_per_word <= 8)
248 cs->rx_shift = 8;
249 else
250 cs->rx_shift = 0;
251 }
252
253 mpc83xx_spi->rx_shift = cs->rx_shift;
254 mpc83xx_spi->tx_shift = cs->tx_shift;
255 mpc83xx_spi->get_rx = cs->get_rx;
256 mpc83xx_spi->get_tx = cs->get_tx;
257
258 if (bits_per_word == 32)
259 bits_per_word = 0;
260 else
261 bits_per_word = bits_per_word - 1;
262
263 /* mask out bits we are going to set */
264 cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
265 | SPMODE_PM(0xF));
266
267 cs->hw_mode |= SPMODE_LEN(bits_per_word);
268
269 if ((mpc83xx_spi->spibrg / hz) >= 64) {
270 pm = mpc83xx_spi->spibrg / (hz * 64) - 1;
271 if (pm > 0x0f) {
272 dev_err(&spi->dev, "Requested speed is too "
273 "low: %d Hz. Will use %d Hz instead.\n",
274 hz, mpc83xx_spi->spibrg / 1024);
275 pm = 0x0f;
276 }
277 cs->hw_mode |= SPMODE_PM(pm) | SPMODE_DIV16;
278 } else {
279 pm = mpc83xx_spi->spibrg / (hz * 4);
280 if (pm)
281 pm--;
282 cs->hw_mode |= SPMODE_PM(pm);
283 }
284 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
285 if (cs->hw_mode != regval) {
286 unsigned long flags;
287 void *tmp_ptr = &mpc83xx_spi->base->mode;
288
289 regval = cs->hw_mode;
290 /* Turn off IRQs locally to minimize time
291 * that SPI is disabled
292 */
293 local_irq_save(flags);
294 /* Turn off SPI unit prior changing mode */
295 mpc83xx_spi_write_reg(tmp_ptr, regval & ~SPMODE_ENABLE);
296 mpc83xx_spi_write_reg(tmp_ptr, regval);
297 local_irq_restore(flags);
298 }
299 return 0;
300 }
301
302 static int mpc83xx_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
303 {
304 struct mpc83xx_spi *mpc83xx_spi;
305 u32 word, len, bits_per_word;
306
307 mpc83xx_spi = spi_master_get_devdata(spi->master);
308
309 mpc83xx_spi->tx = t->tx_buf;
310 mpc83xx_spi->rx = t->rx_buf;
311 bits_per_word = spi->bits_per_word;
312 if (t->bits_per_word)
313 bits_per_word = t->bits_per_word;
314 len = t->len;
315 if (bits_per_word > 8)
316 len /= 2;
317 if (bits_per_word > 16)
318 len /= 2;
319 mpc83xx_spi->count = len;
320 INIT_COMPLETION(mpc83xx_spi->done);
321
322 /* enable rx ints */
323 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, SPIM_NE);
324
325 /* transmit word */
326 word = mpc83xx_spi->get_tx(mpc83xx_spi);
327 mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
328
329 wait_for_completion(&mpc83xx_spi->done);
330
331 /* disable rx ints */
332 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
333
334 return mpc83xx_spi->count;
335 }
336
337 static void mpc83xx_spi_work(struct work_struct *work)
338 {
339 struct mpc83xx_spi *mpc83xx_spi =
340 container_of(work, struct mpc83xx_spi, work);
341
342 spin_lock_irq(&mpc83xx_spi->lock);
343 mpc83xx_spi->busy = 1;
344 while (!list_empty(&mpc83xx_spi->queue)) {
345 struct spi_message *m;
346 struct spi_device *spi;
347 struct spi_transfer *t = NULL;
348 unsigned cs_change;
349 int status, nsecs = 50;
350
351 m = container_of(mpc83xx_spi->queue.next,
352 struct spi_message, queue);
353 list_del_init(&m->queue);
354 spin_unlock_irq(&mpc83xx_spi->lock);
355
356 spi = m->spi;
357 cs_change = 1;
358 status = 0;
359 list_for_each_entry(t, &m->transfers, transfer_list) {
360 if (t->bits_per_word || t->speed_hz) {
361 /* Don't allow changes if CS is active */
362 status = -EINVAL;
363
364 if (cs_change)
365 status = mpc83xx_spi_setup_transfer(spi, t);
366 if (status < 0)
367 break;
368 }
369
370 if (cs_change)
371 mpc83xx_spi_chipselect(spi, BITBANG_CS_ACTIVE);
372 cs_change = t->cs_change;
373 if (t->len)
374 status = mpc83xx_spi_bufs(spi, t);
375 if (status) {
376 status = -EMSGSIZE;
377 break;
378 }
379 m->actual_length += t->len;
380
381 if (t->delay_usecs)
382 udelay(t->delay_usecs);
383
384 if (cs_change) {
385 ndelay(nsecs);
386 mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
387 ndelay(nsecs);
388 }
389 }
390
391 m->status = status;
392 m->complete(m->context);
393
394 if (status || !cs_change) {
395 ndelay(nsecs);
396 mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
397 }
398
399 mpc83xx_spi_setup_transfer(spi, NULL);
400
401 spin_lock_irq(&mpc83xx_spi->lock);
402 }
403 mpc83xx_spi->busy = 0;
404 spin_unlock_irq(&mpc83xx_spi->lock);
405 }
406
407 /* the spi->mode bits understood by this driver: */
408 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
409 | SPI_LSB_FIRST | SPI_LOOP)
410
411 static int mpc83xx_spi_setup(struct spi_device *spi)
412 {
413 struct mpc83xx_spi *mpc83xx_spi;
414 int retval;
415 u32 hw_mode;
416 struct spi_mpc83xx_cs *cs = spi->controller_state;
417
418 if (spi->mode & ~MODEBITS) {
419 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
420 spi->mode & ~MODEBITS);
421 return -EINVAL;
422 }
423
424 if (!spi->max_speed_hz)
425 return -EINVAL;
426
427 if (!cs) {
428 cs = kzalloc(sizeof *cs, GFP_KERNEL);
429 if (!cs)
430 return -ENOMEM;
431 spi->controller_state = cs;
432 }
433 mpc83xx_spi = spi_master_get_devdata(spi->master);
434
435 if (!spi->bits_per_word)
436 spi->bits_per_word = 8;
437
438 hw_mode = cs->hw_mode; /* Save orginal settings */
439 cs->hw_mode = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
440 /* mask out bits we are going to set */
441 cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
442 | SPMODE_REV | SPMODE_LOOP);
443
444 if (spi->mode & SPI_CPHA)
445 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
446 if (spi->mode & SPI_CPOL)
447 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
448 if (!(spi->mode & SPI_LSB_FIRST))
449 cs->hw_mode |= SPMODE_REV;
450 if (spi->mode & SPI_LOOP)
451 cs->hw_mode |= SPMODE_LOOP;
452
453 retval = mpc83xx_spi_setup_transfer(spi, NULL);
454 if (retval < 0) {
455 cs->hw_mode = hw_mode; /* Restore settings */
456 return retval;
457 }
458
459 dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u Hz\n",
460 __func__, spi->mode & (SPI_CPOL | SPI_CPHA),
461 spi->bits_per_word, spi->max_speed_hz);
462 #if 0 /* Don't think this is needed */
463 /* NOTE we _need_ to call chipselect() early, ideally with adapter
464 * setup, unless the hardware defaults cooperate to avoid confusion
465 * between normal (active low) and inverted chipselects.
466 */
467
468 /* deselect chip (low or high) */
469 spin_lock(&mpc83xx_spi->lock);
470 if (!mpc83xx_spi->busy)
471 mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
472 spin_unlock(&mpc83xx_spi->lock);
473 #endif
474 return 0;
475 }
476
477 irqreturn_t mpc83xx_spi_irq(s32 irq, void *context_data)
478 {
479 struct mpc83xx_spi *mpc83xx_spi = context_data;
480 u32 event;
481 irqreturn_t ret = IRQ_NONE;
482
483 /* Get interrupt events(tx/rx) */
484 event = mpc83xx_spi_read_reg(&mpc83xx_spi->base->event);
485
486 /* We need handle RX first */
487 if (event & SPIE_NE) {
488 u32 rx_data = mpc83xx_spi_read_reg(&mpc83xx_spi->base->receive);
489
490 if (mpc83xx_spi->rx)
491 mpc83xx_spi->get_rx(rx_data, mpc83xx_spi);
492
493 ret = IRQ_HANDLED;
494 }
495
496 if ((event & SPIE_NF) == 0)
497 /* spin until TX is done */
498 while (((event =
499 mpc83xx_spi_read_reg(&mpc83xx_spi->base->event)) &
500 SPIE_NF) == 0)
501 cpu_relax();
502
503 mpc83xx_spi->count -= 1;
504 if (mpc83xx_spi->count) {
505 u32 word = mpc83xx_spi->get_tx(mpc83xx_spi);
506 mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
507 } else {
508 complete(&mpc83xx_spi->done);
509 }
510
511 /* Clear the events */
512 mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, event);
513
514 return ret;
515 }
516 static int mpc83xx_spi_transfer(struct spi_device *spi,
517 struct spi_message *m)
518 {
519 struct mpc83xx_spi *mpc83xx_spi = spi_master_get_devdata(spi->master);
520 unsigned long flags;
521
522 m->actual_length = 0;
523 m->status = -EINPROGRESS;
524
525 spin_lock_irqsave(&mpc83xx_spi->lock, flags);
526 list_add_tail(&m->queue, &mpc83xx_spi->queue);
527 queue_work(mpc83xx_spi->workqueue, &mpc83xx_spi->work);
528 spin_unlock_irqrestore(&mpc83xx_spi->lock, flags);
529
530 return 0;
531 }
532
533
534 static void mpc83xx_spi_cleanup(struct spi_device *spi)
535 {
536 kfree(spi->controller_state);
537 }
538
539 static int __init mpc83xx_spi_probe(struct platform_device *dev)
540 {
541 struct spi_master *master;
542 struct mpc83xx_spi *mpc83xx_spi;
543 struct fsl_spi_platform_data *pdata;
544 struct resource *r;
545 u32 regval;
546 int ret = 0;
547
548 /* Get resources(memory, IRQ) associated with the device */
549 master = spi_alloc_master(&dev->dev, sizeof(struct mpc83xx_spi));
550
551 if (master == NULL) {
552 ret = -ENOMEM;
553 goto err;
554 }
555
556 platform_set_drvdata(dev, master);
557 pdata = dev->dev.platform_data;
558
559 if (pdata == NULL) {
560 ret = -ENODEV;
561 goto free_master;
562 }
563
564 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
565 if (r == NULL) {
566 ret = -ENODEV;
567 goto free_master;
568 }
569 master->setup = mpc83xx_spi_setup;
570 master->transfer = mpc83xx_spi_transfer;
571 master->cleanup = mpc83xx_spi_cleanup;
572
573 mpc83xx_spi = spi_master_get_devdata(master);
574 mpc83xx_spi->activate_cs = pdata->activate_cs;
575 mpc83xx_spi->deactivate_cs = pdata->deactivate_cs;
576 mpc83xx_spi->qe_mode = pdata->qe_mode;
577 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
578 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
579 mpc83xx_spi->spibrg = pdata->sysclk;
580
581 mpc83xx_spi->rx_shift = 0;
582 mpc83xx_spi->tx_shift = 0;
583 if (mpc83xx_spi->qe_mode) {
584 mpc83xx_spi->rx_shift = 16;
585 mpc83xx_spi->tx_shift = 24;
586 }
587
588 init_completion(&mpc83xx_spi->done);
589
590 mpc83xx_spi->base = ioremap(r->start, r->end - r->start + 1);
591 if (mpc83xx_spi->base == NULL) {
592 ret = -ENOMEM;
593 goto put_master;
594 }
595
596 mpc83xx_spi->irq = platform_get_irq(dev, 0);
597
598 if (mpc83xx_spi->irq < 0) {
599 ret = -ENXIO;
600 goto unmap_io;
601 }
602
603 /* Register for SPI Interrupt */
604 ret = request_irq(mpc83xx_spi->irq, mpc83xx_spi_irq,
605 0, "mpc83xx_spi", mpc83xx_spi);
606
607 if (ret != 0)
608 goto unmap_io;
609
610 master->bus_num = pdata->bus_num;
611 master->num_chipselect = pdata->max_chipselect;
612
613 /* SPI controller initializations */
614 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
615 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
616 mpc83xx_spi_write_reg(&mpc83xx_spi->base->command, 0);
617 mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, 0xffffffff);
618
619 /* Enable SPI interface */
620 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
621 if (pdata->qe_mode)
622 regval |= SPMODE_OP;
623
624 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
625 spin_lock_init(&mpc83xx_spi->lock);
626 init_completion(&mpc83xx_spi->done);
627 INIT_WORK(&mpc83xx_spi->work, mpc83xx_spi_work);
628 INIT_LIST_HEAD(&mpc83xx_spi->queue);
629
630 mpc83xx_spi->workqueue = create_singlethread_workqueue(
631 master->dev.parent->bus_id);
632 if (mpc83xx_spi->workqueue == NULL) {
633 ret = -EBUSY;
634 goto free_irq;
635 }
636
637 ret = spi_register_master(master);
638 if (ret < 0)
639 goto unreg_master;
640
641 printk(KERN_INFO
642 "%s: MPC83xx SPI Controller driver at 0x%p (irq = %d)\n",
643 dev->dev.bus_id, mpc83xx_spi->base, mpc83xx_spi->irq);
644
645 return ret;
646
647 unreg_master:
648 destroy_workqueue(mpc83xx_spi->workqueue);
649 free_irq:
650 free_irq(mpc83xx_spi->irq, mpc83xx_spi);
651 unmap_io:
652 iounmap(mpc83xx_spi->base);
653 put_master:
654 spi_master_put(master);
655 free_master:
656 kfree(master);
657 err:
658 return ret;
659 }
660
661 static int __exit mpc83xx_spi_remove(struct platform_device *dev)
662 {
663 struct mpc83xx_spi *mpc83xx_spi;
664 struct spi_master *master;
665
666 master = platform_get_drvdata(dev);
667 mpc83xx_spi = spi_master_get_devdata(master);
668
669 flush_workqueue(mpc83xx_spi->workqueue);
670 destroy_workqueue(mpc83xx_spi->workqueue);
671 spi_unregister_master(master);
672
673 free_irq(mpc83xx_spi->irq, mpc83xx_spi);
674 iounmap(mpc83xx_spi->base);
675
676 return 0;
677 }
678
679 MODULE_ALIAS("platform:mpc83xx_spi");
680 static struct platform_driver mpc83xx_spi_driver = {
681 .remove = __exit_p(mpc83xx_spi_remove),
682 .driver = {
683 .name = "mpc83xx_spi",
684 .owner = THIS_MODULE,
685 },
686 };
687
688 static int __init mpc83xx_spi_init(void)
689 {
690 return platform_driver_probe(&mpc83xx_spi_driver, mpc83xx_spi_probe);
691 }
692
693 static void __exit mpc83xx_spi_exit(void)
694 {
695 platform_driver_unregister(&mpc83xx_spi_driver);
696 }
697
698 module_init(mpc83xx_spi_init);
699 module_exit(mpc83xx_spi_exit);
700
701 MODULE_AUTHOR("Kumar Gala");
702 MODULE_DESCRIPTION("Simple MPC83xx SPI Driver");
703 MODULE_LICENSE("GPL");
kmemtrace - Kernel memory tracer