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Linux 2.6.33-rc8
[linux-2.6/lguest.git] / drivers / mfd / asic3.c
blob95c1e6bd1729d84c3e176f3990a95655628f6c17
1 /*
2 * driver/mfd/asic3.c
3 *
4 * Compaq ASIC3 support.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Copyright 2001 Compaq Computer Corporation.
11 * Copyright 2004-2005 Phil Blundell
12 * Copyright 2007-2008 OpenedHand Ltd.
13 *
14 * Authors: Phil Blundell <pb@handhelds.org>,
15 * Samuel Ortiz <sameo@openedhand.com>
16 *
17 */
18
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/irq.h>
22 #include <linux/gpio.h>
23 #include <linux/io.h>
24 #include <linux/spinlock.h>
25 #include <linux/platform_device.h>
26
27 #include <linux/mfd/asic3.h>
28 #include <linux/mfd/core.h>
29 #include <linux/mfd/ds1wm.h>
30 #include <linux/mfd/tmio.h>
31
32 enum {
33 ASIC3_CLOCK_SPI,
34 ASIC3_CLOCK_OWM,
35 ASIC3_CLOCK_PWM0,
36 ASIC3_CLOCK_PWM1,
37 ASIC3_CLOCK_LED0,
38 ASIC3_CLOCK_LED1,
39 ASIC3_CLOCK_LED2,
40 ASIC3_CLOCK_SD_HOST,
41 ASIC3_CLOCK_SD_BUS,
42 ASIC3_CLOCK_SMBUS,
43 ASIC3_CLOCK_EX0,
44 ASIC3_CLOCK_EX1,
45 };
46
47 struct asic3_clk {
48 int enabled;
49 unsigned int cdex;
50 unsigned long rate;
51 };
52
53 #define INIT_CDEX(_name, _rate) \
54 [ASIC3_CLOCK_##_name] = { \
55 .cdex = CLOCK_CDEX_##_name, \
56 .rate = _rate, \
57 }
58
59 struct asic3_clk asic3_clk_init[] __initdata = {
60 INIT_CDEX(SPI, 0),
61 INIT_CDEX(OWM, 5000000),
62 INIT_CDEX(PWM0, 0),
63 INIT_CDEX(PWM1, 0),
64 INIT_CDEX(LED0, 0),
65 INIT_CDEX(LED1, 0),
66 INIT_CDEX(LED2, 0),
67 INIT_CDEX(SD_HOST, 24576000),
68 INIT_CDEX(SD_BUS, 12288000),
69 INIT_CDEX(SMBUS, 0),
70 INIT_CDEX(EX0, 32768),
71 INIT_CDEX(EX1, 24576000),
72 };
73
74 struct asic3 {
75 void __iomem *mapping;
76 unsigned int bus_shift;
77 unsigned int irq_nr;
78 unsigned int irq_base;
79 spinlock_t lock;
80 u16 irq_bothedge[4];
81 struct gpio_chip gpio;
82 struct device *dev;
83 void __iomem *tmio_cnf;
84
85 struct asic3_clk clocks[ARRAY_SIZE(asic3_clk_init)];
86 };
87
88 static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);
89
90 static inline void asic3_write_register(struct asic3 *asic,
91 unsigned int reg, u32 value)
92 {
93 iowrite16(value, asic->mapping +
94 (reg >> asic->bus_shift));
95 }
96
97 static inline u32 asic3_read_register(struct asic3 *asic,
98 unsigned int reg)
99 {
100 return ioread16(asic->mapping +
101 (reg >> asic->bus_shift));
102 }
103
104 void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set)
105 {
106 unsigned long flags;
107 u32 val;
108
109 spin_lock_irqsave(&asic->lock, flags);
110 val = asic3_read_register(asic, reg);
111 if (set)
112 val |= bits;
113 else
114 val &= ~bits;
115 asic3_write_register(asic, reg, val);
116 spin_unlock_irqrestore(&asic->lock, flags);
117 }
118
119 /* IRQs */
120 #define MAX_ASIC_ISR_LOOPS 20
121 #define ASIC3_GPIO_BASE_INCR \
122 (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)
123
124 static void asic3_irq_flip_edge(struct asic3 *asic,
125 u32 base, int bit)
126 {
127 u16 edge;
128 unsigned long flags;
129
130 spin_lock_irqsave(&asic->lock, flags);
131 edge = asic3_read_register(asic,
132 base + ASIC3_GPIO_EDGE_TRIGGER);
133 edge ^= bit;
134 asic3_write_register(asic,
135 base + ASIC3_GPIO_EDGE_TRIGGER, edge);
136 spin_unlock_irqrestore(&asic->lock, flags);
137 }
138
139 static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc)
140 {
141 int iter, i;
142 unsigned long flags;
143 struct asic3 *asic;
144
145 desc->chip->ack(irq);
146
147 asic = desc->handler_data;
148
149 for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) {
150 u32 status;
151 int bank;
152
153 spin_lock_irqsave(&asic->lock, flags);
154 status = asic3_read_register(asic,
155 ASIC3_OFFSET(INTR, P_INT_STAT));
156 spin_unlock_irqrestore(&asic->lock, flags);
157
158 /* Check all ten register bits */
159 if ((status & 0x3ff) == 0)
160 break;
161
162 /* Handle GPIO IRQs */
163 for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) {
164 if (status & (1 << bank)) {
165 unsigned long base, istat;
166
167 base = ASIC3_GPIO_A_BASE
168 + bank * ASIC3_GPIO_BASE_INCR;
169
170 spin_lock_irqsave(&asic->lock, flags);
171 istat = asic3_read_register(asic,
172 base +
173 ASIC3_GPIO_INT_STATUS);
174 /* Clearing IntStatus */
175 asic3_write_register(asic,
176 base +
177 ASIC3_GPIO_INT_STATUS, 0);
178 spin_unlock_irqrestore(&asic->lock, flags);
179
180 for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
181 int bit = (1 << i);
182 unsigned int irqnr;
183
184 if (!(istat & bit))
185 continue;
186
187 irqnr = asic->irq_base +
188 (ASIC3_GPIOS_PER_BANK * bank)
189 + i;
190 desc = irq_to_desc(irqnr);
191 desc->handle_irq(irqnr, desc);
192 if (asic->irq_bothedge[bank] & bit)
193 asic3_irq_flip_edge(asic, base,
194 bit);
195 }
196 }
197 }
198
199 /* Handle remaining IRQs in the status register */
200 for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {
201 /* They start at bit 4 and go up */
202 if (status & (1 << (i - ASIC3_NUM_GPIOS + 4))) {
203 desc = irq_to_desc(asic->irq_base + i);
204 desc->handle_irq(asic->irq_base + i,
205 desc);
206 }
207 }
208 }
209
210 if (iter >= MAX_ASIC_ISR_LOOPS)
211 dev_err(asic->dev, "interrupt processing overrun\n");
212 }
213
214 static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
215 {
216 int n;
217
218 n = (irq - asic->irq_base) >> 4;
219
220 return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE));
221 }
222
223 static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
224 {
225 return (irq - asic->irq_base) & 0xf;
226 }
227
228 static void asic3_mask_gpio_irq(unsigned int irq)
229 {
230 struct asic3 *asic = get_irq_chip_data(irq);
231 u32 val, bank, index;
232 unsigned long flags;
233
234 bank = asic3_irq_to_bank(asic, irq);
235 index = asic3_irq_to_index(asic, irq);
236
237 spin_lock_irqsave(&asic->lock, flags);
238 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
239 val |= 1 << index;
240 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
241 spin_unlock_irqrestore(&asic->lock, flags);
242 }
243
244 static void asic3_mask_irq(unsigned int irq)
245 {
246 struct asic3 *asic = get_irq_chip_data(irq);
247 int regval;
248 unsigned long flags;
249
250 spin_lock_irqsave(&asic->lock, flags);
251 regval = asic3_read_register(asic,
252 ASIC3_INTR_BASE +
253 ASIC3_INTR_INT_MASK);
254
255 regval &= ~(ASIC3_INTMASK_MASK0 <<
256 (irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
257
258 asic3_write_register(asic,
259 ASIC3_INTR_BASE +
260 ASIC3_INTR_INT_MASK,
261 regval);
262 spin_unlock_irqrestore(&asic->lock, flags);
263 }
264
265 static void asic3_unmask_gpio_irq(unsigned int irq)
266 {
267 struct asic3 *asic = get_irq_chip_data(irq);
268 u32 val, bank, index;
269 unsigned long flags;
270
271 bank = asic3_irq_to_bank(asic, irq);
272 index = asic3_irq_to_index(asic, irq);
273
274 spin_lock_irqsave(&asic->lock, flags);
275 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
276 val &= ~(1 << index);
277 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
278 spin_unlock_irqrestore(&asic->lock, flags);
279 }
280
281 static void asic3_unmask_irq(unsigned int irq)
282 {
283 struct asic3 *asic = get_irq_chip_data(irq);
284 int regval;
285 unsigned long flags;
286
287 spin_lock_irqsave(&asic->lock, flags);
288 regval = asic3_read_register(asic,
289 ASIC3_INTR_BASE +
290 ASIC3_INTR_INT_MASK);
291
292 regval |= (ASIC3_INTMASK_MASK0 <<
293 (irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
294
295 asic3_write_register(asic,
296 ASIC3_INTR_BASE +
297 ASIC3_INTR_INT_MASK,
298 regval);
299 spin_unlock_irqrestore(&asic->lock, flags);
300 }
301
302 static int asic3_gpio_irq_type(unsigned int irq, unsigned int type)
303 {
304 struct asic3 *asic = get_irq_chip_data(irq);
305 u32 bank, index;
306 u16 trigger, level, edge, bit;
307 unsigned long flags;
308
309 bank = asic3_irq_to_bank(asic, irq);
310 index = asic3_irq_to_index(asic, irq);
311 bit = 1<<index;
312
313 spin_lock_irqsave(&asic->lock, flags);
314 level = asic3_read_register(asic,
315 bank + ASIC3_GPIO_LEVEL_TRIGGER);
316 edge = asic3_read_register(asic,
317 bank + ASIC3_GPIO_EDGE_TRIGGER);
318 trigger = asic3_read_register(asic,
319 bank + ASIC3_GPIO_TRIGGER_TYPE);
320 asic->irq_bothedge[(irq - asic->irq_base) >> 4] &= ~bit;
321
322 if (type == IRQ_TYPE_EDGE_RISING) {
323 trigger |= bit;
324 edge |= bit;
325 } else if (type == IRQ_TYPE_EDGE_FALLING) {
326 trigger |= bit;
327 edge &= ~bit;
328 } else if (type == IRQ_TYPE_EDGE_BOTH) {
329 trigger |= bit;
330 if (asic3_gpio_get(&asic->gpio, irq - asic->irq_base))
331 edge &= ~bit;
332 else
333 edge |= bit;
334 asic->irq_bothedge[(irq - asic->irq_base) >> 4] |= bit;
335 } else if (type == IRQ_TYPE_LEVEL_LOW) {
336 trigger &= ~bit;
337 level &= ~bit;
338 } else if (type == IRQ_TYPE_LEVEL_HIGH) {
339 trigger &= ~bit;
340 level |= bit;
341 } else {
342 /*
343 * if type == IRQ_TYPE_NONE, we should mask interrupts, but
344 * be careful to not unmask them if mask was also called.
345 * Probably need internal state for mask.
346 */
347 dev_notice(asic->dev, "irq type not changed\n");
348 }
349 asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER,
350 level);
351 asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER,
352 edge);
353 asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE,
354 trigger);
355 spin_unlock_irqrestore(&asic->lock, flags);
356 return 0;
357 }
358
359 static struct irq_chip asic3_gpio_irq_chip = {
360 .name = "ASIC3-GPIO",
361 .ack = asic3_mask_gpio_irq,
362 .mask = asic3_mask_gpio_irq,
363 .unmask = asic3_unmask_gpio_irq,
364 .set_type = asic3_gpio_irq_type,
365 };
366
367 static struct irq_chip asic3_irq_chip = {
368 .name = "ASIC3",
369 .ack = asic3_mask_irq,
370 .mask = asic3_mask_irq,
371 .unmask = asic3_unmask_irq,
372 };
373
374 static int __init asic3_irq_probe(struct platform_device *pdev)
375 {
376 struct asic3 *asic = platform_get_drvdata(pdev);
377 unsigned long clksel = 0;
378 unsigned int irq, irq_base;
379 int ret;
380
381 ret = platform_get_irq(pdev, 0);
382 if (ret < 0)
383 return ret;
384 asic->irq_nr = ret;
385
386 /* turn on clock to IRQ controller */
387 clksel |= CLOCK_SEL_CX;
388 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
389 clksel);
390
391 irq_base = asic->irq_base;
392
393 for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
394 if (irq < asic->irq_base + ASIC3_NUM_GPIOS)
395 set_irq_chip(irq, &asic3_gpio_irq_chip);
396 else
397 set_irq_chip(irq, &asic3_irq_chip);
398
399 set_irq_chip_data(irq, asic);
400 set_irq_handler(irq, handle_level_irq);
401 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
402 }
403
404 asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),
405 ASIC3_INTMASK_GINTMASK);
406
407 set_irq_chained_handler(asic->irq_nr, asic3_irq_demux);
408 set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING);
409 set_irq_data(asic->irq_nr, asic);
410
411 return 0;
412 }
413
414 static void asic3_irq_remove(struct platform_device *pdev)
415 {
416 struct asic3 *asic = platform_get_drvdata(pdev);
417 unsigned int irq, irq_base;
418
419 irq_base = asic->irq_base;
420
421 for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
422 set_irq_flags(irq, 0);
423 set_irq_handler(irq, NULL);
424 set_irq_chip(irq, NULL);
425 set_irq_chip_data(irq, NULL);
426 }
427 set_irq_chained_handler(asic->irq_nr, NULL);
428 }
429
430 /* GPIOs */
431 static int asic3_gpio_direction(struct gpio_chip *chip,
432 unsigned offset, int out)
433 {
434 u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg;
435 unsigned int gpio_base;
436 unsigned long flags;
437 struct asic3 *asic;
438
439 asic = container_of(chip, struct asic3, gpio);
440 gpio_base = ASIC3_GPIO_TO_BASE(offset);
441
442 if (gpio_base > ASIC3_GPIO_D_BASE) {
443 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
444 gpio_base, offset);
445 return -EINVAL;
446 }
447
448 spin_lock_irqsave(&asic->lock, flags);
449
450 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);
451
452 /* Input is 0, Output is 1 */
453 if (out)
454 out_reg |= mask;
455 else
456 out_reg &= ~mask;
457
458 asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg);
459
460 spin_unlock_irqrestore(&asic->lock, flags);
461
462 return 0;
463
464 }
465
466 static int asic3_gpio_direction_input(struct gpio_chip *chip,
467 unsigned offset)
468 {
469 return asic3_gpio_direction(chip, offset, 0);
470 }
471
472 static int asic3_gpio_direction_output(struct gpio_chip *chip,
473 unsigned offset, int value)
474 {
475 return asic3_gpio_direction(chip, offset, 1);
476 }
477
478 static int asic3_gpio_get(struct gpio_chip *chip,
479 unsigned offset)
480 {
481 unsigned int gpio_base;
482 u32 mask = ASIC3_GPIO_TO_MASK(offset);
483 struct asic3 *asic;
484
485 asic = container_of(chip, struct asic3, gpio);
486 gpio_base = ASIC3_GPIO_TO_BASE(offset);
487
488 if (gpio_base > ASIC3_GPIO_D_BASE) {
489 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
490 gpio_base, offset);
491 return -EINVAL;
492 }
493
494 return asic3_read_register(asic, gpio_base + ASIC3_GPIO_STATUS) & mask;
495 }
496
497 static void asic3_gpio_set(struct gpio_chip *chip,
498 unsigned offset, int value)
499 {
500 u32 mask, out_reg;
501 unsigned int gpio_base;
502 unsigned long flags;
503 struct asic3 *asic;
504
505 asic = container_of(chip, struct asic3, gpio);
506 gpio_base = ASIC3_GPIO_TO_BASE(offset);
507
508 if (gpio_base > ASIC3_GPIO_D_BASE) {
509 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
510 gpio_base, offset);
511 return;
512 }
513
514 mask = ASIC3_GPIO_TO_MASK(offset);
515
516 spin_lock_irqsave(&asic->lock, flags);
517
518 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);
519
520 if (value)
521 out_reg |= mask;
522 else
523 out_reg &= ~mask;
524
525 asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg);
526
527 spin_unlock_irqrestore(&asic->lock, flags);
528
529 return;
530 }
531
532 static __init int asic3_gpio_probe(struct platform_device *pdev,
533 u16 *gpio_config, int num)
534 {
535 struct asic3 *asic = platform_get_drvdata(pdev);
536 u16 alt_reg[ASIC3_NUM_GPIO_BANKS];
537 u16 out_reg[ASIC3_NUM_GPIO_BANKS];
538 u16 dir_reg[ASIC3_NUM_GPIO_BANKS];
539 int i;
540
541 memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
542 memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
543 memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
544
545 /* Enable all GPIOs */
546 asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff);
547 asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff);
548 asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff);
549 asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff);
550
551 for (i = 0; i < num; i++) {
552 u8 alt, pin, dir, init, bank_num, bit_num;
553 u16 config = gpio_config[i];
554
555 pin = ASIC3_CONFIG_GPIO_PIN(config);
556 alt = ASIC3_CONFIG_GPIO_ALT(config);
557 dir = ASIC3_CONFIG_GPIO_DIR(config);
558 init = ASIC3_CONFIG_GPIO_INIT(config);
559
560 bank_num = ASIC3_GPIO_TO_BANK(pin);
561 bit_num = ASIC3_GPIO_TO_BIT(pin);
562
563 alt_reg[bank_num] |= (alt << bit_num);
564 out_reg[bank_num] |= (init << bit_num);
565 dir_reg[bank_num] |= (dir << bit_num);
566 }
567
568 for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) {
569 asic3_write_register(asic,
570 ASIC3_BANK_TO_BASE(i) +
571 ASIC3_GPIO_DIRECTION,
572 dir_reg[i]);
573 asic3_write_register(asic,
574 ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT,
575 out_reg[i]);
576 asic3_write_register(asic,
577 ASIC3_BANK_TO_BASE(i) +
578 ASIC3_GPIO_ALT_FUNCTION,
579 alt_reg[i]);
580 }
581
582 return gpiochip_add(&asic->gpio);
583 }
584
585 static int asic3_gpio_remove(struct platform_device *pdev)
586 {
587 struct asic3 *asic = platform_get_drvdata(pdev);
588
589 return gpiochip_remove(&asic->gpio);
590 }
591
592 static int asic3_clk_enable(struct asic3 *asic, struct asic3_clk *clk)
593 {
594 unsigned long flags;
595 u32 cdex;
596
597 spin_lock_irqsave(&asic->lock, flags);
598 if (clk->enabled++ == 0) {
599 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
600 cdex |= clk->cdex;
601 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
602 }
603 spin_unlock_irqrestore(&asic->lock, flags);
604
605 return 0;
606 }
607
608 static void asic3_clk_disable(struct asic3 *asic, struct asic3_clk *clk)
609 {
610 unsigned long flags;
611 u32 cdex;
612
613 WARN_ON(clk->enabled == 0);
614
615 spin_lock_irqsave(&asic->lock, flags);
616 if (--clk->enabled == 0) {
617 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
618 cdex &= ~clk->cdex;
619 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
620 }
621 spin_unlock_irqrestore(&asic->lock, flags);
622 }
623
624 /* MFD cells (SPI, PWM, LED, DS1WM, MMC) */
625 static struct ds1wm_driver_data ds1wm_pdata = {
626 .active_high = 1,
627 };
628
629 static struct resource ds1wm_resources[] = {
630 {
631 .start = ASIC3_OWM_BASE,
632 .end = ASIC3_OWM_BASE + 0x13,
633 .flags = IORESOURCE_MEM,
634 },
635 {
636 .start = ASIC3_IRQ_OWM,
637 .start = ASIC3_IRQ_OWM,
638 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
639 },
640 };
641
642 static int ds1wm_enable(struct platform_device *pdev)
643 {
644 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
645
646 /* Turn on external clocks and the OWM clock */
647 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
648 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
649 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
650 msleep(1);
651
652 /* Reset and enable DS1WM */
653 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
654 ASIC3_EXTCF_OWM_RESET, 1);
655 msleep(1);
656 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
657 ASIC3_EXTCF_OWM_RESET, 0);
658 msleep(1);
659 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
660 ASIC3_EXTCF_OWM_EN, 1);
661 msleep(1);
662
663 return 0;
664 }
665
666 static int ds1wm_disable(struct platform_device *pdev)
667 {
668 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
669
670 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
671 ASIC3_EXTCF_OWM_EN, 0);
672
673 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
674 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
675 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
676
677 return 0;
678 }
679
680 static struct mfd_cell asic3_cell_ds1wm = {
681 .name = "ds1wm",
682 .enable = ds1wm_enable,
683 .disable = ds1wm_disable,
684 .driver_data = &ds1wm_pdata,
685 .num_resources = ARRAY_SIZE(ds1wm_resources),
686 .resources = ds1wm_resources,
687 };
688
689 static void asic3_mmc_pwr(struct platform_device *pdev, int state)
690 {
691 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
692
693 tmio_core_mmc_pwr(asic->tmio_cnf, 1 - asic->bus_shift, state);
694 }
695
696 static void asic3_mmc_clk_div(struct platform_device *pdev, int state)
697 {
698 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
699
700 tmio_core_mmc_clk_div(asic->tmio_cnf, 1 - asic->bus_shift, state);
701 }
702
703 static struct tmio_mmc_data asic3_mmc_data = {
704 .hclk = 24576000,
705 .set_pwr = asic3_mmc_pwr,
706 .set_clk_div = asic3_mmc_clk_div,
707 };
708
709 static struct resource asic3_mmc_resources[] = {
710 {
711 .start = ASIC3_SD_CTRL_BASE,
712 .end = ASIC3_SD_CTRL_BASE + 0x3ff,
713 .flags = IORESOURCE_MEM,
714 },
715 {
716 .start = 0,
717 .end = 0,
718 .flags = IORESOURCE_IRQ,
719 },
720 };
721
722 static int asic3_mmc_enable(struct platform_device *pdev)
723 {
724 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
725
726 /* Not sure if it must be done bit by bit, but leaving as-is */
727 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
728 ASIC3_SDHWCTRL_LEVCD, 1);
729 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
730 ASIC3_SDHWCTRL_LEVWP, 1);
731 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
732 ASIC3_SDHWCTRL_SUSPEND, 0);
733 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
734 ASIC3_SDHWCTRL_PCLR, 0);
735
736 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
737 /* CLK32 used for card detection and for interruption detection
738 * when HCLK is stopped.
739 */
740 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
741 msleep(1);
742
743 /* HCLK 24.576 MHz, BCLK 12.288 MHz: */
744 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
745 CLOCK_SEL_CX | CLOCK_SEL_SD_HCLK_SEL);
746
747 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
748 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
749 msleep(1);
750
751 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
752 ASIC3_EXTCF_SD_MEM_ENABLE, 1);
753
754 /* Enable SD card slot 3.3V power supply */
755 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
756 ASIC3_SDHWCTRL_SDPWR, 1);
757
758 /* ASIC3_SD_CTRL_BASE assumes 32-bit addressing, TMIO is 16-bit */
759 tmio_core_mmc_enable(asic->tmio_cnf, 1 - asic->bus_shift,
760 ASIC3_SD_CTRL_BASE >> 1);
761
762 return 0;
763 }
764
765 static int asic3_mmc_disable(struct platform_device *pdev)
766 {
767 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
768
769 /* Put in suspend mode */
770 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
771 ASIC3_SDHWCTRL_SUSPEND, 1);
772
773 /* Disable clocks */
774 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
775 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
776 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
777 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
778 return 0;
779 }
780
781 static struct mfd_cell asic3_cell_mmc = {
782 .name = "tmio-mmc",
783 .enable = asic3_mmc_enable,
784 .disable = asic3_mmc_disable,
785 .driver_data = &asic3_mmc_data,
786 .num_resources = ARRAY_SIZE(asic3_mmc_resources),
787 .resources = asic3_mmc_resources,
788 };
789
790 static int __init asic3_mfd_probe(struct platform_device *pdev,
791 struct resource *mem)
792 {
793 struct asic3 *asic = platform_get_drvdata(pdev);
794 struct resource *mem_sdio;
795 int irq, ret;
796
797 mem_sdio = platform_get_resource(pdev, IORESOURCE_MEM, 1);
798 if (!mem_sdio)
799 dev_dbg(asic->dev, "no SDIO MEM resource\n");
800
801 irq = platform_get_irq(pdev, 1);
802 if (irq < 0)
803 dev_dbg(asic->dev, "no SDIO IRQ resource\n");
804
805 /* DS1WM */
806 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
807 ASIC3_EXTCF_OWM_SMB, 0);
808
809 ds1wm_resources[0].start >>= asic->bus_shift;
810 ds1wm_resources[0].end >>= asic->bus_shift;
811
812 asic3_cell_ds1wm.platform_data = &asic3_cell_ds1wm;
813 asic3_cell_ds1wm.data_size = sizeof(asic3_cell_ds1wm);
814
815 /* MMC */
816 asic->tmio_cnf = ioremap((ASIC3_SD_CONFIG_BASE >> asic->bus_shift) +
817 mem_sdio->start, 0x400 >> asic->bus_shift);
818 if (!asic->tmio_cnf) {
819 ret = -ENOMEM;
820 dev_dbg(asic->dev, "Couldn't ioremap SD_CONFIG\n");
821 goto out;
822 }
823 asic3_mmc_resources[0].start >>= asic->bus_shift;
824 asic3_mmc_resources[0].end >>= asic->bus_shift;
825
826 asic3_cell_mmc.platform_data = &asic3_cell_mmc;
827 asic3_cell_mmc.data_size = sizeof(asic3_cell_mmc);
828
829 ret = mfd_add_devices(&pdev->dev, pdev->id,
830 &asic3_cell_ds1wm, 1, mem, asic->irq_base);
831 if (ret < 0)
832 goto out;
833
834 if (mem_sdio && (irq >= 0))
835 ret = mfd_add_devices(&pdev->dev, pdev->id,
836 &asic3_cell_mmc, 1, mem_sdio, irq);
837
838 out:
839 return ret;
840 }
841
842 static void asic3_mfd_remove(struct platform_device *pdev)
843 {
844 struct asic3 *asic = platform_get_drvdata(pdev);
845
846 mfd_remove_devices(&pdev->dev);
847 iounmap(asic->tmio_cnf);
848 }
849
850 /* Core */
851 static int __init asic3_probe(struct platform_device *pdev)
852 {
853 struct asic3_platform_data *pdata = pdev->dev.platform_data;
854 struct asic3 *asic;
855 struct resource *mem;
856 unsigned long clksel;
857 int ret = 0;
858
859 asic = kzalloc(sizeof(struct asic3), GFP_KERNEL);
860 if (asic == NULL) {
861 printk(KERN_ERR "kzalloc failed\n");
862 return -ENOMEM;
863 }
864
865 spin_lock_init(&asic->lock);
866 platform_set_drvdata(pdev, asic);
867 asic->dev = &pdev->dev;
868
869 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
870 if (!mem) {
871 ret = -ENOMEM;
872 dev_err(asic->dev, "no MEM resource\n");
873 goto out_free;
874 }
875
876 asic->mapping = ioremap(mem->start, resource_size(mem));
877 if (!asic->mapping) {
878 ret = -ENOMEM;
879 dev_err(asic->dev, "Couldn't ioremap\n");
880 goto out_free;
881 }
882
883 asic->irq_base = pdata->irq_base;
884
885 /* calculate bus shift from mem resource */
886 asic->bus_shift = 2 - (resource_size(mem) >> 12);
887
888 clksel = 0;
889 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);
890
891 ret = asic3_irq_probe(pdev);
892 if (ret < 0) {
893 dev_err(asic->dev, "Couldn't probe IRQs\n");
894 goto out_unmap;
895 }
896
897 asic->gpio.base = pdata->gpio_base;
898 asic->gpio.ngpio = ASIC3_NUM_GPIOS;
899 asic->gpio.get = asic3_gpio_get;
900 asic->gpio.set = asic3_gpio_set;
901 asic->gpio.direction_input = asic3_gpio_direction_input;
902 asic->gpio.direction_output = asic3_gpio_direction_output;
903
904 ret = asic3_gpio_probe(pdev,
905 pdata->gpio_config,
906 pdata->gpio_config_num);
907 if (ret < 0) {
908 dev_err(asic->dev, "GPIO probe failed\n");
909 goto out_irq;
910 }
911
912 /* Making a per-device copy is only needed for the
913 * theoretical case of multiple ASIC3s on one board:
914 */
915 memcpy(asic->clocks, asic3_clk_init, sizeof(asic3_clk_init));
916
917 asic3_mfd_probe(pdev, mem);
918
919 dev_info(asic->dev, "ASIC3 Core driver\n");
920
921 return 0;
922
923 out_irq:
924 asic3_irq_remove(pdev);
925
926 out_unmap:
927 iounmap(asic->mapping);
928
929 out_free:
930 kfree(asic);
931
932 return ret;
933 }
934
935 static int __devexit asic3_remove(struct platform_device *pdev)
936 {
937 int ret;
938 struct asic3 *asic = platform_get_drvdata(pdev);
939
940 asic3_mfd_remove(pdev);
941
942 ret = asic3_gpio_remove(pdev);
943 if (ret < 0)
944 return ret;
945 asic3_irq_remove(pdev);
946
947 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);
948
949 iounmap(asic->mapping);
950
951 kfree(asic);
952
953 return 0;
954 }
955
956 static void asic3_shutdown(struct platform_device *pdev)
957 {
958 }
959
960 static struct platform_driver asic3_device_driver = {
961 .driver = {
962 .name = "asic3",
963 },
964 .remove = __devexit_p(asic3_remove),
965 .shutdown = asic3_shutdown,
966 };
967
968 static int __init asic3_init(void)
969 {
970 int retval = 0;
971 retval = platform_driver_probe(&asic3_device_driver, asic3_probe);
972 return retval;
973 }
974
975 subsys_initcall(asic3_init);
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