drivers/mfd/mc13783-core.c

   1 /*
   2  * Copyright 2009 Pengutronix
   3  * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
   4  *
   5  * loosely based on an earlier driver that has
   6  * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
   7  *
   8  * This program is free software; you can redistribute it and/or modify it under
   9  * the terms of the GNU General Public License version 2 as published by the
  10  * Free Software Foundation.
  11  */
  12 #include <linux/module.h>
  13 #include <linux/spi/spi.h>
  14 #include <linux/mfd/core.h>
  15 #include <linux/mfd/mc13783-private.h>
  16
  17 #define MC13783_IRQSTAT0        0
  18 #define MC13783_IRQSTAT0_ADCDONEI       (1 << 0)
  19 #define MC13783_IRQSTAT0_ADCBISDONEI    (1 << 1)
  20 #define MC13783_IRQSTAT0_TSI            (1 << 2)
  21 #define MC13783_IRQSTAT0_WHIGHI         (1 << 3)
  22 #define MC13783_IRQSTAT0_WLOWI          (1 << 4)
  23 #define MC13783_IRQSTAT0_CHGDETI        (1 << 6)
  24 #define MC13783_IRQSTAT0_CHGOVI         (1 << 7)
  25 #define MC13783_IRQSTAT0_CHGREVI        (1 << 8)
  26 #define MC13783_IRQSTAT0_CHGSHORTI      (1 << 9)
  27 #define MC13783_IRQSTAT0_CCCVI          (1 << 10)
  28 #define MC13783_IRQSTAT0_CHGCURRI       (1 << 11)
  29 #define MC13783_IRQSTAT0_BPONI          (1 << 12)
  30 #define MC13783_IRQSTAT0_LOBATLI        (1 << 13)
  31 #define MC13783_IRQSTAT0_LOBATHI        (1 << 14)
  32 #define MC13783_IRQSTAT0_UDPI           (1 << 15)
  33 #define MC13783_IRQSTAT0_USBI           (1 << 16)
  34 #define MC13783_IRQSTAT0_IDI            (1 << 19)
  35 #define MC13783_IRQSTAT0_SE1I           (1 << 21)
  36 #define MC13783_IRQSTAT0_CKDETI         (1 << 22)
  37 #define MC13783_IRQSTAT0_UDMI           (1 << 23)
  38
  39 #define MC13783_IRQMASK0        1
  40 #define MC13783_IRQMASK0_ADCDONEM       MC13783_IRQSTAT0_ADCDONEI
  41 #define MC13783_IRQMASK0_ADCBISDONEM    MC13783_IRQSTAT0_ADCBISDONEI
  42 #define MC13783_IRQMASK0_TSM            MC13783_IRQSTAT0_TSI
  43 #define MC13783_IRQMASK0_WHIGHM         MC13783_IRQSTAT0_WHIGHI
  44 #define MC13783_IRQMASK0_WLOWM          MC13783_IRQSTAT0_WLOWI
  45 #define MC13783_IRQMASK0_CHGDETM        MC13783_IRQSTAT0_CHGDETI
  46 #define MC13783_IRQMASK0_CHGOVM         MC13783_IRQSTAT0_CHGOVI
  47 #define MC13783_IRQMASK0_CHGREVM        MC13783_IRQSTAT0_CHGREVI
  48 #define MC13783_IRQMASK0_CHGSHORTM      MC13783_IRQSTAT0_CHGSHORTI
  49 #define MC13783_IRQMASK0_CCCVM          MC13783_IRQSTAT0_CCCVI
  50 #define MC13783_IRQMASK0_CHGCURRM       MC13783_IRQSTAT0_CHGCURRI
  51 #define MC13783_IRQMASK0_BPONM          MC13783_IRQSTAT0_BPONI
  52 #define MC13783_IRQMASK0_LOBATLM        MC13783_IRQSTAT0_LOBATLI
  53 #define MC13783_IRQMASK0_LOBATHM        MC13783_IRQSTAT0_LOBATHI
  54 #define MC13783_IRQMASK0_UDPM           MC13783_IRQSTAT0_UDPI
  55 #define MC13783_IRQMASK0_USBM           MC13783_IRQSTAT0_USBI
  56 #define MC13783_IRQMASK0_IDM            MC13783_IRQSTAT0_IDI
  57 #define MC13783_IRQMASK0_SE1M           MC13783_IRQSTAT0_SE1I
  58 #define MC13783_IRQMASK0_CKDETM         MC13783_IRQSTAT0_CKDETI
  59 #define MC13783_IRQMASK0_UDMM           MC13783_IRQSTAT0_UDMI
  60
  61 #define MC13783_IRQSTAT1        3
  62 #define MC13783_IRQSTAT1_1HZI           (1 << 0)
  63 #define MC13783_IRQSTAT1_TODAI          (1 << 1)
  64 #define MC13783_IRQSTAT1_ONOFD1I        (1 << 3)
  65 #define MC13783_IRQSTAT1_ONOFD2I        (1 << 4)
  66 #define MC13783_IRQSTAT1_ONOFD3I        (1 << 5)
  67 #define MC13783_IRQSTAT1_SYSRSTI        (1 << 6)
  68 #define MC13783_IRQSTAT1_RTCRSTI        (1 << 7)
  69 #define MC13783_IRQSTAT1_PCI            (1 << 8)
  70 #define MC13783_IRQSTAT1_WARMI          (1 << 9)
  71 #define MC13783_IRQSTAT1_MEMHLDI        (1 << 10)
  72 #define MC13783_IRQSTAT1_PWRRDYI        (1 << 11)
  73 #define MC13783_IRQSTAT1_THWARNLI       (1 << 12)
  74 #define MC13783_IRQSTAT1_THWARNHI       (1 << 13)
  75 #define MC13783_IRQSTAT1_CLKI           (1 << 14)
  76 #define MC13783_IRQSTAT1_SEMAFI         (1 << 15)
  77 #define MC13783_IRQSTAT1_MC2BI          (1 << 17)
  78 #define MC13783_IRQSTAT1_HSDETI         (1 << 18)
  79 #define MC13783_IRQSTAT1_HSLI           (1 << 19)
  80 #define MC13783_IRQSTAT1_ALSPTHI        (1 << 20)
  81 #define MC13783_IRQSTAT1_AHSSHORTI      (1 << 21)
  82
  83 #define MC13783_IRQMASK1        4
  84 #define MC13783_IRQMASK1_1HZM           MC13783_IRQSTAT1_1HZI
  85 #define MC13783_IRQMASK1_TODAM          MC13783_IRQSTAT1_TODAI
  86 #define MC13783_IRQMASK1_ONOFD1M        MC13783_IRQSTAT1_ONOFD1I
  87 #define MC13783_IRQMASK1_ONOFD2M        MC13783_IRQSTAT1_ONOFD2I
  88 #define MC13783_IRQMASK1_ONOFD3M        MC13783_IRQSTAT1_ONOFD3I
  89 #define MC13783_IRQMASK1_SYSRSTM        MC13783_IRQSTAT1_SYSRSTI
  90 #define MC13783_IRQMASK1_RTCRSTM        MC13783_IRQSTAT1_RTCRSTI
  91 #define MC13783_IRQMASK1_PCM            MC13783_IRQSTAT1_PCI
  92 #define MC13783_IRQMASK1_WARMM          MC13783_IRQSTAT1_WARMI
  93 #define MC13783_IRQMASK1_MEMHLDM        MC13783_IRQSTAT1_MEMHLDI
  94 #define MC13783_IRQMASK1_PWRRDYM        MC13783_IRQSTAT1_PWRRDYI
  95 #define MC13783_IRQMASK1_THWARNLM       MC13783_IRQSTAT1_THWARNLI
  96 #define MC13783_IRQMASK1_THWARNHM       MC13783_IRQSTAT1_THWARNHI
  97 #define MC13783_IRQMASK1_CLKM           MC13783_IRQSTAT1_CLKI
  98 #define MC13783_IRQMASK1_SEMAFM         MC13783_IRQSTAT1_SEMAFI
  99 #define MC13783_IRQMASK1_MC2BM          MC13783_IRQSTAT1_MC2BI
 100 #define MC13783_IRQMASK1_HSDETM         MC13783_IRQSTAT1_HSDETI
 101 #define MC13783_IRQMASK1_HSLM           MC13783_IRQSTAT1_HSLI
 102 #define MC13783_IRQMASK1_ALSPTHM        MC13783_IRQSTAT1_ALSPTHI
 103 #define MC13783_IRQMASK1_AHSSHORTM      MC13783_IRQSTAT1_AHSSHORTI
 104
 105 #define MC13783_ADC1            44
 106 #define MC13783_ADC1_ADEN               (1 << 0)
 107 #define MC13783_ADC1_RAND               (1 << 1)
 108 #define MC13783_ADC1_ADSEL              (1 << 3)
 109 #define MC13783_ADC1_ASC                (1 << 20)
 110 #define MC13783_ADC1_ADTRIGIGN          (1 << 21)
 111
 112 #define MC13783_NUMREGS 0x3f
 113
 114 void mc13783_lock(struct mc13783 *mc13783)
 115 {
 116         if (!mutex_trylock(&mc13783->lock)) {
 117                 dev_dbg(&mc13783->spidev->dev, "wait for %s from %pf\n",
 118                                 __func__, __builtin_return_address(0));
 119
 120                 mutex_lock(&mc13783->lock);
 121         }
 122         dev_dbg(&mc13783->spidev->dev, "%s from %pf\n",
 123                         __func__, __builtin_return_address(0));
 124 }
 125 EXPORT_SYMBOL(mc13783_lock);
 126
 127 void mc13783_unlock(struct mc13783 *mc13783)
 128 {
 129         dev_dbg(&mc13783->spidev->dev, "%s from %pf\n",
 130                         __func__, __builtin_return_address(0));
 131         mutex_unlock(&mc13783->lock);
 132 }
 133 EXPORT_SYMBOL(mc13783_unlock);
 134
 135 #define MC13783_REGOFFSET_SHIFT 25
 136 int mc13783_reg_read(struct mc13783 *mc13783, unsigned int offset, u32 *val)
 137 {
 138         struct spi_transfer t;
 139         struct spi_message m;
 140         int ret;
 141
 142         BUG_ON(!mutex_is_locked(&mc13783->lock));
 143
 144         if (offset > MC13783_NUMREGS)
 145                 return -EINVAL;
 146
 147         *val = offset << MC13783_REGOFFSET_SHIFT;
 148
 149         memset(&t, 0, sizeof(t));
 150
 151         t.tx_buf = val;
 152         t.rx_buf = val;
 153         t.len = sizeof(u32);
 154
 155         spi_message_init(&m);
 156         spi_message_add_tail(&t, &m);
 157
 158         ret = spi_sync(mc13783->spidev, &m);
 159
 160         /* error in message.status implies error return from spi_sync */
 161         BUG_ON(!ret && m.status);
 162
 163         if (ret)
 164                 return ret;
 165
 166         *val &= 0xffffff;
 167
 168         dev_vdbg(&mc13783->spidev->dev, "[0x%02x] -> 0x%06x\n", offset, *val);
 169
 170         return 0;
 171 }
 172 EXPORT_SYMBOL(mc13783_reg_read);
 173
 174 int mc13783_reg_write(struct mc13783 *mc13783, unsigned int offset, u32 val)
 175 {
 176         u32 buf;
 177         struct spi_transfer t;
 178         struct spi_message m;
 179         int ret;
 180
 181         BUG_ON(!mutex_is_locked(&mc13783->lock));
 182
 183         dev_vdbg(&mc13783->spidev->dev, "[0x%02x] <- 0x%06x\n", offset, val);
 184
 185         if (offset > MC13783_NUMREGS || val > 0xffffff)
 186                 return -EINVAL;
 187
 188         buf = 1 << 31 | offset << MC13783_REGOFFSET_SHIFT | val;
 189
 190         memset(&t, 0, sizeof(t));
 191
 192         t.tx_buf = &buf;
 193         t.rx_buf = &buf;
 194         t.len = sizeof(u32);
 195
 196         spi_message_init(&m);
 197         spi_message_add_tail(&t, &m);
 198
 199         ret = spi_sync(mc13783->spidev, &m);
 200
 201         BUG_ON(!ret && m.status);
 202
 203         if (ret)
 204                 return ret;
 205
 206         return 0;
 207 }
 208 EXPORT_SYMBOL(mc13783_reg_write);
 209
 210 int mc13783_reg_rmw(struct mc13783 *mc13783, unsigned int offset,
 211                 u32 mask, u32 val)
 212 {
 213         int ret;
 214         u32 valread;
 215
 216         BUG_ON(val & ~mask);
 217
 218         ret = mc13783_reg_read(mc13783, offset, &valread);
 219         if (ret)
 220                 return ret;
 221
 222         valread = (valread & ~mask) | val;
 223
 224         return mc13783_reg_write(mc13783, offset, valread);
 225 }
 226 EXPORT_SYMBOL(mc13783_reg_rmw);
 227
 228 int mc13783_mask(struct mc13783 *mc13783, int irq)
 229 {
 230         int ret;
 231         unsigned int offmask = irq < 24 ? MC13783_IRQMASK0 : MC13783_IRQMASK1;
 232         u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
 233         u32 mask;
 234
 235         if (irq < 0 || irq >= MC13783_NUM_IRQ)
 236                 return -EINVAL;
 237
 238         ret = mc13783_reg_read(mc13783, offmask, &mask);
 239         if (ret)
 240                 return ret;
 241
 242         if (mask & irqbit)
 243                 /* already masked */
 244                 return 0;
 245
 246         return mc13783_reg_write(mc13783, offmask, mask | irqbit);
 247 }
 248 EXPORT_SYMBOL(mc13783_mask);
 249
 250 int mc13783_unmask(struct mc13783 *mc13783, int irq)
 251 {
 252         int ret;
 253         unsigned int offmask = irq < 24 ? MC13783_IRQMASK0 : MC13783_IRQMASK1;
 254         u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
 255         u32 mask;
 256
 257         if (irq < 0 || irq >= MC13783_NUM_IRQ)
 258                 return -EINVAL;
 259
 260         ret = mc13783_reg_read(mc13783, offmask, &mask);
 261         if (ret)
 262                 return ret;
 263
 264         if (!(mask & irqbit))
 265                 /* already unmasked */
 266                 return 0;
 267
 268         return mc13783_reg_write(mc13783, offmask, mask & ~irqbit);
 269 }
 270 EXPORT_SYMBOL(mc13783_unmask);
 271
 272 int mc13783_irq_request_nounmask(struct mc13783 *mc13783, int irq,
 273                 irq_handler_t handler, const char *name, void *dev)
 274 {
 275         BUG_ON(!mutex_is_locked(&mc13783->lock));
 276         BUG_ON(!handler);
 277
 278         if (irq < 0 || irq >= MC13783_NUM_IRQ)
 279                 return -EINVAL;
 280
 281         if (mc13783->irqhandler[irq])
 282                 return -EBUSY;
 283
 284         mc13783->irqhandler[irq] = handler;
 285         mc13783->irqdata[irq] = dev;
 286
 287         return 0;
 288 }
 289 EXPORT_SYMBOL(mc13783_irq_request_nounmask);
 290
 291 int mc13783_irq_request(struct mc13783 *mc13783, int irq,
 292                 irq_handler_t handler, const char *name, void *dev)
 293 {
 294         int ret;
 295
 296         ret = mc13783_irq_request_nounmask(mc13783, irq, handler, name, dev);
 297         if (ret)
 298                 return ret;
 299
 300         ret = mc13783_unmask(mc13783, irq);
 301         if (ret) {
 302                 mc13783->irqhandler[irq] = NULL;
 303                 mc13783->irqdata[irq] = NULL;
 304                 return ret;
 305         }
 306
 307         return 0;
 308 }
 309 EXPORT_SYMBOL(mc13783_irq_request);
 310
 311 int mc13783_irq_free(struct mc13783 *mc13783, int irq, void *dev)
 312 {
 313         int ret;
 314         BUG_ON(!mutex_is_locked(&mc13783->lock));
 315
 316         if (irq < 0 || irq >= MC13783_NUM_IRQ || !mc13783->irqhandler[irq] ||
 317                         mc13783->irqdata[irq] != dev)
 318                 return -EINVAL;
 319
 320         ret = mc13783_mask(mc13783, irq);
 321         if (ret)
 322                 return ret;
 323
 324         mc13783->irqhandler[irq] = NULL;
 325         mc13783->irqdata[irq] = NULL;
 326
 327         return 0;
 328 }
 329 EXPORT_SYMBOL(mc13783_irq_free);
 330
 331 static inline irqreturn_t mc13783_irqhandler(struct mc13783 *mc13783, int irq)
 332 {
 333         return mc13783->irqhandler[irq](irq, mc13783->irqdata[irq]);
 334 }
 335
 336 int mc13783_ackirq(struct mc13783 *mc13783, int irq)
 337 {
 338         unsigned int offstat = irq < 24 ? MC13783_IRQSTAT0 : MC13783_IRQSTAT1;
 339         unsigned int val = 1 << (irq < 24 ? irq : irq - 24);
 340
 341         BUG_ON(irq < 0 || irq >= MC13783_NUM_IRQ);
 342
 343         return mc13783_reg_write(mc13783, offstat, val);
 344 }
 345 EXPORT_SYMBOL(mc13783_ackirq);
 346
 347 /*
 348  * returns: number of handled irqs or negative error
 349  * locking: holds mc13783->lock
 350  */
 351 static int mc13783_irq_handle(struct mc13783 *mc13783,
 352                 unsigned int offstat, unsigned int offmask, int baseirq)
 353 {
 354         u32 stat, mask;
 355         int ret = mc13783_reg_read(mc13783, offstat, &stat);
 356         int num_handled = 0;
 357
 358         if (ret)
 359                 return ret;
 360
 361         ret = mc13783_reg_read(mc13783, offmask, &mask);
 362         if (ret)
 363                 return ret;
 364
 365         while (stat & ~mask) {
 366                 int irq = __ffs(stat & ~mask);
 367
 368                 stat &= ~(1 << irq);
 369
 370                 if (likely(mc13783->irqhandler[baseirq + irq])) {
 371                         irqreturn_t handled;
 372
 373                         handled = mc13783_irqhandler(mc13783, baseirq + irq);
 374                         if (handled == IRQ_HANDLED)
 375                                 num_handled++;
 376                 } else {
 377                         dev_err(&mc13783->spidev->dev,
 378                                         "BUG: irq %u but no handler\n",
 379                                         baseirq + irq);
 380
 381                         mask |= 1 << irq;
 382
 383                         ret = mc13783_reg_write(mc13783, offmask, mask);
 384                 }
 385         }
 386
 387         return num_handled;
 388 }
 389
 390 static irqreturn_t mc13783_irq_thread(int irq, void *data)
 391 {
 392         struct mc13783 *mc13783 = data;
 393         irqreturn_t ret;
 394         int handled = 0;
 395
 396         mc13783_lock(mc13783);
 397
 398         ret = mc13783_irq_handle(mc13783, MC13783_IRQSTAT0,
 399                         MC13783_IRQMASK0, MC13783_IRQ_ADCDONE);
 400         if (ret > 0)
 401                 handled = 1;
 402
 403         ret = mc13783_irq_handle(mc13783, MC13783_IRQSTAT1,
 404                         MC13783_IRQMASK1, MC13783_IRQ_1HZ);
 405         if (ret > 0)
 406                 handled = 1;
 407
 408         mc13783_unlock(mc13783);
 409
 410         return IRQ_RETVAL(handled);
 411 }
 412
 413 #define MC13783_ADC1_CHAN0_SHIFT        5
 414 #define MC13783_ADC1_CHAN1_SHIFT        8
 415
 416 struct mc13783_adcdone_data {
 417         struct mc13783 *mc13783;
 418         struct completion done;
 419 };
 420
 421 static irqreturn_t mc13783_handler_adcdone(int irq, void *data)
 422 {
 423         struct mc13783_adcdone_data *adcdone_data = data;
 424
 425         mc13783_ackirq(adcdone_data->mc13783, irq);
 426
 427         complete_all(&adcdone_data->done);
 428
 429         return IRQ_HANDLED;
 430 }
 431
 432 #define MC13783_ADC_WORKING (1 << 16)
 433
 434 int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode,
 435                 unsigned int channel, unsigned int *sample)
 436 {
 437         u32 adc0, adc1, old_adc0;
 438         int i, ret;
 439         struct mc13783_adcdone_data adcdone_data = {
 440                 .mc13783 = mc13783,
 441         };
 442         init_completion(&adcdone_data.done);
 443
 444         dev_dbg(&mc13783->spidev->dev, "%s\n", __func__);
 445
 446         mc13783_lock(mc13783);
 447
 448         if (mc13783->flags & MC13783_ADC_WORKING) {
 449                 ret = -EBUSY;
 450                 goto out;
 451         }
 452
 453         mc13783->flags |= MC13783_ADC_WORKING;
 454
 455         mc13783_reg_read(mc13783, MC13783_ADC0, &old_adc0);
 456
 457         adc0 = MC13783_ADC0_ADINC1 | MC13783_ADC0_ADINC2;
 458         adc1 = MC13783_ADC1_ADEN | MC13783_ADC1_ADTRIGIGN | MC13783_ADC1_ASC;
 459
 460         if (channel > 7)
 461                 adc1 |= MC13783_ADC1_ADSEL;
 462
 463         switch (mode) {
 464         case MC13783_ADC_MODE_TS:
 465                 adc0 |= MC13783_ADC0_ADREFEN | MC13783_ADC0_TSMOD0 |
 466                         MC13783_ADC0_TSMOD1;
 467                 adc1 |= 4 << MC13783_ADC1_CHAN1_SHIFT;
 468                 break;
 469
 470         case MC13783_ADC_MODE_SINGLE_CHAN:
 471                 adc0 |= old_adc0 & MC13783_ADC0_TSMOD_MASK;
 472                 adc1 |= (channel & 0x7) << MC13783_ADC1_CHAN0_SHIFT;
 473                 adc1 |= MC13783_ADC1_RAND;
 474                 break;
 475
 476         case MC13783_ADC_MODE_MULT_CHAN:
 477                 adc0 |= old_adc0 & MC13783_ADC0_TSMOD_MASK;
 478                 adc1 |= 4 << MC13783_ADC1_CHAN1_SHIFT;
 479                 break;
 480
 481         default:
 482                 mc13783_unlock(mc13783);
 483                 return -EINVAL;
 484         }
 485
 486         dev_dbg(&mc13783->spidev->dev, "%s: request irq\n", __func__);
 487         mc13783_irq_request(mc13783, MC13783_IRQ_ADCDONE,
 488                         mc13783_handler_adcdone, __func__, &adcdone_data);
 489         mc13783_ackirq(mc13783, MC13783_IRQ_ADCDONE);
 490
 491         mc13783_reg_write(mc13783, MC13783_REG_ADC_0, adc0);
 492         mc13783_reg_write(mc13783, MC13783_REG_ADC_1, adc1);
 493
 494         mc13783_unlock(mc13783);
 495
 496         ret = wait_for_completion_interruptible_timeout(&adcdone_data.done, HZ);
 497
 498         if (!ret)
 499                 ret = -ETIMEDOUT;
 500
 501         mc13783_lock(mc13783);
 502
 503         mc13783_irq_free(mc13783, MC13783_IRQ_ADCDONE, &adcdone_data);
 504
 505         if (ret > 0)
 506                 for (i = 0; i < 4; ++i) {
 507                         ret = mc13783_reg_read(mc13783,
 508                                         MC13783_REG_ADC_2, &sample[i]);
 509                         if (ret)
 510                                 break;
 511                 }
 512
 513         if (mode == MC13783_ADC_MODE_TS)
 514                 /* restore TSMOD */
 515                 mc13783_reg_write(mc13783, MC13783_REG_ADC_0, old_adc0);
 516
 517         mc13783->flags &= ~MC13783_ADC_WORKING;
 518 out:
 519         mc13783_unlock(mc13783);
 520
 521         return ret;
 522 }
 523 EXPORT_SYMBOL_GPL(mc13783_adc_do_conversion);
 524
 525 static int mc13783_add_subdevice_pdata(struct mc13783 *mc13783,
 526                 const char *name, void *pdata, size_t pdata_size)
 527 {
 528         struct mfd_cell cell = {
 529                 .name = name,
 530                 .platform_data = pdata,
 531                 .data_size = pdata_size,
 532         };
 533
 534         return mfd_add_devices(&mc13783->spidev->dev, -1, &cell, 1, NULL, 0);
 535 }
 536
 537 static int mc13783_add_subdevice(struct mc13783 *mc13783, const char *name)
 538 {
 539         return mc13783_add_subdevice_pdata(mc13783, name, NULL, 0);
 540 }
 541
 542 static int mc13783_check_revision(struct mc13783 *mc13783)
 543 {
 544         u32 rev_id, rev1, rev2, finid, icid;
 545
 546         mc13783_reg_read(mc13783, MC13783_REG_REVISION, &rev_id);
 547
 548         rev1 = (rev_id & 0x018) >> 3;
 549         rev2 = (rev_id & 0x007);
 550         icid = (rev_id & 0x01C0) >> 6;
 551         finid = (rev_id & 0x01E00) >> 9;
 552
 553         /* Ver 0.2 is actually 3.2a.  Report as 3.2 */
 554         if ((rev1 == 0) && (rev2 == 2))
 555                 rev1 = 3;
 556
 557         if (rev1 == 0 || icid != 2) {
 558                 dev_err(&mc13783->spidev->dev, "No MC13783 detected.\n");
 559                 return -ENODEV;
 560         }
 561
 562         dev_info(&mc13783->spidev->dev,
 563                         "MC13783 Rev %d.%d FinVer %x detected\n",
 564                         rev1, rev2, finid);
 565
 566         return 0;
 567 }
 568
 569 static int mc13783_probe(struct spi_device *spi)
 570 {
 571         struct mc13783 *mc13783;
 572         struct mc13783_platform_data *pdata = dev_get_platdata(&spi->dev);
 573         int ret;
 574
 575         mc13783 = kzalloc(sizeof(*mc13783), GFP_KERNEL);
 576         if (!mc13783)
 577                 return -ENOMEM;
 578
 579         dev_set_drvdata(&spi->dev, mc13783);
 580         spi->mode = SPI_MODE_0 | SPI_CS_HIGH;
 581         spi->bits_per_word = 32;
 582         spi_setup(spi);
 583
 584         mc13783->spidev = spi;
 585
 586         mutex_init(&mc13783->lock);
 587         mc13783_lock(mc13783);
 588
 589         ret = mc13783_check_revision(mc13783);
 590         if (ret)
 591                 goto err_revision;
 592
 593         /* mask all irqs */
 594         ret = mc13783_reg_write(mc13783, MC13783_IRQMASK0, 0x00ffffff);
 595         if (ret)
 596                 goto err_mask;
 597
 598         ret = mc13783_reg_write(mc13783, MC13783_IRQMASK1, 0x00ffffff);
 599         if (ret)
 600                 goto err_mask;
 601
 602         ret = request_threaded_irq(spi->irq, NULL, mc13783_irq_thread,
 603                         IRQF_ONESHOT | IRQF_TRIGGER_HIGH, "mc13783", mc13783);
 604
 605         if (ret) {
 606 err_mask:
 607 err_revision:
 608                 mutex_unlock(&mc13783->lock);
 609                 dev_set_drvdata(&spi->dev, NULL);
 610                 kfree(mc13783);
 611                 return ret;
 612         }
 613
 614         /* This should go away (BEGIN) */
 615         if (pdata) {
 616                 mc13783->flags = pdata->flags;
 617                 mc13783->regulators = pdata->regulators;
 618                 mc13783->num_regulators = pdata->num_regulators;
 619         }
 620         /* This should go away (END) */
 621
 622         mc13783_unlock(mc13783);
 623
 624         if (pdata->flags & MC13783_USE_ADC)
 625                 mc13783_add_subdevice(mc13783, "mc13783-adc");
 626
 627         if (pdata->flags & MC13783_USE_CODEC)
 628                 mc13783_add_subdevice(mc13783, "mc13783-codec");
 629
 630         if (pdata->flags & MC13783_USE_REGULATOR) {
 631                 struct mc13783_regulator_platform_data regulator_pdata = {
 632                         .num_regulators = pdata->num_regulators,
 633                         .regulators = pdata->regulators,
 634                 };
 635
 636                 mc13783_add_subdevice_pdata(mc13783, "mc13783-regulator",
 637                                 &regulator_pdata, sizeof(regulator_pdata));
 638         }
 639
 640         if (pdata->flags & MC13783_USE_RTC)
 641                 mc13783_add_subdevice(mc13783, "mc13783-rtc");
 642
 643         if (pdata->flags & MC13783_USE_TOUCHSCREEN)
 644                 mc13783_add_subdevice(mc13783, "mc13783-ts");
 645
 646         return 0;
 647 }
 648
 649 static int __devexit mc13783_remove(struct spi_device *spi)
 650 {
 651         struct mc13783 *mc13783 = dev_get_drvdata(&spi->dev);
 652
 653         free_irq(mc13783->spidev->irq, mc13783);
 654
 655         mfd_remove_devices(&spi->dev);
 656
 657         return 0;
 658 }
 659
 660 static struct spi_driver mc13783_driver = {
 661         .driver = {
 662                 .name = "mc13783",
 663                 .bus = &spi_bus_type,
 664                 .owner = THIS_MODULE,
 665         },
 666         .probe = mc13783_probe,
 667         .remove = __devexit_p(mc13783_remove),
 668 };
 669
 670 static int __init mc13783_init(void)
 671 {
 672         return spi_register_driver(&mc13783_driver);
 673 }
 674 subsys_initcall(mc13783_init);
 675
 676 static void __exit mc13783_exit(void)
 677 {
 678         spi_unregister_driver(&mc13783_driver);
 679 }
 680 module_exit(mc13783_exit);
 681
 682 MODULE_DESCRIPTION("Core driver for Freescale MC13783 PMIC");
 683 MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
 684 MODULE_LICENSE("GPL v2");